Battery tester

Abstract

A battery tester includes a test signal circuit including a first capacitor, a response sensing circuit, and an arc suppression circuit. The arc suppression circuit includes a first resistor and a control switch coupled in parallel with each other and a control circuit. The control circuit is configured to detect information indicative of an access impedance value between a first test signal terminal and a second test signal terminal, and receive information of a measured impedance value between a first response sensing terminal and a second response sensing terminal from an impedance measurement circuit in the response sensing circuit, and control the battery tester to operate in a measurement mode or a non-measurement mode according to the access impedance value and the measured impedance value. In the non-measurement mode, the control circuit controls the control switch to be open such that a test current flows through the battery under test via the first resistor. In the measurement mode, the control circuit controls the control switch to be closed such that the test current flows through the battery under test via the closed control switch.

Description

TECHNICAL FIELD

[0001] The present application relates to an electronic circuit, and more particularly, to a battery tester. BACKGROUND

[0002] A storage battery is widely used as a power source in industrial production, transportation, communication and other fields. In order to detect the failure or insufficient capacity of the battery in advance, and avoid the resulting accident hazards, it is necessary to comprehensively test the operating parameters of the storage battery. Generally, the working state of the battery can be evaluated by measuring the internal resistance of the battery. For an uninterruptible power supply system (UPS), the voltage of the battery pack is usually between 400V and 600V. However, if the voltage between the two poles of the battery to be tested is too high, or the current in the line is too large, it will cause damage to the measuring equipment. SUMMARY

[0003] One of the purposes of the present application is to provide a battery tester capable of inhibiting arc discharge generated when the test pen of the battery tester contacts the positive and negative poles of the battery to be tested.

[0004] According to an aspect of the present application, there is provided a battery tester, comprising: a test signal circuit, comprising: a test current source for generating an alternating test current; first and second test signal terminals for coupling to a positive and a negative terminal of a battery under test, respectively, and applying the test current to the battery under test during a test of the battery under test; and a first capacitor coupled between the test current source and the first test signal terminal; a response sensing circuit, comprising: first and second response sensing terminals for coupling to the positive and the negative terminal of the battery under test, respectively, and receiving a response signal excited by the test current within the battery under test during the test of the battery under test; and an impedance measurement circuit for measuring an internal impedance of the battery under test based on the response signal and the test current; and an arc suppression circuit, comprising: a first resistor and a control switch coupled in parallel to each other, the parallel coupled first resistor and the control switch being coupled between the test current source and the first test signal terminal, and in series with the first capacitor; and a control circuit configured to: detect information indicative of an access impedance value between the first test signal terminal and the second test signal terminal, and receive information of a measured impedance value between the first response sensing terminal and the second response sensing terminal from the impedance measurement circuit; and control the battery tester to operate in a measurement mode or a non-measurement mode according to the access impedance value and the measured impedance value, wherein: in the non-measurement mode, the control circuit controls the control switch to be open such that the test current flows through the battery under test via the first resistor; and in the measurement mode, the control circuit controls the control switch to be closed such that the test current flows through the battery under test via the closed control switch.

[0005] In some embodiments, the test current source is a variable current source, and the control circuit is further configured to: control the test current source to output a first test current in the non-measurement mode; and control the test current source to output a second test current in the measurement mode, the second test current having a current value greater than the first test current.

[0006] In some embodiments, the control circuit is further configured to: compare the access impedance value with a first reference impedance value; and generate a non-measurement mode start signal to control the battery tester to operate in the non-measurement mode when the access impedance value is greater than the first reference impedance value.

[0007] In some embodiments, the control circuit is further configured to: compare the measured impedance value to a second reference impedance value; and generate a measurement mode enable signal to control the battery tester to operate in a measurement mode when the access impedance value is less than the first reference impedance value and the measured impedance value is less than the second reference impedance value.

[0008] In some embodiments, the first reference impedance value is greater than the second reference impedance value.

[0009] In some embodiments, the control circuit further comprises: a first comparator having a first input configured to receive the first reference impedance value, a second input coupled to the test current source for detecting information indicative of the access impedance value, and an output outputting a first comparison result regarding the first reference impedance value and the access impedance value; a second comparator having a first input configured to receive a second reference impedance value, a second input coupled to the impedance measurement circuit for receiving information indicative of the measured impedance value, and an output outputting a second comparison result regarding the second reference impedance value and the measured impedance value; and a mode switching circuit configured to receive the first comparison result and the second comparison result and generate the measurement mode enable signal or the non-measurement mode enable signal indicating the battery tester to operate in the measurement mode or the non-measurement mode based on the first comparison result and the second comparison result.

[0010] In some embodiments, the control circuit further comprises: a delay circuit configured to receive the measurement mode enable signal or the non-measurement mode enable signal and delay the measurement mode enable signal or the non-measurement mode enable signal to generate a delayed measurement mode enable signal or a delayed non-measurement mode enable signal, the control circuit being configured to control the battery tester to operate in the measurement mode based on the delayed measurement mode enable signal or to control the battery tester to operate in the non-measurement mode based on the delayed non-measurement mode enable signal.

[0011] In some embodiments, the mode switching circuit is further configured to receive the delayed measurement mode enable signal or the delayed non-measurement mode enable signal and generate the measurement mode enable signal or the non-measurement mode enable signal indicating the battery tester to operate in the measurement mode or the non-measurement mode based on the first comparison result, the second comparison result, and the delayed measurement mode enable signal or the delayed non-measurement mode enable signal.

[0012] In some embodiments, the mode switching circuit comprises an OR gate, a first input of the OR gate is coupled to an output of the second comparator to receive the second comparison result, a second input of the OR gate is configured to receive the delayed measurement mode start signal or the delayed non-measurement mode start signal; and an AND gate, a first input of the AND gate is coupled to an output of the first comparator to receive the first comparison result, a second input of the AND gate is coupled to an output of the OR gate, and an output of the AND gate outputs the measurement mode start signal or the non-measurement mode start signal.

[0013] In some embodiments, the control circuit further comprises a conversion circuit coupled between an output of the test current source and a second input of the first comparator, configured to convert an alternating voltage signal at the output of the test current source into information of the access impedance value.

[0014] In some embodiments, the control circuit further comprises a switch driving circuit coupled between the delay circuit and the control switch, configured to control the control switch to open or close according to the delayed measurement mode start signal or the delayed non-measurement mode start signal.

[0015] In some embodiments, the delay circuit delays the measurement mode start signal by a predetermined time period to generate the delayed measurement mode start signal, the predetermined time period is greater than or equal to a time constant determined by a capacitance of the first capacitor and a resistance of the first resistor.

[0016] In some embodiments, the delay circuit comprises a second resistor, a first end of the second resistor is configured to receive the measurement mode start signal; a second capacitor, a first end of the second capacitor is coupled to a second end of the second resistor, and a second end of the second capacitor is coupled to ground; and a third comparator, a first input of the third comparator is coupled to the second end of the second resistor and the first end of the second capacitor, a second input of the third comparator is configured to receive a reference voltage, and an output of the third comparator outputs the delayed measurement mode start signal.

[0017] In some embodiments, the predetermined time period is equal to a time required for the measurement mode start signal to charge the second capacitor via the second resistor until a voltage at the first end of the second capacitor is at least equal to the reference voltage.

[0018] In some embodiments, the delay circuit further comprises a diode, a negative electrode of the diode is coupled to the first end of the second resistor, and a positive electrode of the diode is coupled to the second end of the second resistor.

[0019] In some embodiments, the test signal circuit further includes a fuse coupled in series with the first capacitor between the test current source and the first test signal terminal.

[0020] In some embodiments, the response sensing circuit further includes a third resistor coupled between the first test signal terminal and the first response sensing terminal, and a fourth resistor coupled between the second test signal terminal and the second response sensing terminal.

[0021] The above is a summary of the present application, which may have simplified, generalized or omitted details, and therefore those skilled in the art should recognize that this section is merely illustrative and is not intended to limit the scope of the present application in any way. This summary section is neither intended nor used to identify key or essential features of the claimed subject matter, nor used to build an aid for determining the scope of the claimed subject matter. BRIEF DESCRIPTION OF DRAWINGS

[0022] The above and other features of the present application will become more fully understood from the following detailed description, taken in conjunction with the accompanying drawings. Understanding that these drawings and detailed description are not limiting on the scope of the application, it will be appreciated that the description is intended only to illustrate examples of the application, and is not intended to limit the scope of the application. The content of the present application will become more apparent and will be better understood from the following detailed description when taken in conjunction with the accompanying drawings.

[0023] Figure 1 The overall appearance of the battery tester is shown.

[0024] Figure 2 The structure of the battery tester is shown.

[0025] Figure 3 The structure of the battery tester is shown.

[0026] Figure 4 The structure of the battery tester is shown.

[0027] Figure 5 The structure of the mode switching circuit is shown. DETAILED DESCRIPTION

[0028] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments can be utilized, and other changes can be made, without departing from the spirit or scope of the subject matter presented herein. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the Figures, can be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which are explicitly contemplated and form part of this disclosure.

[0029] Figure 1 The overall appearance of a battery tester 1 according to some embodiments of the present disclosure is shown by way of example. The battery tester 1 includes a display screen 2, which can visually present measured values to a user, and a function selection switch 3, by which different measurement functions can be selected. The battery tester 1 is externally connected to a pair of test probes 4A and 4B, which are respectively brought into contact with the positive and negative terminals of a battery 5 under test. Each test probe is internally provided with two leads for electrically connecting to a test signal circuit and a response sensing circuit inside the battery tester 1. As shown in Figure 1 The faceplate of the battery tester 1 also includes soft function keys F1-F4 and a range switch key ("RANGE") for selecting different measurement functions and test ranges. Figure 1 The faceplate of the battery tester 1 shown in FIG. 1 also includes a power key, a backlight key, a DMM / String function selection key ("DMM / String"), a setup key ("SETUP"), and a hold key ("HOLD"). Of course, Figure 1 The battery tester 1 shown in FIG. 1 is merely by way of example, and one of ordinary skill in the art can make various changes to its appearance, faceplate layout, key arrangement, etc., without departing from the spirit and scope of the present disclosure.

[0030] Figure 2 A schematic diagram of a battery tester for measuring the internal resistance of a battery according to the AC injection method is shown. As shown in Figure 2 The battery tester includes two test signal terminals SRC_Hi and SRC_Lo for applying an AC test current Is provided by a test current source to a battery under test, e.g., the terminal SRC_Hi is coupled to the positive terminal of the battery under test, and the terminal SRC_Lo is coupled to the negative terminal of the battery under test. The AC test current source used in the AC injection method typically needs to have sufficient stability and as little waveform distortion as possible.

[0031] The battery tester also includes two response sensing terminals, SNS_Hi and SNS_Lo, used to detect the response signals of the positive and negative electrodes of the battery under test, respectively. For example, it detects the AC potentials of the two electrodes, V_Hi and V_Lo, through DC blocking capacitors C3 and C4, respectively, obtaining the voltage response signal ΔV = V_Hi - V_Lo. The sinusoidal current injected into the two electrodes is Is. According to Ohm's law, the battery impedance Z = ΔV / Is can be calculated. If the phase difference between the AC test current signal and the voltage response signal is... The internal resistance of the battery under test can then be obtained.

[0032] Since the phase difference between the AC current signal Is and the voltage response signal ΔV may interfere with measurement accuracy, a synchronous demodulation circuit can be used to simultaneously demodulate the injected AC test current Is and the measured voltage response signal ΔV to improve accuracy. For example, these two signals can be input to an analog multiplier for synchronous demodulation. In this method, let the injected AC test current signal Is = Acosωt, and the measured voltage response signal... Where A is the maximum amplitude of the AC current signal Is, B is the maximum amplitude of the voltage response signal ΔV, and ω is the frequency of the injected AC test current signal. Let be the phase difference between the AC test current signal Is and the voltage response signal ΔV. Then, after synchronous demodulation, the resulting signal is:

[0033] Where k is the amplification factor of the analog multiplier. After low-pass filtering to remove the AC components, we get:

[0034]

[0035] Due to the internal resistance of the battery Substituting equation 2 above into the equation, we get:

[0036] R = 2u / (kA) 2 (Equation 3);

[0037] Given the parameters k and A in Equation 3, the resistance of the battery under test can be calculated by measuring and processing the signal u, thus eliminating the phase difference of the AC signal. Interference. The above calculation process can be completed by the microcontroller unit inside the battery tester.

[0038] In such Figure 2In the shown battery tester, a blocking capacitor C1 is usually provided between the response sense terminal SNS_Hi and the test current source Is to protect the test current source. However, if the voltage of the battery under test is relatively high, for example, 400V or 600V, a very large transient current will be injected into the blocking capacitor C1 once the test probe contacts the positive and negative terminals of the battery under test, which can cause an arc discharge. The arc discharge is harmful to the battery under test, the test probe, and the battery tester.

[0039] The present application provides a battery tester with an arc suppression circuit, which can effectively suppress the arc discharge. Figure 3 A structural schematic diagram of a battery tester with an arc suppression circuit according to some embodiments of the present application is shown. As shown in Figure 3 The battery tester includes a test signal circuit, a response sense circuit 200, and an arc suppression circuit 300.

[0040] The test signal circuit includes a test current source 110, a first test signal terminal SRC_Hi, and a second test signal terminal SRC_Lo. The test current source 110 is configured to generate an alternating test current Is, and the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo are configured to be coupled to the positive (+) and negative (-) terminals of the battery under test 400, respectively, and to apply the test current Is to the battery under test 400 during the test of the battery under test 400. In addition, the test signal circuit further includes a first capacitor C1 coupled between the test current source 110 and the first test signal terminal SRC_Hi, which is configured to isolate the direct voltage generated by the battery under test 400 from the test current source 110 to avoid damaging the test current source 110.

[0041] The response sense circuit 200 includes a first response sense terminal SNS_Hi, a second response sense terminal SNS_Lo, and an impedance measurement circuit 210. The first response sense terminal SNS_Hi and the second response sense terminal SNS_Lo are configured to be coupled to the positive and negative terminals of the battery under test 400, respectively, and to receive a response signal excited by the test current Is in the battery under test 400 during the test of the battery under test 400. The impedance measurement circuit 210 can calculate the internal impedance of the battery under test 400 based on the response signal received by the first response sense terminal SNS_Hi and the second response sense terminal SNS_Lo and the test current Is.

[0042] The arc suppression circuit 300 includes a first resistor R1, a control switch S1, and a control circuit 310. The first resistor R1 is coupled in parallel with the control switch S1, and the parallel-coupled first resistor R1 and control switch S1 are coupled between the test current source 110 and the first test signal terminal SNS_Hi, and are coupled in series with the first capacitor C1. In some embodiments, as shown inFigure 3 In some embodiments, the first resistor R1 coupled in parallel with the control switch S1 is coupled between the first test signal terminal SRC_Hi and the first capacitor C1. In other embodiments, the first resistor R1 coupled in parallel with the control switch S1 can also be coupled between the first capacitor C1 and the test current source 110. In some embodiments, the first resistor R1 has a large resistance value, for example, 100 kΩ; the first capacitor C1 can have a capacitance value of 2 uF; and the control switch S1 can be a non-latching type relay having a small resistance value when closed. The time constant τ = 100 kΩ*2 uF = 0.2 s is determined by the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1. It should be noted that the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 given above are only for example, and other values can be selected as needed without departing from the spirit and scope of the present application.

[0043] The control circuit 310 is coupled with the control switch S1 and can control the opening and closing of the control switch S1. For example, the control circuit 310 can be configured to control the control switch S1 to remain open for a predetermined period of time when the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo of the battery tester are connected to the battery under test 400, so that the first resistor R1 with a large resistance value is connected in the current loop from the first test signal terminal SRC_Hi to the first capacitor C1 and the current source 110, which can effectively reduce the size of the transient current injected into the first capacitor C1, thereby avoiding arc discharge and damage to the battery under test 400 and the test current source 110. As the voltage across the first capacitor C1 rises until it approaches the voltage of the battery under test 400, the control circuit 310 can control the control switch S1 to close to bypass the first resistor R1, so that the test current Is generated by the test current source 110 can be substantially entirely applied to the battery under test 400 through the first capacitor C1, the closed control switch S1, and the first test signal terminal SRC_Hi. Thereafter, the battery tester can perform measurements on the battery under test.

[0044] In particular, the control circuit 310 can detect information indicative of an access impedance value between the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo, and can also receive from the impedance measuring circuit 210 a signal indicative of a measured impedance value between the first response sensing terminal SNS_Hi and the second response sensing terminal SNS_Lo; and control the battery tester to operate in a measuring mode or a non-measuring mode according to the access impedance value and the measured impedance value. In the non-measuring mode, for example, within a predetermined time period after the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo are connected to the battery under test 400, the control circuit 310 controls the control switch S1 to be open so that the test current Is flows through the battery under test 400 via the first resistor Rl. In the measuring mode, for example, after the predetermined time period has elapsed after the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo are connected to the battery under test 400, the control circuit 310 controls the control switch S1 to be closed so that the test current Is flows through the battery under test 400 via the closed control switch S1, and almost none or very little of the test current Is flows through the first resistor Rl.

[0045] Next, with reference to Figure 4 , according to some embodiments of the present application, further specific embodiments of the battery tester of Figure 3 are shown.

[0046] In some embodiments, for example, as shown in Figure 4In the illustrated embodiment, impedance measurement circuit 210 includes third and fourth capacitors C3 and C4, an instrumentation amplifier INA, a signal conditioning circuit, a synchronous demodulation circuit, and a low-pass filter. During a measurement of a battery under test, instrumentation amplifier INA receives a response signal collected by first and second sense terminals SNS_Hi and SNS_Lo at the positive and negative terminals of the battery under test through third and fourth capacitors C3 and C4, which are able to isolate a DC voltage signal across the battery under test, so that instrumentation amplifier INA is able to obtain an AC potential difference across the battery under test. The AC potential difference amplified by instrumentation amplifier INA is transmitted to the signal conditioning circuit for band-pass filtering, amplification, or attenuation as needed, and then to the synchronous demodulation circuit, which interacts with (e.g., multiplies) the test current obtained from test current source 110 to remove a phase difference between the AC potential difference and the test current, and finally through the low-pass filter to filter out high-frequency signals and retain a DC voltage signal proportional to the internal impedance value of the battery. In some embodiments, the battery tester further includes an analog-to-digital converter, a microcontroller unit, a display, and a memory. The analog-to-digital converter is used to convert the DC voltage signal into a digital signal and transmit it to the microcontroller unit for calculating the internal impedance value of the battery under test. The display is used to display the internal impedance value calculated by the microcontroller unit to the user, and the memory can store the internal impedance value inside the battery tester. For more details about the impedance measurement circuit, please refer to the description of the illustrated embodiment of the impedance measurement circuit in conjunction with Figure 2 the description of the illustrated embodiment.

[0047] In Figure 4 In the illustrated embodiment, test current source 110 is a variable current source that can output different sizes of AC test currents, such as different sizes of sinusoidal wave currents. For example, control circuit 310 is coupled with test current source 110, which can control test current source 110 to output a first test current I1 in a non-measurement mode, and control test current source 110 to output a second test current I2 in a measurement mode, where the current value of second test current I2 is greater than the current value of first test current I1. In some embodiments, first test current I1 and second test current I2 can be represented as:

[0048] I1 = A1 cos 2πft (Equation 4);

[0049] I2 = A2 cos 2πft (Equation 5);

[0050] where A1 is the current peak value of first test current I1, A2 is the current peak value of second test current I2, and f is the frequency of first test current I1 and second test current I2.

[0051] In some embodiments, the peak value of the first test current I1 is 0.1mA, which can be configured to match the first resistor R1 such that when the first test current I1 flows through the first resistor R1 (e.g., 100kΩ), it generates an appropriate voltage drop without distorting the output voltage of the test current source 110. Unlike the first test current I1, the second test current I2 is used in the measurement mode and can have a larger current value. Corresponding to different ranges of the battery tester, the second test current I2 can have different peak values. For example, for ranges with battery internal resistance of 3mΩ and 30mΩ, the peak value of the second test current I2 can be 100mA; for ranges with battery internal resistance of 30mΩ and 300mΩ, the peak value of the second test current I2 can be 20mA; and for ranges with battery internal resistance of 300mΩ and 3000mΩ, the peak value of the second test current I2 can be 2mA. In some embodiments, the first test current I1 and the second test current I2 are sinusoidal alternating currents with a frequency of 1000Hz. It should be noted that the peak value, waveform, and frequency of the test current given above are for illustrative purposes only. Those skilled in the art can select other values ​​as needed without departing from the purpose and scope of this application.

[0052] In some embodiments, such as Figure 4 As shown, the test signal circuit also includes a fuse 120, which is connected in series with the first capacitor C1 between the test current source 110 and the first test signal terminal SRC_Hi. For example, the fuse 120 can be configured as follows: Figure 4 The fuse 120 is coupled between the first test signal terminal SRC_Hi and the first resistor R1. Alternatively, the fuse 120 can also be coupled between the first resistor R1 and the first capacitor C1, or between the first capacitor C1 and the test current source 110. The fuse 120 can blow when the current flowing through the first test signal terminal SRC_Hi and the AC current source 110 exceeds a set threshold, thus providing overcurrent protection for the AC current source 110.

[0053] The control circuit 310 is configured to control the battery tester to operate in measurement mode or non-measurement mode. To determine whether the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo are connected to the battery under test, the control circuit 310 compares the connection impedance value Rcnt between the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo with the first reference impedance value Rref1. When the connection impedance value Rcnt is greater than the first reference impedance value Rref1, it indicates that the connection impedance value Rcnt between the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo is large, and the battery tester is not yet connected to the battery under test. In this case, the control circuit 310 generates a non-measurement mode start signal to control the battery tester to operate in non-measurement mode.

[0054] In some embodiments, in addition to comparing the access impedance value Rcnt between the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo with the first reference impedance value Rrefl, the control circuit 310 receives a signal representing the measured impedance value Rms between the first response sense terminal SNS_Hi and the second response sense terminal SNS_Lo from the impedance measurement circuit 210 and compares the measured impedance value Rms with a second reference impedance value Rref2; when the access impedance value Rcnt is less than the first reference impedance value Rrefl and the measured impedance value Rms is less than the second reference impedance value Rref2, indicating that the battery tester is likely to have been connected to the battery under test, the control circuit 310 generates the measurement mode enable signal to control the battery tester to operate in the measurement mode. In some embodiments, the first reference impedance value Rrefl is greater than the second reference impedance value Rref2.

[0055] In the following embodiments, for the sake of clarity, the non-measurement mode enable signal is represented by a logic low level "0" and the measurement mode enable signal is represented by a logic high level "1". It can be appreciated that one skilled in the art can also represent the non-measurement mode enable signal and the measurement mode enable signal by different logic levels by making corresponding modifications to the circuit.

[0056] Reference Figure 4 which shows an implementation of the control circuit 310 according to some embodiments. As shown, the control circuit 310 includes a first comparator COMP1, a second comparator COMP2 and a mode switching circuit 314.

[0057] The first input terminal, e.g. the non-inverting input terminal (+), of the first comparator COMP1 is configured to receive information representing the first reference impedance value Rrefl; the second input terminal, e.g. the inverting input terminal (-), of the first comparator COMP1 is coupled to the test current source 110 for detecting information representing the access impedance value Rcnt; the output terminal of the first comparator COMP1 outputs a first comparison result RS1 regarding the first reference impedance value Rrefl and the access impedance value Rcnt. As Figure 4As shown, the control circuit 310 further comprises a conversion circuit 312 coupled between the output of the test current source 110 and the second input of the first comparator COMP1 for converting the AC voltage signal at the output of the test current source 110 into information of the access impedance value Rcnt. For example, the conversion circuit 312 can be a peak detector, a RMS converter or a rectifying circuit. It is noted that in the present embodiment, the comparison of the first reference impedance value Rrefl and the access impedance value Rcnt by the first comparator COMP1 is realized by comparing the value of the first reference voltage Vrefl representing the first reference impedance value Rrefl and the voltage value representing the access impedance value Rcnt.

[0058] The first input, e.g. the non-inverting input (+), of the second comparator COMP2 is configured to receive information representing the second reference impedance value Rref2, and the second input, e.g. the inverting input (-), of the second comparator COMP2 is coupled to the impedance measurement circuit 210 for receiving information representing the measured impedance value Rms, and the output of the second comparator COMP2 outputs a second comparison result RS2 regarding the second reference impedance value Rref2 and the measured impedance value Rms. As shown, the second input of the second comparator COMP2 is connected to the output of the low-pass filter circuit in the impedance measurement circuit 210 for receiving information representing the measured impedance value Rms. In the present embodiment, the comparison of the second reference impedance value Rref2 and the measured impedance value Rms by the second comparator COMP2 is realized by comparing the value of the second reference voltage Vref2 representing the second reference impedance value Rref2 and the voltage value representing the measured impedance value Rms. Figure 4

[0059] It is noted that in order to realize the circuit functions, the first reference voltage Vrefl and the second reference voltage Vref2 in the above satisfy the following equations 6 and 7, respectively:

[0060]

[0061] Vref2 = A1 x Rref2 x K2 (Equation 7);

[0062] wherein A1 is the peak current of the first test current II, A2 is the peak current of the second test current I2, K1 is a coefficient determined by the conversion circuit 312, and K2 is a coefficient determined by the instrumentation amplifier INA, the signal conditioning circuit and the synchronous demodulation circuit. In addition, Rrefl, Rref2, Vrefl and Vref2 further satisfy the following equations 8 to 10:

[0063] ​Rmax < Rref2 < Rrefl (Equation 8);

[0064]

[0065]

[0066] where Rmax is the maximum value of the battery resistance that the battery tester can measure. For example, in one embodiment, Rmax has a value of 3.3 Ω. The second reference resistance Rref2 being less than the first reference resistance Rrefl ensures that the resistance hysteresis is effectively formed between the battery tester entering the measurement mode and exiting the measurement mode. In order to ensure that the maximum resistance value set by the battery tester can be effectively measured, the second reference resistance Rref2 must be greater than Rmax.

[0067] The mode switching circuit 314 is configured to receive the first comparison result RS1 and the second comparison result RS2, and generate a measurement mode enable signal or a non-measurement mode enable signal indicating that the battery tester is operating in the measurement mode or the non-measurement mode based on the first comparison result RS1 and the second comparison result RS2. For example, the mode switching circuit 314 can generate the non-measurement mode enable signal indicating that the battery tester is operating in the non-measurement mode when the first comparison result RS1 indicates that the access impedance value Rcnt is greater than the first reference impedance value Rrefl, and can generate the measurement mode enable signal indicating that the battery tester is operating in the measurement mode when the first comparison result RS1 indicates that the access impedance value Rcnt is less than the first reference impedance value Rrefl and the second comparison result RS2 indicates that the measurement impedance value Rms is less than the second reference impedance value Rref2. The control circuit 310 controls the control switch S1 to be closed or opened and controls the test current source 110 to output the second test current I2 or the first test current I1 based on the measurement mode enable signal or the non-measurement mode enable signal generated by the mode switching circuit 314. In some embodiments, the control circuit 310 includes a switch driving circuit 316 coupled between the mode switching circuit 314 and the control switch S1, and the control circuit 310 controls the control switch S1 to be opened or closed based on the measurement mode enable signal or the non-measurement mode enable signal by the switch driving circuit 316.

[0068] Reference Figure 5 FIG. 4 shows one embodiment of the mode switching circuit 314 according to embodiments of the present application. Figure 5The mode switching circuit 314 shown includes an OR gate and an AND gate. The first input of the OR gate is coupled to the output of the second comparator COMP2 to receive the second comparison result RS2, and the second input of the OR gate is configured to receive the feedback measurement mode enable signal or the non-measurement mode enable signal (labeled as RS3 in the figure); the first input of the AND gate is coupled to the output of the first comparator COMP1 to receive the first comparison result RS1, and the second input of the AND gate is coupled to the output of the OR gate, and the output of the AND gate outputs the measurement mode enable signal or the non-measurement mode enable signal. As can be seen, Figure 5 The mode switching circuit 314 shown generates the new measurement mode enable signal or the non-measurement mode enable signal based on the first comparison result RS1, the second comparison result RS2, and the feedback measurement mode enable signal or the non-measurement mode enable signal.

[0069] It should be noted that, Figure 5 The mode switching circuit 314 shown is for illustration only, and one skilled in the art can also use other circuits to implement the function of the mode switching circuit 314. For example, any circuit that can implement the truth table logic of Table 1 below can be used as the mode switching circuit 314.

[0070] Table 1 Truth table of mode switching circuit

[0071] Input 1 (RS1) Input 2 (RS2) Input 3 (RS3) Output 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 1 1 1

[0072] With continued reference to Figure 4 In some embodiments, the control circuit 310 further includes a delay circuit 320 configured to receive the measurement mode enable signal or the non-measurement mode enable signal and delay the measurement mode enable signal or the non-measurement mode enable signal to generate a delayed measurement mode enable signal or a delayed non-measurement mode enable signal. At this time, the control circuit 310 is configured to control the battery tester to operate in the measurement mode based on the delayed measurement mode enable signal, or to control the battery tester to operate in the non-measurement mode based on the delayed non-measurement mode enable signal. Further, the mode switching circuit 314 also receives the delayed measurement mode enable signal or the delayed non-measurement mode enable signal as the feedback measurement mode enable signal or the non-measurement mode enable signal RS3 described above, so as to generate the measurement mode enable signal or the non-measurement mode enable signal indicating the battery tester to operate in the measurement mode or the non-measurement mode based on the first comparison result RS1, the second comparison result RS2, and the delayed measurement mode enable signal or the delayed non-measurement mode enable signal RS3.

[0073] For the measurement mode activation signal, the delay circuit 320 needs to delay it for a predetermined time period ΔT to generate the delayed measurement mode activation signal. This predetermined time period ΔT is greater than or equal to the time constant τ = R1 * C1 determined by the capacitance of the first capacitor C1 and the resistance of the first resistor R1, for example, it can be 10τ. Referring to the specific embodiment above, when the resistance of the first resistor R1 is 100kΩ and the capacitance of the first capacitor C1 is 2uF, this predetermined time period can be ΔT = 10τ = 10 * 0.2s = 2s.

[0074] like Figure 4 As shown, the delay circuit 320 includes a second resistor R2, a second capacitor C2, and a third comparator COMP3. The first terminal of the second resistor R2 receives a measurement mode activation signal (“1”), and its second terminal is coupled to the first terminal of the second capacitor C2; the second terminal of the second capacitor C2 is coupled to ground. The first input terminal of the third comparator COMP3, for example, a non-inverting input terminal, is coupled to the second terminal of the second resistor R2 and the first terminal of the second capacitor C2. The second input terminal of the third comparator COMP3, for example, an inverting input terminal, receives a third reference voltage Vref3. The output terminal of the third comparator COMP3 outputs the delayed measurement mode activation signal. It can be seen that the predetermined delay time of the delay circuit 320 is equal to the time required for the measurement mode activation signal to charge the second capacitor C2 via the second resistor R2 until the voltage at the first terminal of the second capacitor C2 is at least equal to the third reference voltage Vref3. In one embodiment, the resistance of the second resistor R2 is 150kΩ, the capacitance of the second capacitor C2 is 10uF, and the third reference voltage Vref3 is 2.5V. Of course, the above values ​​are merely examples, and those skilled in the art can choose other values ​​as needed without departing from the spirit and scope of this application.

[0075] In some embodiments, the delay circuit 320 further includes a diode D1, the cathode of which is coupled to the first terminal of the second resistor R2, and the anode of which is coupled to the second terminal of the second resistor R2. When the output of the mode switching circuit switches from "1" to "0", that is, when the first terminal of the second resistor R2 receives a non-measurement mode start signal, the diode D1 provides a fast discharge path for the second capacitor C2, causing the voltage at the first terminal of the second capacitor C2 to quickly discharge below the third reference voltage Vref3, thereby causing the output of the third comparator COMP3 to quickly switch from "1" to "0". It can be seen that, due to the presence of the diode D1, the delay time of the delay circuit 320 for the non-measurement mode start signal is much smaller than the predetermined time period ΔT for the measurement mode start signal, and can be almost ignored.

[0076] In some embodiments, the response sensing circuit 200 further comprises a third resistor R3 and a fourth resistor R4, wherein the third resistor R3 is coupled between the first test signal terminal SRC_Hi and the first response sensing terminal SNS_Hi, and the fourth resistor R4 is coupled between the second test signal terminal SRC_Lo and the second response sensing terminal SNS_Lo.

[0077] In the non-measurement mode, since the test current source 110 outputs a small first test current I1, the first reference voltage Vref1 corresponds to a third reference impedance value Rref3, which is expressed as the following equation 11.

[0078]

[0079] At this time, the first reference voltage Vref1, the third resistor R3 and the fourth resistor R4 also need to satisfy the following equations 12 and 13:

[0080]

[0081]

[0082] wherein A1 is the current peak value of the first test current I1, and K1 is a coefficient determined by the conversion circuit 312.

[0083] The third resistor R3 and the fourth resistor R4 can avoid various test faults that may occur when there is a contact fault. For example, the contact fault includes that only the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo are in contact with the battery electrode to be measured, or only the first test signal terminal SRC_Hi, the second test signal terminal SRC_Lo and the second response sensing terminal SNS_Lo are in contact with the battery electrode to be measured.

[0084] For example, when the battery tester does not include the third resistor R3 and the fourth resistor R4, if the access impedance value between the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo is between the first reference impedance value Rrefl and the third reference impedance value Rref3, the first comparator COMP1 in the non-measuring mode will output a high level. If the aforementioned contact failure occurs, the response signal of the battery under test in the non-measuring mode cannot be coupled to the instrument amplifier INA, the direct current voltage output by the low-pass filter in the impedance measuring circuit 210 will be less than the second reference voltage Vref2 corresponding to the second reference impedance value Rref2, and the second comparator COMP2 will output a high level. Since the first comparator COMP1 and the second comparator COMP2 in the non-measuring mode both output a high level, after the predetermined time period ΔT delayed by the delay circuit 320, the battery tester will enter the measuring mode. In the measuring mode, the test current source outputs the second test current I2, and the output voltage of the conversion circuit 312 will be greater than the first reference voltage Vrefl corresponding to the first reference impedance value Rrefl, so that the output of the first comparator COMP1 will change to a low level at the same time when the battery tester enters the measuring mode, thereby causing the battery tester to exit the measuring mode (refer to the truth table shown in Table 1) and enter the non-measuring mode. At this time, the battery tester will have a test failure and enter a cycle state, i.e., after staying in the non-measuring mode for the predetermined time period ΔT, it will enter the measuring mode and immediately exit the measuring mode, and then wait for the predetermined time period ΔT again before entering the measuring mode and immediately exiting the measuring mode again.

[0085] When the battery tester includes the third resistor R3 and the fourth resistor R4, if the access impedance value between the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo is between the first reference impedance value Rrefl and the third reference impedance value Rref3, even if the aforementioned contact failure occurs, the response signal of the positive electrode of the battery under test will be coupled to the instrument amplifier INA through the third resistor R3 and the third capacitor C3, and the response signal of the negative electrode of the battery under test will be coupled to the instrument amplifier INA through the fourth resistor R4 and the fourth capacitor C4, and the direct current voltage output by the low-pass filter in the impedance measuring circuit 210 will be greater than the second reference voltage Vref2 corresponding to the second reference impedance value Rref2, and the second comparator COMP2 will output a low level. In the non-measuring mode, the output of the second comparator COMP2 is a low level, and the battery tester will not be triggered to enter the measuring mode (refer to the truth table shown in Table 1), and the aforementioned cycle state will not occur without the third resistor R3 and the fourth resistor R4.

[0086] For another example, when the battery tester does not include the third resistor R3 and the fourth resistor R4, if the access impedance value between the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo is less than the first reference impedance value Rrefl, the first comparator COMP1 in the non-measuring mode will output a high level. If the aforementioned contact failure occurs, the response signal of the battery under test in the non-measuring mode cannot be coupled to the instrumentation amplifier INA, the direct current voltage outputted by the low pass filter in the impedance measuring circuit 210 will be less than the second reference voltage Vref2 corresponding to the second reference impedance value Rref2, and the second comparator COMP2 will output a high level. Since the first comparator COMP1 and the second comparator COMP2 in the non-measuring mode both output a high level, after the predetermined time period ΔT delayed by the delay circuit 320, the battery tester will enter the measuring mode. Because of the contact failure between the first response sensing terminal SNS_Hi and the second response sensing terminal SNS_Lo and the positive and negative terminals of the battery under test, the response signal generated by the second test current I2 outputted by the test current source flowing through the battery under test will not be coupled to the instrumentation amplifier INA through the third capacitor C3 and the fourth capacitor C4, the direct current voltage outputted by the low pass filter in the impedance measuring circuit 210 will be very small, and thus the resistance reading displayed by the battery tester will be incorrect, resulting in a test failure.

[0087] When the battery tester includes the third resistor R3 and the fourth resistor R4, the above-mentioned test failure will not occur. For example, if the access impedance value between the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo is between the second reference impedance value Rref2 and the first reference impedance value Rrefl, even if there is a contact failure between the first response sensing terminal SNS_Hi and the second response sensing terminal SNS_Lo and the positive and negative terminals of the battery under test, the response signal of the positive terminal of the battery under test will be coupled to the instrumentation amplifier INA through the third resistor R3 and the third capacitor C3, and the response signal of the negative terminal of the battery under test will be coupled to the instrumentation amplifier INA through the fourth resistor R4 and the fourth capacitor C4, the DC voltage output by the low-pass filter in the impedance measurement circuit 210 will be greater than the second reference voltage Vref2 corresponding to the second reference impedance value Rref2, and the second comparator COMP2 will output a low level. The battery tester will not enter the measurement mode. For another example, if the access impedance value between the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo is less than the second reference impedance value Rref2, both the first comparator COMP1 and the second comparator COMP2 in the non-measurement mode will output a high level, and after the predetermined time period ΔT delayed by the delay circuit 320, the battery tester will enter the measurement mode. At this time, even if there is a contact failure between the first response sensing terminal SNS_Hi and the second response sensing terminal SNS_Lo and the positive and negative terminals of the battery under test, the response signal of the positive terminal of the battery under test will be coupled to the instrumentation amplifier INA through the third resistor R3 and the third capacitor C3, and the response signal of the negative terminal of the battery under test will be coupled to the instrumentation amplifier INA through the fourth resistor R4 and the fourth capacitor C4, the DC voltage output by the low-pass filter in the impedance measurement circuit 210 is proportional to the access impedance value between the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo, and the resistance reading displayed by the battery tester is also the value of the correct access resistance, and the above-mentioned test failure of the resistance reading displayed by the battery tester without the third resistor R3 and the fourth resistor R4 will not occur.

[0088] The working process of the battery tester of the present application will be described below. Figure 4 and Figure 5 The working process of the battery tester of the present application will be described below.

[0089] First, before the two test pens of the battery tester (including the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo, and the first response sensing terminal SNS_Hi and the second response sensing terminal SNS_Lo) are connected to the positive and negative electrodes of the battery 400 to be tested, the output of the test current source 110 will be distorted because the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo are floating. Specifically, the voltage of the output of the test current source 110 is a square wave, and the peak value of the square wave is close to the power rail. At this time, the voltage output by the conversion circuit 312 will be greater than the first reference voltage Vref1 representing the first reference impedance value Rref1, and the output of the first comparator COMP1 is set to "0". In turn, the output of the AND gate and the output of the third comparator COMP3 are also set to "0", and the battery tester works in the non-measuring mode. In the non-measuring mode, the test current source 110 outputs the first test current I1, and the switch driving circuit 316 controls the control switch S1 to be open. Accordingly, the output "0" of the AND gate and the output "0" of the third comparator COMP3 are transmitted to the microcontroller, so that the microcontroller can control the display to display "OL" (overload) to the user, prompting the user that the battery tester is overloaded and in the non-measuring mode. This non-measuring mode will remain until the test pens of the battery tester are in contact with the electrodes of the battery to be tested.

[0090] After the two test probes of the battery tester are connected to the positive and negative terminals of the battery 400 under test, the battery 400 under test is charged through the first resistor Rl to the first capacitor Cl. Since the resistance of the first resistor Rl is large, the charging current is low and no arc discharge phenomenon occurs between the first test signal terminal SRC_Hi and the electrode of the battery 400 under test. Usually, after a time constant determined by the capacitance of the first capacitor Cl and the resistance of the first resistor Rl is 2.2 times, the voltage at the first terminal of the first capacitor Cl is charged to about the voltage of the battery 400 under test. For example, when Rl = 100 kΩ and Cl = 2 μF, after 2.2τ = 2.2Rl*Cl = 0.44 s, the voltage at the first terminal of the first capacitor Cl is charged to about the voltage of the battery 400 under test. At the same time, the control circuit 310 detects the information indicating the impedance value between the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo, and receives the information indicating the measured impedance value between the first response sensing terminal SNS_Hi and the second response sensing terminal SNS_Lo from the impedance measuring circuit 210. Specifically, the first test current I1 output by the test current source 110 flows through the first capacitor Cl, the first resistor Rl, the fuse 120, the positive terminal of the battery 400 under test, the battery body, and the negative terminal, and then flows back to the ground terminal AGND of the battery tester. At this time, the output voltage of the test current source 110 is not distorted. If the internal impedance value of the battery 400 under test is less than the first reference impedance value Rrefl, the output voltage of the conversion circuit 312 will be less than the first reference voltage Vrefl indicating the first reference impedance value Rrefl, and the output of the first comparator COMP1 will be set to "1". In addition, the instrument amplifier INA in the impedance measuring circuit 210 receives the response signal collected at the positive and negative terminals of the battery under test through the third capacitor C3 and the fourth capacitor C4, and generates a direct current voltage value related to the internal impedance value of the battery 400 under test after passing through the signal conditioning circuit, the synchronous demodulation circuit, and the low pass filter. If the internal impedance value of the battery 400 under test is less than the second reference impedance value Rref2, the voltage value output by the low pass filter will be less than the second reference voltage Vref2 indicating the second reference impedance value Rref2, and the output of the second comparator COMP2 will also be set to "1".

[0091] It can be seen that only when the internal impedance value of the battery 400 is less than the first reference impedance value Rrefl and less than the second reference impedance value Rref2, that is, when the output voltage of the conversion circuit 312 is less than the first reference voltage Vrefl representing the first reference impedance value Rrefl, and the voltage value output by the low-pass filter is less than the second reference voltage Vref2 representing the second reference impedance value Rref2, the output of the first comparator COMP1 will be set to "1" and the output of the OR gate will also be set to "1", so that the output of the AND gate is set to "1", that is, the "measurement mode start signal" is generated. The output of the AND gate charges the second capacitor C2 in the delay circuit 320, and after a predetermined time period ΔT, the voltage at the first end of the second capacitor C2 is at least equal to the third reference voltage Vref3, and the output of the third comparator COMP3 will be switched from "0" to "1", so that the battery tester works in the measurement mode. In the measurement mode, the output second test current I2 of the test current source 110, and the switch driving circuit 316 controls the control switch S1 to close. During the above-mentioned predetermined time period ΔT, the output "1" of the AND gate and the output "0" of the third comparator COMP3 are transmitted to the microcontroller, and the microcontroller can control the display to display "--" to the user, prompting the user that the battery tester is in the state transition process. After the above-mentioned predetermined time period ΔT, the output "1" of the AND gate and the output "1" of the third comparator COMP3 are transmitted to the microcontroller, and the microcontroller can control the display to display the measured internal resistance value of the battery 400 calculated based on the DC voltage output by the low-pass filter to the user, indicating that the battery tester works in the measurement mode. This measurement mode will remain until the test pen of the battery tester is disconnected from the electrode of the battery to be tested.

[0092] Continuing, after the two test probes of the battery tester are disconnected from the positive and negative terminals of the battery 400 under test, the output of the test current source 110 will be distorted because the first test signal terminal SRC_Hi and the second test signal terminal SRC_Lo are floating. Specifically, the voltage output by the test current source 110 is a square wave with a peak value close to the supply rail. At this time, the voltage output by the conversion circuit 312 will be greater than the first reference voltage Vrefl representing the first reference impedance value Rrefl, the output of the first comparator COMP1 is set to "0", and the output of the AND gate is also set to "0". Next, the second capacitor C2 will discharge rapidly through the diode Dl, and the output of the third comparator COMP3 will also quickly switch to "0", indicating that the battery tester is exiting the measurement mode and entering the non-measurement mode. In the non-measurement mode, the test current source 110 is controlled to output the first test current II, and the switch drive circuit 316 controls the control switch SI to open. Accordingly, the output "0" of the AND gate and the output "0" of the third comparator COMP3 are transmitted to the microcontroller, so that the microcontroller controls the display to display "OL" to the user, prompting the user that the battery tester is overloaded and in the non-measurement mode.

[0093] Those skilled in the art can understand and implement other changes to the disclosed embodiments by studying the specification, the disclosed content, and the accompanying drawings and the appended claims. In the claims, the word "comprising" does not exclude other elements and steps, and the word "a" or "one" does not exclude a plurality. In the practical application of the present application, a part can perform the functions of multiple technical features referred to in the claims. Any reference signs in the claims should not be understood as limiting the scope.

Claims

1. A battery tester, comprising: The battery tester comprises: a test signal circuit comprising: a test current source for generating an alternating test current; a first test signal terminal and a second test signal terminal for being coupled to a positive electrode and a negative electrode of a battery under test respectively during a test of the battery under test, and for applying the test current to the battery under test; and a first capacitor coupled between the test current source and the first test signal terminal; a response sensing circuit comprising: a first response sensing terminal and a second response sensing terminal for being coupled to the positive electrode and the negative electrode of the battery under test respectively during the test of the battery under test, and for receiving a response signal excited by the test current within the battery under test; and an impedance measurement circuit for measuring an internal impedance of the battery under test based on the response signal and the test current; and an arc suppression circuit comprising: a first resistor and a control switch coupled in parallel to each other, the parallel-coupled first resistor and the control switch being coupled between the test current source and the first test signal terminal, and being coupled in series with the first capacitor; and a control circuit configured to: detect information indicative of an access impedance value between the first test signal terminal and the second test signal terminal, and receive information of a measured impedance value between the first response sensing terminal and the second response sensing terminal from the impedance measurement circuit; and control the battery tester to operate in a measurement mode or a non-measurement mode according to the access impedance value and the measured impedance value, which comprises: comparing the access impedance value with a first reference impedance value, generating a non-measurement mode start signal to control the battery tester to operate in the non-measurement mode when the access impedance value is greater than the first reference impedance value; comparing the measured impedance value with a second reference impedance value, generating a measurement mode start signal to control the battery tester to operate in the measurement mode when the access impedance value is less than the first reference impedance value and the measured impedance value is less than the second reference impedance value, the first reference impedance value being greater than the second reference impedance value; wherein: in the non-measurement mode, the control circuit controls the control switch to be open so that the test current flows through the battery under test via the first resistor; and in the measurement mode, the control circuit controls the control switch to be closed so that the test current flows through the battery under test via the closed control switch.

2. The battery tester of claim 1 wherein, The test current source is a variable current source, and the control circuit is further configured to: control the test current source to output a first test current in the non-measurement mode; and control the test current source to output a second test current in the measurement mode, the second test current having a current value greater than the first test current.

3. The battery tester of claim 1 wherein, The control circuit further comprises: a first comparator having a first input configured to receive the first reference impedance value and a second input coupled to the test current source to detect information indicative of the access impedance value, the first comparator having an output configured to output a first comparison result regarding the first reference impedance value and the access impedance value; a second comparator having a first input configured to receive a second reference impedance value and a second input coupled to the impedance measurement circuit to receive information indicative of the measured impedance value, the second comparator having an output configured to output a second comparison result regarding the second reference impedance value and the measured impedance value; and a mode switching circuit configured to receive the first comparison result and the second comparison result and generate the measurement mode enable signal or the non-measurement mode enable signal indicating that the battery tester is to operate in the measurement mode or the non-measurement mode based on the first comparison result and the second comparison result.

4. The battery tester of claim 3 wherein, The control circuit further includes: a delay circuit configured to receive the measurement mode enable signal or the non-measurement mode enable signal and delay the measurement mode enable signal or the non-measurement mode enable signal to generate a delayed measurement mode enable signal or a delayed non-measurement mode enable signal, the control circuit configured to control the battery tester to operate in the measurement mode based on the delayed measurement mode enable signal or to control the battery tester to operate in the non-measurement mode based on the delayed non-measurement mode enable signal.

5. The battery tester of claim 4 wherein, The mode switching circuit is further configured to receive the delayed measurement mode enable signal or the delayed non-measurement mode enable signal and generate the measurement mode enable signal or the non-measurement mode enable signal indicating that the battery tester is to operate in the measurement mode or the non-measurement mode based on the first comparison result, the second comparison result, and the delayed measurement mode enable signal or the delayed non-measurement mode enable signal.

6. The battery tester of claim 5 wherein, The mode switching circuit includes: an OR gate having a first input coupled to the output of the second comparator to receive the second comparison result and a second input configured to receive the delayed measurement mode enable signal or the delayed non-measurement mode enable signal; and an AND gate having a first input coupled to the output of the first comparator to receive the first comparison result, a second input coupled to the output of the OR gate, and an output configured to output the measurement mode enable signal or the non-measurement mode enable signal.

7. The battery tester of claim 5 wherein, The control circuit further includes a conversion circuit coupled between the output of the test current source and the second input of the first comparator and configured to convert an AC voltage signal at the output of the test current source to the information indicative of the access impedance value.

8. The battery tester of claim 5 wherein, The control circuit further includes a switch driving circuit coupled between the delay circuit and the control switch for controlling the control switch to open or close according to the delayed measurement mode start signal or the delayed non-measurement mode start signal.

9. The battery tester of claim 4 wherein, The delay circuit delays the measurement mode start signal for a predetermined time period to generate the delayed measurement mode start signal, the predetermined time period being greater than or equal to a time constant determined by a capacitance of the first capacitor and a resistance of the first resistor.

10. The battery tester of claim 9 wherein, The delay circuit includes: a second resistor having a first end for receiving the measurement mode start signal; and a second capacitor having a first end coupled to a second end of the second resistor and a second end coupled to ground; and a third comparator having a first input end coupled to the second end of the second resistor and the first end of the second capacitor, a second input end for receiving a reference voltage, and an output end outputting the delayed measurement mode start signal.

11. The battery tester of claim 10 wherein, The predetermined time period is equal to a time required for charging the second capacitor via the second resistor from the first end of the second capacitor until a voltage of the first end of the second capacitor is at least equal to the reference voltage.

12. The battery tester of claim 10 wherein, The delay circuit further includes: a diode having a negative electrode coupled to the first end of the second resistor and a positive electrode coupled to the second end of the second resistor.

13. The battery tester of claim 1, wherein, The test signal circuit further includes a fuse coupled in series with the first capacitor between the test current source and the first test signal terminal.

14. The battery tester of claim 1, wherein, The response sensing circuit further includes: a third resistor coupled between the first test signal terminal and the first response sensing terminal; and a fourth resistor coupled between the second test signal terminal and the second response sensing terminal.

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