Storage device, recessed channel array transistor and manufacturing method thereof

Abstract

The present disclosure provides a storage device, a recessed channel array transistor and a preparation method thereof, which belongs to the field of storage technology. The recessed channel array transistor includes an active area and a gate structure. The active area is provided with a recessed channel, and the active area includes a well area and a source and drain area; the gate structure includes a gate and a gate insulating layer, the gate and the gate insulating layer are filled in the recessed channel, and the gate insulating layer isolates the active area and the gate; the gate insulating layer includes a first gate insulating layer and a second gate insulating layer, the first gate insulating layer is arranged on the side of the second gate insulating layer close to the notch of the recessed channel, and the second gate insulating layer is arranged on the side of the first gate insulating layer away from the notch of the recessed channel; the dielectric constant of the first gate insulating layer is less than the dielectric constant of the second gate insulating layer. The recessed channel array transistor can improve the uniformity of the threshold voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a storage device, a recessed channel array transistor and a manufacturing method thereof. Background Art

[0002] As the size of devices continues to decrease, recessed channel access transistors (RCAT) can be applied to DRAM (dynamic random access memory). However, as the size of recessed channel array transistors decreases, the curvature effect of the trench channel becomes more obvious, resulting in greater differences in the threshold voltage of the transistor at different locations in the trench channel, which reduces the performance of the recessed channel array transistor.

[0003] The above information disclosed in the Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may include information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0004] The purpose of the present disclosure is to provide a storage device, a recessed channel array transistor and a method for manufacturing the same, so as to improve the uniformity of the threshold voltage of the recessed channel array transistor.

[0005] In order to achieve the above-mentioned invention object, the present disclosure adopts the following technical solutions:

[0006] According to a first aspect of the present disclosure, there is provided a recessed channel array transistor, comprising:

[0007] An active area is provided with a groove channel, and the active area includes a well area and a source and drain area;

[0008] A gate structure, comprising a gate and a gate insulating layer, wherein the gate and the gate insulating layer are filled in the groove channel, and the gate insulating layer isolates the active area and the gate;

[0009] Among them, the gate insulation layer includes a first gate insulation layer and a second gate insulation layer, the first gate insulation layer is arranged on a side of the second gate insulation layer close to the notch of the groove channel, and the second gate insulation layer is arranged on a side of the first gate insulation layer away from the notch of the groove channel; the dielectric constant of the first gate insulation layer is smaller than the dielectric constant of the second gate insulation layer.

[0010] In an exemplary embodiment of the present disclosure, the material of the second gate insulating layer is a high dielectric constant material.

[0011] In an exemplary embodiment of the present disclosure, a thickness of an end of the first gate insulating layer close to the second gate insulating layer is equal to a thickness of an end of the second gate insulating layer close to the first gate insulating layer.

[0012] In an exemplary embodiment of the present disclosure, in a cross section perpendicular to the extension direction of the groove channel, the length of the second gate insulating layer: the length of the gate insulating layer = 0.4 to 0.8.

[0013] In an exemplary embodiment of the present disclosure, the second gate insulating layer is close to a surface of the first gate insulating layer and is lower than a surface of the well region close to the source and drain region.

[0014] In an exemplary embodiment of the present disclosure, the recessed channel array transistor further includes:

[0015] An interlayer dielectric layer covers a surface of the gate electrode close to a notch of the groove channel.

[0016] According to a second aspect of the present disclosure, a storage device is provided, comprising the above-mentioned recessed channel array transistor.

[0017] According to a third aspect of the present disclosure, a method for preparing a recessed channel array transistor is provided, comprising:

[0018] forming an active material layer;

[0019] forming a groove channel in the active material layer;

[0020] forming a second gate insulating layer, wherein the second gate insulating layer covers a side wall surface of the groove channel away from a notch of the groove channel;

[0021] forming a first gate insulating layer, wherein the first gate insulating layer covers the remaining sidewall surfaces of the groove channel; the dielectric constant of the second gate insulating layer is greater than the dielectric constant of the first gate insulating layer;

[0022] forming a gate, wherein the gate is filled in the groove channel and covers the second gate insulating layer and a portion of the first gate insulating layer;

[0023] The active material layer is transformed into an active region by ion implantation.

[0024] In an exemplary embodiment of the present disclosure, the material of the second gate insulating layer is a high dielectric constant material.

[0025] In an exemplary embodiment of the present disclosure, a thickness of an end of the first gate insulating layer close to the second gate insulating layer is equal to a thickness of an end of the second gate insulating layer close to the first gate insulating layer.

[0026] In an exemplary embodiment of the present disclosure, in a cross section perpendicular to the extension direction of the groove channel, the length of the second gate insulating layer: the length of the side wall of the groove channel = 0.4 to 0.8.

[0027] In an exemplary embodiment of the present disclosure, the method for preparing the recessed channel array transistor further includes:

[0028] An interlayer dielectric layer is formed, wherein the interlayer dielectric layer covers a surface of the gate electrode close to the notch of the groove channel.

[0029] In the storage device, recessed channel array transistor and preparation method thereof disclosed in the present invention, affected by the preparation process, the thickness of the second gate insulating layer will be greater than the thickness of the first gate insulating layer; therefore, under the influence of the curvature effect and the uneven thickness of the gate insulating layer, the recessed channel array transistor presents a trend that the threshold voltage at the bottom of the groove channel is greater than the threshold voltage at the sidewall of the groove channel. However, the dielectric constant of the first gate insulating layer is less than the dielectric constant of the second gate insulating layer, which will cause the recessed channel array transistor to present a trend that the threshold voltage at the sidewall of the groove channel is greater than the threshold voltage at the bottom of the groove channel. Therefore, the larger dielectric constant of the second gate insulating layer offsets the influence of the larger thickness of the second gate insulating layer, so that the difference between the threshold voltage of the recessed channel array transistor at the bottom of the groove channel and the threshold voltage at the sidewall of the groove channel is reduced or eliminated, thereby improving the uniformity of the threshold voltage of the recessed channel array transistor at various positions of the groove channel, and improving the performance of the recessed channel array transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0031] Figure 1 is a schematic structural diagram of a recessed channel array transistor according to an embodiment of the present disclosure.

[0032] Figure 2 It is a schematic structural diagram of a recessed channel of a recessed channel array transistor according to an embodiment of the present disclosure.

[0033] Figure 3 It is a schematic flow chart of a method for preparing a recessed channel array transistor according to an embodiment of the present disclosure.

[0034] Figure 4 It is a schematic diagram of the structure of forming an active material layer according to an embodiment of the present disclosure.

[0035] Figure 5 It is a schematic structural diagram of forming a second gate insulating material layer according to an embodiment of the present disclosure.

[0036] Figure 6 It is a schematic structural diagram of forming a protective material layer according to an embodiment of the present disclosure.

[0037] Figure 7 It is a schematic diagram of the structure of an embodiment of the present disclosure in which part of the protective material layer is removed.

[0038] Figure 8 It is a schematic structural diagram of forming a second gate insulating layer according to an embodiment of the present disclosure.

[0039] Fig. 9 It is a schematic structural diagram of forming a first gate insulating layer according to an embodiment of the present disclosure.

[0040] Fig.10 It is a schematic diagram of a structure for forming a gate according to an embodiment of the present disclosure.

[0041] The main component reference numerals in the figure include:

[0042] 100, substrate; 200, active area; 210, groove channel; 211, bottom of groove channel; 212, notch of groove channel; 213, sidewall of groove channel; 220, well area; 300, gate; 410, source layer; 411, sidewall of source layer close to notch of groove channel; 420, drain layer; 421, sidewall of drain layer close to notch of groove channel; 430, source-drain material layer; 431, first source-drain material layer; 432, second source-drain material layer; 500, gate insulating layer; 510, first gate insulating layer; 520, second gate insulating layer; 530, second gate insulating material layer; 540, protective material layer; 600, interlayer dielectric layer. DETAILED DESCRIPTION

[0043] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure.

[0044] In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

[0045] The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, materials, etc. may be adopted. In other cases, known structures, materials or operations are not shown or described in detail to avoid blurring the main technical ideas of the present disclosure.

[0046] The terms "a", "an", "the" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc. The terms "first" and "second" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0047] In the related art, when forming the gate insulating layer of the recessed channel array transistor, the thickness of the gate insulating layer at the bottom of the groove channel (the part away from the groove opening of the groove channel) is greater than the thickness of the gate insulating layer at the top of the groove channel (the part close to the groove opening of the groove channel) due to the influence of the preparation process. Under the influence of the uneven thickness of the gate insulating layer and the curvature effect, the threshold voltage of the recessed channel array transistor at the bottom of the groove channel is greater than the threshold voltage at the top of the groove channel, which seriously affects the performance of the recessed channel array transistor.

[0048] In an embodiment of the present disclosure, a recessed channel array transistor is provided, such as Figure 1 and Figure 2 As shown, the recessed channel array transistor includes an active region 200 and a gate structure; wherein,

[0049] The active area 200 is provided with a groove channel 210; the gate structure includes a gate 300 and a gate insulating layer 500, the gate 300 and the gate insulating layer 500 are filled in the groove channel 210, and the gate insulating layer 500 isolates the active area 200 and the gate 300; the gate insulating layer 500 includes a first gate insulating layer 510 and a second gate insulating layer 520, the first gate insulating layer 510 is arranged on a side of the second gate insulating layer 520 close to the notch 212 of the groove channel, and the second gate insulating layer 520 is arranged on a side of the first gate insulating layer 510 away from the notch 212 of the groove channel; the dielectric constant of the first gate insulating layer 510 is smaller than the dielectric constant of the second gate insulating layer 520.

[0050] In the recessed channel array transistor disclosed in the present invention, the thickness of the second gate insulating layer 520 will be greater than the thickness of the first gate insulating layer 510 due to the influence of the preparation process; therefore, under the influence of the curvature effect and the uneven thickness of the gate insulating layer 500, the recessed channel array transistor presents a trend that the threshold voltage at the bottom 211 of the groove channel is greater than the threshold voltage at the sidewall of the groove channel. However, the dielectric constant of the first gate insulating layer 510 is less than the dielectric constant of the second gate insulating layer 520, which will cause the recessed channel array transistor to present a trend that the threshold voltage at the sidewall of the groove channel is greater than the threshold voltage at the bottom 211 of the groove channel. Therefore, the larger dielectric constant of the second gate insulating layer 520 offsets the influence of the larger thickness of the second gate insulating layer 520, so that the difference between the threshold voltage at the bottom 211 of the groove channel and the threshold voltage at the sidewall of the groove channel of the recessed channel array transistor is reduced or eliminated, thereby improving the uniformity of the threshold voltage of the recessed channel array transistor at various positions of the groove channel 210, and improving the performance of the recessed channel array transistor.

[0051] The components of the recessed channel array transistor provided in the embodiment of the present disclosure are described in detail below with reference to the accompanying drawings:

[0052] like Figure 1 As shown, in one embodiment, the recessed channel array transistor may be disposed on a substrate 100. Figure 1 As shown, the active region 200 is disposed on one side of the substrate 100 .

[0053] Optionally, the active area 200 may include a well area 220 and a source-drain area, wherein the source-drain area includes a source layer 410 and a drain layer 420, wherein the well area 220 is arranged on one side of the substrate 100, and the source layer 410 and the drain layer 420 are arranged on a side of the well area 220 away from the substrate 100; the source layer 410 and the drain layer 420 are arranged on both sides of the groove channel 210.

[0054] The well region 220, the source layer 410, and the drain layer 420 may be doped semiconductors, and the doping types are different. For example, in one embodiment, the well region 220 is a semiconductor layer with P-type doped ions, that is, the well region 220 is a P-type doped semiconductor layer; the source layer 410 and the drain layer 420 are semiconductor layers with N-type heavily doped ions, that is, the source layer 410 and the drain layer 420 are N-type heavily doped regions. In another embodiment, the well region 220 is an N-type doped semiconductor layer; the source layer 410 and the drain layer 420 are P-type heavily doped regions.

[0055] The gate 300 is a conductive material, which can be metal, conductive metal oxide, conductive metal nitride or other conductive materials. In one embodiment, the material of the gate 300 includes one or more of tungsten, molybdenum, silver, aluminum, gold, copper and titanium.

[0056] like Figure 2 As shown, the gate insulating layer 500 may completely cover the surface of the sidewall 213 of the groove channel to completely isolate the active area 200 and the gate 300. That is, the first gate insulating layer 510 and the second gate insulating layer 520 may be complementary in shape.

[0057] The material of the first gate insulating layer 510 may be an organic insulating material or an inorganic insulating material, which is not particularly limited in the present disclosure. In one embodiment, the material of the first gate insulating layer 510 may be silicon oxide.

[0058] The dielectric constant of the second gate insulating layer 520 is greater than the dielectric constant of the first gate insulating layer 510. Optionally, the material of the second gate insulating layer 520 may be a high dielectric constant material. In one embodiment, the dielectric constant of the material of the second gate insulating layer 520 is greater than 4. For example, the material of the second gate insulating layer 520 may include one or more of silicon oxynitride (SiON), silicon nitride (SiN), and hafnium oxide (HfO2).

[0059] In one embodiment, if Figure 1 As shown, the thickness of one end of the first gate insulating layer 510 close to the second gate insulating layer 520 is equal to the thickness of one end of the second gate insulating layer 520 close to the first gate insulating layer 510. In this way, the surface between the first gate insulating layer 510 and the second gate insulating layer 520 is smoothly transitioned, avoiding the gate 300 from having a sudden size change at the junction of the first gate insulating layer 510 and the second gate insulating layer 520, and ensuring the stability of the electric field on the surface of the gate 300.

[0060] like Figure 1 As shown, in the cross section perpendicular to the extension direction of the groove channel 210, the length of the second gate insulating layer 520: the length of the gate insulating layer 500 = 0.4 to 0.8, so that the recessed channel array transistor can fully overcome the influence of the curvature effect of the bottom 211 of the groove channel, and improve the uniformity of the threshold voltage of the recessed channel array transistor at each position of the groove channel 210. It can be understood that, as Figure 2As shown, the groove channel 210 includes three opening ends, namely the first opening end, the second opening end and the third opening end, wherein the second opening end opposite to the bottom 211 of the groove channel is the notch 212 of the groove channel, and the first opening end and the third opening end are both connected to the bottom 211 of the groove channel and the notch 212 of the groove channel. The extension direction of the groove channel 210 is from the first opening end to the third opening end, or from the third opening end to the first opening end. In other words, see Figure 2 , the extending direction of the groove channel 210 is perpendicular to the paper surface. Figure 1 As shown, the recessed channel array transistor may further include an interlayer dielectric layer 600, which covers the surface of the gate 300 near the notch 212 of the recessed channel. Optionally, the surface of the interlayer dielectric layer 600 away from the substrate 100 is flush with the source layer 410 and the drain layer 420. In this way, the interlayer dielectric layer 600 can isolate the source layer 410 and the drain layer 420.

[0061] In one embodiment, if Figure 1 As shown, the second gate insulating layer 520 is far away from the surface of the substrate 100 and is lower than the surface of the well region 220 near the source and drain regions. That is, the second gate insulating layer 520 is far away from the surface of the substrate 100 and is located on the side of the source and drain regions near the substrate 100, thereby ensuring that the threshold voltage at the bottom of the groove channel is similar to the threshold voltage of the sidewall of the groove channel.

[0062] In one embodiment, if Figure 1 As shown, the first gate insulating layer 510 is located between the interlayer dielectric layer 600 and the source layer 410 and the drain layer 420. In another embodiment, the material of the interlayer dielectric layer 600 may include silicon nitride.

[0063] The present disclosure also provides a storage device, which includes the recessed channel array transistor of the recessed channel array transistor embodiment. The recessed channel array transistor used in the storage device of the present disclosure is the same as the recessed channel array transistor in the recessed channel array transistor embodiment, and therefore has the same beneficial effects, which will not be described in detail here.

[0064] In one embodiment, the storage device is a dynamic random access memory; wherein the capacitor of the dynamic random access memory is connected to one of the source layer 410 or the drain layer 420 of the recessed channel array transistor, the bit line of the dynamic random access memory is connected to the other of the source layer 410 or the drain layer 420 of the recessed channel array transistor; and the word line of the dynamic random access memory is connected to the gate 300 of the recessed channel array transistor.

[0065] The present disclosure also provides a method for preparing a recessed channel array transistor. Figure 3 As shown, the method for preparing the recessed channel array transistor includes:

[0066] Step S110, as Figure 4 As shown, an active material layer is formed;

[0067] Step S120, forming a groove channel 210 in the active material layer;

[0068] Step S130, as Figure 8 As shown, a second gate insulating layer 520 is formed, and the second gate insulating layer 520 covers the side wall surface of the groove channel 210 away from the notch 212 of the groove channel;

[0069] Step S140, as Fig. 9 As shown, a first gate insulating layer 510 is formed, and the first gate insulating layer 510 covers the remaining sidewall surfaces of the groove channel 210; the dielectric constant of the second gate insulating layer 520 is greater than the dielectric constant of the first gate insulating layer 510;

[0070] Step S150, as Fig.10 As shown, a gate 300 is formed, and the gate 300 fills the groove channel 210 and covers the second gate insulating layer 520 and a portion of the first gate insulating layer 510;

[0071] Step S160, as Figure 1 As shown, the active material layer is transformed into an active region 220 by ion implantation.

[0072] In the recessed channel array transistor preparation method disclosed in the present invention, due to the influence of the curvature effect of the recessed channel 210 and the thickness of the second gate insulating layer 520 being greater than the thickness of the first gate insulating layer 510, the recessed channel array transistor presents a trend that the threshold voltage at the bottom 211 of the recessed channel is greater than the threshold voltage at the sidewall of the recessed channel. However, the dielectric constant of the first gate insulating layer 510 is less than the dielectric constant of the second gate insulating layer 520, which will cause the recessed channel array transistor to present a trend that the threshold voltage at the sidewall of the recessed channel is greater than the threshold voltage at the bottom 211 of the recessed channel. Therefore, the larger dielectric constant of the second gate insulating layer 520 offsets the influence of the larger thickness of the second gate insulating layer 520, so that the difference between the threshold voltage at the bottom 211 of the recessed channel and the threshold voltage at the sidewall of the recessed channel of the recessed channel array transistor is reduced or eliminated, thereby improving the uniformity of the threshold voltage of the recessed channel array transistor at various positions of the recessed channel 210, and improving the performance of the recessed channel array transistor.

[0073] In step S110, Figure 4As shown, an active material layer can be formed on one side of a substrate 100, so that a recessed channel array transistor can be disposed on a substrate 100. In step S120, a notch 212 of a recessed channel is opened on a surface of a well region 220 away from the substrate 100.

[0074] In one embodiment, if Figure 4 As shown, step S110 may include sequentially forming a well region 220 and a source-drain material layer 430 on one side of the substrate 100, forming an active material layer including a stacked well region 220 and a source-drain material layer 430. The materials of the source-drain material layer 430 and the well region 220 may be the same. In step S120, the groove channel 210 divides the source-drain material layer 430 into a first source-drain material layer 431 and a second source-drain material layer 432. In step S160, by doping the first source-drain material layer 431 and the second source-drain material layer 432, the first source-drain material layer 431 and the second source-drain material layer 432 are converted into a source layer 410 and a drain layer 420, respectively, to form a source-drain region.

[0075] In step S110 and step S160, the well region 220, the source layer 410 and the drain layer 420 may be doped semiconductors, and the doping types are different. For example, in one embodiment, the well region 220 is a semiconductor layer with P-type doped ions, that is, the well region 220 is a P-type doped semiconductor layer; the source layer 410 and the drain layer 420 are semiconductor layers with N-type doped ions, that is, the source layer 410 and the drain layer 420 are N-type heavily doped regions. Active region In another embodiment, the well region 220 is an N-type doped semiconductor layer; the source layer 410 and the drain layer 420 are P-type heavily doped regions.

[0076] In step S120 , the groove channel 210 penetrates the source and drain regions and extends to the well region 220 .

[0077] In step S130, the second gate insulating layer 520 may be formed by the following method:

[0078] Step S210, as Figure 5 As shown, a second gate insulating material layer 530 is formed to cover the surface of the side wall 213 of the groove channel, the material of the second gate insulating material layer 530 is the same as that of the second gate insulating layer 520, and the thickness of the second gate insulating layer 520 at the bottom 211 of the groove channel is the same as the thickness of the second gate insulating layer 520 at the bottom 211 of the groove channel.

[0079] Step S220, as Figure 6As shown, a protective material layer 540 is formed on the side of the second gate insulating material layer 530 away from the well region 220. Optionally, the protective material layer 540 is filled in the groove channel 210 and extends upward, so that the surface of the protective material layer 540 away from the bottom 211 of the groove channel is flush with the surface of the source and drain material layer 430 away from the well region 220, so that it is easy to control the etching depth of the protective material layer 540 in subsequent etching. Optionally, the material of the protective material layer 540 is the same as that of the gate 300.

[0080] Step S230, as Figure 7 As shown, part of the protection material layer 540 is removed by etching, so that the surface of the remaining protection material layer 540 away from the bottom 211 of the groove channel is flush with the surface of the second gate insulation layer 520 away from the bottom 211 of the groove channel.

[0081] Step S240, as Figure 8 As shown, the second gate insulating material layer 530 not covered by the remaining protection material layer 540 is removed by etching, and the remaining second gate insulating material layer 530 forms a second gate insulating layer 520 .

[0082] In one embodiment, the material of the second gate insulating layer 520 is a high dielectric constant material. Further, the dielectric constant of the material of the second gate insulating layer 520 is greater than 4. Optionally, the material of the second gate insulating layer 520 includes one or more of silicon oxynitride, silicon nitride and hafnium oxide.

[0083] In step S140, if Fig. 9 As shown, a first gate insulating layer 510 is formed; wherein the dielectric constant of the second gate insulating layer 520 is greater than the dielectric constant of the first gate insulating layer 510 .

[0084] Optionally, the thickness of one end of the first gate insulating layer 510 close to the second gate insulating layer 520 is equal to the thickness of one end of the second gate insulating layer 520 close to the first gate insulating layer 510 .

[0085] It is understandable that if Fig. 9 As shown, the first gate insulating layer 510 also covers the sidewalls of the first source-drain material layer 431 close to the notch 212 of the groove channel, and covers the sidewalls of the second source-drain material layer 432 close to the notch 212 of the groove channel.

[0086] Optionally, the second gate insulating layer 520 and the first gate insulating layer 510 form a gate insulating layer 500 of a recessed channel array transistor. In a cross section perpendicular to the extension direction of the groove channel 210, the length of the second gate insulating layer 520: the length of the gate insulating layer 500 = 0.4-0.8.

[0087] In step S150, if Fig.10 As shown, the gate 300 material can be filled in the groove channel 210 to form the gate 300. It is understood that if the material of the protective material layer 540 is different from the material of the gate 300, the remaining protective material layer 540 needs to be removed in advance. If the material of the protective material layer 540 is the same as the material of the gate 300, the gate material can continue to be deposited on the remaining protective material layer 540 until the gate 300 is formed.

[0088] In one embodiment, along the direction in which the well region 220 is away from the substrate 100, the surface of the well region 220 away from the substrate 100 does not exceed the surface of the gate 300 away from the substrate 100. For example, Figure 1 As shown, the gate 300 is away from the surface of the substrate 100 , and is located at a side of the well region 220 away from the substrate 100 .

[0089] In step S160, if Figure 1 As shown, ions may be implanted into the first source-drain material layer 431 and the second source-drain material layer 432 by ion implantation, so that the first source-drain material layer 431 is converted into the source layer 410, and the second source-drain material layer 432 is converted into the drain layer 420. Optionally, step S160 may be performed before performing step S130 or step S120, or after performing step S150.

[0090] In one embodiment, the method for preparing a recessed channel array transistor may further include:

[0091] Step S170, as Figure 1 As shown, an interlayer dielectric layer 600 is formed, and the interlayer dielectric layer 600 covers the surface of the gate 300 near the notch 212 of the groove channel. Optionally, a first gate insulating layer 510 is provided between the interlayer dielectric layer 600 and the source layer 410 and the drain layer 420. Optionally, the material of the interlayer dielectric layer 600 is silicon nitride. In one embodiment, the interlayer dielectric layer 600 is away from the surface of the bottom 211 of the groove channel and is flush with the source layer 410. Optionally, step S170 is located between step 150 and step 160.

[0092] It should be noted that, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in the specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc., which shall all be considered as part of the present disclosure.

[0093] It should be understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components proposed in this specification. The present disclosure can have other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. A recessed channel array transistor, characterized in that: include: An active area is provided with a groove channel, and the active area includes a well area and a source and drain area; A gate structure, comprising a gate and a gate insulating layer, wherein the gate and the gate insulating layer are filled in the groove channel, and the gate insulating layer isolates the active area and the gate; Among them, the gate insulation layer includes a first gate insulation layer and a second gate insulation layer, the first gate insulation layer is arranged on a side of the second gate insulation layer close to the notch of the groove channel, and the second gate insulation layer is arranged on a side of the first gate insulation layer away from the notch of the groove channel; the dielectric constant of the first gate insulation layer is smaller than the dielectric constant of the second gate insulation layer.

2. The recessed channel array transistor according to claim 1, characterized in that: The material of the second gate insulating layer is a high dielectric constant material.

3. The recessed channel array transistor according to claim 1, wherein: The thickness of one end of the first gate insulating layer close to the second gate insulating layer is equal to the thickness of one end of the second gate insulating layer close to the first gate insulating layer.

4. The recessed channel array transistor according to claim 1, wherein: In a cross section perpendicular to the extending direction of the groove channel, the length of the second gate insulating layer: the length of the gate insulating layer=0.4~0.

8.

5. The recessed channel array transistor according to claim 1, wherein: The second gate insulating layer is close to a surface of the first gate insulating layer and is lower than a surface of the well region close to the source and drain region.

6. The recessed channel array transistor according to claim 1, wherein: The recessed channel array transistor further comprises: An interlayer dielectric layer covers a surface of the gate electrode close to a notch of the groove channel.

7. A storage device, characterized in that: A recessed channel array transistor comprising the method according to any one of claims 1 to 6.

8. A method for preparing a recessed channel array transistor, characterized in that: include: forming an active material layer; forming a groove channel in the active material layer; forming a second gate insulating layer, wherein the second gate insulating layer covers a side wall surface of the groove channel away from a notch of the groove channel; forming a first gate insulating layer, wherein the first gate insulating layer covers the remaining sidewall surfaces of the groove channel; the dielectric constant of the second gate insulating layer is greater than the dielectric constant of the first gate insulating layer; forming a gate, wherein the gate is filled in the groove channel and covers the second gate insulating layer and a portion of the first gate insulating layer; The active material layer is transformed into an active region by ion implantation.

9. The method for preparing a recessed channel array transistor according to claim 8, characterized in that: The material of the second gate insulating layer is a high dielectric constant material.

10. The method for manufacturing a recessed channel array transistor according to claim 8, characterized in that: The thickness of one end of the first gate insulating layer close to the second gate insulating layer is equal to the thickness of one end of the second gate insulating layer close to the first gate insulating layer.

11. The method for manufacturing a recessed channel array transistor according to claim 8, characterized in that: In a cross section perpendicular to the extending direction of the groove channel, the length of the second gate insulating layer: the length of the side wall of the groove channel=0.4-0.

8.

12. The method for manufacturing a recessed channel array transistor according to claim 8, characterized in that: The method for preparing the recessed channel array transistor further includes: An interlayer dielectric layer is formed, wherein the interlayer dielectric layer covers a surface of the gate electrode close to the notch of the groove channel.

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