Single-inductor multi-output DC-DC converter

Abstract

A single-inductor multi-output DC-DC converter includes a regulation circuit that controls a switch to alternately charge at least two capacitors associated with at least two DC output voltages via a single inductor from a DC input port. The regulation circuit determines whether the DC-DC converter operates in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). In CCM mode, the regulation circuit regulates the charging duty cycle of a first output voltage and generates an initial charging duty cycle for each of the other output voltages by scaling the first output voltage duty cycle. In DCM mode, the regulation circuit independently regulates the charging duty cycle of each output voltage and stores each duty cycle to be used for the next charging period of the same output voltage. The regulation circuit detects and handles undershoot and overshoot conditions to accelerate recovery at the output port.

Description

Technical Field

[0001] This invention relates to DC-DC converters, and more particularly, to single-inductor multi-output DC-DC converters. Background Technology

[0002] Single-inductor multi-output DC-DC converters that use a single inductor to generate two or more different DC output voltages from a single DC input voltage are known, for example, in U.S. Patent Nos. 6,204,651 and 6,977,447 (hereinafter referred to as 447 patents).

[0003] In 447 patent Figure 4 A single-inductor dual-output DC-DC boost converter is illustrated. The boost converter alternates between a phase where energy is transferred from the battery to the inductor and a phase where energy is transferred from the inductor to one of the two capacitors that generate two DC output voltages. Furthermore, the boost converter alternates between a period of charging the first capacitor associated with the first DC output voltage and a period of charging the second capacitor associated with the second DC output voltage, based on which of the two DC output voltages is relatively more insufficient compared to its target voltage level.

[0004] Figure 6 of patent 447 illustrates a single-inductor dual-output DC-DC buck converter. The buck converter alternates between a phase where the inductor and one of the two capacitors generating the two DC output voltages are charged by a battery and a phase where the inductor discharges. Furthermore, the buck converter alternates between a period of charging the first capacitor associated with the first DC output voltage and a period of charging the second capacitor associated with the second DC output voltage, based on which of the two DC output voltages is relatively more insufficient compared to its target voltage level.

[0005] In these two single-inductor dual-output DC-DC converters, one of the two DC output voltages is selected as the master regulated output voltage, such that the duty cycle of the charging signal used to charge and discharge the inductor for the master regulated output voltage is independently adjusted by the converter's regulation module. The initial duty cycle of the charging signal used to charge and discharge the inductor for the other output voltage is generated by scaling the most recent duty cycle of the master regulated output voltage according to a fixed scaling factor based on the different target voltage levels of the two output voltages. Therefore, the regulation of the other output voltage depends on the regulation of the master regulated output voltage.

[0006] While the DC-DC converters of the 447 patent exhibit relatively low output ripple levels when operating in continuous conduction mode (CCM), they perform poorly and exhibit relatively high output ripple levels when operating in discontinuous conduction mode (DCM). In CCM mode, current continuously flows through the inductor. In some cases (e.g., optical output loads), the inductor current may change from positive to negative and then from negative to positive; however, except for the instantaneous transitions between positive and negative, current continuously flows through the inductor. On the other hand, in DCM mode, the inductor current reaches zero and remains zero for varying periods of time without becoming negative.

[0007] Therefore, reducing the output ripple in a single-inductor multi-output DC-DC converter would be advantageous. Attached Figure Description

[0008] Embodiments of the invention have been illustrated by way of example, and are not limited to the accompanying drawings, in which the same reference numerals indicate similar elements. Elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the thickness of layers and regions may be exaggerated for clarity.

[0009] Figure 1 This is a schematic circuit diagram of a single-inductor dual-output buck DC-DC converter according to an embodiment of the present invention;

[0010] Figure 2 yes Figure 1 A flowchart illustrating the operation of a DC-DC converter;

[0011] Figure 3 yes Figure 1 Timing diagram of example operation of the DC-DC converter for output voltage Vout1 or Vout2 during the conversion from CCM mode to DCM mode;

[0012] Figure 4 yes Figure 1 Timing diagrams of the DC-DC converter for example operation of output voltage Vout1 or Vout2 during overshoot conditions; and

[0013] Figure 5 yes Figure 1 Timing diagram of example operation of the DC-DC converter for output voltage Vout1 or Vout2 during undershoot conditions. Detailed Implementation

[0014] This document discloses detailed exemplary embodiments of the invention. However, the specific structural and functional details disclosed herein are merely for the purpose of describing exemplary embodiments of the invention. Embodiments of the invention may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein. Furthermore, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments of the invention.

[0015] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” “having,” “containing,” or “comprise” specify the presence of the stated feature, step, or component, but do not exclude the presence or addition of one or more other features, steps, or components. It should also be noted that in some alternative embodiments, the described functions / actions may not occur in the order shown in the figures. For example, two figures shown consecutively may actually be performed substantially simultaneously, or sometimes in reverse order, depending on the functions / actions involved. The term “or” is to be interpreted inclusively, unless otherwise stated.

[0016] As previously described, the dual-output DC-DC converter of patent 447 has a first so-called "master-regulated" output voltage and a second so-called "other" output voltage. The DC-DC converter regulates the duty cycle of the charging signal used to control the master-regulated output voltage and generates an initial duty cycle for the charging signal used to control the other output voltage by applying a fixed scaling factor to the most recent duty cycle used for the master-regulated output voltage. When this DC-DC converter operates in CCM mode, it switches between charging periods of capacitors at two different output voltages, resulting in relatively small output ripple in the output voltage. However, when the DC-DC converter operates in DCM mode, significant output ripple appears in one or both output voltages after the switching between the charging periods of capacitors at the two output voltages, when the same fixed scaling factor is used to generate the initial duty cycle of the other output voltage.

[0017] According to certain embodiments of the invention, the control of a single-inductor multi-output DC-DC converter is designed to provide reduced output ripple during both CCM and DCM operation.

[0018] In one embodiment, the present invention is a single-inductor multi-output DC-DC converter that converts a DC input voltage at an input port into at least first and second output voltages at corresponding first and second output ports. The DC-DC converter includes an inductor; at least first and second capacitors respectively connected to the first and second output ports; a plurality of switches selectively connecting the input port to either the first or second capacitor via the inductor; and regulation circuitry for controlling the switches. The regulation circuitry determines whether the DC-DC converter operates in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). In CCM mode, (i) the regulation circuitry regulates the first output voltage, and (ii) the regulation circuitry regulates the second output voltage based on the regulation of the first output voltage. In DCM mode, (i) the regulation circuitry regulates the first output voltage independently of the regulation of the second output voltage, and (ii) the regulation circuitry regulates the second output voltage independently of the regulation of the first output voltage.

[0019] Now for reference Figure 1 A schematic circuit diagram of a single-inductor dual-output buck DC-DC converter 100 according to an embodiment of the present invention is shown. The converter 100 has a single inductor L and two capacitors C1 and C2, which are selectively charged and discharged based on four switching control signals V1CTRL, V2CTRL, PCTRL, and NTRL applied to the gates of four transistor switches Vout1_SW, Vout2_SW, P_SW, and N_SW, respectively, to convert the DC input voltage DCDC_IN into two different DC output voltages Vout1 and Vout2.

[0020] For the following discussion, it is assumed that Vout1 is the "master regulated" output voltage and Vout2 is the "other" output voltage. Those skilled in the art will understand how the DC-DC converter 100 operates when Vout2 is the master regulated output voltage and Vout1 is the other output voltage.

[0021] Switch control signals V1CTRL and V2CTRL control p-type switches Vout1_SW and Vout2_SW, respectively, to control whether capacitor C1 or capacitor C2 is being charged. Specifically, to charge capacitor C1 (and thus control Vout1), V1CTRL is driven low to turn on Vout1_SW, and V2CTRL is driven high to turn off Vout2_SW, thereby allowing energy stored in inductor L to flow to capacitor C1. Similarly, to charge capacitor C2 (and thus control Vout2), V1CTRL is driven high to turn off Vout1_SW, and V2CTRL is driven low to turn on Vout2_SW, thereby allowing energy stored in inductor L to flow to capacitor C2.

[0022] The switch control signals PCTRL and NCTRL control the p-type charging switch P_SW and the n-type discharging switch N_SW, respectively, to control whether inductor L is charging or discharging from DC-DC_IN. Specifically, to charge inductor L from DC-DC_IN, both PCTRL and NCTRL are driven low to turn on P_SW and turn off N_SW, thereby allowing energy to flow from DC-DC_IN to inductor L, and thus to the currently selected output voltage Vout1 or Vout2. Similarly, to discharge inductor L, both PCTRL and NCTRL are driven high to turn off P_SW and turn on N_SW, thereby stopping charging of the inductor while still allowing energy in the inductor to flow to the currently selected output Vout1 or Vout2.

[0023] Figure 1 The remainder shows the regulation circuitry for converter 100, which generates four switch control signals V1CTRL, V2CTRL, PCTRL, and NCTRL, respectively, to control four switches Vout1_SW, Vout2_SW, P_SW, and N_SW. As further described below, the regulation circuitry selects either Vout1 or Vout2, which is less than its desired voltage level, as the currently selected output voltage. As a result, the regulation circuitry alternates between periods of charging output voltage Vout1 and periods of charging output voltage Vout2.

[0024] Furthermore, the regulating circuit repeatedly turns switches P_SW and N_SW on and off in a complementary manner to charge capacitor C1 or C2 corresponding to the currently selected output voltage Vout1 or Vout2. The resulting current flowing intermittently from the input port DCDC_IN to inductor L can be characterized as a charging signal for the currently selected output voltage Vout1 or Vout2, which has a duty cycle corresponding to the timing of the on and off of switches P_SW and N_SW, where a higher duty cycle corresponds to more charging of inductor L from DCDC_IN. The charging signal is high during the charging phase when P_SW is on and N_SW is off in each charge-discharge cycle of inductor L, and low during the discharging phase when P_SW is off and N_SW is on in each charge-discharge cycle of inductor L.

[0025] The regulating circuit also determines whether the DC-DC converter 100 operates in CCM mode or DCM mode, and controls the duty cycle of the charging signal differently for the two different modes. Specifically, if the regulating circuit determines that the DC-DC converter 100 is operating in CCM mode, the regulating circuit (i) adjusts the duty cycle of the charging signal used to control the output voltage Vout1 of the main regulation, and (ii) similar to the technique described in patent 447, generates an initial duty cycle for the charging signal used to control the other output voltage Vout2 by applying a scaling factor (based on the relative desired output voltage levels of Vout1 and Vout2) to the most recent duty cycle of the charging signal used for the output voltage Vout1 of the main regulation.

[0026] In CCM mode, when controlling the output voltage Vout1 of the master regulator, the regulator circuit stores information in its local memory about the current duty cycle of the Vout1 charging signal. When the charging period switches to another output voltage Vout2, the regulator circuit retrieves the most recent Vout1 duty cycle from memory and scales that value to generate the initial duty cycle for the charging signal of the output voltage Vout2. When the charging period switches back to the output voltage Vout1, the regulator circuit retrieves the most recent Vout1 duty cycle from memory and uses that value as the initial duty cycle for the charging signal of the output voltage Vout1. In this way, it can be said that the regulator circuit independently controls the Vout1 duty cycle, but controls the Vout2 duty cycle in dependence on the Vout1 duty cycle. Note that the regulator circuit also stores the current Vout2 duty cycle in its local memory, but during CCM mode, only the stored Vout1 duty cycle is used (i.e., directly for Vout1 and scaled for Vout2).

[0027] In an alternative embodiment, instead of retrieving and using the previous Vout1 duty cycle as the initial duty cycle for the current Vout1 charging period during CCM operation, the adjustment circuit "descales" the most recent Vout2 duty cycle to generate the initial duty cycle for the current Vout1 charging period. In this embodiment, for CCM mode, the adjustment of Vout2 will depend on the adjustment of Vout1, and the adjustment of Vout1 will depend on the adjustment of Vout2.

[0028] In another alternative embodiment, during CCM operation, the regulating circuit generates the initial duty cycle for the current Vout1 charging period by selecting the maximum value of (i) the previous Vout1 duty cycle and (ii) the most recent Vout2 duty cycle, both of which are "descaled" versions. Similarly, the regulating circuit generates the initial duty cycle for the current Vout2 charging period by selecting the maximum value of (i) the previous Vout2 duty cycle and (ii) the most recent Vout1 duty cycle, both of which are scaled versions. In this embodiment, for CCM mode, the regulation of Vout2 depends on the regulation of Vout1, and the regulation of Vout1 depends on the regulation of Vout2.

[0029] If the regulating circuit determines that the DC-DC converter 100 is operating in DCM mode, the regulating circuit alternates between (i) a charging period that regulates the duty cycle of the charging signal used to control the output voltage Vout1 and (ii) a charging period that regulates the duty cycle of the charging signal used to control the output voltage Vout2, wherein the regulation of each output voltage is independent of the regulation of the other output voltage. In doing so, the regulating circuit stores both duty cycles in local memory such that at the beginning of a charging period for an output voltage, the regulating circuit retrieves the stored duty cycle from a previous charging period for that output voltage and uses that value as the initial duty cycle for the current charging period for that output voltage.

[0030] Note that when the operation of the DC-DC converter 100 switches from CCM mode to DCM mode, the regulating circuit retrieves the previously stored CCM charging period of Vout1 and uses the stored Vout1 duty cycle as the initial duty cycle for the first DCM charging period of Vout1. Similarly, the regulating circuit retrieves the stored Vout2 duty cycle from the previously stored CCM charging period of Vout2 and uses the stored Vout2 duty cycle as the initial duty cycle for the first DCM charging period of Vout2.

[0031] Furthermore, the regulating circuit detects both voltage overshoot and undershoot conditions. If the regulating circuit detects that the currently selected output voltage is determined to be an excessively high overshoot condition, it controls switches P_SW and N_SW to reduce the output voltage. In one possible implementation, in DCM mode, the regulating circuit reduces the duty cycle of the charging signal to zero by keeping switch P_SW off and keeping switch N_SW on until the inductor current decreases to zero. Switch N_SW is then turned off, and both switches N_SW and P_SW remain off to allow capacitor C1 or C2 corresponding to the currently selected output voltage Vout1 or Vout2 to discharge through the load until the output overshoot condition no longer exists.

[0032] If the regulating circuit detects an undershoot condition where the currently selected output voltage is determined to be too low, it controls switches P_SW and N_SW to increase the output voltage. In one possible implementation, the regulating circuit increases the initial duty cycle of the charging signal by a specified amount, so that when an undershoot occurs, the currently selected output voltage can charge faster with a higher initial duty cycle, thus allowing the output to recover from the undershoot sooner.

[0033] To perform these various regulation functions, the regulation circuit of the DC-DC converter 100 includes a resistor network 102, a comparator 104, a load selection module 106, a regulation module 108, a pulse width modulation (PWM) module 110, OR gates 112 and 114, an AND gate 116, a zero-crossing detection (ZCD) module 118, a pulse detection module 120, a comparator 122, a switching module SW1, a switching control module 124, an overshoot detection module 126, and an undershoot detection module 128.

[0034] The resistor network 102 has two resistor dividers RD1 and RD2, each with four resistors: R11-R14 in RD1 and R21-R24 in RD2, wherein the output voltage Vout1 is applied to the resistor divider RD1 and the output voltage Vout2 is applied to the resistor divider RD2. The resistance levels of resistors R11-R14 and R21-R24 are selected to generate three pairs of different voltage dividers, sensed feedback voltages: (1) Vout1_hi and Vout2_hi between R11 and R12 and between R21 and R22, respectively, which are used by undershoot detection module 128, as further described below; (2) Vout1_sns and Vout2_sns between R12 and R13 and between R22 and R23, respectively, as further described below; (3) Vout1_lo and Vout2_lo between R13 and R14 and between R23 and R24, respectively, which are used by overshoot detection module 126, as further described below.

[0035] The divided, sensed feedback voltages Vout1_sns and Vout2_sns are compared by comparator 104 to generate a load selection control signal Load_Select. Load_Select will be high when Vout1_sns is greater than Vout2_sns; otherwise, Load_Select will be low. The resistance levels of resistors R11-R14 and R21-R24 are selected based on the relative magnitudes of the target voltage levels of Vout1 and Vout2, such that the sensed feedback voltages Vout1_sns and Vout2_sns will be equal when both Vout1 and Vout2 are at their target voltage levels. For example, if the target voltage level of Vout1 is 9 volts and the target voltage level of Vout2 is 5 volts, in one possible implementation, the resistor network 102 is designed to divide Vout1 by 9 and Vout2 by 5, such that when Vout1 = 9V and Vout2 = 5V, both Vout1_sns and Vout2_sns are equal to 1V. Thus, the load selection control signal Load_Select will indicate which of the two outputs, Vout1 and Vout2, is more deficient relative to its target voltage level. Specifically, Load_Select will be high when Vout2 is more deficient than Vout1, and low when Vout1 is more deficient than Vout2.

[0036] The load selection control signal Load_Select is applied to the load selection module 106, which generates switching control signals V1CTRL and V2CTRL. When Vout2 is less than Vout1 and Load_Select is high, the load selection module 106 generates a high V1CTRL and a low V2CTRL to allow capacitor C2 to be connected to inductor L and charged by inductor L. Conversely, when Vout1 is less than Vout2 and Load_Select is low, the load selection module 106 generates a low V1CTRL and a high V2CTRL to allow capacitor C1 to be connected to inductor L and charged by inductor L.

[0037] The regulation module 108 generates a regulation signal 109, which controls the duty cycle of the charging signal used to charge capacitor C1 or C2 for the currently selected output voltage Vout1 or Vout2. The regulation signal 109 is applied to the PWM module 110, which generates PWM pulse streams 111a and 111b with PWM pulses having the duty cycle indicated by the regulation signal 109. Pulse stream 111a is applied to an OR gate 112, which generates a switch control signal PCTRL, while pulse stream 111b is applied to an OR gate 114, the output of which is applied to an AND gate 116, which generates a switch control signal NCTRL.

[0038] PWM pulse streams 111a and 111b contain similar PWM pulses, where the pulse transitions are slightly offset from each other in time to prevent switches P_SW and N_SW from turning on simultaneously. Specifically, the rising edge of the PWM pulse in pulse stream 111a slightly leads the rising edge of the PWM pulse in pulse stream 111b to ensure that switch P_SW is turned off before switch N_SW turns on. Similarly, the falling edge of the PWM pulse in pulse stream 111b slightly leads the falling edge of the PWM pulse in pulse stream 111a to ensure that switch N_SW is turned off before switch P_SW turns on.

[0039] As further explained below, during normal CCM operating conditions without overshoot, the overshoot detection control signal Overshoot_det_sig from the overshoot detection module 126 is low and the ZCD control signal zcd_b_latch from the ZCD module 118 is high. In that case, the switch control signal NCTRL generated by AND gate 116 is equal to pulse stream 111b, and the switch control signal PCTRL generated by OR gate 112 is equal to pulse stream 111a. Therefore, during those normal CCM operating conditions, when both pulse streams 111a and 111b are low, the n-type switch N_SW is off and the p-type switch P_SW is on. When both pulse streams 111a and 111b are high, N_SW is on and P_SW is off. Therefore, the duty cycle of the PWM pulses in pulse streams 111a and 111b determines how long the switch P_SW is on and off in each charge-discharge cycle, which in turn determines how much the inductor L and the currently selected capacitor C1 or C2 are charged from the input node DC-CDC_IN.

[0040] Because switch P_SW is a p-type transistor switch, a lower duty cycle of pulse current 111a means more charging of inductor L and the currently selected capacitor, and vice versa. Therefore, a decrease in the duty cycle of pulse current 111a corresponds to an increase in the duty cycle of the charging signal applied to inductor L and capacitor for the currently selected output voltage, and vice versa.

[0041] The zero-crossing detector (ZCD) module 118 and the pulse detection module 120 determine whether the DC-DC converter 100 operates in CCM mode or DCM mode. As previously described, the DC-DC converter 100 operates in CCM mode when the current in the inductor L remains positive and never reaches zero, while in DCM mode, the inductor current does reach zero during the discharge phase of at least some charge-discharge cycles.

[0042] During each charging phase of inductor L, control signals PCTRL and NCTRL are both low, causing switch P_SW to turn on and switch N_SW to turn off. In that case, positive current will flow from the input port DC-DC_in through P_SW to node LP through inductor L, and through switch Vout1_SW or Vout2_SW to the selected capacitor C1 or C2. In that case, the voltage at node LP will always be positive.

[0043] During each discharge phase of inductor L, control signals PCTRL and NCTRL are both high, causing switch P_SW to turn off and switch N_SW to turn on. In that case, node LP will be connected to ground through N_SW. This is as long as the current through inductor L remains positive (i.e., from...). Figure 1 The current flows from node LP to node LN. Due to the voltage drop from ground across N_SW to node LP, the voltage at node LP will be negative. If and when the current through inductor L becomes negative (i.e., from... Figure 1 When the current flows from node LN to node LP, the voltage at node LP will be positive due to the voltage drop from node LP across N_SW to ground.

[0044] The ZCD comparator ZCD_CMP compares the voltage at node LP with the ground voltage GND. The output of ZCD_CMP is applied to the clock input port of the D-type ZCD flip-flop DFF_zcd, whose D input port is fixed at a high signal TIE_HIGH, and whose reset input port receives the ZCD reset signal reset_zcd from inverter 118A, which receives the switch control signal NCTRL. The output signal zcd_latch appearing at the Q output port of DFF_zcd is applied as a set signal to the set-reset (SR) latch SR_LATCH and pulse detection module 120. The inverted value of the switch control signal PCTRL from inverter 118B is applied as the latch reset signal reset_latch to SR_LATCH, which generates the output signal zcd_b_latch.

[0045] During operation, in each inductor charging phase when both PCTRL and NCTRL are low, the voltage at node LP will be positive, the output of comparator ZCD_CMP will be high, and both reset signals reset_zcd and reset_latch will be high. This will reset flip-flop DFF_zcd, causing the Q output zcd_latch to go low, and also reset latch SR_LATCH, causing the latch output zcd_b_latch to go high.

[0046] During each inductor discharge phase when both PCTRL and NCTRL are high, the reset signals reset_zcd and reset_latch will be low, releasing the flip-flop DFF_zcd and latch SR_LATCH from their reset state. In this case, as long as the inductor current L remains positive, the voltage at node LP will remain negative, the output of comparator ZCD_CMP will remain low, zcd_latch will remain low, and zcd_b_latch will remain high. If, and when the inductor current L becomes negative, the voltage at node LP will become positive, the output of comparator ZCD_CMP will be driven high, which will trigger flip-flop DFF_zcd to drive zcd_latch high, which will drive zcd_b_latch low.

[0047] Driving zcd_b_latch low will cause NCTRL to go low, which will turn off switch N_SW, preventing the inductor current from being further driven negative. NCTRL going low will also drive reset_zcd high, which will reset flip-flop DFF_zcd and drive zcd_latch low again. Note that zcd_b_latch will remain low until the latch SR_LATCH is reset (i.e., at the start of the next inductor current charging phase when PCTRL is driven low again).

[0048] The pulse detection module 120 detects a pulse that is driven high in the zcd_latch and drives the DCM mode detection control signal DCM_mode_det high, indicating that the DC-DC converter 100 is currently operating in DCM mode. Note that in some embodiments, after a pulse is detected, the pulse detection module 120 is configured to hold DCM_mode_det for up to a specified number (e.g., 16) of adjustment cycles to avoid unwanted jitter between DCM and CCM modes.

[0049] like Figure 1As shown. The adjustment module 108 generates an adjustment signal 109 based on a one-bit binary feedback charge signal Feedback_Charge_Sig generated by comparator 122. Comparator 122 compares the sensed feedback voltage Feedback_sns with a reference voltage VREF (e.g., 1V for the previously described resistor network 102 example). If Feedback_sns is less than VREF, Feedback_charge_sig will be high, indicating that the charging duty cycle of the selected output voltage needs to be increased. Otherwise, Feedback_charge_sig will be low, indicating that the charging duty cycle of the selected output voltage needs to be decreased.

[0050] The sensed feedback voltage Feedback_sns is generated based on the states of switches SW11 and SW12 in switch module SW1, which are controlled by switch control signal SW_CTRL, generated by switch control module 124. When DCM_mode_det is low, indicating that DC-DC converter 100 is currently operating in CCM mode, switch control module 124 sets SW_CTRL to the value of switches SW11 and SW12 in switch module SW1 to be turned on (i.e., closed), which causes Feedback_sns to be based on the common-mode voltage between Vout1_sns and Vout2_sns. This operating mode is called "common regulation" mode. When DCM_mode_det is high, indicating that the DC-DC converter 100 is currently operating in DCM mode, the switch control module 124 sets SW_CTRL to the load selection control signal Load_Select, causing the switches SW11 or SW12 in the switch module SW1 to be turned on only for the currently selected output voltage Vout1 or Vout2. This results in Feedback_sns being based solely on the corresponding voltage Vout1_sns or Vout2_sns. This operating mode is called "separate adjustment" mode.

[0051] Therefore, when the DC-DC converter 100 operates in CCM mode, the regulation module 108 operates in common regulation mode, and when the DC-DC converter 100 operates in DCM mode, the regulation module 108 operates in separate regulation mode.

[0052] like Figure 1As shown. The regulation module 108 has a CCM submodule 108A and a DCM submodule 108B. When the DC-DC converter 100 operates in CCM mode (indicated low by DCM_mode_det), the CCM submodule 108A generates an initial duty cycle for the other output voltage Vout2 by scaling the most recent duty cycle of the master-regulated output voltage Vout1 with a fixed scaling factor based on the relative target voltage levels of the two output voltages. However, when the DC-DC converter 100 operates in DCM mode (indicated high by DCM_mode_det), the DCM submodule 108B regulates the two output voltages Vout1 and Vout2 alternately and independently, wherein the two duty cycles are stored in local memory such that the initial value of the duty cycle for each output voltage at the start of the next charging period is the corresponding stored value of the duty cycle of that output voltage from its previous charging period.

[0053] For CCM mode, even if only the duty cycle of the master-regulated output voltage is subsequently used, two duty cycles are stored, where the duty cycle of the other output voltage is generated by scaling the duty cycle of the master-regulated output voltage with a fixed scaling factor. However, note that when switching from CCM mode to DCM mode, the stored duty cycles of the two output voltages from CCM mode are used as the initial duty cycle for DCM mode.

[0054] Referring again to resistor network 102, the low-voltage sensing voltages Vout1_lo and Vout2_lo generated by resistor network 102 are applied to switches SW21 and SW22 of switch module SW2 of overshoot detection module 126, respectively. When DC-DC converter 100 operates in DCM mode such that DCM_mode_det is high, the regulation circuit operates in separate regulation mode, and the switch control signal SW_CTRL generated by switch control module 124 is equal to the load selection control signal Load_Select. In that case, when Load_Select is high indicating that Vout2 is the currently selected output voltage, switch SW21 is open and switch SW22 is closed, so that Vout2_lo is applied as the sensed low feedback voltage FB_L0 to overshoot comparator 126A. Similarly, when DC-DC converter 100 operates in DCM mode and Load_Select is low, indicating that Vout1 is the currently selected output voltage, switch SW21 is closed and switch SW22 is open, so that Vout1_lo is applied as FB_LO to overshoot comparator 126A.

[0055] On the other hand, when the DC-DC converter 100 operates in CCM mode and DCM_mode_det is low, the regulation circuit operates in common regulation mode, and the switch control signal SW_CTRL generated by the switch control module 124 causes the switches SW21 and SW22 in the switch module SW2 to close independently of the value of Load_Select, so that the common mode voltage between Vout1_lo and Vout2_lo is applied to the overshoot comparator 126A as FB_L0.

[0056] In all cases, the overshoot comparator 126A compares the sensed low feedback voltage FB_LO with the reference voltage VREF to generate an overshoot detection signal Overshoot_det_sig. If FB_LO is greater than VREF, Overshoot_det_sig will be high, indicating the presence of an overshoot condition. Otherwise, Overshoot_det_sig will be low, indicating the absence of an overshoot condition. An overshoot condition exists when the currently selected output voltage is significantly higher than its target voltage level.

[0057] The overshoot detection signal Overshoot_det_sig is applied (i) to OR gate 112, which also receives PWM pulse stream 111a, and (ii) to OR gate 114, which also receives PWM pulse stream 111b. The output of OR gate 114 is applied to AND gate 116, which also receives the ZCD output signal zcd_b_latch.

[0058] Under normal CCM operation without overshoot conditions, zcd_b_latch from ZCD module 118 is high and Overshoot_det_sig is low. In this case, switch P_SW will be turned on and off based solely on PWM pulse flow 111a, and switch N_SW will be turned on and off based solely on PWM pulse flow 111b.

[0059] However, if and when an overshoot comparator 126A detects an overshoot condition during CCM operation, Overshoot_det_sig will be driven high. In that case, PCTRL will be driven high independently of PWM pulse flow 111a, and switch P_SW will be driven off, thus stopping charging of inductor L from DC-DC_IN. Furthermore, if both Overshoot_det_sig and zcd_b_latch are high, NCTRL will be driven high independently of PWM pulse flow 111b. In that case, switch N_SW will be driven on, and inductor L will discharge. When inductor L discharges, at some point, the voltage level of the currently selected output voltage Vout1 or Vout2 will drop, causing the feedback voltage FB_LO to drop below VREF again, causing the overshoot detection signal Overshoot_det_sig to go low again. In that case, PCTRL and NCTRL will again be determined solely by PWM pulse flows 111a and 111b, respectively.

[0060] If, when the current in inductor L reaches zero, indicating that DC-DC converter 100 is now operating in DCM mode, ZCD module 118 will drive zcd_b_latch low, which will drive NCTRL low, thus turning off switch N_SW. Driving NTRL low also causes ZCD flip-flop DFF_zcd to reset, which in turn resets SR_latch, which again drives zcd_b_latch high, so that NCTRL will again be determined solely by PWM pulse flow 111b. If, in response to a detected overshoot condition, inductor L is discharged to zero current, this allows switch N_SW to turn off. Even if no overshoot condition is detected, if inductor L discharges to zero current, it will also turn off switch N_SW.

[0061] Referring again to resistor network 102, the high-voltage sensing voltages Vout1_hi and Vout2_hi are applied to switches SW31 and SW32 of the switching module SW3 of undershoot detection module 128, respectively. Unlike overshoot detection module 126, the switching module SW3 of undershoot detection module 128 is always controlled based on Load_Select, regardless of whether DC-DC converter 100 operates in CCM or DCM mode, to ensure that undershoot detection module 128 always detects a more insufficient output voltage. Thus, when Load_Select is high, switch SW31 is open and switch SW32 is closed, causing Vout2_hi to be applied as the sensed high feedback voltage FB_HI to undershoot comparator 128A. Similarly, when Load_Select is low, switch SW31 is closed and switch SW32 is open, causing Vout1_hi to be applied as FB_HI to undershoot comparator 128A.

[0062] In all cases, the undershoot comparator 128A compares the sensed high feedback voltage FB_HI with the reference voltage VREF to generate an undershoot detection signal Undershoot_det_sig. If VREF is greater than FB_HI, Undershoot_det_sig will be high, indicating the presence of an undershoot condition. Otherwise, Undershoot_det_sig will be low, indicating the absence of an undershoot condition. An undershoot condition exists when the currently selected output voltage is significantly lower than its target voltage level.

[0063] The adjustment module 108 receives an undershoot detection signal Undershoot_det_sig, and if an undershoot condition exists, at submodule 108C, the adjustment module 108 adjusts the adjustment signal 109 based on a specified feedforward value to reduce the duty cycle of pulse currents 111a and 111b in order to increase the duty cycle of the charging signal used for the currently selected output voltage, thereby accelerating recovery from the undershoot condition. In some embodiments, the adjustment signal 109 is adjusted by adding the specified feedforward value. In other embodiments, the adjustment signal 109 is adjusted by multiplying by the specified feedforward value.

[0064] Figure 2 yes Figure 1 The flowchart illustrates the operation of the DC-DC converter 100 for charging Vout1 or Vout2. Vout1 is assumed to be the primary regulated output voltage, while Vout2 is another output voltage. In step 202, when the DC-DC converter 100 starts up, the initial values ​​of the duty cycles of the two output voltages Vout1 and Vout2 are set to, for example, pre-programmed values.

[0065] In step 204, comparator 104 determines whether to charge Vout1 or Vout2 based on which of Vout1 or Vout2 is less than its target voltage level.

[0066] In step 206, the ZCD module 118 and the pulse detection module 120 determine whether the DC-DC converter 100 is operating in CCM or DCM mode.

[0067] If the DC-DC converter 100 is operating in CCM mode, in step 208, the undershoot detection module 128 determines whether an undershoot condition exists. If not, the process proceeds to step 212. If an undershoot condition exists, in step 210, the adjustment module 108 increases the duty cycle of the currently selected output voltage based on a specified feedforward value.

[0068] In step 212, the regulation module 108 determines whether the currently selected output voltage is the first output voltage Vout1 of the main regulation. If Vout1 is currently selected, in step 214, the regulation signal 109 of Vout1, generated by the regulation module 108 based on the feedback charge signal Feedback_charge_sig and stored in the local memory, is applied to the PWM module 110 without any scaling. However, if Vout2 is currently selected, in step 216, the regulation module 108 generates the initial regulation signal 109 of Vout2 by scaling the stored regulation signal of Vout1 based on a specified fixed scaling factor. The regulation signal 109 of Vout2 is also stored in the local memory.

[0069] In either case, in step 218, the overshoot detection module 126 determines whether an overshoot condition exists. If not, the process returns to step 206 for the next charge-discharge cycle. If an overshoot condition exists, in step 220, OR gate 112 turns off switch P_SW, and AND gate 116 turns on switch N_SW to discharge inductor L until (i) the overshoot condition no longer exists or (ii) the current in inductor L becomes zero. The process then returns to step 206 for the next charge-discharge cycle.

[0070] If, in step 206, the ZCD module 118 and the pulse detection module 120 determine that the DC-DC converter 100 is operating in DCM mode, then in step 222, the undershoot detection module 128 determines whether an undershoot condition exists. If not, the process proceeds to step 224. If an undershoot condition exists, the process proceeds to step 230.

[0071] In step 224 (i.e., if no undershoot condition exists), the regulation module 108 determines whether the currently selected output voltage is the first output voltage Vout1 of the main regulation. If Vout1 is currently selected, then in step 226, the regulation module 108 retrieves the stored regulation signal from the previous charge-discharge cycle of Vout1 and generates a current regulation signal for Vout1 based on Feedback_charge_sig. If Vout2 is currently selected, then in step 228, the regulation module 108 retrieves the stored regulation signal from the previous charge-discharge cycle of Vout2 and generates a current regulation signal for Vout2 based on Feedback_charge_sig. The process then proceeds to step 236.

[0072] In step 230 (i.e., if an undershoot condition does exist), the regulation module 108 determines whether the currently selected output voltage is the first output voltage Vout1 of the main regulation. If Vout1 is currently selected, then in step 232, the regulation module 108 retrieves the stored regulation signal from the previous charge-discharge cycle of Vout1 and generates a current regulation signal for Vout1 based on Feedback_charge_sig, including adjusting the regulation signal based on the feedforward value. If Vout2 is currently selected, then in step 234, the regulation module 108 retrieves the stored regulation signal from the previous charge-discharge cycle of Vout2 and generates a current regulation signal for Vout2 based on Feedback_charge_sig, including adjusting the regulation signal based on the feedforward value. The process then proceeds to step 236.

[0073] In step 236, the overshoot detection module 126 determines whether an overshoot condition exists. If yes, the process proceeds to step 220 as described above. If no overshoot condition exists, in step 238, the ZCD module 118 and the pulse detection module 120 determine whether the DC-DC converter 100 is still operating in DCM mode. If yes, the process returns to step 206 for the next charge-discharge cycle. If not, the DC-DC converter 100 has just switched to CCM mode, and the process proceeds to step 240.

[0074] In step 240, the regulation module 108 generates an initial regulation signal for the currently selected output voltage Vout1 or Vout2, as the maximum value between (i) the regulation signal saved from the previous charge-discharge cycle of Vout1 and (ii) the regulation signal saved from the previous charge-discharge cycle of Vout2. Processing then proceeds to step 208 as described above. Because the duty cycle in DCM is smaller than that in CCM, a large voltage drop may occur at the output port when switching from DCM mode to CCM mode. Selecting the maximum duty cycle in step 240 helps to handle this transition with less output ripple.

[0075] Figure 3 yes Figure 1 The timing diagram shows an example of the operation of the DC-DC converter 100 during the transition from CCM mode to DCM mode for the output voltage Vout1 or Vout2. When the DC-DC converter 100 operates in CCM mode with a positive inductor current at time t0, DCM_mode_det is low, zcd_latch is low, and zcd_latch_b is high. During the inductor charging phase from time t0 to time t1, both PCTRL and NCTRL are low, and the inductor current rises.

[0076] The inductor discharge phase begins at time t1, with both PCTRL and NCTRL going high and the inductor current starting to decrease. Note that the time offset between the rising and falling edges of PCTRL and NCTRL is not specified in the original text. Figure 3 The Chinese side indicated that...

[0077] At time t2, the inductor current reaches zero, which causes zcd_batch to go high, zcd_batch_b to go low, DCM_mode_det to go high, NCTRL to go low, and PCTRL to remain high to prevent the inductor current from becoming negative. At time t3, zcd_latch returns to low.

[0078] With DCM_mode_det high, the inductor charging phase of the first full charge cycle in DCM mode begins at time t4, where PCTRL goes low, causing zcd_latch_b to go high and the inductor current to rise. The inductor discharging phase begins at time t5, where both PCTRL and NCTRL go high and the inductor current decreases. At time t6, the inductor current reaches zero again, causing zcd_batch to go high, zcd_batch_b to go low, NCTRL to go low, and PCTRL to remain high to prevent the inductor current from becoming negative. At time t7, zcd_latch returns low.

[0079] The time interval from t8 to t12 shows a similar inductor charging cycle in the DCM mode.

[0080] Figure 4 yes Figure 1 A timing diagram of example operation of the DC-DC converter 100 during the overshoot condition of the output voltage Vout1 or Vout2. When the DC-DC converter 100 operates in CCM mode with a positive inductor current at time t0, DCM_mode_det is low, zcd_latch is low, and zcd_latch_b is high. During the inductor charging phase from time t0 to time t1, both PCTRL and NCTRL are low, and the inductor current rises. At the start of the inductor discharging phase at time t1, both PCTRL and NCTRL go high, and the inductor current begins to decrease. Note the time offset between the rising and falling edges in PCTRL and NCTRL. Figure 4 This is indicated in the text. Similar CCM charging cycles occur from time t2 to time t4 and from time t4 to time t6.

[0081] During the next inductor charging phase starting at time t6, the DC-DC converter 100 detects an overshoot condition at the currently selected output voltage Vout1 or Vout2 at time t7. As a result, Overshoot_det_sig goes high, PCTRL and NCTRL are also driven high, and the inductor current begins to decrease.

[0082] At time t8, the inductor current reaches zero, causing zcd_latch to go high, zcd_latch_b to go low, and DCM_mode_det to go high. This, in turn, causes PCTRL to remain high and NCTRL to go low to prevent the inductor current from becoming negative. At time t9, zcd_latch is driven low.

[0083] At time t10, the DC-DC converter 100 determines that the overshoot condition at the currently selected output voltage no longer exists, causing Overshoot_det_sig to be driven low. This allows the next inductor charging phase to begin at time t10, with PCTRL going low and NCTRL remaining low, causing zcd_latch_b to go high. Two DCM charging cycles are shown from time t10 to time t12 and from time t12 to time t14. Note that the DCM duty cycle of the charging signal from time t10 to time t14 is greater than the CCM duty cycle of the charging signal from time t0 to time t6 to prevent the inductor current from reaching zero.

[0084] Figure 5 yes Figure 1 Timing diagram of example operation of DC-DC converter 100 during undershoot conditions of output voltage Vout1 or Vout2. Two normal CCM charging cycles occur from time t0 to time t2 and from time t2 to time t4.

[0085] During the next inductor charging phase starting at time t4, the DC-DC converter 100 detects an undershoot condition at the currently selected output voltage Vout1 or Vout2 at time t5. Consequently, Undershoot_det_sig goes high at time t5. As a result, for the next three charging cycles—from time t8 to time t10, from time t10 to time t13, and from time t13 to time t15—the duty cycle of the charging signal increases compared to the duty cycle of the charging signal from time t0 to time t8, in order to recover from the undershoot condition. Note that at time t11, the DC-DC converter 100 detects that the overshoot condition no longer exists (Undershoot_det_sig).

[0086] Although the regulation module 108 responds to a detected undershoot condition by adjusting the regulation signal 109 based on a specified feedforward value, in other embodiments, the DC-DC converter may handle the undershoot condition in other ways. For example, the load current may be sensed, and if the load current increases faster than a specified threshold level, the regulation module may increase the duty cycle of the charging signal more quickly in an attempt to prevent the undershoot condition from occurring.

[0087] Although the DC-DC converter 100 responds to detected overshoot conditions by cutting off the switch P_SW and intermittently turning on the switch N_SW, in other embodiments, the DC-DC converter may handle overshoot conditions in other ways. For example, the load current may be sensed, and if the load current decreases faster than a specified threshold level, the regulation module may reduce the duty cycle of the charging signal more quickly in an attempt to prevent overshoot conditions from occurring. Another option is to switch from DCM mode to CCM mode upon detection of an overshoot condition to allow negative current to flow through the inductor L to discharge the output capacitor used for the overshoot output voltage.

[0088] Although the invention has been described in the context of a DC-DC converter 100, wherein (i) it has an undershoot detection module 128, (ii) it has an overshoot detection module 126, (iii) it stores a duty cycle for subsequent use, and (iii) it handles CCM and DCM modes in different ways, in other embodiments, the DC-DC converter may be implemented without one or more of these features.

[0089] Although the invention has been described with respect to switches Vout1_SW, Vout2_SW and P_SW being p-type switches and switch N_SW being an n-type switch, those skilled in the art will understand that one or more of the p-type switches can be n-type switches, and / or an n-type switch can be a p-type switch, by making appropriate modifications to the circuitry controlling those switches.

[0090] Although already Figure 1 The invention is described in the context of a single-inductor dual-output buck DC-DC converter 100. Generally, the invention can be implemented in the context of single-inductor multi-output DC-DC converters with two or more outputs, as well as in the context of full-bridge, half-bridge, buck, boost, buck / boost, or any other suitable type of DC-DC converter, and AC-DC converters with an initial AC-DC conversion stage and a subsequent single-inductor multi-output DC-DC conversion stage.

[0091] References to "an embodiment" or "embodiment" herein mean that a particular feature, structure, or characteristic described in connection with that embodiment may be included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment, nor is it necessarily a separate or alternative embodiment that is mutually exclusive with other embodiments. The same applies to the term "implementation".

Claims

1. A single-inductor multi-output DC-DC converter, which converts a DC input voltage at an input port to at least a first output voltage and a second output voltage at corresponding first and second output ports, the DC-DC converter comprising: Inductor; At least a first capacitor and a second capacitor are respectively connected to the first output port and the second output port; Multiple switches, wherein the multiple switches selectively connect the input port to the first capacitor or the second capacitor via the inductor; as well as The regulating circuit that controls the switch, wherein: The regulating circuit determines whether the DC-DC converter operates in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). For the CCM mode, (i) the regulating circuit regulates the first output voltage, and (ii) the regulating circuit regulates the second output voltage according to the regulation of the first output voltage; and For the DCM mode, (i) the regulating circuit regulates the first output voltage independently of the regulation of the second output voltage, and (ii) the regulating circuit regulates the second output voltage independently of the regulation of the first output voltage; In the DCM mode, the regulation circuit (1) generates and saves (i) a first regulation signal for the first output voltage and (ii) a second regulation signal for the second output voltage; and (2) retrieves and uses the first regulation signal saved in (i) for the subsequent DCM charging period of the first output voltage and the second regulation signal saved in (ii) for the subsequent DCM charging period of the second output voltage.

2. The DC-DC converter according to claim 1, wherein, For the CCM mode, the regulation circuit (1) generates and stores the first regulation signal for the first output voltage, and (2) retrieves and uses the stored first regulation signal (i) for the subsequent CCM charging period of the first output voltage, and (ii) for the subsequent CCM charging period of the second output voltage.

3. The DC-DC converter according to claim 1, wherein: The regulating circuit detects whether there is an undershoot condition on the currently selected output voltage, and controls the switch differently depending on whether the undershoot condition is detected; as well as When the regulating circuit detects the undershoot condition, the regulating circuit controls the switch to increase the duty cycle of the charging signal for the currently selected output voltage more than if the undershoot condition were not detected.

4. The DC-DC converter according to claim 3, wherein, For both CCM mode and DCM mode, the regulation circuit detects the undershoot condition based on the currently selected output voltage rather than other output voltages.

5. The DC-DC converter according to claim 1, wherein: The regulating circuit detects overshoot conditions on the currently selected output voltage and controls the switch differently depending on whether the overshoot condition is detected. as well as When the regulating circuit detects the overshoot condition, the regulating circuit controls the switch to stop charging the currently selected output voltage from the input port until the overshoot condition is no longer present.

6. The DC-DC converter according to claim 5, wherein: For the CCM mode, the regulation circuit detects the overshoot condition based on the common-mode sensing voltage based on the first output voltage and the second output voltage; as well as In the DCM mode, the regulation circuit detects the overshoot condition based on the currently selected output voltage rather than other output voltages.

7. The DC-DC converter of claim 1, wherein the regulation circuit detects when the voltage at the inductor crosses zero to determine that the DC-DC converter is operating in the DCM mode.

8. The DC-DC converter according to claim 1, wherein: The adjustment circuit selects the output voltage that is relatively less sufficient between the first output voltage and the second output voltage as the currently selected output voltage to be adjusted. For the CCM mode, the adjustment circuit adjusts the currently selected output voltage based on the common-mode sensing voltage based on the first output voltage and the second output voltage; as well as In the DCM mode, the adjustment circuit adjusts the currently selected output voltage based on the currently selected output voltage rather than other output voltages.

9. The DC-DC converter according to claim 1, wherein: In the CCM mode, the adjustment circuit adjusts the first output voltage independently of the adjustment of the second output voltage; as well as In the CCM mode, the adjustment circuit adjusts the first output voltage according to the adjustment of the second output voltage.

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