Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes an antenna region and a winding region. The winding region is disposed on the antenna region, wherein the antenna region includes a first insulating layer and two or more second insulating layers, and a thickness of the first insulating layer is different from a thickness of the second insulating layers.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of manufacturing them, and more specifically, to semiconductor devices comprising antenna regions. Background Technology

[0002] The desire to reduce the size of semiconductor devices has been a constant. Miniaturization has significantly impacted semiconductor device design; specifically, it has a profound impact on wireless communication devices, such as radio frequency (RF) modules. As RF modules move towards higher frequency applications (such as 5G), their antenna regions need to be thicker to enable them to transmit over specific distances. However, a thicker antenna region cannot meet miniaturization requirements.

[0003] Furthermore, miniaturization significantly impacts the assembly stresses generated during the production of semiconductor devices, especially when the device contains multiple metal interconnects. These stresses can cause the semiconductor device to warp or even detach its die, resulting in poor electrical connections between the die and the interconnects.

[0004] Therefore, there is a need to provide semiconductor devices with novel antenna structures to reduce the assembly stress they generate and prevent poor electrical connections between the chip and the metal interconnect structure without compromising miniaturization and high frequency requirements. Summary of the Invention

[0005] In one aspect, a semiconductor device includes an antenna region and a winding region. The winding region is disposed on the antenna region, wherein the antenna region includes a first insulating layer and two or more second insulating layers, and the thickness of the first insulating layer is different from the thickness of the second insulating layers.

[0006] In one aspect, a semiconductor device includes an antenna region and an RF winding region. The RF winding region is disposed on the antenna region, wherein the RF winding region includes one or more first insulating layers and second insulating layers, and the thickness of the first insulating layer is different from the thickness of the second insulating layer.

[0007] In one aspect, a method of manufacturing a semiconductor device includes: providing a first antenna layer having a first surface and a second surface opposite to the first surface; disposing a second antenna layer adjacent to the second surface of the antenna layer, wherein the second antenna layer includes one or more second conductive vias; and disposing a first insulating layer adjacent to the first surface of the first antenna layer and opposite to the second antenna layer, wherein the first insulating layer includes one or more first conductive vias, wherein the first conductive vias are substantially shaped to match the second conductive vias through the first antenna layer. Attached Figure Description

[0008] Figure 1 A cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 A cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 3 A cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4 A cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 5 A cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 6 A cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0014] Figures 7A-7C Instructions for use in manufacturing, for example Figure 1 Methods for developing semiconductor devices.

[0015] Figures 7A-7D Instructions for use in manufacturing, for example Figure 2 Methods for developing semiconductor devices.

[0016] Figures 8A-8C Instructions for use in manufacturing, for example Figure 3 Methods for developing semiconductor devices.

[0017] Figures 9A-9E Instructions for use in manufacturing, for example Figure 4 Methods for developing semiconductor devices. Detailed Implementation

[0018] Unless otherwise stated, spatial descriptions such as “above,” “top,” and “bottom” are relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantage of the embodiments of this disclosure is not deviated from by such arrangement.

[0019] This disclosure provides an improved semiconductor device with an improved antenna structure that reduces warpage of the semiconductor device and meets miniaturization and high-frequency requirements.

[0020] Figure 1 A cross-sectional view illustrating a semiconductor device 100 according to an embodiment of the present disclosure. Figure 1The semiconductor device 100 includes an antenna region 102 and a routing zone 103.

[0021] Antenna region 102 can be applied to a semiconductor device that can operate at high frequencies. In some embodiments, antenna region 102 can be applied to a semiconductor device that can operate at frequencies in the range of about 2 GHz to about 300 GHz, about 5 GHz to about 300 GHz, about 10 GHz to about 300 GHz, about 15 GHz to about 300 GHz, about 20 GHz to about 300 GHz, about 25 GHz to about 300 GHz, about 30 GHz to about 300 GHz, about 35 GHz to about 300 GHz, about 40 GHz to about 300 GHz, or about 45 GHz to about 300 GHz.

[0022] Antenna region 102 includes a first insulating layer 101 and two or more second insulating layers 105, 120. The thickness and material of the first insulating layer 101 and the second insulating layers 105, 120 are determined depending on the desired function or nature of antenna region 102. For example, if antenna region 102 is designed to operate at high frequencies, such as in the range of 30 GHz to 300 GHz, then to reduce transmission loss and transmit over long distances, antenna region 102 should be thicker and / or contain materials with low dielectric constant and dielectric loss. However, as antenna region 102 becomes thicker, for example when through-holes are placed in antenna region 102 or circuitry is placed on antenna region 102, the cost becomes increasingly high and the process becomes increasingly difficult, requiring highly precise control and costly equipment. Furthermore, miniaturization requirements may not be met.

[0023] Therefore, in some embodiments, the first insulating layer 101 may have a thickness of about 180 μm to about 600 μm, about 190 μm to about 600 μm, about 200 μm to about 600 μm, about 210 μm to about 600 μm, about 220 μm to about 600 μm, about 230 μm to about 600 μm, about 240 μm to about 600 μm, about 250 μm to about 600 μm, about 260 μm to about 600 μm, about 270 μm to about 600 μm, or about 280 μm to about 600 μm. Thickness D1 of approximately 290 μm to approximately 600 μm, approximately 300 μm to approximately 600 μm, approximately 310 μm to approximately 600 μm, approximately 320 μm to approximately 600 μm, approximately 330 μm to approximately 600 μm, approximately 340 μm to approximately 600 μm, approximately 350 μm to approximately 600 μm, approximately 360 μm to approximately 600 μm, approximately 370 μm to approximately 600 μm, approximately 380 μm to approximately 600 μm, approximately 390 μm to approximately 600 μm, or approximately 400 μm to approximately 600 μm.

[0024] By forming a first insulating layer 101 having a thickness D1 within a specific range, the warpage of the semiconductor device can be reduced because a thicker insulating layer can provide greater strength to reduce stress caused by conventional structural arrangements of antennas, such as those with conventional insulating layers and vias, where the insulating layers have similar thicknesses and the vias are formed in the same direction.

[0025] The first insulating layer 101 has a first surface 101a and a second surface 101b opposite to the first surface 101a.

[0026] The first insulating layer 101 includes one or more first conductive vias 107a, 107b. The first conductive vias 107a, 107b can be formed by mechanical drilling or by laser drilling. In some embodiments, the first conductive vias 107a, 107b are through-holes formed by mechanical drilling, extending from a first surface 101a of the first insulating layer 101 to a second surface 101b of the first insulating layer 101, so that electrical signals can be transmitted from one side of the first insulating layer 101 to the other side. Alternatively, the first conductive vias 107a, 107b extend from the first surface 101a of the first insulating layer 101 but terminate before reaching the second surface 101b of the first insulating layer 101.

[0027] One or more first connecting elements 108a, 108b may be disposed adjacent to the first surface 101a of the first insulating layer 101. In some embodiments, the first connecting elements 108a, 108b are electrically connected to the first conductive vias 107a, 107b, respectively. The first connecting elements 108a, 108b may be solder pads and / or traces. Solder pads may be contact pads, such as traces. The first connecting elements 108a, 108b may contain, for example, one or a combination of copper, gold, indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel, or zinc or other metals or metal alloys.

[0028] One or more second connecting elements 114a, 114b may be disposed adjacent to the second surface 101b of the first insulating layer 101. In some embodiments, the second connecting elements 114a, 114b are electrically connected to the first conductive vias 107a, 107b, respectively. The second connecting elements 114a, 114b may be solder pads and / or traces. Solder pads may be contact pads, such as traces. The second connecting elements 114a, 114b may contain, for example, one or a combination of copper, gold, indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel, or zinc or other metals or metal alloys.

[0029] One or more solder pads and / or traces and one or more overlaid interconnect structures 117a, 117b may be disposed on the first surface 101a of the first insulating layer 101. The solder pads and / or traces 117a, 117b may be part of a circuit.

[0030] The first insulating layer 101 may comprise an insulating material or other suitable material having a low dielectric constant and / or low dielectric loss as a base material. In some embodiments, the first insulating layer 101 comprises polypropylene.

[0031] The second insulating layer 105 is disposed adjacent to the second surface 101b of the first insulating layer 101. The second insulating layer 105 has a second top surface 105a, a second bottom surface 105b opposite to the second top surface 105a, and a second thickness D2. Figure 1 As shown in the embodiment, the second insulating layer 105 is disposed above the second surface 101b of the first insulating layer 101.

[0032] The thickness D1 of the first insulating layer 101 is different from the thickness D2 of the second insulating layer 105. In some embodiments, the thickness D1 of the first insulating layer 101 is greater than the thickness D2 of the second insulating layer 105. By designing the first insulating layer 101 to have a thickness D1 greater than the thickness D2 of the second insulating layer 105 (or another insulating layer disposed above the second insulating layer 105), warpage of the semiconductor device caused by conventional antenna configurations can be mitigated because a thicker insulating layer can provide greater strength to reduce stress caused by conventional antenna structure arrangements, such as those using conventional insulating layers and vias as described above. In some embodiments, the thickness D2 of the second insulating layer 105 may be in the range of about 70 μm to about 200 μm, about 75 μm to about 195 μm, about 80 μm to about 190 μm, about 85 μm to about 185 μm, about 90 μm to about 180 μm, about 95 μm to about 175 μm, about 100 μm to about 170 μm, about 105 μm to about 165 μm, about 110 μm to about 160 μm, about 115 μm to about 155 μm, about 120 μm to about 145 μm, or about 125 μm to about 140 μm.

[0033] The second insulating layer 105 defines one or more openings 119a, 119b. Each opening 119a, 119b corresponds to a corresponding second conductive via 111a, 111b. The openings 119a, 119b have a first width W1 near the opening and a second width W2 near the bottom. In some embodiments, the openings 119a, 119b slope inwards and towards the bottom from the opening. Therefore, the openings 119a, 119b have a first width W1 greater than the second width W2. Consequently, the corresponding second conductive vias 111a, 111b formed therein will also have a first width W1 greater than the second width W2 (i.e., the corresponding second conductive vias 111a, 111b are formed by a shape that slopes inwards and towards the bottom from the opening). In some embodiments, the second conductive vias 111a, 111b are electrically connected to second connecting elements 114a, 114b.

[0034] One or more third connecting elements 112a, 112b may be disposed adjacent to the second top surface 105a of the second insulating layer 105. In some embodiments, the third connecting elements 112a, 112b are electrically connected to the second conductive vias 111a, 111b. The third connecting elements 112a, 112b may be solder pads and / or traces. Solder pads may be contact pads, such as traces. The third connecting elements 112a, 112b may comprise, for example, one or a combination of copper, gold, indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel, or zinc or other metals or metal alloys.

[0035] The second insulating layer 105 may comprise an insulating material or other suitable material having a low dielectric constant and / or low dielectric loss as a substrate material. In some embodiments, the second insulating layer 105 comprises polypropylene.

[0036] Antenna region 102 may include at least one first insulating layer 101 and at least one second insulating layer 105. In some embodiments, a plurality of first insulating layers 101 and a plurality of second insulating layers 105 are stacked together. In some embodiments, the first insulating layers 101 and the second insulating layers 105 are stacked alternately. In some embodiments, two or more first insulating layers 101 are stacked alternately with a single second insulating layer 105. In some embodiments, two or more second insulating layers 105 are stacked alternately with a single first insulating layer 101.

[0037] A winding region 103 is disposed on the antenna region 102. The winding region 103 may be an RF winding region. The winding region 103 includes two or more third insulating layers 106, 113. In some embodiments, the third insulating layers 106, 113 are disposed adjacent to the first insulating layer 101 and away from the second insulating layer 105. The third insulating layers 106, 113 have third top surfaces 106a, 113a, third bottom surfaces 106b, 113b respectively opposite to the third top surfaces 106a, 113b, and a third thickness D3.

[0038] The thickness D3 of the third insulating layers 106 and 113 differs from the thickness D1 of the first insulating layer 101. In some embodiments, the thickness D3 of the third insulating layers 106 and 113 is less than the thickness D1 of the first insulating layer 101. By designing the third insulating layers 106 and 113 to have a thickness D3 that is less than the thickness D1 of the first insulating layer 101, warping of the semiconductor device caused by conventional antenna configurations can be mitigated because a thicker insulating layer provides greater strength compared to a thinner insulating layer.

[0039] The thickness D3 of the third insulating layers 106, 113 may be substantially the same as or different from the thickness D2 of the second insulating layer 105. In some embodiments, the thickness D3 of the third insulating layers 106, 113 is substantially the same as the thickness D2 of the second insulating layer 105. By forming a third insulating layer 106, 113 having a thickness D3 that is substantially equal to or corresponds to the thickness D2 of the second insulating layer 105, the third insulating layer 106 can substantially match the thickness of the second insulating layer 105 through the first insulating layer 101. Therefore, semiconductor device warpage can be further mitigated because the antenna exhibits a more symmetrical structure compared to conventional antennas, which reduces stress caused by asymmetrical structures. In some embodiments, the thickness D3 of the third insulating layer 106, 113 may be in the range of about 70 μm to about 200 μm, about 75 μm to about 195 μm, about 80 μm to about 190 μm, about 85 μm to about 185 μm, about 90 μm to about 180 μm, about 95 μm to about 175 μm, about 100 μm to about 170 μm, about 105 μm to about 165 μm, about 110 μm to about 160 μm, about 115 μm to about 155 μm, about 120 μm to about 145 μm, or about 125 μm to about 140 μm.

[0040] The third insulating layer 106 defines one or more openings 104a, 104b. Each opening 104a, 104b corresponds to a corresponding third conductive via 109a, 109b. The openings 104a, 104b are defined by the shape and / or position such that the first insulating layer 101 substantially matches the openings 119a, 119b in the second insulating layer 105, such that the third conductive vias 109a, 109b formed in the openings 104a, 104b can substantially match the second conductive vias 111a, 111b in shape and / or position via the first insulating layer 101. The openings 104a, 104b have a third width W3 near the opening and a fourth width W4 near the bottom. In some embodiments, the openings 104a, 104b are inclined inward and towards the bottom from the opening. Therefore, the openings 104a, 104b have a third width W3 greater than the fourth width W4. Therefore, the corresponding third conductive vias 109a and 109b will also have a third width W3 greater than the fourth width W4 (i.e., the corresponding third conductive vias 109a and 109b are formed by a shape that slopes inward from the opening to the bottom). In some embodiments, the third conductive vias 109a and 109b are electrically connected to the first connecting elements 108a and 108b.

[0041] The third conductive vias 109a and 109b can be substantially matched in shape with the second conductive vias 111a and 111b via the first insulating layer 101 (i.e., both are inclined from the outside to the inside or from the opening to the bottom). The third conductive vias 109a and 109b can also be substantially matched in position with the second conductive vias 111a and 111b via the first insulating layer 101. Unlike the conventional design where all conductive vias are formed to be inclined in the same direction, this configuration of the third conductive vias 109a and 109b and the second conductive vias 111a and 111b of this disclosure can be achieved by arranging the third conductive vias and the second conductive vias in a more significantly symmetrical arrangement, for example, by arranging the third conductive vias and the second conductive vias in a substantially symmetrical shape via the first insulating layer 101 (e.g., as shown in the figure). Figure 1 (as shown in the diagram) or by placing the third conductive via at a position more significantly symmetrical to the second conductive via through the first insulating layer 101, or both, device warping or chip die detachment from the device that occurs in a conventional via configuration is mitigated.

[0042] The number of second insulating layers 105 may be the same as or different from the number of third insulating layers 106. In some embodiments, the number of second insulating layers 105 may be the same as the number of third insulating layers 106 to further improve the symmetry effect.

[0043] One or more fourth connecting elements 110a, 110b, 118a, 118b may be disposed adjacent to the third top surface 106a of the third insulating layer 106 of the winding region 103. In some embodiments, the fourth connecting elements 110a, 110b are electrically connected to third conductive vias 109a, 109b. The fourth connecting elements 110a, 110b may be solder pads and / or traces. Solder pads may be contact pads, such as those of traces. The fourth connecting elements 110a, 110b may comprise, for example, one or a combination of copper, gold, indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel, or zinc or other metals or metal alloys.

[0044] The third insulating layer 106 may comprise an insulating material or other suitable material having a low dielectric constant and / or low dielectric loss as a substrate material. In some embodiments, the third insulating layer 106 comprises polypropylene.

[0045] Figure 2 This illustration shows a cross-sectional view of a semiconductor device 200 according to an embodiment of the present disclosure. The semiconductor device 200 is similar to... Figure 1The semiconductor device described herein differs in that the fourth insulating layer 213 is disposed adjacent to the winding region 103. In some embodiments, the fourth insulating layer 213 is disposed adjacent to the third top surface 113a of the third insulating layer 113 and away from the first insulating layer 101. In some embodiments, the second insulating layer 105 is disposed adjacent to the first insulating layer 101 and away from the third insulating layer 106. In some embodiments, the second insulating layer 105 is disposed adjacent to the first insulating layer 101 and away from the fourth insulating layer 213.

[0046] The fourth insulating layer 213 has a fourth top surface 213a, a fourth bottom surface 213b opposite to the fourth top surface 213a, and a fourth thickness D4. For example... Figure 2 As shown in the embodiment, the fourth insulating layer 213 is disposed on the third insulating layer 113.

[0047] The thickness D4 of the fourth insulating layer 213 is different from the thickness D3 of the third insulating layer 113. The thickness D4 of the fourth insulating layer 213 may also be different from the thickness D1 of the first insulating layer 101. In some embodiments, the thickness D4 of the fourth insulating layer 213 is less than the thickness D3 of the third insulating layer 113. In some embodiments, the thickness D4 of the fourth insulating layer 213 is less than the thickness D1 of the first insulating layer 101. In some embodiments, the thickness D4 of the fourth insulating layer 213 is less than the thickness D2 of the second insulating layer 105. In some embodiments, the thickness D4 of the fourth insulating layer 213 is less than the thickness D1 of the first insulating layer 101 and the thickness D3 of the third insulating layer 106.

[0048] By designing the third insulating layers 106, 113 to have a thickness D3 greater than the thickness D4 of the fourth insulating layer 213 (or another insulating layer disposed above the fourth insulating layer 213), antenna device warping in conventional antenna configurations can be mitigated. This is because a thicker insulating layer provides greater strength compared to a thinner insulating layer, thereby reducing the stress caused by conventional antenna arrangements of insulating layers and vias. In some embodiments, the thickness D4 of the fourth insulating layer 213 may be in the range of about 30 μm to about 150 μm, about 30 μm to about 145 μm, about 30 μm to about 140 μm, about 30 μm to about 135 μm, about 30 μm to about 130 μm, about 30 μm to about 125 μm, about 30 μm to about 120 μm, about 30 μm to about 115 μm, about 30 μm to about 110 μm, about 30 μm to about 105 μm, or about 30 μm to about 100 μm.

[0049] The fourth insulating layer 213 defines one or more openings 218a, 218b. Each opening 218a, 218b corresponds to a corresponding fourth conductive via 215a, 215b. In some embodiments, the openings 218a, 218b are inclined inwards and to the bottom. Therefore, the corresponding fourth conductive vias 215a, 215b will also be shaped to be inclined inwards and to the bottom. The openings 218a, 218b are defined by the shape and / or position such that the first insulating layer 101 generally corresponds to the openings 119a, 119b in the second insulating layer 105, such that the fourth conductive vias 215a, 215b formed in the openings 218a, 218b can be substantially matched in shape and / or position by the first insulating layer 101 to the second conductive vias 111a, 111b. The openings 218a and 218b may also be defined by the following shape and / or position: substantially the same as the openings 104a and 104b in the third insulating layer 106, such that the fourth conductive vias 215a and 215b may be substantially the same in shape and / or position as the third conductive vias 109a and 109b in the third insulating layer 106.

[0050] One or more fifth connecting elements 216a, 216b may be disposed adjacent to the fourth top surface 213a of the fourth insulating layer 213. In some embodiments, the fifth connecting elements 216a, 216b are electrically connected to the fourth conductive vias 215a, 215b. The fifth connecting elements 216a, 216b may be solder pads and / or traces. Solder pads may be contact pads, such as traces. The fifth connecting elements 216a, 216b may comprise, for example, one or a combination of copper, gold, indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel, or zinc or other metals or metal alloys.

[0051] The fourth insulating layer 213 may be a portion of a stack of layers having substantially the same or different thicknesses, or a portion of a winding region. In some embodiments, the fourth insulating layer 213 is a portion of a second winding region or a portion of a second RF winding region.

[0052] Figure 3 A cross-sectional view illustrating a semiconductor device 300 according to an embodiment of the present disclosure. Figure 3 The semiconductor device 300 includes an antenna region 302, a winding region 303, a first protective layer 317, and a second protective layer 319.

[0053] Antenna region 302 can be applied to a semiconductor device that can operate at high frequencies. In some embodiments, antenna region 302 can be applied to a semiconductor device that can operate at frequencies in the range of about 2 GHz to about 300 GHz, about 5 GHz to about 300 GHz, about 10 GHz to about 300 GHz, about 15 GHz to about 300 GHz, about 20 GHz to about 300 GHz, about 25 GHz to about 300 GHz, about 30 GHz to about 300 GHz, about 35 GHz to about 300 GHz, about 40 GHz to about 300 GHz, or about 45 GHz to about 300 GHz.

[0054] Antenna region 302 includes a first insulating layer 301 and a second insulating layer 305. The thickness and material of the first insulating layer 301 and the second insulating layer 305 are determined depending on the desired function or nature of antenna region 302. For example, if antenna region 302 is designed to operate at high frequencies in the range of 30 GHz to 300 GHz, and to reduce transmission loss and transmit over long distances, then antenna region 302 should be thicker and / or contain materials with low dielectric constant and dielectric loss. However, as antenna region 302 becomes thicker, for example when placing through-holes or circuitry in antenna region 302, the cost becomes increasingly high and the process becomes increasingly difficult, requiring highly precise control and costly equipment. Furthermore, miniaturization requirements may not be met. The thickness of the first insulating layer 301 and the thickness of the second insulating layer 305 may be approximately the same or different depending on the desired function of antenna region 302.

[0055] In some embodiments, the first insulating layer 301 may have a thickness D5 of about 90 μm to about 300 μm, about 100 μm to about 290 μm, about 110 μm to about 280 μm, about 120 μm to about 270 μm, about 130 μm to about 260 μm, about 140 μm to about 250 μm, about 150 μm to about 240 μm, about 160 μm to about 230 μm, about 170 μm to about 220 μm, or about 180 μm to about 210 μm.

[0056] One or more first connecting elements 308a, 308b, 308c may be disposed adjacent to the top surface of the first insulating layer 301 for electrical connection. The first connecting elements 308a, 308b, 308c may be solder pads and / or traces. Solder pads may be, for example, contact pads of traces. The first connecting elements 308a, 308b, 308c may comprise, for example, one or a combination of copper, gold, indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel, or zinc or other metals or metal alloys.

[0057] The first insulating layer 301 may comprise an insulating material or other suitable material having a low dielectric constant and / or low dielectric loss as a substrate material. In some embodiments, the first insulating layer 301 comprises polypropylene.

[0058] The second insulating layer 305 is disposed adjacent to the bottom surface of the first insulating layer 301. In some embodiments, the first insulating layer 301 and the second insulating layer 305 in the antenna region 302 are disposed close to each other. In some embodiments, the first insulating layer 301 and the second insulating layer 305 are stacked together without any layer disposed therebetween. In some embodiments, the first insulating layer 301 and the second insulating layer 305 are stacked together without any metal layer disposed therebetween. The first insulating layer 301 and the second insulating layer 305 may be as follows: Figure 1 The embodiment shown includes a conductive via. Alternatively, the first insulating layer 301 and the second insulating layer 305 may be as follows: Figure 3 The embodiments shown do not include conductive vias.

[0059] In some embodiments, the thickness D5 of the second insulating layer 305 is approximately the same as the thickness D5 of the first insulating layer 301. The thickness D5 of the second insulating layer 305 and the thickness D5 of the first insulating layer 301 should be considered together and determined depending on the thickness requirements of the antenna region 302.

[0060] One or more second connecting elements 314 may be disposed adjacent to the top surface of the second insulating layer 305 for electrical connection. The second connecting element 314 may be a solder pad and / or a trace. The solder pad may be, for example, a contact pad for a trace. The second connecting element 314 may contain, for example, one or a combination of copper, gold, indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel, or zinc, or other metals or metal alloys.

[0061] The second insulating layer 305 may comprise an insulating material or other suitable material having a low dielectric constant and / or low dielectric loss as a substrate material. In some embodiments, the second insulating layer 305 comprises polypropylene.

[0062] The winding region 303 is disposed on the antenna region 302. The winding region 303 includes at least one third insulating layer 306 and at least one fourth insulating layer 313.

[0063] The third insulating layer 306 is disposed adjacent to the first insulating layer 301 and away from the second insulating layer 305. The third insulating layer 306 has a third thickness D3* and includes one or more third conductive vias 309a, 309b, and 309c.

[0064] The thickness D3* of the third insulating layer 306 is different from the thickness D5 of the first insulating layer 301. In some embodiments, the thickness D3* of the third insulating layer 306 is less than the thickness D5 of the first insulating layer 301. By designing the third insulating layer 306 to have a thickness D3* that is less than the thickness D5 of the first insulating layer 301, warping of the semiconductor device caused by conventional antenna configurations can be mitigated because a thicker insulating layer is provided and a thicker insulating layer provides greater strength compared to a thinner insulating layer.

[0065] In some embodiments, the thickness D3* of the third insulating layer 306 may be in the range of about 70 μm to about 200 μm, about 75 μm to about 195 μm, about 80 μm to about 190 μm, about 85 μm to about 185 μm, about 90 μm to about 180 μm, about 95 μm to about 175 μm, about 100 μm to about 170 μm, about 105 μm to about 165 μm, about 110 μm to about 160 μm, about 115 μm to about 155 μm, about 120 μm to about 145 μm, or about 125 μm to about 140 μm.

[0066] A fourth insulating layer 313 is disposed adjacent to the third insulating layer 306. In some embodiments, the fourth insulating layer 313 is disposed adjacent to the top surface of the third insulating layer 306 and away from the first insulating layer 301. The fourth insulating layer 213 has a fourth thickness D4* and includes one or more second conductive vias 315a, 315b.

[0067] The thickness D4* of the fourth insulating layer 313 may be approximately the same as or different from the thickness D3* of the third insulating layer 306. The thickness D4* of the fourth insulating layer 313 may also be different from the thickness D5 of the first insulating layer 301. In some embodiments, the thickness D4* of the fourth insulating layer 313 is less than the thickness D3* of the third insulating layer 306. In some embodiments, the thickness D4* of the fourth insulating layer 313 is approximately the same as the thickness D3* of the third insulating layer 306.

[0068] In some embodiments, the thickness D4 of the fourth insulating layer 213 may be in the range of about 30 μm to about 150 μm, about 30 μm to about 145 μm, about 30 μm to about 140 μm, about 30 μm to about 135 μm, about 30 μm to about 130 μm, about 30 μm to about 125 μm, about 30 μm to about 120 μm, about 30 μm to about 115 μm, about 30 μm to about 110 μm, about 30 μm to about 105 μm, or about 30 μm to about 100 μm.

[0069] The first conductive vias 309a, 309b, and 309c in the third insulating layer 306 may be formed with a shape having a different orientation than the second conductive vias 315a and 315b in the fourth insulating layer 313. In some embodiments, the first conductive vias 309a, 309b, and 309c are formed with a shape that slopes inward from the bottom to the opening, and the second conductive vias 315a and 315b are formed with a shape that slopes inward from the opening to the bottom. In some embodiments, the first conductive vias 309a, 309b, and 309c are shaped to match the second conductive vias 315a and 315b at the interface between the third insulating layer 306 and the fourth insulating layer 313. In some embodiments, the first conductive vias 309a, 309b, and 309c and the second conductive vias 315a and 315b are formed at alternating positions. In some embodiments, first conductive vias 309a, 309b, and 309c are electrically connected to first connecting elements 308a, 308b, and 308c disposed adjacent to the surface of the first insulating layer 301, and the winding region 303 is electrically connected to the antenna region 302 via the first conductive vias 309a, 309b, and 309c connected to the first connecting elements 308a, 308b, and 308c. In some embodiments, the winding region 303 may be electrically connected via fourth connecting elements 316a and 316b disposed adjacent to the surface of the fourth insulating layer 313. In some embodiments, second conductive vias 315a and 315b are electrically connected to third connecting elements 310a and 310b and fourth connecting elements 316a and 316b.

[0070] A first protective layer 317 is disposed adjacent to the top surface of the fourth insulating layer 313. In some embodiments, the first protective layer 317 covers a portion of the top surface of the fourth insulating layer 313. The first protective layer 317 may define at least one opening exposing at least a portion of the fourth connecting elements 316a, 316b for external electrical connection, such as connection to a copper pillar, solder, or cylindrical bump. Alternatively, the first protective layer 317 may completely cover the fourth connecting elements 316a, 316b. The first protective layer 317 may be, for example, a solder mask (made of, for example, PI) or a passivation layer (made of, for example, a metal oxide).

[0071] A second protective layer 319 is disposed adjacent to the top surface of the second insulating layer 305. In some embodiments, the second protective layer 319 covers a portion of the top surface of the second insulating layer 305. The second protective layer 319 may completely cover the second connecting element 314. Alternatively, the second protective layer 319 may define at least one opening exposing at least a portion of the second connecting element 314 for external electrical connection, such as connection to a copper pillar, solder, or cylindrical bump. The second protective layer 319 may be, for example, a solder mask (made of, for example, PI) or a passivation layer (made of, for example, a metal oxide).

[0072] Figure 4 This illustration shows a cross-sectional view of a semiconductor device 400 according to an embodiment of the present disclosure. The semiconductor device 400 is similar to... Figure 3 The semiconductor device described herein differs in that the first conductive vias 409a, 409b, and 409c in the third insulating layer 403 may be formed by a shape inclined in substantially the same direction as the second conductive vias 415a and 415b in the fourth insulating layer 413. In some embodiments, the first conductive vias 409a, 409b, and 409c are formed by a shape inclined inward and towards the bottom from the opening, and the second conductive vias 415a and 415b are also formed by a shape inclined inward and towards the bottom from the opening.

[0073] Figure 5 This illustration shows a cross-sectional view of a semiconductor device 500 according to an embodiment of the present disclosure. The semiconductor device 500 is similar to... Figure 1 The semiconductor device described herein differs in that the first conductive vias 507a and 507b are formed in an X or X-like shape to further alleviate device warping caused by stress in the trace layer of the conventional antenna structure above (due to the high via density in the trace layer). This is because the X or X-like shape in the antenna region can provide greater strength and effectiveness, similar to a rivet. In some embodiments, the first conductive vias 507a and 507b in an X or X-like shape can be formed by laser drilling.

[0074] Figure 6 This illustration shows a cross-sectional view of a semiconductor device 600 according to an embodiment of the present disclosure. The semiconductor device 600 is similar to... Figure 2 The semiconductor device described herein differs in that it provides a second winding region 603, a semiconductor component 631, a first protective layer 625, and a second protective layer 619.

[0075] The second winding region 603 is disposed adjacent to the first winding region 103. In some embodiments, the second winding region 603 is disposed adjacent to the top surface of the first winding region 103. The second winding region 603 may include one or more fourth insulating layers 613, 621, 623 having a thickness substantially the same as the thickness D4 described above. In some embodiments, the second winding region 603 includes three fourth insulating layers 613, 621, 623. The fourth insulating layers 613, 621, 623 may include one or more conductive vias 627, 629, and one or more connecting elements 628, 630 may be disposed on the surface of the fourth insulating layers 613, 621, 623 for electrical connections between layers or to the external environment.

[0076] Semiconductor component 631 is disposed adjacent to the top surface of the second winding region 603. Semiconductor component 631 can be any semiconductor component, including, for example, a chip, package, interposer, or a combination thereof. Figure 6In the embodiment shown, the semiconductor component 631 includes at least one solder pad 632.

[0077] The solder pad 632 is disposed adjacent to the surface of the semiconductor component 631. The solder pad 632 may be, for example, a contact pad for a trace. The solder pad 632 may contain, for example, copper, gold, indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel or zinc, other metals, metal alloys, or combinations of two or more thereof.

[0078] A first protective layer 625 is disposed adjacent to the top surface of the second winding region 603. In some embodiments, the first protective layer 625 covers a portion of the top surface of the fourth insulating layer 623 and encapsulates the semiconductor assembly 631. The first protective layer 625 may define at least one opening exposing at least a portion of the connection element 630 for external electrical connection, such as connection to a copper pillar, solder, or cylindrical bump. Alternatively, the first protective layer 625 may completely cover the connection element 630. Figure 6 In the illustrated embodiment, the first protective layer 625 defines at least one opening that exposes at least a portion of the connecting element 630 for electrical connection to solder. The first protective layer 625 may be, for example, a solder mask (made of, for example, PI) or a passivation layer (made of, for example, a metal oxide).

[0079] A second protective layer 619 is disposed adjacent to the top surface of the antenna region 102. In some embodiments, the second protective layer 619 covers a portion of the top surface of the antenna region 102. The second protective layer 619 may completely cover the third connecting element 112a. Alternatively, the second protective layer 619 may define at least one opening exposing at least a portion of the third connecting element 112a for external electrical connection, such as connection to a copper pillar, solder, or cylindrical bump. The second protective layer 619 may be, for example, a solder mask (made of, for example, PI) or a passivation layer (made of, for example, a metal oxide).

[0080] Figures 7A-7C Instructions for use in manufacturing, for example Figure 1 A method for using a semiconductor device 100. Figures 7A-7D Instructions for use in manufacturing, for example Figure 2 Method of semiconductor device 200.

[0081] refer to Figure 7AA first antenna layer 101 with a thickness D1 is provided. The first antenna layer 101 has a first surface 101a and a second surface 101b opposite to the first surface 101a. Additionally, the first antenna layer 101 includes one or more antenna conductive vias 107a, 107b. One or more first antenna connection elements 108a, 108b are provided on the first surface 101a, and one or more second antenna connection elements 114a, 114b are provided on the second surface 101b of the first antenna layer 101. One or more pads and / or traces and one or more overlaid interconnect structures 117a, 117b are provided on the surface of the first antenna layer 101. The compartments or antenna conductive vias 107a, 107b can be formed by mechanical drilling or laser drilling (or etching) and electroplating. In some embodiments, the antenna conductive vias 107a, 107b are through-holes formed by mechanical drilling. In some embodiments, the antenna conductive vias 107a and 107b are X-shaped or X-like shapes formed by laser drilling.

[0082] refer to Figure 7B The second antenna layer 105 is disposed adjacent to the second surface 101b of the first antenna layer 101, which has a thickness D2. The thickness D1 of the first insulating layer 101 is different from the thickness D2 of the second insulating layer 105. In some embodiments, the thickness D1 of the first insulating layer 101 is greater than the thickness D2 of the second insulating layer 105. The second antenna layer 105 has or defines one or more openings 119a, 119b having a first width W1 near the opening and a second width W2 near the bottom to expose the second antenna connection elements 114a, 114b. Each opening 119a, 119b corresponds to a corresponding second conductive via 111a, 111b. The openings 119a, 119b have a first width W1 greater than the second width W2. Therefore, the corresponding second conductive vias 111a, 111b will also have a first width W1 greater than the second width W2.

[0083] Third connecting elements 112a and 112b are disposed adjacent to the second top surface 105a of the second antenna layer 105. In some embodiments, the third connecting elements 112a and 112b are electrically connected to the second conductive vias 111a and 111b and may be pads and / or traces. In some embodiments, openings 119a and 119b may be formed by, for example, wire cutting, etching, or other suitable processes. The second conductive vias 111a and 111b may be formed by electroplating. In some embodiments, the second conductive vias 111a and 111b may be formed by forming openings 119a and 119b with opposite directions in the antenna layer, and by forming a shape inclined in a direction different from that of the antenna conductive vias 107a and 107b. The second conductive vias 111a and 111b may be formed by electroplating.

[0084] A first insulating layer 106 is disposed adjacent to a first surface 101a of a first antenna layer 101 having a thickness D3 and opposite to a second antenna layer 105. The first insulating layer 106 has or defines one or more openings 104a, 104b having a third width W3 near the opening and a fourth width W4 near the bottom to expose first antenna connection elements 108a, 108b. Each opening 104a, 104b corresponds to a corresponding third conductive via 109a, 109b. The openings 104a, 104b are defined by the shape and / or position of openings 119a, 119b in the second antenna layer 105, which substantially match the shape of the openings 119a, 119b in the first antenna layer 101. The openings 104a, 104b have a third width W3 greater than the fourth width W4. Therefore, the corresponding third conductive vias 109a, 109b will also have a third width W3 greater than the fourth width W4. Fourth connection elements 110a, 110b are disposed adjacent to a first top surface 106a of the first insulating layer 106. In some embodiments, the fourth connecting elements 110a, 110b are electrically connected to the third conductive vias 109a, 109b and may be pads and / or traces. In some embodiments, the openings 104a, 104b may be formed by, for example, wire cutting, etching or other suitable processes. The third conductive vias 109a, 109b may be formed by electroplating.

[0085] The first insulating layer 106 and the second antenna layer 105 can be disposed using the same process or using different processes. In some embodiments, the first insulating layer 106 and the second antenna layer 105 are disposed using the same process.

[0086] refer to Figure 7C The third antenna layer 120 is disposed adjacent to the second top surface 105a of the second antenna layer 105, which has a thickness D2. The components and processes for forming the third antenna layer 120 are similar to those for forming the second antenna layer 105.

[0087] The second insulating layer 113 is disposed adjacent to the first top surface 106a of the first insulating layer 106 having a thickness D3 and opposite to the third antenna layer 120. The thickness D3 of the third insulating layer 106 is different from the thickness D1 of the first insulating layer 101. In some embodiments, the thickness D3 of the third insulating layer 106 is less than the thickness D1 of the first insulating layer 101. The components and processes for forming the second insulating layer 113 are similar to those for forming the first insulating layer 106. In some embodiments, the third antenna layer 120 and the second insulating layer 113 are disposed in the same process.

[0088] refer to Figure 7DA third insulating layer 213 is disposed adjacent to the second top surface 113a of a second insulating layer 113 having a thickness D4. The thickness D4 of the third insulating layer 213 is different from the thickness D3 of the second insulating layer 113. In some embodiments, the thickness D4 of the third insulating layer 213 is less than the thickness D3 of the second insulating layer 113. The third insulating layer 213 defines one or more openings 218a, 218b. Each opening 218a, 218b corresponds to a corresponding fourth conductive via 215a, 215b. The openings 218a, 218b are defined by the shape and / or position of the openings 119a, 119b in the second antenna layer 105, which are generally corresponding to those in the first antenna layer 101, such that the fourth conductive vias 215a, 215b formed in the openings 218a, 218b can generally match the second conductive vias 111a, 111b in shape and / or position through the first antenna layer 101. The components and processes for forming the third insulating layer 213 are similar to those for forming the second insulating layer 113.

[0089] Fifth connecting elements 216a and 216b are disposed adjacent to the fourth top surface 213a of the third insulating layer 213. In some embodiments, the fifth connecting elements 216a and 216b are electrically connected to the fourth conductive vias 215a and 215b. The fifth connecting elements 216a and 216b may be formed, for example, by photolithography combined with etching and electroplating or physical vapor deposition.

[0090] Figures 8A-8C Instructions for use in manufacturing, for example Figure 3 The method of the semiconductor device 300.

[0091] refer to Figure 8A A third insulating layer 306 is provided. The third insulating layer 306 has a third thickness D3* and one or more third conductive vias 309a, 309b, 309c. Additionally, one or more first connecting elements 308a, 308b, 308c and one or more third connecting elements 310a, 310b may be provided on the surface of the third insulating layer 306. In some embodiments, the first conductive vias 309a, 309b, 309c are electrically connected to the first connecting elements 308a, 308b, 308c. The first conductive vias 309a, 309b, 309c may be formed, for example, by laser drilling combined with electroplating or physical vapor deposition. The first connecting elements 308a, 308b, 308c and the third connecting elements 310a, 310b may be formed, for example, by photolithography combined with etching and electroplating or physical vapor deposition.

[0092] refer to Figure 8BA fourth insulating layer 313 is disposed adjacent to the third insulating layer 306. In some embodiments, the third insulating layer 306 and the fourth insulating layer 313 may form a first winding region 303. The fourth insulating layer 313 has a fourth thickness D4* and one or more second conductive vias 315a, 315b. Additionally, one or more fourth connecting elements 316a, 316b may be provided on the surface of the fourth insulating layer 313. In some embodiments, the second conductive vias 315a, 315b are electrically connected to the third connecting elements 310a, 310b. The second conductive vias 315a, 315b may be formed, for example, by laser drilling combined with electroplating or physical vapor deposition. The fourth connecting elements 316a, 316b may be formed, for example, by photolithography combined with etching and electroplating or physical vapor deposition.

[0093] Additionally, a first winding region 303 is disposed on a surface adjacent to the antenna region 302. The antenna region 302 may include two or more insulating layers 301, 305 having substantially the same thickness. One or more second connecting elements 314 may be provided on the surface of the antenna region 302 for electrical connection. The second connecting elements 314 may be formed, for example, by a combination of photolithography, etching, and electroplating or physical vapor deposition.

[0094] refer to Figure 8C The first protective layer 317 is disposed adjacent to the top surface of the first winding region 303. Figure 8C In the embodiment described herein, the first protective layer 317 covers a portion of the top surface of the fourth insulating layer 313 and defines at least one opening that exposes at least a portion of the fourth connecting elements 316a, 316b for external electrical connection, such as connection to a copper pillar, solder, or cylindrical bump.

[0095] The second protective layer 319 is disposed on the top surface adjacent to the antenna region 302. Figure 8C In the embodiment described herein, the second protective layer 319 covers a portion of the top surface of the antenna region 302 and completely covers the second connecting element 314.

[0096] Figures 9A-9E Instructions for use in manufacturing, for example Figure 4 The method of the semiconductor device 400.

[0097] refer to Figure 9A An antenna region 302 is provided. The antenna region 302 includes a first insulating layer 301 and a second insulating layer 305 having a thickness D5.

[0098] refer to Figure 9B One or more first connecting elements 308a, 308b, 308c are disposed adjacent to the surface of antenna region 302. The first connecting elements 308a, 308b, 308c can be formed, for example, by photolithography combined with etching and electroplating or physical vapor deposition.

[0099] refer to Figure 9C A third insulating layer 403 is disposed adjacent to the top surface of the antenna region 302. The third insulating layer 403 has a third thickness D3* and one or more first conductive vias 409a, 409b, 409c. One or more third connecting elements 310a, 310b may be provided on the surface of the third insulating layer 403. In some embodiments, the first conductive vias 409a, 409b, 409c are electrically connected to the third connecting elements 310a, 310b and the first connecting elements 308a, 308b, 308c. The first conductive vias 409a, 409b, 409c may be formed, for example, by laser drilling combined with electroplating or physical vapor deposition. The third connecting elements 310a, 310b may be formed, for example, by photolithography combined with etching and electroplating or physical vapor deposition.

[0100] refer to Figure 9D A fourth insulating layer 413 is disposed adjacent to the top surface of the third insulating layer 403. The fourth insulating layer 413 has a fourth thickness D4* and one or more second conductive vias 415a, 415b. One or more fourth connecting elements 316a, 316b may be provided on the surface of the fourth insulating layer 413. In some embodiments, the second conductive vias 415a, 415b are electrically connected to the third connecting elements 310a, 310b and the fourth connecting elements 316a, 316b. The second conductive vias 415a, 415b may be formed, for example, by laser drilling combined with electroplating or physical vapor deposition. The fourth connecting elements 316a, 316b may be formed, for example, by photolithography combined with etching and electroplating or physical vapor deposition.

[0101] refer to Figure 9E The first protective layer 417 is disposed adjacent to the top surface of the first winding region 303. Figure 9E In the embodiment described herein, the first protective layer 417 covers a portion of the top surface of the fourth insulating layer 413 and defines at least one opening that exposes at least a portion of the fourth connecting elements 316a, 316b for external electrical connection, such as connection to a copper pillar, solder, or cylindrical bump.

[0102] Additionally, a second protective layer 419 is disposed adjacent to the top surface of the antenna region 302. Figure 9E In the embodiment described herein, the second protective layer 419 covers a portion of the top surface of the antenna region 302 and completely covers the second connecting element 314.

[0103] As used herein and unless otherwise defined, the terms “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or situation, the terms may cover situations where the event or situation has clearly occurred and situations where the event or situation is very close to occurring. For example, when used in conjunction with numerical values, the terms may cover a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, a straight line or plane may be substantially flat if the peak or depression is no greater than 5 μm, no greater than 1 μm, or no greater than 0.5 μm.

[0104] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. The drawings may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual apparatus due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically described. This specification and the drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A semiconductor device comprising: Antenna area; and A winding region disposed on the antenna region, wherein the antenna region includes a first insulating layer and two or more second insulating layers, and the thickness of the first insulating layer is different from the thickness of the second insulating layers, wherein the winding region includes two or more third insulating layers disposed adjacent to the first insulating layer and opposite to the second insulating layer, and the thickness of the third insulating layer is less than the thickness of the first insulating layer, wherein the winding region includes a fourth insulating layer disposed adjacent to the third insulating layer, and the thickness of the fourth insulating layer is different from the thickness of the third insulating layer.

2. The semiconductor device of claim 1, wherein the first insulating layer is closer to the winding region than the second insulating layer, and the thickness of the first insulating layer is greater than the thickness of the second insulating layer.

3. The semiconductor device of claim 1, wherein the thickness of the third insulating layer is equal to the thickness of the second insulating layer.

4. The semiconductor device of claim 1, wherein the third insulating layer is closer to the first insulating layer than the fourth insulating layer, and the thickness of the fourth insulating layer is less than the thickness of the third insulating layer.

5. The semiconductor device of claim 4, wherein the thickness of the fourth insulating layer is less than the thickness of the second insulating layer.

6. The semiconductor device of claim 1, wherein the number of the second insulating layers is equal to the number of the third insulating layers.

7. The semiconductor device of claim 1, wherein the second insulating layer includes one or more second conductive vias, the third insulating layer includes one or more third conductive vias, and the third conductive vias are shaped to match the second conductive vias through the first insulating layer.

8. The semiconductor device of claim 7, wherein the fourth insulating layer includes one or more fourth conductive vias, and the shape of the fourth conductive via is the same as the shape of the third conductive via.

9. The semiconductor device of claim 8, wherein the first insulating layer includes one or more first conductive vias, wherein the shape of the first conductive via is different from that of the second conductive via and the third conductive via.

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