Semiconductor device and method of manufacturing semiconductor device

Abstract

Semiconductor devices and methods of manufacturing semiconductor devices. In one example, a semiconductor device includes a substrate including a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture and the first conductor includes a partial via that contacts an underfill of the second conductor through the aperture; an electronic device having an interconnect electrically coupled to the first conductor; and an encapsulant on a top side of the substrate, the encapsulant contacting a side of the electronic device. Other examples and related methods are also disclosed herein.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to electronic devices, and more particularly to semiconductor devices and methods for manufacturing semiconductor devices. BACKGROUND

[0002] Existing semiconductor packages and methods for forming semiconductor packages suffer from deficiencies, such as resulting in excessive cost, reduced reliability, relatively low performance, or too large a package size. Additional limitations and disadvantages of such methods will become apparent to one of ordinary skill in the art through comparison of such methods with the present disclosure, and by reference to the figures. SUMMARY

[0003] In one example, a semiconductor device includes a substrate including a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture and the first conductor includes a partial via that contacts a pad of the second conductor through the aperture; an electronic device having an interconnect electrically coupled to the first conductor; and an encapsulant on a top side of the substrate, the encapsulant contacting a side of the electronic device.

[0004] In the semiconductor device of the example, the substrate includes a third conductor on the top side of the dielectric and a fourth conductor on the bottom side of the dielectric, wherein the dielectric has a further aperture and the third conductor includes a partial via that contacts a pad of the fourth conductor through the further aperture.

[0005] The semiconductor device of the example further includes a trace between the partial via of the first conductor and the partial via of the third conductor on the dielectric.

[0006] In the semiconductor device of the example, an end of the partial via of the first conductor and an end of the partial via of the third conductor are spaced apart by 30 microns or less.

[0007] In the semiconductor device of the example, the first conductor includes a first trace on the top side of the dielectric and continuous with the partial via; and a width of the first trace and the partial via are the same.

[0008] In the semiconductor device in the described examples, an end of the partial via contacts the pad of the second conductor; and a trace adjacent to the end of the partial via overlaps a portion of the pad of the second conductor that is not covered by the partial via.

[0009] In the semiconductor device in the described examples, the trace overlaps a portion of a gap between the pad of the second conductor and an adjacent pad.

[0010] In the semiconductor device in the described examples, the partial via comprises a linear shape.

[0011] In the semiconductor device in the described examples, the partial via comprises a semi-circular shape.

[0012] In the semiconductor device in the described examples, the partial via covers half or less than half of a base portion of the pad exposed by the aperture.

[0013] In the semiconductor device in the described examples, an end of the partial via is at a center of the pad of the second conductor.

[0014] In the semiconductor device in the described examples, the partial via covers half or less than half of a sidewall of the aperture.

[0015] In another example, a method for manufacturing a semiconductor device includes providing a first conductor on a top side of a dielectric; providing a second conductor on a bottom side of the dielectric; providing an aperture in the dielectric, wherein the first conductor comprises a partial via that contacts a pad of the second conductor through the aperture; providing an electronic device having an interconnect that contacts the first conductor; and providing an encapsulant on the top side of the dielectric and contacting a side of the electronic device.

[0016] The method in the other example further includes providing a third conductor on the top side of the dielectric; providing a fourth conductor on the bottom side of the dielectric; and providing a further aperture in the dielectric, wherein the third conductor comprises a partial via that contacts a pad of the fourth conductor through the further aperture.

[0017] In the method in the other example, the partial via of the first conductor and the partial via of the third conductor are spaced apart in the dielectric by a reduced distance compared to a distance between full vias through the same dielectric.

[0018] In the method in the other example, a size of the pad of the second conductor for the partial via is reduced compared to a size of a pad for a full via through the same dielectric.

[0019] In yet another example, a semiconductor structure includes a redistribution layer (RDL) substrate including: a first dielectric layer having a first aperture; a first conductive layer on the first dielectric layer, wherein the first conductive layer has a full via in the first aperture; a second dielectric layer having a second aperture, wherein the second dielectric layer is on a top surface of the first dielectric layer; and a second conductive layer on a top surface of the second dielectric layer, wherein the second conductive layer has a partial via in the second aperture that contacts the first conductive layer through the second aperture. The semiconductor structure further includes: an electronic device on a top side of the RDL substrate, wherein the electronic device includes an interconnect electrically coupled with the second conductive layer; and an encapsulant on the top side of the RDL substrate, the encapsulant contacting a side of the electronic device.

[0020] In the semiconductor structure in the yet another example, the first dielectric layer has a third aperture and the first conductive layer has a full via in the third aperture, and wherein the second dielectric layer has a fourth aperture and the second conductive layer has a partial via in the fourth aperture, wherein the full via of the first conductive layer contacts an underlying pad exposed at a bottom surface of the first dielectric layer, and the partial via of the second conductive layer contacts a pad of the first conductive layer, wherein a size of the pad of the first conductive layer is smaller than a size of the underlying pad.

[0021] In the semiconductor structure in the yet another example, an end of the partial via contacts a pad of the first conductive layer; and a trace adjacent to the end of the partial via overlaps a portion of the pad of the first conductive layer that is not covered by the partial via.

[0022] In the semiconductor structure in the yet another example, the partial via covers one half or less than one half of the first conductive layer exposed at a bottom of the aperture. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A cross-sectional view of an example semiconductor device is shown.

[0024] Figures 2A to 2M A cross-sectional view of an example method for fabricating an example semiconductor device is shown.

[0025] Figures 3A to 3F A cross-sectional view of a portion of the semiconductor device is shown. Figures 2B to 2G A partial enlarged plan view in the cross-sectional view of the semiconductor device is shown. DETAILED DESCRIPTION

[0026] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms “example” and “for example” mean serving as an instance or illustration.

[0027] The drawings depict one general manner in which the structures can be implemented, and descriptions and details of well-known features and techniques can be omitted to avoid unnecessarily obscuring the disclosure. Additionally, elements in the drawings can not be to scale. For example, the dimensions of some of the elements in the figures can be exaggerated relative to other elements to help improve understanding of the examples under discussion. The same reference numbers in different drawings indicate the same or similar elements.

[0028] The term “or” means any one or any combination of the open-ended list of items following the “or.” As an example, “x or y” means any element of the three-element set {(x), (y), (x, y)}. As another example, “x, y, or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0029] The terms “comprises,” “comprising,” “includes,” or “including” are “open-ended” terms and specify the presence of stated features but do not preclude the presence or addition of one or more other features. The terms “first,” “second,” and the like can be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0030] Unless otherwise noted, the term “coupled” can be used to describe two elements or components that are either directly in contact with each other or indirectly in contact with each other through one or more intermediate elements or components. For example, if a first element A is coupled to a second element B, then element A can be either directly connected to element B or be indirectly connected to element B through an intermediate element C. Similarly, the term “on” or “above” can be used to describe two elements or components that are either directly in contact with each other or indirectly in contact with each other through one or more intermediate elements or components.

[0031] Other examples are included in the disclosure. Such examples can be found in the drawings, claims, or specification of the disclosure.

[0032] Figure 1 A cross-sectional view of an example semiconductor device 100 is shown. In Figure 1 In the example shown, the semiconductor device 100 can include a substrate 110, an electronic device 120, an encapsulant 130, and an interconnect 140.

[0033] The substrate 110 can include conductive layers 111, 113, 115, 117, and 119 and dielectric layers 112, 114, 116, and 118. The electronic device 120 can include a terminal 121 and an interconnect 122 electrically connected to the terminal 121. The terminal 121 can be formed on a bottom surface of the electronic device 120. The interconnect 122 can be made of a conductive material and can be electrically connected to the conductive layer 119 of the substrate 110.

[0034] The encapsulant 130 can cover a top surface of the substrate 110 and a top surface or a side surface of the electronic device 120. In addition, the interconnect 140 can be made of a conductive material and can be formed on a bottom surface of the substrate 110. The substrate 110, the encapsulant 130, and the interconnect 140 can be referred to as a semiconductor package 101 or a package 101. The semiconductor package 101 can protect the electronic device 120 from external factors or environments. In addition, the semiconductor package 101 can provide electrical connections between external components, such as a printed circuit board, and the electronic device 120.

[0035] In some examples, the substrate 110 can be a redistribution layer (“RDL”) substrate. An RDL substrate can include one or more electrically conductive redistribution layers and one or more dielectric layers that (a) can be formed layer-by-layer on top of an electronic device to which the RDL substrate is to be electrically coupled, or (b) can be formed layer-by-layer on top of a carrier that is completely removed or at least partially removed after coupling the electronic device and the RDL substrate together. An RDL substrate can be fabricated layer-by-layer as a wafer-level substrate on a circular wafer in a wafer-level process, or as a panel-level substrate on a rectangular or square panel carrier in a panel-level process. An RDL substrate can be formed with an additive build-up process that can include one or more dielectric layers stacked alternately with one or more electrically conductive layers that define respective electrically conductive redistribution patterns or traces configured to collectively (a) fan out electrical traces outside of a footprint of the electronic device, or (b) fan in electrical traces inside of the footprint of the electronic device. The electrically conductive patterns can be formed using a plating process, such as an electroplating process or a chemical plating process. The electrically conductive patterns can include an electrically conductive material, such as copper or other platable metal. The locations of the electrically conductive patterns can be made using a photopatterning process, such as a photolithography process and a photoresist material used to form a photolithographic mask. The dielectric layers of the RDL substrate can be patterned with a photopatterning process that can include the photolithographic mask through which light is exposed to features of the photopatterning process, such as vias in the dielectric layers. The dielectric layers can be made of a photo-definable organic dielectric material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Such photo-definable dielectric materials can be spin-coated or otherwise applied in a liquid form, rather than attached in a pre-formed film form. To allow for proper formation of the desired photo-defined features, such photo-definable dielectric materials can omit structural enhancers, or can be filler-free, without threads, fabrics, or other particles that can interfere with light from the photopatterning process. In some examples, such filler-free properties of the filler-free dielectric materials can allow for a reduction in the thickness of the resulting dielectric layers. Although the photo-definable dielectric materials described above can be organic materials, in other examples, the dielectric materials of the RDL substrate can include one or more inorganic dielectric layers. Some examples of the one or more inorganic dielectric layers can include silicon nitride (Si3N4), silicon oxide (SiO2), or SiON. The one or more inorganic dielectric layers can be formed by growing inorganic dielectric layers using an oxidation or nitridation process, rather than using photo-definable organic dielectric materials. Such inorganic dielectric layers can be filler-free, without threads, fabrics, or other different inorganic particles. In some examples, the RDL substrate can omit a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates can be referred to as coreless substrates. Other substrates in the present disclosure can also include RDL substrates.

[0036] Figures 2A to 2M A cross-sectional view is shown for an example method of manufacturing an example semiconductor device 100. Figures 3A to 3D are shown. Figure 3D It shows Figures 2B to 2E A partially enlarged plan view of the cross-sectional view of the semiconductor device 100 shown.

[0037] Figure 2A A semiconductor device 100 in an early stage of manufacturing is shown. Figure 2A In the illustrated examples, the carrier 10 may be in the shape of a substantially planar plate. In some examples, the carrier 10 may include or be referred to as a plate, wafer, panel, or strip. Additionally, in some examples, the carrier 10 may be made of at least one or more of a metal (e.g., SUS), a wafer (e.g., silicon), a ceramic (e.g., alumina), a glass (e.g., soda-lime glass), or any equivalent thereof. The thickness of the carrier 10 may range from about 50 μm (micrometers) to about 1000 μm, and the width may range from about 100 mm to about 300 mm. The carrier 10 can be used to integrate multiple components, thereby providing structural integrity while forming the substrate 110, attaching the electronic device 120, and applying the encapsulation 130.

[0038] A conductive layer 111 can be formed on the carrier 10. The conductive layer 111 can be formed using a patterned mask having a pattern on the top surface 10x of the carrier 10. The conductive layer 111 can be shaped, for example, circular, rectangular, or polygonal. In some instances, the conductive layer 111 may include, or be referred to as, a conductive stud, under-bump metallization (UBM), a lower pad, or an outer pad. In some instances, the outer pad 111 can be made of any conductive material from a variety of conductive materials (e.g., copper, gold, silver, or equivalents). Additionally, in some instances, the outer pad 111 can be formed using any of a variety of processes, including but not limited to, sputtering, electroless plating, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or equivalents. After the outer pad 111 is formed, the mask can be removed. The thickness of the outer pad 111 can range from about 0.1 μm to about 20 μm. The outer pad 111 can be an external input / output terminal of the substrate 110 to allow interconnects 140 to be formed or attached under the substrate 110.

[0039] Figure 2B and Figure 3AA semiconductor device 100 in a later manufacturing stage is shown. In Figure 2B and Figure 3A In the example shown, a dielectric layer 112 can be formed to cover the top surface 10x of the carrier 10 and the outer liner 111. An aperture 112a exposing a base 111d of the outer liner 111 can be formed by patterning the dielectric layer 112.

[0040] The dielectric layer 112 can include or be referred to as, for example, a passivation layer, an insulating layer, or a protective layer. In some examples, the dielectric layer 112 can include an electrically insulating material including, for example, a polymer, a polyimide (PI), a benzocyclobutene (BCB), a polybenzoxazole (PBO), a bismaleimide triazine (BT), a molding material, a phenol resin, an epoxy resin, a silicone resin, or an acrylate polymer. In some examples, the dielectric layer 112 can be formed using any of various processes, for example, spin coating, spray coating, printing, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. The thickness of the dielectric layer 112 can be in a range of about 3 pm to about 30 pm.

[0041] After forming a mask pattern on the top surface of the dielectric layer 112, the aperture 112a can be formed by removing a portion of the dielectric layer 112 exposed by etching. The aperture 112a can include or be referred to as an opening or a hole. The dielectric layer 112 can expose the base 111d, which is a portion of the top surface of the outer liner 111, through the aperture 112a. The dielectric layer 112 can cover a portion of the top outer periphery of the outer liner 111 and the top surface 10x of the carrier 10. The base 111d exposed by the aperture 112a can be shaped, for example, circular, rectangular, or polygonal. The shape of the base 111d exposed by the aperture 112a can be the same as the shape of the outer liner 111. The area of the base 111d exposed by the aperture 112a can be less than the area of the outer liner 111. In addition, the diameter of the base 111d exposed by the aperture 112a can be in a range of about 10 pm to about 500 pm.

[0042] Figure 2C and Figure 3B A semiconductor device 100 in a later manufacturing stage is shown. In Figure 2C and Figure 3B In the example shown, a conductive layer 113 can be formed to cover the base 111d of the outer liner 111 and a portion of the exposed surface of the dielectric layer 112.

[0043] The conductive layer 113 can be formed to have a plurality of patterns that can be electrically connected to the base 111d of the outer liner 111 exposed through the aperture 112a, respectively. In addition, the conductive layer 113 electrically connected to the base 111d of the outer liner 111 can extend to the top surface of the dielectric layer 112.

[0044] The conductive layer 113 may include, or be referred to as, a redistribution layer (RDL), wiring pattern, trace pattern, or circuit pattern. In some instances, the redistribution layer 113 may be made of any conductive material of various conductive materials (e.g., copper, gold, silver, or equivalents). The redistribution layer 113 may be formed using various processes, including but not limited to sputtering, electroless plating, electroplating, PVD, CVD, MODVD, ALD, LPCVD, PECVD, or equivalents. After the redistribution layer 113 is formed to a predetermined thickness covering the substrate 111d of the outer pad 111 and the exposed surface of the dielectric layer 112, the redistribution layer 113 may be patterned using a mask to create multiple wiring patterns or traces. The redistribution layer 113 may include a through-hole 113a that completely covers the substrate 111d of the outer pad 111 and a trace 113b extending from the through-hole 113a to the top surface of the dielectric layer 112. Additionally, the redistribution layer 113 may further include a pad 113c formed at the end of the trace 113b. The pad 113c may be positioned on the top surface of the dielectric layer 112. The trace 113b may electrically connect the through-hole 113a and the pad 113c. The through-hole 113a and the pad 113c may be shaped, for example, circular, rectangular, or polygonal. The size of the through-hole 113a and the pad 113c may range from approximately 15 μm to approximately 550 μm. The thickness of the redistribution layer 113 may range from approximately 3 μm to approximately 20 μm.

[0045] Figure 2D and Figure 3C A semiconductor device 100 in a late-stage manufacturing process is shown. Figure 2D and Figure 3C In the example shown, a dielectric layer 114 can be formed to completely cover the redistribution layer 113 and the dielectric layer 112, and an aperture 114a exposing the substrate 113d of the redistribution layer 113 can be formed by patterning the dielectric layer 114. The aperture 114a can expose the substrate 113d, which is part of the top surface of the pad 113c, to the outside. The substrate 113d can be positioned approximately at the center of the pad 113c. The dielectric layer 114 can cover a portion of the top surface of the pad 113c.

[0046] The dielectric layer 114 may include, or be referred to as, for example, a passivation layer, an insulating layer, or a protective layer. In some instances, the dielectric layer 114 may comprise an electrically insulating material, including, for example, polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding materials, phenolic resins, epoxy resins, silicone resins, or acrylate polymers. In some instances, the dielectric layer 114 may be formed using any of a variety of processes (e.g., spin coating, spraying, printing, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD). The thickness of the dielectric layer 114 may range from approximately 3 μm to approximately 30 μm.

[0047] After a mask pattern is formed on the top surface of dielectric layer 114, an aperture 114a can be formed by removing the dielectric layer 114 exposed by etching. The aperture 114a may include, or be referred to as, an opening or hole. The dielectric layer 114 can expose a substrate 113d, which is part of the top surface of pad 113c, through the aperture 114a. The substrate 113d exposed by the aperture 114a can be shaped, for example, circular, rectangular, or polygonal. The area of ​​the substrate 113d exposed by the aperture 114a can be smaller than the area of ​​the pad 113c of the redistribution layer 113. Additionally, the diameter of the substrate 113d exposed by the aperture 114a can range from approximately 10 μm to approximately 500 μm. The dielectric layer 114 may further include a peripheral portion 114b covering the top surface of the pad 113c. The peripheral portion 114b can be located in the outer region surrounding the aperture 114a, and the width of the peripheral portion can be in the range of approximately 5 μm to approximately 50 μm.

[0048] Figure 2E and Figure 3D A semiconductor device 100 in a late-stage manufacturing process is shown. Figure 2E and Figure 3D In the example shown, a conductive layer 115 may be formed to cover a portion of the exposed surface of the substrate 113d of the redistribution layer 113 and the dielectric layer 114.

[0049] The substrate 110 can include a redistribution layer (RDL) substrate. The conductive layer 115 can be formed to have a plurality of patterns that can be electrically connected to the base 113d of the redistribution layer 113 exposed through the aperture 114a, respectively. In addition, the conductive layer 115 electrically connected to the redistribution layer 113 can extend to the top surface of the dielectric layer 114. The conductive layer 115 can be electrically connected to the external pad 111 through the redistribution layer 113. In some examples, a first conductor 115 can be provided on the top side of the dielectric 114, and a second conductor 113 can be provided on the bottom side of the dielectric 114. An aperture 114a can be provided in the dielectric 114. The first conductor 115 can include a partial via 115a that contacts the pad base 113d of the second conductor 113 through the aperture 114a.

[0050] The conductive layer 115 can include or be referred to as a redistribution layer (RDL), a wiring pattern, a trace pattern, or a circuit pattern. In some examples, the redistribution layer 115 can be made of any of various conductive materials, such as copper, gold, silver, or equivalents. The redistribution layer 115 can be formed using various processes, including but not limited to any of sputtering, electroless plating, electroplating, PVD, CVD, MODVD, ALD, LPCVD, PECVD, or equivalents. After the redistribution layer 115 is formed to a predetermined thickness covering the exposed surfaces of the base 113d of the redistribution layer 113 and the dielectric layer 114, a mask pattern can be used to pattern the redistribution layer 115 to have a plurality of patterns. The redistribution layer 115 can include a partial via 115a covering a portion of the base 113d of the redistribution layer 113 and a trace 115b extending from the partial via 115a to the top surface of the dielectric layer 114. In addition, the redistribution layer 115 can further include a pad 115c formed at an end of the trace 115b.

[0051] The partial via 115a contacts but does not completely cover the base 113d of the redistribution layer 113. In addition, the partial via 115a contacts but does not completely cover the sidewall of the aperture 114a. In the present example, the partial via 115a can be shaped as a line having a constant width. The end 115ax of the partial via 115a can be positioned approximately at the center of the base 113d of the redistribution layer 113. In the base 113d of the redistribution layer 113, a portion not covered by the partial via 115a can remain exposed to the outside. The redistribution layer 115 can be electrically connected to the redistribution layer 113 through the partial via 115a. Although the partial via 115a is shown here as having a linear shape, other shapes, such as a semicircular or other geometric or non-geometric shape, that only partially cover the base 113d of the redistribution layer 113 are also possible. For example, the partial via 115a can cover up to half or less than half of the area or diameter of the base 113d, or cover up to half or less than half of the area of the sidewall of the aperture 114a.

[0052] In some examples, as shown in FIG. 1, the substrate 110 includes a redistribution layer (RDL) substrate including a first dielectric layer 112 having a first aperture 112a and a first conductive layer 113 on the first dielectric layer 112, where the first conductive layer 113 has a full via 113a in the first aperture 112a. Figure 2B As shown in FIG. 1, the RDL substrate 110 can include a second dielectric layer 114 having a second aperture 114a on a top surface of the first dielectric layer 112 and a second conductive layer 115 on a top surface of the second dielectric layer 114, where the second conductive layer 115 has a partial via 115a in the second aperture 114a that electrically contacts the first conductive layer 113 through the second aperture 114a. Figure 2E As shown in FIG. 1, the RDL substrate 110 can include a second dielectric layer 114 having a second aperture 114a on a top surface of the first dielectric layer 112 and a second conductive layer 115 on a top surface of the second dielectric layer 114, where the second conductive layer 115 has a partial via 115a in the second aperture 114a that electrically contacts the first conductive layer 113 through the second aperture 114a.

[0053] The trace 115b can be shaped as a line having a constant or almost constant width. In addition, the width of the trace 115b can be the same as the width of the partial via 115a. The width of the trace 115b can be in the range of about 1 pm to about 100 pm. The trace 115b can electrically connect the partial via 115a to the pad 115c. The trace 115b can be positioned on the top surface of the dielectric layer 114. A peripheral portion 114b of the dielectric layer 114 can be partially covered by the trace 115d extending from the partial via 115a electrically connected to the base 113d. In addition, a portion of the peripheral portion 114b of the dielectric layer 114 can remain exposed except for the portion covered by the trace 115b.

[0054] The pad 115c can be shaped, for example, into a circle, rectangle, or polygon. The pad 115c can be positioned on the top surface of the dielectric layer 114. The size of the pad 115c can range from approximately 15 μm to approximately 550 μm. The thickness of the redistribution layer 115 can range from approximately 3 μm to approximately 20 μm. Furthermore, compared to forming a fully viad substrate 113d, the redistribution layer 115 can reduce the distance between the conductive patterns of the redistribution layer 115 by forming partially viad vias 115a that partially cover the substrate 113d and the peripheral portion 114b, thereby achieving miniaturization or reduction of the spacing between pads or between pad ends, as described below regarding... Figure 2G and Figure 2F Further details are shown and described.

[0055] Figure 2F and Figure 3E A semiconductor device 100 in a late-stage manufacturing process is shown. Figure 2F and Figure 3E In the example shown, a dielectric layer 116 can be formed to completely cover the substrate 113d, the redistribution layer 115, and the dielectric layer 114. An aperture 116a exposing the substrate 115d of the redistribution layer 115 can be formed by patterning the dielectric layer 116. The aperture 116a exposes the substrate 115d, which is part of the top surface of the pad 115c of the redistribution layer 115, to the outside. The substrate 115d can be positioned approximately at the center of the pad 115c.

[0056] The dielectric layer 116 may include, or be referred to as, for example, a passivation layer, an insulating layer, or a protective layer. In some instances, the dielectric layer 116 may comprise an electrically insulating material, including, for example, polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding materials, phenolic resins, epoxy resins, silicone resins, or acrylate polymers. In some instances, the dielectric layer 116 may be formed using any of a variety of processes (e.g., spin coating, spraying, printing, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD). The thickness of the dielectric layer 116 may range from approximately 3 μm to approximately 30 μm.

[0057] After forming the mask pattern on the top surface of the dielectric layer 116, an aperture 116a can be formed by removing a portion of the dielectric layer 116 exposed by the etching. The aperture 116a can include or be referred to as an opening or a hole. The dielectric layer 116 can expose a base 115d, which is a portion of the top surface of the pad 115c of the redistribution layer 115, to the outside. The base 115d exposed by the aperture 116a can be shaped, for example, as a circle, a rectangle, or a polygon. The area of the base 115d exposed by the aperture 116a can be less than the area of the pad 115c. In addition, the diameter of the base 115d exposed by the aperture 116a can be in a range of about 10 pm to about 500 pm. The dielectric layer 116 can further include a peripheral portion 116b covering a top surface of the pad 115c. The peripheral portion 116b can be located at an outer region around the aperture 116a and the width of the peripheral portion can be in a range of about 5 pm to about 50 pm.

[0058] Figure 2G and Figure 3F A semiconductor device 100 in a later manufacturing stage is shown. In Figure 2G and Figure 3F In the example shown, a conductive layer 117 can be formed to cover a portion of the base 115d of the redistribution layer 115 and the exposed surface of the dielectric layer 116. In some examples, the substrate 110 includes a dielectric 116, a first conductor 117 on a top side of the dielectric 116, and a second conductor 115 on a bottom side of the dielectric 116. The dielectric 116 can have an aperture 116a, and the first conductor 117 includes a partial via 117a that contacts a portion of the pad base 115d of the second conductor 115 through the aperture 116a. In some examples, the first conductor 117 includes a first trace 117e on the top side of the dielectric 116 and continuous with the partial via 117a. In some examples, the first trace 117e and the partial via 117a have the same width. In some examples, an end 117ax of the partial via 117a contacts the pad base 115d of the second conductor 115, and a trace 117e adjacent to the end 117ax of the partial via 117a overlaps a portion of the pad base 115d of the second conductor 115 that is not covered by the partial via 117a. In some examples, there can be a gap between adjacent pads 115c of the second conductor 115, and the trace 117e overlaps a portion of the gap between the pad 115c of the second conductor 115 and an adjacent pad 115c of the second conductor 115.

[0059] The conductive layer 117 can be formed to have a plurality of patterns that can be electrically connected to the base 115d of the redistribution layer 115 exposed through the aperture 116a, respectively. In addition, the conductive layer 117 electrically connected to the redistribution layer 115 can extend to the top surface of the dielectric layer 116. The conductive layer 117 can be electrically connected to the external pad 111 through the redistribution layer 115 as well as the redistribution layer 113.

[0060] The conductive layer 117 can include or be referred to as a redistribution layer (RDL), a wiring pattern, or a circuit pattern. In some examples, the redistribution layer 117 can be made of any of various conductive materials, such as copper, gold, silver, or equivalents. The redistribution layer 117 can be formed using any of various processes, including but not limited to sputtering, electroless plating, electroplating, PVD, CVD, M0D VD, ALD, LPCVD, PECVD, or equivalents. After the redistribution layer 117 is formed to a predetermined thickness so as to cover the base 115d of the redistribution layer 115 and the exposed surface of the dielectric layer 116, a mask pattern can be used to pattern the redistribution layer to have a plurality of wiring patterns or circuit patterns. The redistribution layer 117 can include a partial via 117a covering a portion of the pad base 115d of the redistribution layer 115 and a trace 117b extending from the partial via 117a to the top surface of the dielectric layer 116. In addition, the redistribution layer 117 can further include a pad 117c formed at an end of the trace 117b.

[0061] The partial via 117a can be similar to the partial via 115a and can be similarly formed. The partial via 117a is formed such that it does not only partially cover the pad base 115d of the redistribution layer 115. Also, the partial via 117a is formed such that it does not only partially cover the sidewall of the aperture 116a of the dielectric layer 116. In some examples, the partial via 115a or the partial via 117a can include a linear shape or another shape, such as a semi-circular shape as shown by the example of the partial via 117a. Figure 3F The example of the partial via 117a shows a semi-circular shape. In some examples, the partial via 115a or the partial via 117a can cover half or less than half of the pad base 115d.

[0062] The trace 117b can be similar to the trace 115b and can be similarly formed. The trace 117b can be formed on the dielectric layer 116 and can connect the partial via 117a to the pad 117c. The trace 117b can be positioned on the top surface of the dielectric layer 116. Other patterns, such as the trace 117e, can also be formed between two adjacent partial vias 117a.

[0063] Without reaching or covering the dielectric periphery portion 116b of the pad 115c, which is positioned adjacent to each other and is located on the outer region of the partial via 117a, the partial via covers its pad base 115d (and in this example, only partially). This further minimizes the via-to-via distance 117z compared to the case where a full via, such as a full via 113a, is used instead of covering the pad base 115d. Figure 2C (3B). In some instances, the reduced via-to-via distance 117z allows the ends 117ax to be spaced closer together with a reduced pitch. Additionally, because extra space is provided in the conductive layer 117 by using adjacent partial vias 117a instead of adjacent full vias, patterns such as traces 117e can be positioned between such partial vias 117a without violating layout design rules for minimum distances between adjacent traces or circuit patterns. In some instances, using adjacent partial vias 117a can allow the via-to-via distance 117z to be reduced by, for example, at least by about 25% compared to the corresponding case using adjacent full vias. For example, using adjacent partial vias 117a will allow the via-to-via distance 117z to be minimized to at least about 30 μm compared to the case using adjacent full vias that would require a via-to-via distance 117z of at least about 40 μm, but the scope of the invention is not limited to this aspect.

[0064] Pad 117c can be similar to pad 115c and can be similarly shaped to the pad. Pad 117c is formed on dielectric layer 116 and coupled to trace 117b. Compared to forming a full via that completely covers the substrate, redistribution layer 117 can reduce the distance between each pattern in the pattern of redistribution layer 117 by forming partial vias 117a that partially cover the substrate 115d and the peripheral portion 116b, thereby achieving miniaturization.

[0065] Figure 2H A semiconductor device 100 in a late-stage manufacturing process is shown. Figure 2H In the example shown, a dielectric layer 118 can be formed to completely cover the substrate 115d, the redistribution layer 117, and the dielectric layer 116, and an aperture 118a exposing the substrate 117d of the redistribution layer 117 can be formed by patterning the dielectric layer 118. The aperture 118a can expose the substrate 117d, which is part of the top surface of the pad 117c, to the outside.

[0066] The dielectric layer 118 can include or be referred to as, for example, a passivation layer, an insulating layer, or a protective layer. In some examples, the dielectric layer 118 can include an electrically insulating material including, for example, a polymer, a polyimide (PI), a benzocyclobutene (BCB), a polybenzoxazole (PBO), a bismaleimide triazine (BT), a molding material, a phenol resin, an epoxy resin, a silicone resin, or an acrylate polymer. In some examples, the dielectric layer 118 can be formed using any of various processes, for example, spin coating, spray coating, printing, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. The thickness of the dielectric layer 118 can be in a range of about 3 μm to about 30 μm.

[0067] After forming the mask pattern on the top surface of the dielectric layer 118, the via 118a can be formed by removing the dielectric layer 118 exposed by the etching. The via 118a can include or be referred to as an opening or a hole. The dielectric layer 118 can expose the substrate 117d, which is a portion of the top surface of the pad 117c, through the via 118a. The substrate 117d exposed by the via 118a can be shaped, for example, circular, rectangular, or polygonal. The shape of the substrate 117d exposed by the via 118a can be identical to that of the pad 117c of the redistribution layer 117. The area of the substrate 117d exposed by the via 118a can be smaller than that of the pad 117c of the redistribution layer 117. In addition, the diameter of the substrate 117d exposed by the via 118a can be in a range of about 10 μm to about 500 μm.

[0068] Figure 2I The semiconductor device 100 is shown in a later manufacturing stage. In the shown example, the conductive layer 119 can be formed to cover the substrate 117d of the redistribution layer 117 and the exposed surface of the dielectric layer 118. Figure 2I In the shown example, the conductive layer 119 can be formed to cover the substrate 117d of the redistribution layer 117 and the exposed surface of the dielectric layer 118.

[0069] The conductive layer 119 can be formed to have a plurality of patterns, which can be electrically connected to the substrate 117d of the redistribution layer 117 exposed through the via 118a, respectively. In addition, the conductive layer 119 electrically connected to the redistribution layer 117 can be formed to partially cover the top surface of the dielectric layer 118. The conductive layer 119 can be electrically connected to the external pad 111 through the redistribution layer 117 as well as the redistribution layer 115 and the redistribution layer 113.

[0070] The conductive layer 119 can include or be referred to as a conductive pad, an interconnect pad, a micro pad, a bond pad, a bump pad, or an under bump metallization (UBM). In some examples, the interconnect pad 119 can be made of any of a variety of conductive materials, such as copper, gold, silver, or equivalents. An anti-oxidation layer made of tin, gold, silver, nickel, palladium, or equivalents can be further formed on the interconnect pad 119 for preventing the interconnect pad 119 from being oxidized. The interconnect pad 119 can be formed using any of a variety of processes, including but not limited to sputtering, electroless plating, electroplating, PVD, CVD, MODVD, ALD, LPCVD, PECVD, or equivalents. After the interconnect pad 119 is formed to a predetermined thickness of the exposed surfaces of the base 117d and the dielectric layer 118 covering the redistribution layer 117, a mask pattern can be used to pattern the redistribution layer 117 to have a plurality of patterns. The thickness of the interconnect pad 119 can be in a range of about 5 pm to about 300 pm.

[0071] Because the interconnect pad 119 is formed in the manner described above, the substrate 110 can be completed. Although the substrate 110 is shown to include five conductive layers 111, 113, 115, 117, and 119 and four dielectric layers 112, 114, 116, and 118, the number of layers of the substrate 110 can be less than or greater than the five conductive layers 111, 113, 115, 117, and 119 and the four dielectric layers 112, 114, 116, and 118, and the scope of the disclosed subject matter is not limited in these respects.

[0072] Figure 2J The semiconductor device 100 is shown in a late manufacturing stage. In Figure 2J In the example shown, the device 120 can be electrically connected to the conductive pad 119 of the substrate 110. In some examples, the substrate 110 can be a redistribution layer (RDL) substrate.

[0073] In some examples, a pick-and-place apparatus can pick up the electronic device 120 to place it on the interconnect pad 119 of the substrate 110. Next, the electronic device 120 can be electrically connected to the substrate 110 by mass reflow, thermal compression, or laser-assisted bonding. The electronic device 120 can be provided with an interconnect 122 that is electrically coupled to the first conductor 117 or electrically coupled to the conductor 115, the conductor 113, or the conductor 111.

[0074] In some examples, the electronic device 120 can include or be referred to as a semiconductor die or a semiconductor chip. Additionally, in some examples, the electronic device 120 can include at least one of a logic die, a micro control unit, a memory, a digital signal processor, a network processor, a power management unit, an audio processor, an RF circuit, a wireless baseband system-on-chip processor, an application specific integrated circuit, or equivalents.

[0075] In some examples, the electronic device 120 can include an active area and a non-active area. Further, in some examples, the active area can be disposed to face the substrate 110. Further, in some examples, the active area can include an interconnect 121. In some examples, the interconnect 121 can be referred to as a die pad, a bond pad, an aluminum pad, a bump, a conductive pillar, or a conductive stud.

[0076] Further, the interconnect 121 can be connected to the interconnect pad 119 of the substrate 110 using a low melting point material 122. In one example, the low melting point material 122 can include one or more of Sn, Ag, Pb, Cu, Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, Sn-Ag-Cu, or equivalents. The interconnect 121 of the electronic device 120 and the interconnect pad 119 of the substrate 110 can be electrically connected to each other through the low melting point material 122. The thickness of the interconnect 121 and the low melting point material 122 can be in a range of about 5 pm to about 300 pm.

[0077] Figure 2K The semiconductor device 100 is shown in a later manufacturing stage. In Figure 2K In the example shown, an encapsulant 130 can be formed to partially or completely cover the top surface 110x of the substrate 110 and the top surface or side surface of the electronic device 120. In some examples, the encapsulant 130 can include or be referred to as an epoxy molding compound, an epoxy molding resin, or a sealant. Further, in some examples, the encapsulant 130 can include or be referred to as a molding member, a sealing member, an encapsulating member, a protecting member, a package, or a body member. In some examples, the encapsulant 130 can include, but is not limited to, an organic resin, an inorganic filler, a curing agent, a catalyst, a colorant, a flame retardant, and the like. The molding based on the encapsulant 130 can be formed by any of various processes. In some examples, the encapsulant 130 can be formed by, but is not limited to, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, paste printing, or film assisted molding. The thickness of the encapsulant 130 can be in a range of about 50 pm to about 300 pm. The encapsulant 130 can encapsulate the electronic device 120, thereby protecting the electronic device 120 in a packaged state from external factors or environments. In some examples, the encapsulant 130 can be provided on the top side of the substrate 110 that contacts the side of the electronic device 120. In some examples, the substrate 110 can be a redistribution layer (RDL) substrate.

[0078] Figure 2L The semiconductor device 100 is shown in a later manufacturing stage. In Figure 2LIn the illustrated example, the bottom surface 110y of the substrate 110 can be exposed by removing the carrier 10. If the carrier 10 is removed, the external pads 111 and the dielectric layer 112 can be exposed by the bottom surface 110y of the substrate 110. The carrier 10 can be removed by conventional grinding or chemical etching. Alternatively, the carrier 10 can be removed by a release process using ultraviolet (UV) radiation or a laser.

[0079] Figure 2M The semiconductor device 100 is shown in a later stage of manufacture. In this stage, the external pads 111 can be exposed by removing the dielectric layer 112. Figure 2M In the illustrated example, interconnects 140 can be formed on the external pads 111 that are exposed by the bottom surface 110y of the substrate 110.

[0080] The interconnects 140 can be electrically connected to the bottom surface of the external pads 111. The interconnects 140 can be electrically connected to the electronic device 120 through the conductive layers 111, 113, 115, 117, and 119 of the substrate 110. In some examples, the interconnects 140 can include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu or equivalents.

[0081] The interconnects 140 can be formed by, for example, a ball drop process, a screen printing process, or an electroplating process. In some examples, the interconnects 140 can be formed by forming a conductive material, including solder on the bottom surface of the external pads 111 of the substrate 110, a conductive layer 122 using a ball drop process, and then by a reflow process. At this stage, the bottom surface 110y of the substrate 110 can be disposed to face upward. The interconnects 140 can include or be referred to as conductive balls such as solder balls, conductive pillars such as copper pillars, or conductive stakes with a solder cap on a copper pillar. The size of the interconnects 140 can range from about 20 pm to about 500 pm.

[0082] The present disclosure includes references to certain examples as described herein. Those skilled in the art will understand that various changes can be made and equivalents substituted without departing from the scope of the present disclosure. In addition, modifications can be made to the disclosed examples without departing from the scope of the present disclosure. Therefore, the present disclosure is intended to not be limited to the disclosed examples but is to include all examples falling within the scope of the appended claims.

Claims

1. A semiconductor device comprising: a substrate comprising a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture and the first conductor comprises a partial via that contacts an underfill of the second conductor through the aperture; an electronic device having an interconnect electrically coupled to the first conductor; and an encapsulant on a top side of the substrate that contacts a side of the electronic device; wherein the partial via extends over half or less than half of a width of the underfill exposed at a bottom of the aperture; and wherein a width of the partial via is less than half of a width of the bottom of the aperture.

2. The semiconductor device of claim 1, wherein the substrate comprises a third conductor on the top side of the dielectric and a fourth conductor on the bottom side of the dielectric, wherein the dielectric has a further aperture and the third conductor comprises a partial via that contacts an underfill of the fourth conductor through the further aperture.

3. The semiconductor device of claim 2, further comprising a trace between the partial via of the first conductor and the partial via of the third conductor on the dielectric.

4. The semiconductor device of claim 2, wherein an end of the partial via of the first conductor and an end of the partial via of the third conductor are spaced apart by 30 microns or less.

5. The semiconductor device of claim 2, wherein: the first conductor comprises a first trace on the top side of the dielectric and continuous with the partial via; and the first trace and the partial via are the same width.

6. The semiconductor device of claim 1, wherein: an end of the partial via contacts the underfill of the second conductor; and a trace adjacent to the end of the partial via overlaps a portion of the underfill of the second conductor not covered by the partial via.

7. The semiconductor device of claim 6, wherein the trace overlaps a portion of a gap between the underfill of the second conductor and an adjacent underfill.

8. The semiconductor device of claim 1, wherein the partial via comprises a linear shape.

9. The semiconductor device of claim 1, wherein the partial via comprises a semi-circular shape.

10. The semiconductor device of claim 1, wherein an end of the partial via is at a center of the underfill of the second conductor.

11. The semiconductor device of claim 1, wherein the partial via covers half or less than half of a sidewall of the aperture.

12. A method for manufacturing a semiconductor device, the method comprising: providing a first conductor on a top side of a dielectric; providing a second conductor on a bottom side of the dielectric; ​ ​ providing an aperture in the dielectric, wherein the first conductor includes a partial via that contacts a pad of the second conductor through the aperture; providing an electronic device having an interconnect electrically coupled with the first conductor; and providing an encapsulant on a top side of the dielectric and contacting a side of the electronic device; wherein the partial via extends over half or less than half of a width of the pad exposed at a bottom of the aperture; and wherein a width of the partial via is less than half of a width of the bottom of the aperture.

13. The method of claim 12, further comprising: providing a third conductor on the top side of the dielectric; providing a fourth conductor on the bottom side of the dielectric; and providing a further aperture in the dielectric, wherein the third conductor includes a partial via that contacts a pad of the fourth conductor through the further aperture.

14. The method of claim 13, wherein the partial via of the first conductor and the partial via of the third conductor are spaced apart in the dielectric by a reduced distance compared to a distance between full vias through the same dielectric.

15. The method of claim 13, wherein a size of the pad of the second conductor for the partial via is reduced compared to a size of a pad for a full via through the same dielectric.

16. A semiconductor structure, comprising: a redistribution layer substrate, the redistribution layer substrate comprising: a first dielectric layer having a first aperture; a first conductive layer on the first dielectric layer, wherein the first conductive layer has a full via in the first aperture; a second dielectric layer having a second aperture, wherein the second dielectric layer is on a top surface of the first dielectric layer; and a second conductive layer on a top surface of the second dielectric layer, wherein the second conductive layer has a partial via in the second aperture that contacts the first conductive layer through the second aperture; an electronic device on a top side of the redistribution layer substrate, wherein the electronic device includes an interconnect electrically coupled with the second conductive layer; and an encapsulant on the top side of the redistribution layer substrate, the encapsulant contacting a side of the electronic device; wherein the partial via covers half or less than half of the first conductive layer exposed at a bottom of the second aperture; and wherein a width of the partial via is less than half of a width of the bottom of the second aperture.

17. The semiconductor structure of claim 16, wherein the first dielectric layer has a third via and the first conductive layer has a full via in the third via, and wherein the second dielectric layer has a fourth via and the second conductive layer has a partial via in the fourth via, wherein the full via of the first conductive layer contacts a lower pad exposed at a bottom surface of the first dielectric layer, and the partial via of the second conductive layer contacts a pad of the first conductive layer, wherein the pad of the first conductive layer is smaller in size than the lower pad.

18. The semiconductor structure of claim 16, wherein: an end of the partial via contacts a pad of the first conductive layer; and a trace adjacent to the end of the partial via overlaps a portion of the pad of the first conductive layer not covered by the partial via.

19. The semiconductor structure of claim 16, wherein: the first dielectric layer has a third via and the first conductive layer has a full via in the third via; the second dielectric layer has a fourth via and the second conductive layer has a partial via in the fourth via; the full via of the first conductive layer contacts a lower pad exposed at a bottom surface of the first dielectric layer; the partial via of the second conductive layer contacts a pad of the first conductive layer; the pad of the first conductive layer is smaller in size than the lower pad; and an end of the partial via of the second conductive layer contacts the pad of the first conductive layer.

20. The semiconductor structure of claim 16, wherein: the first dielectric layer has a third via and the first conductive layer has a full via in the third via; the second dielectric layer has a fourth via and the second conductive layer has a partial via in the fourth via; the full via of the first conductive layer contacts a lower pad exposed at a bottom surface of the first dielectric layer; the partial via of the second conductive layer contacts a pad of the first conductive layer; the pad of the first conductive layer is smaller in size than the lower pad; and a trace adjacent to the end of the partial via of the second conductive layer overlaps a portion of the pad of the first conductive layer not covered by the partial via of the second conductive layer.

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