Method of forming semiconductor device

Abstract

The method comprises the following steps: forming a source / drain region; forming a contact etch stop layer over the source / drain region; forming an interlayer dielectric over the contact etch stop layer; and performing an etching process to form contact openings in the interlayer dielectric and the contact etch stop layer. The source / drain region is exposed to the contact opening. A silicide formation process is performed to form a silicide region on a surface of the source / drain region. An etch process is performed to remove metal deposited on the dielectric region, where the dielectric region is exposed during the first silicide formation process. A contact plug is formed in the contact opening. The embodiment of the invention also relates to a method for forming the semiconductor device.

Description

Technical Field

[0001] Embodiments of this application relate to methods for forming semiconductor devices. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the size of the smallest component, which allows more components to be integrated into a given area. However, as the size of the smallest component decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a semiconductor device, including: forming source / drain regions; forming a contact etch stop layer over the source / drain regions; forming an interlayer dielectric over the contact etch stop layer; performing an etching process to form a contact opening in the interlayer dielectric and the contact etch stop layer, such that a dielectric region is exposed to the contact opening, wherein the source / drain regions are exposed to the contact opening; performing a first silicide formation process to form a first silicide region on the surface of the source / drain regions; performing a first etching process to remove metal deposited on the dielectric regions; and forming a contact plug in the contact opening.

[0005] Some other embodiments of this application provide a method for forming a semiconductor device, including: forming a lower source / drain region; forming a first contact etch stop layer above the lower source / drain region; forming a first interlayer dielectric above the first contact etch stop layer; forming an upper source / drain region above the first interlayer dielectric, wherein the upper source / drain region overlaps with the lower source / drain region; forming a second contact etch stop layer above the upper source / drain region; forming a second interlayer dielectric above the second contact etch stop layer; and performing a first etching process to form an interlayer dielectric above the first contact etch stop layer, the first interlayer dielectric, the second contact etch stop layer, and the lower source / drain region. A contact opening is formed in the interlayer dielectric; a first silicide region is selectively formed above the lower source / drain region, wherein the top surface of the upper source / drain region is exposed when the selective formation of the first silicide region is completed; a second silicide region is formed including a first portion located above and in contact with the first silicide region and a second portion located above and in contact with the upper source / drain region; a second etching process is performed, wherein the metal layer deposited in the contact opening and formed by the second silicide region is removed; and contact plugs are formed for contacting the first portion and the second portion of the second silicide region.

[0006] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a lower source / drain region; forming a first contact etch stop layer over the lower source / drain region; forming a first interlayer dielectric over the first contact etch stop layer; forming an upper source / drain region over the first interlayer dielectric, wherein the upper source / drain region overlaps with the lower source / drain region; forming a second contact etch stop layer over the upper source / drain region; forming a second interlayer dielectric over the second contact etch stop layer; forming a first silicide region over the lower source / drain region, wherein the first silicide region includes a p-type silicide region and a first portion of an n-type silicide region located above the p-type silicide region; forming a second silicide region over the upper source / drain region, wherein the second silicide region includes a second portion of the n-type silicide region; and forming a contact plug connecting the first silicide region to the second silicide region. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1A and Figures 1B to 9A and Figure 9B This is a view of an intermediate stage in the formation of the CFET and silicide region according to some embodiments.

[0009] Figure 10A and Figures 10B to 13A and Figure 13B This is a view of an intermediate stage in the formation of the CFET and silicide region according to some embodiments.

[0010] Figure 14A and Figures 14B to 19A and Figure 19B This is a view of an intermediate stage in the formation of the CFET and silicide region according to some embodiments.

[0011] Figures 20 to 23 This is a view of an intermediate stage in the formation of the CFET and silicide region according to some embodiments.

[0012] Figure 24 A flowchart illustrating the formation of CFETs and silicide regions according to some embodiments is shown. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0015] Complementary field-effect transistors (CFETs), silicide regions, and methods for forming the same are provided. According to some embodiments of this disclosure, the silicide region is formed using deposited metal, which simultaneously reacts with an epitaxial semiconductor layer to form the silicide region. An etching process can be performed to remove metal undesirably deposited on the surface of the dielectric region. A reduction process can be performed to reduce metal oxides formed due to vacuum disruption to elemental metals.

[0016] It should be understood that while CFETs include gate-all-around (GAA) transistors (such as nanostructured FETs) as examples, the concepts of embodiments of this disclosure can also be applied to forming silicide regions for other types of transistors such as planar transistors, fin field-effect transistors (FinFETs), etc. Throughout the description, the terms "FET" and "transistor" are used interchangeably.

[0017] The embodiments discussed herein are intended to provide examples of how the subject matter of the embodiments of this disclosure can be made or used, and modifications that can be made while remaining within the scope of consideration of the different embodiments will be readily understood by those skilled in the art. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. While method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0018] Figure 1A and Figures 1B to 9A and Figure 9B A cross-sectional view is shown illustrating intermediate stages in the formation of the CFET and silicide regions according to some embodiments of the present disclosure. The corresponding processes are also schematically reflected in... Figure 24 In the flowchart shown.

[0019] Figure 1A The formation of an exemplary CFET 10 (including FETs (transistors) 10U and 10L) according to some embodiments is shown. The corresponding process is shown as follows. Figure 24 Process 202 in the process flow 200 shown. CFET 10 may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type) opposite to the first device type.

[0020] Nanostructured FETs 10U and 10L include a semiconductor nanostructure 26' (comprising a lower semiconductor nanostructure 26'L and an upper semiconductor nanostructure 26'U), wherein the semiconductor nanostructure 26' serves as the channel region for the nanostructured FET. The lower semiconductor nanostructure 26'L is used in the lower nanostructured FET 10L, and the upper semiconductor nanostructure 26'U is used in the upper nanostructured FET 10U.

[0021] like Figure 1A As shown, a wafer 2 is provided, which includes a substrate 20. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and may be doped (e.g., having p-type or n-type dopants) or undoped. The SOI substrate may include a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate such as a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors, etc., or combinations thereof.

[0022] In the illustrated example, each of the upper FET 10U and the lower FET 10L includes two semiconductor layers 26'U and 26'L as channels, respectively. It should be understood that the upper FET 10U and the lower FET 10L may include any number of channel regions, such as 1, 2, 3, or more. The portions of the gate stack 90 located above and / or below the channel regions 26 form a multilayer stack with the corresponding channel regions 26'U and 26'L.

[0023] Gate stacks 90 (including an upper gate stack 90U and a lower gate stack 90L) are formed between semiconductor layers 26. The upper gate stack 90U includes a gate dielectric 78 and an upper gate electrode 80U. The lower gate stack 90L includes a gate dielectric 78 and a lower gate electrode 80L. The gate dielectric 78 surrounds (when viewed in a side view) the corresponding semiconductor nanostructure 26. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric 78. A dielectric isolation layer 56 is formed to isolate the gate stack 90U of the upper FET 10U from the gate stack 90L of the lower FET 10L. A dummy semiconductor layer 26'M may be formed to contact the dielectric isolation layer 56.

[0024] Source / drain regions 62 (including lower source / drain region 62L and upper source / drain region 62U) are disposed on opposite sides of the gate dielectric 78 and the corresponding gate electrode 80. The source / drain regions may refer to either the source or the drain, individually or collectively, depending on the context.

[0025] An internal spacer 54 (which is a dielectric spacer) is formed on opposite sides of a portion of the gate stack 90 (located between semiconductor layers 26). The internal spacer 54 electrically insulates the source / drain regions 62L and 62U from the corresponding portions of the gate stack 90 to prevent and reduce leakage.

[0026] Gate spacers 44 are formed above the multilayer stack and on the sidewalls of the gate stack 90. ​​Gate spacers 44 can be formed by conformally forming one or more dielectric layers and subsequently anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

[0027] Source / drain regions 62L and 62U are laterally formed between the multilayer stack including channel region 26 and gate stack 90. ​​A lower source / drain region 62L is formed above a substrate (which includes semiconductor substrate 20) to contact the substrate. The lower source / drain region 62L is also in contact with the lower semiconductor nanostructure 26'L, but not with the upper semiconductor nanostructure 26'U.

[0028] The lower source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower source / drain region 62L is an n-type source / drain region, the corresponding material can include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus or arsenic. When the lower source / drain region 62L is a p-type source / drain region, the corresponding material can include silicon or silicon-germanium doped with p-type dopants such as boron or indium. The lower source / drain region 62L can be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopants.

[0029] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed above the lower source / drain region 62L. Suitable dielectric materials for the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc. The first CESL 66 may be formed from a dielectric material that has high etch selectivity relative to the etching of the first ILD 68. For example, the first CESL 66 may include silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc.

[0030] The upper source / drain region 62U is formed to overlap with the first CESL 66 and the first ILD 68, and also with the lower source / drain region 62L. The material of the upper source / drain region 62U can be selected from the same group of candidate materials used to form the lower source / drain region 62L, depending on the desired conductivity type of the upper source / drain region 62U.

[0031] The conductivity type of the upper source / drain region 62U can be opposite to that of the lower source / drain region 62L. In other words, the upper source / drain region 62U can be doped in the opposite way to the lower source / drain region 62L. The upper source / drain region 62U can be in-situ doped with n-type or p-type dopants and / or can be implanted with n-type or p-type dopants.

[0032] A second CESL 70 and a second ILD 72 are formed above the upper source / drain region 62U. The materials can be similar to those of the first CESL 66 and the first ILD 68, and can be the same as or different from those of the first CESL 66 and the first ILD 68 in terms of materials and formation methods, respectively, and will not be discussed in detail herein.

[0033] Figure 1B As shown Figure 1A The cross-sectional view of the structure shown is shown. The cross-section shown can be as follows: Figure 1A Section 1B-1B is formed in the middle. A dielectric isolation region 32, sometimes also called a shallow trench isolation (STI) region 32, is formed above the substrate 20. Semiconductor strips 20' are formed between the STI regions 32 (see also...). Figure 1A Fin spacers 45 can be formed on the sidewall of the top portion of the semiconductor strip 20'. The lower source / drain region 62L, first CESL 66, first ILD 68, upper source / drain region 62U, second CESL 70, and second ILD 72 are shown.

[0034] Figure 1B The formation of contact plug 116 is also shown. According to some embodiments, the formation of contact plug 116 includes etching a second ILD 72, a second CESL 70, a first ILD 68, and a first CESL 66 to form a trench. The trench may extend to an intermediate level between the top and bottom surfaces of the isolation region 32.

[0035] A dielectric pad 114 is formed in the trench. According to some embodiments, the formation of the dielectric pad 114 includes deposition using conformal deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc., to form a conformal dielectric layer. According to some embodiments, the material of the dielectric pad 114 may include silicon oxide, silicon nitride, metal oxides of metals such as Hf, Ti, Al, W, Nb, Re, etc., metal nitrides of metals such as Hf, Ti, Al, W, Nb, Re, etc., or combinations thereof.

[0036] Contact plug 116 is then formed. Contact plug 116 may also be referred to as a vertical local interconnect. According to some embodiments, contact plug 116 comprises a metal, such as tungsten, molybdenum, ruthenium, iridium, or alloys thereof. According to some embodiments, contact plug 116 has a single-layer structure, wherein the entire contact plug 116 is formed of a homogeneous material such as described above.

[0037] According to an optional embodiment, the formation of the contact plug 116 may include depositing a barrier layer, which may include titanium, titanium nitride, tantalum, tantalum nitride, etc. Next, a metallic material in contact with the barrier layer is deposited over the barrier layer. The metallic material may include tungsten, cobalt, copper, nickel, molybdenum, ruthenium, iridium, etc., or combinations thereof.

[0038] After depositing the material used to form the contact plug 116, a planarization process, such as CMP or mechanical polishing, is performed to remove excess material, leaving the contact plug 116. Therefore, the contact plug 116 is surrounded by a dielectric pad 114. The top surfaces of the contact plug 116 and the dielectric pad 114 are coplanar, and can also be coplanar with the top surface of the second ILD 72 when the second ILD 72 is the top layer in the structure.

[0039] refer to Figure 2A and Figure 2B An etch stop layer 118 and a dielectric layer 120 are formed. The corresponding process is shown as follows. Figure 24 Process 204 in the process flow 200 shown. The etch stop layer 118 may include AlN, AlO, SiOC, or multiple layers thereof. The dielectric layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc. The etch stop layer 118 and dielectric layer 120 are patterned by etching to form openings 121 and 122, through which the second ILD 72 and contact plug 116 are exposed.

[0040] Figure 3A and Figure 3B A cross-sectional view showing a further formation of the source / drain contact openings 121 and 122 according to some embodiments is shown. The corresponding process is shown as follows. Figure 24 Process 206 in the process flow 200 shown. For example... Figure 3A The cross-sectional view shown is from Figure 3B The section 3A-3A in the middle was obtained, and as... Figure 3B The cross-sectional view shown is from Figure 3A It was obtained from section 3B-3B.

[0041] Contact openings 121 and 122 are formed by an etching process. In this etching process, the underlying second ILD 72, second CESL 70, contact plug 116, and dielectric pad 114 are exposed. The second ILD 72 and second CESL 70 are etched, exposing the upper source / drain region 62U. On the illustrated right side of contact plug 116, etching passes through portions of the upper source / drain region 62U, followed by etching of the underlying first ILD 68 and first CESL 66. The etching stops on the top surface of the lower epitaxial source / drain region 62L. Some top surfaces of the upper epitaxial source / drain region 62U may also be exposed. For example, on the illustrated left side of contact plug 116, contact opening 121 stops on the top surface of one of the upper source / drain regions 62U.

[0042] It should be understood that etching can be performed using one or more etching masks to achieve the desired pattern. For example, one etching mask can be used to etch through the upper source / drain region 62U, with the etching stopping at the lower source / drain region 62L. Another etching mask can be used to etch portions of the second ILD 72 and the second CESL 70, exposing the top surface of portions of the upper source / drain region 62U.

[0043] refer to Figure 4A and Figure 4B This forms the dielectric pad 124. The corresponding process is shown as follows. Figure 24 Process 208 in the process flow 200 shown. According to some embodiments, the formation of dielectric pad 124 includes depositing a conformal dielectric layer by a conformal deposition process (e.g., by ALD, CVD, PVD, etc.). An anisotropic etching process is then performed to remove the horizontal portion of the conformal layer, leaving the vertical portion as dielectric pad 124.

[0044] The material of dielectric pad 124 may be selected from the same group of candidate materials used to form dielectric pad 114, and may be the same as or different from the material of dielectric pad 114. For example, dielectric pad 124 may be formed of and / or comprise silicon nitride.

[0045] refer to Figure 5A and Figure 5B Selective formation of silicide regions 126P. The corresponding process is shown as follows. Figure 24Process 210 in process flow 200 shown. According to some embodiments, the formation of the silicide region 126P may include introducing certain precursors capable of reacting with germanium but not with silicon into the corresponding reaction chamber. Thus, the p-type silicide region 126P is selectively formed on germanium or SiGe, while no silicide region is formed on the exposed surface of the upper source / drain region 62U (which may include Si but not Ge) and the exposed surface of the dielectric. According to some embodiments, the precursors for selectively forming the silicide region 126P may include M(DAD). x (Where M represents a metal and the value x is an integer). For example, the precursor may include bis(1,4-di-tert-butyl-1,3-diazabutadienyl)nickel(II) (Ni(DAD)2), MeCpMMex (such as trimethyl(methylcyclopentadienyl)platinum(IV)), where the second M represents a metal and x represents a number, etc. Furthermore, an etching gas such as HCl can be added to the precursor to prevent the silicide from growing on the exposed dielectric material.

[0046] Throughout the description, silicides include silicides with high work function (referred to as p-silicides), silicides with low work function (referred to as n-silicides), and silicides with an intermediate work function between that of p-silicides and n-silicides (intermediate work function silicides). For example, intermediate work function silicides may have a work function in the range of about 4.2 eV and about 4.4 eV. P-silicides may have a work function greater than about 4.4 eV. n-silicides may have a work function lower than about 4.2 eV.

[0047] According to some embodiments, silicides having a work function close to that of titanium silicide can be considered intermediate work function silicides, and silicides having a work function greater than that of titanium silicide (Ti(metal)) are p-silicides. Conversely, silicides having a work function lower than that of titanium silicide (Ti(metal)) are n-silicides. Intermediate work function silicides may include VSi, ZnSi, NbSi, AlSi, etc.

[0048] According to some embodiments, depending on the precursor used, the p-type silicide region 126P may include (in addition to Ge or SiGe) a metal selected from molybdenum (Mo), nickel (Ni), ruthenium (Ru), iridium (Ir), palladium (Pd), platinum (Pt), tungsten (W), cobalt (Co), chromium (Cr), osmium (Os), rhenium (Re), rhodium (Rh), iron (Fe), manganese (Mn), vanadium (V), tantalum (Ta), and combinations thereof.

[0049] To initiate the silicide process, gases such as Ar and H2 are introduced along with the precursor gas. Plasma (and RF power) is also turned on. Furthermore, wafer 2 is heated, for example, to a temperature in the range of approximately 300°C to approximately 600°C. The metal in the precursor is deposited on the lower source / drain region 62L and reacts with the exposed surface layer of the lower source / drain region 62L to form a p-type silicide region 126P.

[0050] According to some embodiments, no additional annealing process for forming the p-type silicide region 126P is performed after the silicide process. Furthermore, due to the high selectivity of the selective deposition process, the metal in the precursor does not deposit on the surface of a dielectric material such as the dielectric pad 124.

[0051] Figure 6A and Figure 6B The formation of the n-type silicide region 130N (including n-type silicide regions 130N1 and 130N2) is shown. The corresponding process is shown as follows. Figure 24 Process 212 in the process flow 200 shown. According to some embodiments, the forming process may include introducing a precursor comprising an n-type metal into a corresponding reaction chamber.

[0052] The n-type metal can include Zr, Sb, Ce, Sc, Y, Ub, Er, or combinations thereof. Gases such as Ar and H2 can be introduced. Plasma is also conducted. Furthermore, wafer 2 is heated, for example, to a temperature in the range of approximately 300°C to approximately 600°C. The n-type silicide region 130N can be formed in situ along with the formation of the p-type silicide region 126P, without vacuum disruption between them.

[0053] In the deposition process, silicon and Ge in the lower source / drain region 62L diffuse upward through the p-type silicide region 126P and react with the metal deposited from the precursor to form an n-type silicide region 130N1, which is located above the p-type silicide region 126P. Above the upper source / drain region 62U, silicon reacts with the metal deposited from the precursor to form an n-type silicide region 130N2. According to some embodiments, no additional annealing process for forming the n-type silicide region 130N is performed after the silicide process. The n-type silicide regions 130N1 and 130N2 are collectively referred to as the n-type silicide region 130N.

[0054] In the silicide process, due to the low selectivity in the deposition of n-type metals, a thin metal layer 132 is deposited on the surface of the dielectric layer simultaneously with the silicide process. Therefore, the metal layer 132 comprises the same metal as the n-type silicide region 130N. The metal in the metal layer 132 may comprise an elemental metal (which comprises metal atoms) rather than a metal compound. It should be understood that although the metal layer 132 is shown as a continuous layer, it can also be a discontinuous layer comprising multiple discrete metal islands. The surface of the underlying dielectric region (such as dielectric pad 124) can be exposed by the discrete metal islands. Exemplary discrete metal islands can be formed by, for example, Figure 23 The discrete metal regions 182A and 182B shown are represented in the diagram.

[0055] Further reference Figure 6A and Figure 6B An etching process 134 is performed to selectively etch the metal layer 132 without etching the silicide regions 132N (including silicide regions 132N1 and 132N2) and exposed dielectric regions such as dielectric pads 124. The corresponding process is shown as follows: Figure 24 Process 214 in the process flow 200 shown. According to some embodiments, the selective etching process is implemented using an immersion process with an etching gas comprising metal halides. The resulting structure is... Figure 7A and Figure 7B As shown in the image.

[0056] Metal halides can be selected from titanium chloride (TiCl4), nickel halides (e.g., nickel fluoride (NiF2), nickel dichloride (NiCl2), nickel bromide (NiBr2), nickel iodide (NiI2), molybdenum halides (e.g., molybdenum fluoride (MoF4 and / or MoF5), molybdenum chloride (MoCl2, MoCl3, MoCl4, MoCl5, MoCl6), molybdenum bromide (MoBr2, MoBr4) etc.), platinum halides (e.g., platinum fluoride (PtF2, PtF3), platinum chloride (PtCl2, PtCl4), platinum bromide (PtBr2), platinum iodide (PtI2, PtI4) etc.), palladium halides (… For example, palladium fluoride (PdF2, PdF3, PdF4, PdF6), palladium dichloride (PdCl2, PdCl3, PdCl4), palladium bromide (PdBr2, PdBr4), palladium iodide (PdI2, PdI4)), cobalt halides (e.g., cobalt fluoride (CoF2, CoF3), cobalt chloride (CoCl2, CoCl3), cobalt iodide (CoI2)), titanium halides (e.g., titanium fluoride (TiF3, TiF4), titanium chloride (TiCl2, TiCl3, TiCl4), titanium bromide (TiBr2, TiBr3, TiBr4), titanium iodide (TiI2, TiI4) etc.).

[0057] Metal halides can also be selected from erbium halides (e.g., erbium fluoride (ErF2, ErF3), erbium chloride (ErCl3), erbium bromide (ErBr3), erbium iodide (ErI3), etc.), zirconium halides (e.g., zirconium fluoride (ZrF3, ZrF4), zirconium chloride (ZrCl2, ZrCl3, ZrCl4), zirconium bromide (ZrBr2, ZrBr3, ZrBr4), zirconium iodide (ZrI2, ZrI4), etc.), and hafnium halides (hafnium fluoride (HfF3, HfF4), hafnium chloride (HfCl2, HfCl3, HfCl4)). Hafnium bromide (HfBr2, HfBr3, HFBr4), hafnium iodide (HfI2, HfI4), etc.), tungsten halides (e.g., tungsten fluoride (WF4, WF6), tungsten chloride (WCl2, WCl3, WCl4, WCl5, WCl6), tungsten bromide (WBr2, WBr5, WBr6)), ruthenium halides (e.g., ruthenium chloride (RuCl2, RuCl3, RuCl4), ruthenium bromide (RuBr3, RuBr4), ruthenium fluoride (RuF3, RuF4), ruthenium iodide (RuI3), etc.) or combinations thereof.

[0058] The etching gas may (or may not) include hydrogen halides, such as HF, HBr, HCl, HI, or combinations thereof. No plasma is generated during the etching process. RF power may not be applied, or if applied, it may not be high enough to generate plasma. Furthermore, Ar may not be introduced, and H2 may not be introduced.

[0059] According to some embodiments, etching can be performed at wafer temperatures ranging from about 20°C to about 600°C.

[0060] In comparison, according to some embodiments, during the entire time period after the formation of silicide region 126P and before the formation of n-type silicide region 130N (e.g. Figure 6A and Figure 6B As shown in the diagram, no etching process using metal halides was implemented to etch the metal. This is partly due to the highly selective formation of the silicide region 126P, which resulted in no metal layer being formed on the dielectric material and the upper source / drain region 62U.

[0061] Next step, refer to Figure 8A and Figure 8B This forms contact plugs 140A and 140B, which are individually and collectively referred to as contact plug 140. The corresponding process is shown as follows: Figure 24Process 216 in process flow 200 shown. Contact plugs 140A and 140B may be referred to as source / drain contact plugs, and contact plug 140A may be referred to as upper source / drain contact plug. According to some embodiments, contact plugs 140A and 140B comprise metals such as tungsten, molybdenum, ruthenium, iridium, or alloys thereof. According to some embodiments, contact plugs 140A and 140B have a single-layer structure, wherein the entire contact plugs 140A and 140B are formed of a homogeneous material such as described above.

[0062] According to an optional embodiment, the formation of contact plugs 140A and 140B may include forming a barrier layer, which may include titanium, titanium nitride, tantalum, tantalum nitride, etc. Next, a metallic material in contact with the barrier layer is deposited over the barrier layer. The metallic material may include tungsten, cobalt, copper, nickel, molybdenum, ruthenium, iridium, etc., or combinations thereof.

[0063] Further reference Figure 8A and Figure 8B After depositing the material used to form the contact plugs 140, a planarization process, such as CMP or mechanical polishing, is performed to remove excess material, leaving contact plugs 140A and 140B. Therefore, contact plugs 140A and 140B are surrounded by a dielectric pad 124. Thus, the top surfaces of contact plugs 140A and 140B and the dielectric pad 124 are coplanar, and may also be coplanar with the top surface of the dielectric layer 120.

[0064] According to some embodiments, as discussed above, in etching process 134 ( Figure 6A and Figure 6B The metal layer 132 is removed during etching. According to an optional embodiment, etching process 134 is not performed, and the metal layer 132 is not removed during this stage. During the formation of... Figure 7A and Figure 7B After the structure shown is formed and before the contact plugs 140A and 140B are formed, vacuum destruction can be performed to oxidize the metal layer 132. Therefore, it is possible to perform... Figures 20 to 23 The process shown is used to reduce the oxidized metal layer 132 back to metal. According to these embodiments, discrete metal islands 182A and 182B are schematically shown to represent the elemental metal layer 132 when the metal layer 132 is not etched. The discrete metal islands 182A and 182B comprise the same metal as the underlying n-type silicide layer 130N.

[0065] Figure 9A and Figure 9B The formation of the back-side source / drain contact plug 160 (electrically connected to the lower source / drain region 62L) and the formation of the back-side redistribution lines are also shown. The corresponding process is shown as follows: Figure 24Process 218 in the process flow 200 shown. According to some embodiments, substrate 20 is removed, for example, by a CMP process and / or an etching process. Figure 8A and Figure 8B ). It can form a dielectric substrate 156 ( ). Figure 9A ).

[0066] Etched semiconductor strip 20' ( Figure 8A and Figure 8B A back-side opening is formed, through which the bottom of the lower source / drain region 62L is exposed. A silicide region 158 is formed below the bottom surface of the lower source / drain region 62L, contacting the bottom surface of the lower source / drain region 62L. The material and formation process of the silicide region 158 can be substantially the same as those of silicide regions 126P and / or 130N, and will not be repeated here. For example, the silicide region 158 may include the same p-type silicide region as the p-type silicide region 126P, and may or may not include the same n-type silicide region as the n-type silicide region 130N.

[0067] A back-side contact plug 160 is formed to fill the remaining back-side contact opening. The back-side contact plug 160 contacts the silicide region 158. The back-side contact plug 160 can be formed of a homogeneous metallic material, which may include tungsten, cobalt, ruthenium, etc. Optionally, the formation of the back-side contact plug 160 may include forming a barrier layer (the barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.) and a homogeneous metallic material on the barrier layer. A planarization process, such as CMP or mechanical polishing, is then performed to remove excess material, leaving the back-side contact plug 160.

[0068] Then, a dielectric layer 164 is deposited. A back redistribution line 162 (conductive component 162) is formed on the back side of the CFET and in the dielectric layer 164. The back redistribution line 162 is electrically connected to the contact plug 116 and to the lower source / drain region 62L.

[0069] Figure 10A and Figures 10B to 13A and Figure 13B A cross-sectional view is shown of an intermediate stage in the formation of a CFET according to some embodiments of the present disclosure. According to these embodiments, n-type silicide regions in contact with the lower source / drain region 62L and the upper source / drain region 62U are formed on the lower source / drain region 62L and the upper source / drain region 62U. Unless otherwise stated, these embodiments (and...) Figure 14A and Figures 14B to 19A and Figure 19BThe materials, structure, and forming processes of the components in the embodiments are substantially the same as those of the same components indicated by the same reference numerals in the foregoing embodiments. Throughout the description, the details regarding materials, structure, and forming processes provided in each of the embodiments can be applied to any other embodiments where applicable.

[0070] The initial steps of these embodiments and Figure 1A and Figures 1B to 4A and Figure 4B The results shown are essentially the same. The next step, as... Figure 10A and Figure 10B As shown, silicide regions 130N (including 130N1 and 130N2) are formed. The materials, structures, and formation methods of silicide regions 130N1 and 130N2 can be compared with those of... Figure 6A and Figure 6B The diagram shown is essentially the same and will not be repeated here. The n-type silicide regions 130N1 and 130N2 are physically in contact with the source / drain regions 62L and 62U below, respectively.

[0071] During the formation of n-type silicide regions 130N1 and 130N2, a metal layer 132 can be simultaneously formed on the exposed dielectric regions due to the low selectivity in the deposition of the n-type metal. According to some embodiments, the metal layer 132 is removed by an etching process 134, which can be combined with [reference to...] Figure 6A and Figure 6B The etching process 134 discussed is essentially the same. Therefore, the metal layer 132 is removed, and the resulting structure is as follows: Figure 11A and Figure 11B As shown in the image.

[0072] According to an optional embodiment, the metal layer 132 is not removed, and the subsequent vacuum destruction process can oxidize the metal layer 132, thus forming a metal oxide. Then, the following can be implemented: Figures 21 to 24 The process shown is used to reduce metal oxides to elemental metals.

[0073] Figure 12A and Figure 12B The formation of contact plugs 140A and 140B is shown. The formation process can be compared with... Figure 8A and Figure 8B The formation process is basically the same. Therefore, details will not be repeated here. According to some embodiments, when implementing... Figures 21 to 24During the process shown, metal islands 182A and 182B comprising elemental metals (metal islands 182A and 182B can be discrete islands or continuous metal layers) can be present at the edges and bottom of contact plugs 140A and 140B. The metal in metal islands 182A and 182B can be the same metal used to form silicide regions 130N1 and 130N2. According to an alternative embodiment, metal islands 182A and 182B will not be present when metal layer 132 is removed by etching process 134.

[0074] Figure 13A and Figure 13B The formation of a back-side structure for connecting from the back side of wafer 2 to the lower source / drain region 62L is shown. The materials, structure, and formation process can be compared with reference to... Figure 9A and Figure 9B The discussion is essentially the same, and will not be repeated here.

[0075] Figure 14A and Figures 14B to 19A and Figure 19B A cross-sectional view is shown of an intermediate stage in the formation of the CFET and silicide regions according to some embodiments of the present disclosure. According to these embodiments, an n-type silicide region and a titanium silicide (TiSi) layer are formed on the lower source / drain region 62L and the upper source / drain region 62U.

[0076] refer to Figure 14A and Figure 14B This forms n-type silicide regions 130N1 and 130N2. Materials, structure, and formation process are referenced. Figure 6A and Figure 6B The discussion is essentially the same and will not be repeated here. The n-type silicide regions 130N1 and 130N2 are physically in contact with the source / drain regions 62L and 62U below, respectively.

[0077] During the formation of n-type silicide regions 130N1 and 130N2, a metal layer 132 is also formed on the exposed dielectric regions. According to some embodiments, the metal layer 132 is removed by an etching process 134, which can be compared with a reference... Figure 6A and Figure 6B The discussion is essentially the same. Therefore, metal layer 132 is removed, and the resulting structure is as follows. Figure 15A and Figure 15B As shown in the image.

[0078] According to an optional embodiment, metal layer 132 is not removed, and the subsequent vacuum destruction process may result in the formation of a metal oxide. Then, as... Figures 20 to 23 The process shown is used to reduce metal oxides to elemental metals.

[0079] refer to Figure 16A and Figure 16B Silicide regions 170A and 170B are formed. Silicide regions 170A and 170B are located above and in physical contact with the underlying n-type silicide regions 130N1 and 130N2, respectively. Silicide regions 170A and 170B (individually and collectively referred to as silicide region 170) are intermediate work-function silicide regions and have a work function higher than that of the underlying n-type silicide region 130. According to some embodiments, silicide regions 170A and 170B are formed of or comprise titanium silicide, although other silicides such as VSi, ZnSi, NbSi, AlSi, etc., may be used. Stacked layers comprising n-type silicide layers and intermediate work-function silicide layers have been found to improve the performance of n-type and p-type transistors.

[0080] The formation of silicide regions 170A and 170B can be substantially the same as that of n-type silicide regions 130N1 and 130N2. For example, the formation process may include: introducing a precursor comprising a corresponding metal (such as Ti); introducing Ar and / or H2; conducting plasma; and heating wafer 2. The metal in the precursor reacts with silicon and / or germanium in the lower source / drain region 62L and the upper source / drain region 62U to form silicide regions 170A and 170B. For example, Si and Ge diffuse through n-type silicide regions 130N1 and 130N2 to react with the metal.

[0081] According to some embodiments, when forming silicide regions 170A and 170B, a metal layer 174 is formed on the surface of the exposed dielectric region. The metal layer 174 comprises an elemental metal (rather than a metal compound) corresponding to a metal such as Ti, depending on the metal in the precursor.

[0082] According to some embodiments, the metal layer 174 is removed by an etching process 172, which can be compared with a reference. Figure 6A and Figure 6B The etching process 134 discussed is essentially the same. For example, metal halides (such as TiCl4) as described above can be used as the etching gas, wherein no plasma is conducted and no Ar and H2 are introduced. Thus, the metal layer 174 is removed, and the resulting structure is as follows... Figure 17A and Figure 17B As shown in the image.

[0083] According to an optional embodiment, metal layer 174 is not removed, and the subsequent vacuum destruction process allows for the formation of a metal oxide. Then, the following can be implemented: Figures 20 to 23 The process shown is used to reduce metal oxides to elemental metals.

[0084] Figure 18A and Figure 18B The formation of contact plugs 140A and 140B is shown. The formation process can be compared with... Figure 8A and Figure 8B The formation process is basically the same. Therefore, details will not be repeated here. According to some embodiments, when implementing... Figures 20 to 23 During the process illustrated, metal islands 182A and 182B (which may be discrete islands or continuous metal layers comprising elemental metals) may be present at the edges and bottom of contact plugs 140A and 140B. The metal in metal islands 182A and 182B may be the same metal used to form silicide regions 130N1 and 130N2 and / or silicide regions 170A and 170B. According to an alternative embodiment, metal islands 182A and 182B will not be present when metal layers 132 and 174 are removed by etching processes 134 and 172.

[0085] Figure 19A and Figure 19B The formation of a back-side structure for connecting from the back side of wafer 2 to the lower source / drain region 62L and contact plug 116 is shown. The materials, structure, and formation process can be compared with reference to [reference]. Figure 9A and Figure 9B The discussion is essentially the same, and will not be repeated here.

[0086] Figures 20 to 23 It shows that it can be used as such Figure 1A and Figures 1B to 9A and Figure 9B The process shown, such as Figure 10A and Figures 10B to 13A and Figure 13B The process shown or such Figure 14A and Figures 14B to 19A and Figure 19B The process shown is a portion of the process steps to be implemented. For example... Figures 20 to 23 The process shown can be inserted after the formation of the silicide region and before the formation of contact plugs 140A and 140B.

[0087] refer to Figure 20 This forms silicide region 176. For example... Figure 20 The structure shown can represent Figure 6A and Figure 6B (When metal layer 132 is not removed) or Figure 7A and Figure 7B The structure shown Figure 10A and Figure 10B (When metal layer 132 is not removed) or Figure 11A and Figure 11B The structure shown or as Figure 16A and Figure 16B(When metal layers 132 and / or 174 are not removed) or Figure 17A and Figure 17B The structure shown. Therefore, Figure 20 The silicide region 176 in the figure can represent the corresponding silicide region in these figures.

[0088] Next step, such as Figure 21 As shown, a vacuum destruction process is performed. The vacuum destruction process causes partial oxidation of the surface of the silicide region 176 exposed to open air, forming metal oxide regions 178 (including metal oxide regions 178A and 178B). Metal oxide region 178A is formed on the surface of the dielectric region. Metal oxide region 178B is formed on the surface of the silicide region 176. Metal oxide regions 178B and the possible metal oxide regions 178A may include metal and silicon / germanium from the silicide region 176. The corresponding metal oxide can be represented as M-Si-OX, where M represents a metal, Si represents silicon and / or Ge, and OX represents an oxide formed by M and Si.

[0089] According to some embodiments, metal oxide region 178A may include M-Si-OX, which can be formed on dielectric pad 124 by reacting a metal with oxygen in open air and with SiN when dielectric pad 124 includes SiN. Otherwise, when dielectric pad 124 includes silicon oxide, the resulting metal oxide region 178A includes metal oxide instead of M-Si-OX. Therefore, metal oxide region 178A (which is formed on the top surface of dielectric pad 124 and dielectric region) may include Mi-Si-OX or metal oxide. Metal oxide region 178B (which is the oxidized portion of silicide region 176) may include Mi-Si-OX. It should be understood that metal oxide regions 178A and 178B may form discrete islands separated from each other, or they may form a continuous layer.

[0090] Figure 21 A reduction process 180, also known as a pre-cleaning process, is also shown. Reduction process 180 is performed to reduce metal oxide regions 178 to metal regions 182 (including metal regions 182A and 182B), wherein the metal regions 182 comprise elemental metals (rather than metal compounds). The resulting structure is... Figure 22 As shown in the image.

[0091] The elemental metal is the same as the metal in the silicide region below. According to some embodiments, the reduction process 180 is implemented using an immersion process with a reducing gas comprising a metal halide. The reducing gas can be selected from, for example, etching process 134. Figure 6A and Figure 6BThe same candidate process gas group is used in the reduction process 180. According to some embodiments, the reducing gas may include WCl5, TiCl4, etc. In reduction process 180, no plasma is conducted. Furthermore, no process gases such as H2, Ar, etc., are applied. RF power may also not be applied.

[0092] It should be understood that the same process gases can be used for etching process 134 (or 172) and reduction process 180. Whether the result is etching or reduction depends on the gas and process conditions. For example, TiCl4 is more likely to etch TiO2. x The process reduces the metal to titanium, and more likely etches titanium. It may also etch elemental metals reduced from metal oxides (when further exposed to process gases). Therefore, process conditions such as some process gases, lower flow rates of process gases, and shorter reaction times may produce reduction process 180, while other selected process gases, higher flow rates of process gases, and longer reaction times may produce etching processes 134 and 172.

[0093] like Figure 22 As shown, according to some embodiments, elemental metal regions 182 (including elemental metal islands 182A and / or 182B) are formed. Elemental metal regions 182 comprise the same metal as the silicide regions, and the formation of the silicide regions produces a metal layer. Furthermore, according to some embodiments using WCl5, in addition to the metals in metal layers 132 and 174, elemental tungsten may be left as part of the elemental metal regions 182.

[0094] Figure 23 The formation of contact plugs 140A and 140B is shown, which is also in Figure 9A and Figure 9B , Figure 13A and Figure 13B or Figure 19A and Figure 19B As shown in the diagram, the elemental metal region 182 can be used as a nucleation layer for better deposition to form contact plugs 140A and 140B. Therefore, it is less likely that voids will be formed in contact plugs 140A and 140B. The contact resistance between the resulting contact plugs and the silicide region is also reduced by converting the metal oxide into the elemental metal region.

[0095] The embodiments of this disclosure have several advantageous features. Contact plugs are easier to form by removing the metal layer formed in the contact openings, because the space occupied by the contact openings is freed up for contact plug formation. The undesirable increase in resistance due to the metal oxide is reduced by reducing the metal oxide formed due to vacuum disruption to the elemental metal, and the contact plug formation process is easier because the elemental metal serves as the nucleation layer.

[0096] According to some embodiments of this disclosure, the method includes: forming source / drain regions; forming a contact etch stop layer over the source / drain regions; forming an interlayer dielectric over the contact etch stop layer; performing an etching process to form a contact opening in the interlayer dielectric and the contact etch stop layer, wherein the source / drain regions are exposed to the contact opening; performing a first silicide formation process to form a first silicide region on the surface of the source / drain regions; performing a first etching process to remove metal deposited on the dielectric region, wherein the dielectric region is exposed during the first silicide formation process; and forming a contact plug in the contact opening.

[0097] In one embodiment, the first etching process is performed in a plasma-free and hydrogen-free (H2-free) environment. In another embodiment, the source / drain regions comprise germanium, and the method further includes performing a selective deposition process prior to the first silicide formation process to form a second silicide region contacting the source / drain regions above the source / drain regions, wherein the first silicide region is located above and in contact with the second silicide region. In another embodiment, the first silicide region is an n-type silicide region, and the second silicide region is a p-type silicide region.

[0098] In an embodiment, the first etching process is performed using a first metal halide as the etching gas, and the first silicide formation process is performed using a second metal halide as a precursor. In an embodiment, the first and second metal halides comprise the same metal. In an embodiment, the method further includes: after the first silicide formation process, performing a second silicide formation process to form a second silicide region contacting the first silicide region over the first silicide region; and after the second silicide formation process, performing a second etching process to remove additional metal deposited on the dielectric region. In an embodiment, the second silicide formation process is performed after the first etching process.

[0099] In one embodiment, the method further includes: after forming the first silicide region, performing vacuum destruction to expose the first silicide region to open air, wherein a metal oxide is formed in the contact opening; and after vacuum destruction, introducing a metal halide gas to reduce the metal oxide to an elemental metal. In another embodiment, the first etching process is also performed using a metal halide gas. In yet another embodiment, the method further includes forming a dielectric pad in the contact opening prior to the first silicide formation process.

[0100] According to some embodiments of this disclosure, the method includes: forming a lower source / drain region; forming a first contact etch stop layer above the lower source / drain region; forming a first interlayer dielectric above the first contact etch stop layer; forming an upper source / drain region above the first interlayer dielectric, wherein the upper source / drain region overlaps with the lower source / drain region; forming a second contact etch stop layer above the upper source / drain region; forming a second interlayer dielectric above the second contact etch stop layer; and performing a first etch process to etch the first contact etch stop layer, the first interlayer dielectric, the second contact etch stop layer, and the second interlayer dielectric. A contact opening is formed in the material; a first silicide region is selectively formed above the lower source / drain region, wherein the top surface of the upper source / drain region is exposed when the selective formation of the first silicide region is completed; a second silicide region is formed including a first portion located above and in contact with the first silicide region and a second portion located above and in contact with the upper source / drain region; a second etching process is performed, wherein the metal layer deposited in the contact opening and formed by the formation of the second silicide region is removed; and contact plugs are formed to contact the first portion and the second portion of the second silicide region.

[0101] In one embodiment, the dielectric region facing the contact opening is exposed at the beginning of the formation of the second silicide region. In another embodiment, the second silicide region and the metal layer are formed simultaneously. In yet another embodiment, the second silicide region and the second etching process are performed using a halide gas. In yet another embodiment, no etching process is performed to remove additional metal from the contact opening during the entire period after the formation of the first silicide region and before the formation of the second silicide region.

[0102] According to some embodiments of this disclosure, the method includes: forming a lower source / drain region; forming a first contact etch stop layer over the lower source / drain region; forming a first interlayer dielectric over the first contact etch stop layer; forming an upper source / drain region over the first interlayer dielectric, wherein the upper source / drain region overlaps with the lower source / drain region; forming a second contact etch stop layer over the upper source / drain region; forming a second interlayer dielectric over the second contact etch stop layer; forming a first silicide region over the lower source / drain region, wherein the first silicide region includes a p-type silicide region and a first portion of an n-type silicide region located above the p-type silicide region; forming a second silicide region over the upper source / drain region, wherein the second silicide region includes a second portion of the n-type silicide region; and forming a contact plug connecting the first silicide region to the second silicide region.

[0103] In one embodiment, a second portion of the n-type silicide region is located between the upper source / drain region and the contact plug, and is in physical contact with both the upper source / drain region and the contact plug. In another embodiment, the contact plug comprises a homogeneous material in contact with both the first and second silicide regions. In yet another embodiment, the p-type silicide region is in physical contact with the lower source / drain region.

[0104] Some embodiments of this application provide a method for forming a semiconductor device, including: forming source / drain regions; forming a contact etch stop layer over the source / drain regions; forming an interlayer dielectric over the contact etch stop layer; performing an etching process to form a contact opening in the interlayer dielectric and the contact etch stop layer, such that a dielectric region is exposed to the contact opening, wherein the source / drain regions are exposed to the contact opening; performing a first silicide formation process to form a first silicide region on the surface of the source / drain regions; performing a first etching process to remove metal deposited on the dielectric regions; and forming a contact plug in the contact opening.

[0105] In some embodiments, the first etching process is performed in a plasma-free and hydrogen-free (H2-free) environment. In some embodiments, the source / drain region comprises germanium, and the method further comprises: performing a selective deposition process prior to the first silicide formation process to form a second silicide region contacting the source / drain region over the source / drain region, wherein the first silicide region is located above and in contact with the second silicide region. In some embodiments, the first silicide region is an n-type silicide region, and the second silicide region is a p-type silicide region. In some embodiments, the first etching process is performed using a first metal halide as an etching gas, and the first silicide formation process is performed using a second metal halide as a precursor. In some embodiments, the first metal halide and the second metal halide comprise the same metal. In some embodiments, the method further comprises: performing a second silicide formation process after the first silicide formation process to form a second silicide region contacting the first silicide region over the first silicide region; and performing a second etching process after the second silicide formation process to remove additional metal deposited on the dielectric region. In some embodiments, the second silicide formation process is performed after the first etching process. In some embodiments, the method further includes: after forming the first silicide region, performing a vacuum destruction to expose the first silicide region to open air, wherein a metal oxide is formed in the contact opening; and after the vacuum destruction, introducing a metal halide gas to reduce the metal oxide to an elemental metal. In some embodiments, the first etching process is also performed using the metal halide gas. In some embodiments, the method further includes forming a dielectric pad in the contact opening prior to the first silicide formation process.

[0106] Some other embodiments of this application provide a method for forming a semiconductor device, including: forming a lower source / drain region; forming a first contact etch stop layer above the lower source / drain region; forming a first interlayer dielectric above the first contact etch stop layer; forming an upper source / drain region above the first interlayer dielectric, wherein the upper source / drain region overlaps with the lower source / drain region; forming a second contact etch stop layer above the upper source / drain region; forming a second interlayer dielectric above the second contact etch stop layer; and performing a first etching process to form an interlayer dielectric above the first contact etch stop layer, the first interlayer dielectric, the second contact etch stop layer, and the lower source / drain region. A contact opening is formed in the interlayer dielectric; a first silicide region is selectively formed above the lower source / drain region, wherein the top surface of the upper source / drain region is exposed when the selective formation of the first silicide region is completed; a second silicide region is formed including a first portion located above and in contact with the first silicide region and a second portion located above and in contact with the upper source / drain region; a second etching process is performed, wherein the metal layer deposited in the contact opening and formed by the second silicide region is removed; and contact plugs are formed for contacting the first portion and the second portion of the second silicide region.

[0107] In some embodiments, at the start of the formation of the second silicide region, the dielectric region facing the contact opening is exposed. In some embodiments, the second silicide region and the metal layer are formed simultaneously. In some embodiments, the second silicide region and the second etching process are performed using a halide gas. In some embodiments, no etching process is performed to remove additional metal from the contact opening during the entire period after the formation of the first silicide region and before the formation of the second silicide region.

[0108] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a lower source / drain region; forming a first contact etch stop layer over the lower source / drain region; forming a first interlayer dielectric over the first contact etch stop layer; forming an upper source / drain region over the first interlayer dielectric, wherein the upper source / drain region overlaps with the lower source / drain region; forming a second contact etch stop layer over the upper source / drain region; forming a second interlayer dielectric over the second contact etch stop layer; forming a first silicide region over the lower source / drain region, wherein the first silicide region includes a p-type silicide region and a first portion of an n-type silicide region located above the p-type silicide region; forming a second silicide region over the upper source / drain region, wherein the second silicide region includes a second portion of the n-type silicide region; and forming a contact plug connecting the first silicide region to the second silicide region.

[0109] In some embodiments, the second portion of the n-type silicide region is located between the upper source / drain region and the contact plug, and is in physical contact with both the upper source / drain region and the contact plug. In some embodiments, the method further includes forming a plurality of discrete metal islands between the second silicide region and the contact plug. In some embodiments, the p-type silicide region is in physical contact with the lower source / drain region.

[0110] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method of forming a semiconductor device, comprising: forming a source / drain region; forming a contact etch stop layer over the source / drain region; forming an interlayer dielectric over the contact etch stop layer; performing an etch process to form a contact opening in the interlayer dielectric and the contact etch stop layer such that a dielectric region is exposed to the contact opening, wherein the source / drain region is exposed to the contact opening; performing a first silicide formation process to form a first silicide region on a surface of the source / drain region; performing a first etch process to remove metal deposited on the dielectric region; and forming a contact plug in the contact opening.

2. The method of claim 1, wherein, The first etch process is performed in a plasma-free and hydrogen-free (H2-free) environment.

3. The method of claim 1, wherein, The source / drain region includes germanium, and the method further comprises: prior to the first silicide formation process, performing a selective deposition process to form a second silicide region over the source / drain region that contacts the source / drain region, wherein the first silicide region is over and contacts the second silicide region.

4. The method of claim 3, wherein, The first silicide region is an n-type silicide region, and the second silicide region is a p-type silicide region.

5. The method of claim 1, wherein, The first etch process is performed using a first metal halide as an etch gas, and the first silicide formation process is performed using a second metal halide as a precursor.

6. The method of claim 5, wherein, The first metal halide and the second metal halide include the same metal.

7. The method of claim 1, further comprising: after the first silicide formation process, performing a second silicide formation process to form a second silicide region over the first silicide region that contacts the first silicide region; and after the second silicide formation process, performing a second etch process to remove additional metal deposited on the dielectric region.

8. The method of claim 7, wherein, The second silicide formation process is performed after the first etch process.

9. A method of forming a semiconductor device, comprising: forming a lower source / drain region; forming a first contact etch stop layer over the lower source / drain region; forming a first interlayer dielectric over the first contact etch stop layer; forming an upper source / drain region over the first interlayer dielectric, wherein the upper source / drain region overlaps the lower source / drain region; forming a second contact etch stop layer over the upper source / drain region; forming a second interlayer dielectric over the second contact etch stop layer; performing a first etch process to form a contact opening in the first contact etch stop layer, the first interlayer dielectric, the second contact etch stop layer, and the second interlayer dielectric; selectively forming a first silicide region over the lower source / drain region, wherein a top surface of the upper source / drain region is exposed when the selectively forming the first silicide region is complete; forming a second silicide region including a first portion located over and contacting the first silicide region and a second portion located over and contacting the upper source / drain region; performing a second etch process in which a metal layer located in the contact opening and deposited by forming the second silicide region is removed; and forming a contact plug contacting the first and second portions of the second silicide region.

10. A method of forming a semiconductor device, comprising: forming a lower source / drain region; forming a first contact etch stop layer over the lower source / drain region; forming a first interlayer dielectric over the first contact etch stop layer; forming an upper source / drain region over the first interlayer dielectric, wherein the upper source / drain region overlaps the lower source / drain region; forming a second contact etch stop layer over the upper source / drain region; forming a second interlayer dielectric over the second contact etch stop layer; forming a first silicide region over the lower source / drain region, wherein the first silicide region includes a p-type silicide region and a first portion of an n-type silicide region located over the p-type silicide region; forming a second silicide region over the upper source / drain region, wherein the second silicide region includes a second portion of the n-type silicide region; and forming a contact plug connecting the first silicide region to the second silicide region.

Images