Display device

Abstract

A display device includes a display panel including a display area and a non-display area, a plurality of signal wirings arranged in the display area, a plurality of fan-out wirings arranged in the non-display area and electrically connected to the signal wirings, and a plurality of connection wirings connecting the signal wirings to the fan-out wirings, wherein some of the plurality of fan-out wirings cross and overlap each other in a plan view.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0083332, filed on July 10, 2019, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Exemplary embodiments of the present invention relate to display devices. Background Technology

[0003] The importance of display devices has grown with the development of multimedia. Correspondingly, various display devices such as liquid crystal displays (“LCDs”) and organic light-emitting displays (“OLEDs”) are being used. Among these display devices, OLEDs are self-emitting devices and are attracting attention as the next generation of display devices due to their excellent viewing angles.

[0004] Each OLED panel includes a pixel circuit and a driving section for driving the pixel circuit. The driving section typically includes a scan driving section that provides scan signals to the pixel circuit and a data driving section that provides data signals to the pixel circuit. The driving circuits of the scan driving section and the data driving section can be arranged in a non-display area adjacent to the display area, and from the perspective of the display device's function, the non-display area is an inactive area. Summary of the Invention

[0005] An exemplary embodiment of the present invention provides a display device that can minimize the non-display area of ​​the display device and improve display quality.

[0006] It should be noted that the purpose of this invention is not limited to the above-described purpose, and other purposes of this invention will be apparent to those skilled in the art from the following description.

[0007] An exemplary embodiment provides a display device, including: a display panel including a display area and a non-display area; a plurality of signal wirings arranged in the display area; a plurality of fan-out wirings arranged in the non-display area and electrically connected to the signal wirings; and a plurality of connection wirings connecting the signal wirings to the fan-out wirings, wherein some of the plurality of fan-out wirings intersect each other and overlap each other in a plan view.

[0008] In an exemplary embodiment, the display panel may include a curved region, and some of the fan-out wires of the plurality of fan-out wires intersect each other in a non-display region between the display region and the curved region.

[0009] In an exemplary embodiment, one of the fan-out wires that intersect with each other among the plurality of fan-out wires contacts the signal wire, and another fan-out wire that intersects with each other among the plurality of fan-out wires may contact the connection wire.

[0010] In an exemplary embodiment, the fan-out wiring in contact with the connection wiring may include a first conductive layer, wherein the fan-out wiring in contact with the signal wiring includes a second conductive layer, wherein the signal wiring includes a third conductive layer, and wherein the second conductive layer is disposed between the first conductive layer and the third conductive layer.

[0011] In an exemplary embodiment, the connection wiring may include a fourth conductive layer, and the connection wiring is electrically connected to the signal wiring through a contact hole that passes through an insulating layer disposed between the connection wiring and the signal wiring and exposes one end of the signal wiring.

[0012] In an exemplary embodiment, the connection wiring may include: a first portion extending in a first direction; a second portion extending from one end of the first portion in a second direction intersecting the first direction; and a third portion extending from one end of the second portion in a direction opposite to the first direction, wherein the first portion and the third portion are spaced apart.

[0013] In an exemplary embodiment, the display panel may include a curved region, a main region disposed on one side of the curved region, and a sub-region extending from the other side of the curved region, and some of the fan-out wirings intersect each other in the sub-region.

[0014] An exemplary embodiment provides a display device including a display area and a non-display area. The display device includes: first to fourth signal wirings disposed in the display area; first to fourth fan-out wirings disposed in the non-display area and electrically connected to the first to fourth signal wirings respectively; a first connecting wiring disposed in the display area and connecting the first signal wirings to the first fan-out wirings; and a second connecting wiring disposed in the display area and connecting the second signal wirings to the second fan-out wirings, wherein the second fan-out wirings and the third fan-out wirings intersect and overlap each other in a plan view.

[0015] In an exemplary embodiment, the display device may include a first pixel and a second pixel arranged in a display area, wherein a first signal wiring and a second signal wiring are connected to the first pixel, and wherein a third signal wiring and a fourth signal wiring are connected to the second pixel.

[0016] In an exemplary embodiment, the first pixel and the second pixel may each include first to third sub-pixels that emit different colors from each other, wherein a first signal wiring is connected to the first sub-pixel and the third sub-pixel of the first pixel, wherein a second signal wiring is connected to the second sub-pixel of the first pixel, wherein a third signal wiring is connected to the first sub-pixel and the third sub-pixel of the second pixel, and wherein a fourth signal wiring is connected to the second sub-pixel of the second pixel.

[0017] In an exemplary embodiment, the first to fourth fan-out wiring may include: first to fourth main fan-out wiring, which are respectively connected to the first connection wiring and the second connection wiring, as well as the third signal wiring and the fourth signal wiring; and first to fourth sub-fan-out wiring, which are respectively spaced apart from the first to fourth main fan-out wiring.

[0018] In an exemplary embodiment, the first to fourth fan-out wiring may further include: bending the fan-out wiring to connect the first to fourth main fan-out wiring to the first to fourth sub-fan-out wiring respectively.

[0019] In an exemplary embodiment, the curved fan-out wiring may be arranged in the same layer as the first connection wiring and the second connection wiring.

[0020] In an exemplary embodiment, the second main fan-out wiring and the third main fan-out wiring may cross each other and overlap each other in the thickness direction.

[0021] In an exemplary embodiment, the second main fan-out wiring and the third main fan-out wiring can be disposed in different layers.

[0022] In an exemplary embodiment, the second main fan-out wiring and the second sub-fan-out wiring can be arranged in the same layer.

[0023] In an exemplary embodiment, the third main fan-out wiring and the third sub-fan-out wiring can be arranged in the same layer.

[0024] In an exemplary embodiment, the second sub-fanout wiring and the third sub-fanout wiring may cross each other and overlap each other in the thickness direction.

[0025] In an exemplary embodiment, the second sub-fanout wiring and the third sub-fanout wiring can be disposed in different layers.

[0026] In an exemplary embodiment, the second main fan-out wiring and the fourth main fan-out wiring may include a first conductive layer, wherein the first main fan-out wiring and the third main fan-out wiring include a second conductive layer, wherein the first to fourth signal wirings include a third conductive layer, and wherein the second conductive layer is disposed between the first conductive layer and the third conductive layer. Attached Figure Description

[0027] The above and other exemplary embodiments and features of the present invention will become more apparent from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0028] FIG. 1 This is a plan view of an exemplary embodiment of a display device according to the present invention;

[0029] FIG. 2 yes FIG. 1 A side view of the display device;

[0030] FIG. 3 It is shown FIG. 1 A plan view of the signal wiring, connection wiring, and fan-out wiring of the display device;

[0031] FIG. 4 It is shown FIG. 1 An example diagram of the sub-pixel arrangement of the first and second pixels of a display device;

[0032] FIG. 5 This is a cross-sectional view illustrating an exemplary embodiment of a sub-pixel of a display device according to the present invention;

[0033] FIG. 6 It is shown FIG. 3 An enlarged plan view of region A;

[0034] FIG. 7 It is along FIG. 6 A sectional view taken from line VII-VII;

[0035] FIG. 8 It is shown FIG. 3 An enlarged plan view of region B;

[0036] FIG. 9 It is along FIG. 8 A cross-sectional view taken by line IX-IX';

[0037] FIG. 10 It is along FIG. 8 A sectional view taken by line X-X';

[0038] FIG. 11 It is along FIG. 8 A sectional view taken by line XI-XI';

[0039] FIG. 12 It is along FIG. 8 A sectional view taken by line XII-XII';

[0040] FIG. 13 This is a plan view illustrating another exemplary embodiment of the signal wiring, connection wiring, and fan-out wiring of the display device according to the present invention;

[0041] FIG. 14 It is shown FIG. 13 Enlarged plan view of region C;

[0042] FIG. 15 It is along FIG. 14 A cross-sectional view taken by line XV-XV';

[0043] FIG. 16 It is along FIG. 14 A sectional view taken by line XVI-XVI';

[0044] FIG. 17 This is a perspective view of another exemplary embodiment of a display device according to the present invention;

[0045] FIG. 18 yes FIG. 17 An expanded view of the display device; and

[0046] FIG. 19 It is shown FIG. 17 An expanded view of the signal cabling, connection cabling, and fan-out cabling of the display device. Detailed Implementation

[0047] The advantages and features of the invention, as well as methods for implementing them, will be more readily understood by referring to the following detailed description of embodiments taken in conjunction with the accompanying drawings. However, the invention may be embodied in various other forms and should not be construed as limited to the exemplary embodiments set forth herein. The exemplary embodiments disclosed herein are provided so that the description of the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Furthermore, the invention will be defined only by the scope of the appended claims.

[0048] It will be understood that when an element or layer is referred to as being "on" another element or layer, that element or layer may be directly on the other element or layer, or there may be an intermediate element or layer present. Throughout the specification, the same reference numerals refer to the same elements.

[0049] Although terms such as “first” and “second” are used herein to describe various elements, it will be understood that these elements are not limited by these terms. These terms are used only to distinguish one element from another. Therefore, the first element discussed below may be referred to as the second element without departing from the technical spirit of the invention.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “the,” and “described” are intended to include the plural forms that include “at least one,” unless the context clearly indicates otherwise. “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” or “including” specify the presence of the stated features, regions, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integrals, steps, operations, elements, components, and / or groups thereof.

[0051] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It will be understood that, in addition to the orientations depicted in the figures, the relative terms are intended to cover different orientations of the device. For example, if the device in one of the figures is flipped, an element described as being “below” the other elements will be oriented as being “above” the other elements. Thus, depending on the specific orientation of the figure, the exemplary term “below” may encompass both the “below” and “above” orientations. Similarly, if the device in one of the figures is flipped, an element described as being “below” or “under” the other elements will be oriented as being “above” the other elements. Thus, the exemplary term “below” or “under” may encompass both the “above” and “below” orientations.

[0052] For ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “over” are used herein to describe the relationship between one element or feature and another element(s) as shown in the figures. It will be understood that, in addition to the orientations depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features would be oriented as “above” other elements or features. Thus, the exemplary term “below” can include both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0054] Exemplary embodiments are described herein with reference to cross-sectional views, which are schematic representations of idealized embodiments. Thus, variations in the illustrated shapes, such as those due to manufacturing techniques and / or tolerances, are expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the areas shown herein, but rather include shape deviations, for example, caused by manufacturing processes. For instance, areas shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, acute angles shown may be rounded. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to represent the precise shapes of the areas, nor are they intended to limit the scope of the claims.

[0055] In the following description, embodiments of the invention will be illustrated with reference to the accompanying drawings.

[0056] In this specification, the first direction DR1 indicates the Y-axis direction, the second direction DR2 indicates the X-axis direction, and the third direction DR3 indicates the Z-axis direction.

[0057] FIG. 1 This is a plan view of an exemplary embodiment of a display device according to the present invention. FIG. 2 yes FIG. 1 A side view of the display device. FIG. 3 It is shown FIG. 1 A plan view of the signal wiring, connection wiring, and fan-out wiring of the display device. FIG. 4 It is shown FIG. 1 An example diagram showing the subpixel arrangement of the first and second pixels of a display device. FIG. 5 This is a cross-sectional view illustrating an exemplary embodiment of a sub-pixel of a display device according to the present invention. FIG. 6 It is shown FIG. 3 A magnified plan view of region A. FIG. 7 It is along FIG. 6 The sectional view taken from line VII-VII. FIG. 8 It is shown FIG. 3 A magnified plan view of region B. FIG. 9 It is along FIG. 8 A sectional view taken from line IX-IX'. FIG. 10 It is along FIG. 8 A sectional view taken by line X-X'. FIG. 11 It is along FIG. 8 The sectional view taken by line XI-XI'. FIG. 12 It is along FIG. 8 A sectional view taken from line XII-XII'.

[0058] refer to FIG. 9 Display device 1 is a device for displaying dynamic or still images and can be used as a display screen for various products such as portable electronic devices and products such as televisions, laptop PCs, monitors, advertising panels, Internet of Things (“IoT”), such as mobile phones, smartphones, tablet PCs (“PCs”), smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (“PMPs”), navigation systems, super mobile PCs, etc.

[0059] Display device 1 may include display panel 10. Display panel 10 may be a flexible substrate comprising a flexible polymer material such as polyimide. Therefore, display panel 10 may be deformable, for example, rollable, bent, folded or rolled up.

[0060] The display panel 10 may include a display area DA, which is a portion of the image being displayed, and a non-display area NDA other than the display area DA. The display area DA may include multiple pixels PX.

[0061] A pixel PX indicates a set of subpixels capable of representing grayscale. Each pixel PX may include multiple subpixels R, G, and B. Subpixels R, G, and B may include a first subpixel R emitting a first color, a second subpixel G emitting a second color, and a third subpixel B emitting a third color. One first subpixel R, two second subpixels G, and one third subpixel B can be defined as a pixel PX.

[0062] In an exemplary embodiment, such as FIG. 8 As shown, a pixel PX may include, for example, a first pixel PX1 and a second pixel PX2. A first sub-pixel R and a second sub-pixel G may be arranged in a first row of the first pixel PX1 along a second direction DR2, and a third sub-pixel B and a second sub-pixel G may be arranged in a second row of the first pixel PX1 along the second direction DR2. Sub-pixels R and G arranged in the first row of the first pixel PX1 may be connected to a first scan line SL1, and sub-pixels B and G arranged in the second row of the first pixel PX1 may be connected to a second scan line SL2. Additionally, sub-pixels R and B arranged in a first column of the first pixel PX1 may be connected to a first signal wiring DL1, and sub-pixel G arranged in a second column of the first pixel PX1 may be connected to a second signal wiring DL2.

[0063] Furthermore, the third sub-pixel B and the second sub-pixel G can be arranged in the first row of the second pixel PX2 along the second direction DR2, and the first sub-pixel R and the second sub-pixel G can be arranged in the second row of the second pixel PX2 along the second direction DR2. Sub-pixels B and G arranged in the first row of the second pixel PX2 can be connected to the first scan line SL1, and sub-pixels R and G arranged in the second row of the second pixel PX2 can be connected to the second scan line SL2. Additionally, sub-pixels B and R arranged in the first column of the second pixel PX2 can be connected to the third signal wiring DL3, and sub-pixel G arranged in the second column of the second pixel PX2 can be connected to the fourth signal wiring DL4. References will follow below. FIG. 10 The wiring of the first to fourth signals, DL1, DL2, DL3 and DL4, will be described in detail.

[0064] The display panel 10 may include a main region MR and a curved region BR connected to one side of the main region MR. The display panel 10 may further include a sub-region SR connected to the curved region BR and overlapping the main region MR in the thickness direction when the curved region BR is bent.

[0065] The main region MR may include the display region DA. The outer edge of the display region DA of the main region MR may be the non-display region NDA.

[0066] The main region MR may have a shape similar to the external flat shape of the display device 1. The main region MR may be a flattened area disposed on a surface. However, the invention is not limited thereto, and at least one edge of the main region MR, other than the edge (side) connected to the curved region BR, may be curled to form a bend, or may be bent in the vertical direction.

[0067] When at least one edge of the main region MR, other than the edge (side) connected to the curved region BR, forms a bend or is bent, the display region DA can be disposed on the corresponding edge. However, the invention is not limited thereto; the non-display region NDA, which does not display an image, can be disposed on the bend or curved edge. Alternatively, the display region DA and the non-display region NDA can be arranged together on the bend or curved edge.

[0068] The non-display area NDA of the main region MR can be set in the area from the outer boundary of the display area DA to the edge of the display panel 10. Signal wiring DL can be arranged in the non-display area NDA of the main region MR, and the signal wiring DL applies signals to the display area DA, connection wiring DM, or drive circuitry. Furthermore, the outermost black matrix can be set in the non-display area NDA of the main region MR, but the present invention is not limited thereto.

[0069] The curved region BR is connected to the main region MR. In an exemplary embodiment, the curved region BR can be connected via, for example, a short side of the main region MR. Within the curved region BR, the display panel 10 can be curved with a curvature in a direction opposite to the third direction DR3, i.e., opposite to the display surface. When the display panel 10 is curved within the curved region BR, the surface of the display panel 10 can be reversed. That is, an upward-facing surface of the display panel 10 can be turned outwards via the curved region BR and then switched back to face downwards.

[0070] Sub-region SR extends from the curved region BR. Sub-region SR may begin after the point where the curve ends and extend in a direction parallel to the main region MR. Sub-region SR may overlap with the main region MR in the third direction DR3, i.e., the thickness direction of the display panel 10. Sub-region SR may overlap with the non-display area NDA at the edge of the main region MR, and may additionally overlap with the display area DA of the main region MR.

[0071] A driver chip 20 (or a driver chip and a pad portion electrically connected to the driver chip) may be disposed in a sub-region SR of the display panel 10. The driver chip 20 can generate drive signals required to drive pixels PX and can provide the drive signals to pixels PX defined in the display area DA. In an exemplary embodiment, the driver chip 20 may generate, for example, a data signal determining the luminance of pixel PX. In this case, the driver chip 20 can provide the data signal to pixel PX via connection wiring DM and signal wiring DL.

[0072] The driver chip 20 can be attached to the display panel 10 via an anisotropic conductive film or by ultrasonic bonding. The width of the driver chip 20 in the second direction DR2 can be smaller than the width of the display panel 10 in the second direction DR2.

[0073] The driver chip 20 may include a plurality of output terminals P1, P2, P3 and P4 arranged sequentially along the second direction DR2. When the terminal numbers are assigned based on the signal wiring DL1, DL2, DL3 and DL4 corresponding to the plurality of output terminals P1, P2, P3 and P4, the second output terminal P2, the third output terminal P3, the fourth output terminal P4 and the first output terminal P1 may be arranged sequentially along the second direction DR2.

[0074] The driving substrate 30 can be connected to the end of a sub-region SR of the display panel 10. A pad portion can be disposed at the end of the sub-region SR, and the driving substrate 30 can be connected to the pad portion. In an exemplary embodiment, the driving substrate 30 can be, for example, a flexible printed circuit board (“FPCB”) or a film.

[0075] Multiple signal cables (DL) and connection cables (DM) can be arranged in the display area (DA) of the main region (MR). Multiple fan-out cables (F) can be arranged in the non-display area (NDA), the curved area (BR), and the sub-area (SR) of the main region (MR). Connection cables (DM) can connect some of the signal cables (DL) to some of the fan-out cables (F). That is, fan-out cables (F) can be electrically connected to signal cables (DL) through connection cables (DM).

[0076] Reference FIG. 8 This section describes in detail the multiple signal cabling (DL), multiple connection cabling (DM), and multiple fan-out cabling (F).

[0077] refer to FIG. 11 The display device 1 may include multiple signal wirings DL, multiple connection wirings DM, and multiple fan-out wirings F.

[0078] The arrangement of the signal wiring DL, connection wiring DM, and fan-out wiring F can extend in either the first direction DR1 or the second direction DR2, and can be symmetrical based on a reference axis (not shown) passing through the center of the area of ​​the display device 1. Hereinafter, the signal wiring DL, connection wiring DM, and fan-out wiring F, which are arranged on the left side of the display device 1 and connected to the first pixel PX1 and the second pixel PX2, will be described primarily.

[0079] Multiple signal routing lines (DLs) can extend from the non-display area (NDA) of the main region (MR) and be arranged in the display area (DA). The signal routing lines (DLs) can extend along a first direction (DR1) and can be arranged sequentially at specific intervals along a second direction (DR2). The second direction (DR2) intersects the first direction (DR1) and can be perpendicular to the first direction (DR1).

[0080] One end of the signal wiring DL can be electrically connected to the connection wiring DM. The end of the signal wiring DL connected to the connection wiring DM can be located in the non-display area NDA at the bottom of the main area MR. The signal wiring DL can be, for example, a data line that transmits data signals to multiple pixels PX.

[0081] In an exemplary embodiment, for example, a first signal routing DL1 can transmit a first data signal to a first sub-pixel R and a third sub-pixel B of a first pixel PX1. Furthermore, a second signal routing DL2 can transmit a second data signal to a second sub-pixel G of the first pixel PX1. Furthermore, a third signal routing DL3 can transmit a third data signal to a first sub-pixel R and a third sub-pixel B of a second pixel PX2. Furthermore, a fourth signal routing DL4 can transmit a fourth data signal to a second sub-pixel G of the second pixel PX2.

[0082] Multiple connection lines DM can extend from the non-display area NDA of the main region MR to the display area DA and back to the non-display area NDA. The multiple connection lines DM can be electrically connected to multiple signal lines DL in the non-display area NDA of the main region MR, respectively. In an exemplary embodiment, as... FIG. 8 As shown, for example, the first connection cable DM1 can be connected to the first signal cable DL1, and the second connection cable DM2 can be connected to the second signal cable DL2.

[0083] The connection wiring DM is disposed in a different layer than the layer in which the signal wiring DL is disposed, and an insulating layer may be disposed between the connection wiring DM and the signal wiring DL. In an exemplary embodiment, as... FIG. 12 and FIG. 8As shown, for example, signal wirings DL1, DL2, DL3, and DL4 may include a third conductive layer 300, connection wirings DM1 and DM2 may include a fourth conductive layer 400, and a fourth insulating layer IL4 may be disposed between connection wirings DM1 and DM2 and signal wirings DL1, DL2, DL3, and DL4. A first connection wiring DM1 can be electrically connected to a first signal wiring DL1 through a contact hole that passes through the fourth insulating layer IL4 and exposes one end of the first signal wiring DL1, and a second connection wiring DM2 can be electrically connected to a second signal wiring DL2 through a contact hole that passes through the fourth insulating layer IL4 and exposes one end of the second signal wiring DL2.

[0084] Each of the multiple connection cabling DMs may include: a first portion extending from the non-display area NDA in a first direction DR1, a second portion extending from one end of the first portion in a second direction DR2, and a third portion extending from one end of the second portion in a direction opposite to the first direction DR1. As described above, the first portion located at one end of the non-display area NDA can be electrically connected to one end of the signal cabling DL. The first and third portions may be arranged spaced apart from each other, and the second portion may be located between the first and third portions.

[0085] As described above, the display device 1 may include a connection cable DM provided via the display area DA, and image signals may be provided to the signal cable DL via the connection cable DM. Therefore, the additional invalid area required to directly connect the signal cable DL to the fan-out cable F may be unnecessary. That is, the invalid area can be minimized.

[0086] Multiple fan-out wirings F can extend from the driver chip 20 of the sub-region SR to the non-display region NDA of the main region MR.

[0087] Multiple fan-out cables F can be electrically connected to multiple signal cables DL, respectively. Some of the multiple fan-out cables F can be directly connected to some of the multiple signal cables DL, and others of the multiple fan-out cables F can be directly connected to the connecting cable DM and electrically connected to the signal cables DL through the connecting cable DM.

[0088] In an exemplary embodiment, such as FIG. 9 As shown, for example, the first fan-out wiring F1 can be directly connected to the first connection wiring DM1, and is electrically connected to the first signal wiring DL1 through the first connection wiring DM1. The second fan-out wiring F2 can be directly connected to the second connection wiring DM2, and is electrically connected to the second signal wiring DL2 through the second connection wiring DM2. The third fan-out wiring F3 can be directly connected to the third signal wiring DL3. The fourth fan-out wiring F4 can be directly connected to the fourth signal wiring DL4.

[0089] That is, the first fan-out wiring F1 can be connected to the first sub-pixel R and the third sub-pixel B of the first pixel PX1, the second fan-out wiring F2 can be connected to the second sub-pixel G of the first pixel PX1, the third fan-out wiring F3 can be connected to the first sub-pixel R and the third sub-pixel B of the second pixel PX2, and the fourth fan-out wiring F4 can be connected to the second sub-pixel G of the second pixel PX2.

[0090] In an exemplary embodiment, the second fan-out wiring F2 and the third fan-out wiring F3 may intersect each other and overlap in the thickness direction. The second fan-out wiring F2 and the third fan-out wiring F3 may intersect each other in the non-display area NDA of the main region MR. When the second fan-out wiring F2 and the third fan-out wiring F3 intersect each other, fan-out wiring including the same conductive layer can be applied to sub-pixels R, G, and B that emit the same color. Therefore, since the fan-out wiring connected to the same sub-pixels R, G, and B includes different types of conductive layers to prevent critical dimension (“CD”) skew differences, the brightness difference and color deviation between the same sub-pixels R, G, and B can be improved. That is, the display quality of the display device can be improved.

[0091] refer to FIG. 8 Each of the multiple fan-out wirings F may include: main fan-out wirings 211, 121, 231 and 141; sub-fan-out wirings 212, 122, 232 and 142 spaced apart from the main fan-out wirings 211, 121, 231 and 141; and curved fan-out wirings 410 connecting the main fan-out wirings 211, 121, 231 and 141 to the sub-fan-out wirings 212, 122, 232 and 142.

[0092] The main fan-out wirings 211, 121, 231, and 141 can be arranged in the non-display area NDA of the main region MR. Some of the main fan-out wirings 211, 121, 231, and 141 can intersect each other and overlap in the thickness direction. A detailed description of them is given below.

[0093] One end of the main fan-out wirings 211, 121, 231 and 141 can be connected to the connecting wirings DM1 and DM2 and the signal wirings DL3 and DL4, respectively, and the other end of the main fan-out wirings 211, 121, 231 and 141 can be connected to the curved fan-out wiring 410.

[0094] The main fan-out wirings 211, 121, 231 and 141 can be directly connected to the connection wirings DM1 and DM2 and the signal wirings DL3 and DL4 respectively on one side of the non-display area NDA of the main area MR.

[0095] The main fan-out wirings 211, 121, 231, and 141 can be arranged in a different layer than the layer in which the connecting wirings DM1 and DM2 and the signal wirings DL3 and DL4 are arranged, and an insulating layer can be arranged between the main fan-out wirings 211, 121, 231, and 141 and the connecting wirings DM1 and DM2 and the signal wirings DL3 and DL4. Moreover, some of the main fan-out wirings 211, 121, 231, and 141 can be arranged in different layers and insulated from each other by the insulating layer.

[0096] In an exemplary embodiment, such as FIG. 10 and FIG. 8 As shown, for example, the first main fan-out wiring 211 can be directly connected to the first connection wiring DM1. That is, the first main fan-out wiring 211 can be electrically connected to the first sub-pixel R and the third sub-pixel B of the first pixel PX1.

[0097] The first main fan-out wiring 211 may include a second conductive layer 200, the first connecting wiring DM1 may include a fourth conductive layer 400, and a third insulating layer IL3 and a fourth insulating layer IL4 may be disposed between the first main fan-out wiring 211 and the first connecting wiring DM1. The first connecting wiring DM1 may be directly connected to the first main fan-out wiring 211 through a contact hole that passes through the third insulating layer IL3 and the fourth insulating layer IL4 and exposes one end of the first main fan-out wiring 211.

[0098] In addition, such as FIG. 11 and FIG. 8 As shown, the second main fan-out wiring 121 can be directly connected to the second connection wiring DM2. That is, the second main fan-out wiring 121 can be electrically connected to the second sub-pixel G of the first pixel PX1.

[0099] The second main fan-out wiring 121 can be disposed in a different layer than the layer in which the first main fan-out wiring 211 is disposed. The second main fan-out wiring 121 may include a first conductive layer 100, the second connecting wiring DM2 may include a fourth conductive layer 400, and the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4 may be disposed between the second main fan-out wiring 121 and the second connecting wiring DM2. The second connecting wiring DM2 can be directly connected to the second main fan-out wiring 121 through a contact hole that passes through the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4 and exposes one end of the second main fan-out wiring 121.

[0100] In addition, such as FIG. 12 and FIG. 8 As shown, the third main fan-out wiring 231 can be directly connected to the third signal wiring DL3. That is, the third main fan-out wiring 231 can be electrically connected to the first sub-pixel R and the third sub-pixel B of the second pixel PX2.

[0101] The third main fan-out wiring 231 can be set in the same layer as the layer in which the first main fan-out wiring 211 is set. Moreover, the third main fan-out wiring 231 can be set in a different layer than the layer in which the second main fan-out wiring 121 is set.

[0102] The third main fan-out wiring 231 and the second main fan-out wiring 121 can intersect each other and overlap in the thickness direction. When the third main fan-out wiring 231 and the second main fan-out wiring 121 intersect each other, fan-out wiring including the same conductive layer can be applied to sub-pixels R, G, and B that emit the same color. In an exemplary embodiment, for example, fan-out wirings F1 and F3 including the second conductive layer 200 can be applied to the first sub-pixel R and the third sub-pixel B of the first pixel PX1 and the second pixel PX2, and fan-out wirings F2 and F4 including the first conductive layer 100 can be applied to the second sub-pixel G of the first pixel PX1 and the second pixel PX2. Therefore, since the fan-out wirings connected to the same sub-pixels R, G, and B include different types of conductive layers to prevent CD skew differences, the brightness difference and color deviation between the same sub-pixels R, G, and B can be improved. That is, the display quality of the display device can be improved.

[0103] The third main fan-out wiring 231 may include a second conductive layer 200, the third signal wiring DL3 may include a third conductive layer 300, and a third insulating layer IL3 may be disposed between the third main fan-out wiring 231 and the third signal wiring DL3. The third signal wiring DL3 may be directly connected to the third main fan-out wiring 231 through a contact hole that passes through the third insulating layer IL3 and exposes one end of the third main fan-out wiring 231.

[0104] In addition, such as FIG. 9 and FIG. 8 As shown, the fourth main fan-out wiring 141 can be directly connected to the fourth signal wiring DL4. That is, the fourth main fan-out wiring 141 can be electrically connected to the second sub-pixel G of the second pixel PX2.

[0105] The fourth main fan-out wiring 141 can be disposed in the same layer as the layer in which the second main fan-out wiring 121 is disposed. Furthermore, the fourth main fan-out wiring 141 can be disposed in a different layer than the layer in which the first main fan-out wiring 211 is disposed. That is, the fourth main fan-out wiring 141 may include a first conductive layer 100, the fourth signal wiring DL4 may include a third conductive layer 300, and a second insulating layer IL2 and a third insulating layer IL3 may be disposed between the fourth main fan-out wiring 141 and the fourth signal wiring DL4. The fourth signal wiring DL4 can be directly connected to the fourth main fan-out wiring 141 through a contact hole that passes through the second insulating layer IL2 and the third insulating layer IL3 and exposes one end of the fourth main fan-out wiring 141.

[0106] Sub-fanout wiring 212, 122, 232 and 142 can be arranged in sub-region SR.

[0107] Sub-fanout wirings 212, 122, 232, and 142 can extend along a first direction DR1 and can be arranged sequentially at specific intervals along a second direction DR2. That is, multiple such sub-fanout wirings 212, 122, 232, and 142 can be arranged to be spaced apart from each other. That is, multiple sub-fanout wirings 212, 122, 232, and 142 can be arranged to not overlap each other in the thickness direction.

[0108] Sub-fanout wirings 212, 122, 232, and 142 can be arranged spaced apart from main fanout wirings 211, 121, 231, and 141. Sub-fanout wirings 212, 122, 232, and 142 can be electrically connected to main fanout wirings 211, 121, 231, and 141 respectively via a curved fanout wiring 410, as described below. One end of sub-fanout wirings 212, 122, 232, and 142 can be connected to the output terminals P1, P2, P3, and P4 of driver chip 20, and the other end of sub-fanout wirings 212, 122, 232, and 142 can be connected to curved fanout wiring 410. Sub-fanout wirings 212, 122, 232, and 142 can be arranged in the same layer as the layer in which main fanout wirings 211, 121, 231, and 141 are arranged.

[0109] In an exemplary embodiment, such as FIG. 10 and FIG. 8As shown, for example, one end of the first sub-fan-out wiring 212 can be connected to the first output terminal P1, and the other end of the first sub-fan-out wiring 212 can be connected to the bent fan-out wiring 410. That is, the first sub-fan-out wiring 212 can be electrically connected to the first main fan-out wiring 211 through the bent fan-out wiring 410. The first sub-fan-out wiring 212 can be disposed in the same layer as the layer in which the first main fan-out wiring 211 is disposed. That is, the first sub-fan-out wiring 212 may include a second conductive layer 200.

[0110] In addition, such as FIG. 11 and FIG. 8 As shown, one end of the second sub-fan-out wiring 122 can be connected to the second output terminal P2, and the other end of the second sub-fan-out wiring 122 can be connected to the bent fan-out wiring 410. That is, the second sub-fan-out wiring 122 can be electrically connected to the second main fan-out wiring 121 through the bent fan-out wiring 410. The second sub-fan-out wiring 122 can be disposed in the same layer as the layer in which the second main fan-out wiring 121 is disposed. That is, the second sub-fan-out wiring 122 may include a first conductive layer 100.

[0111] In addition, such as FIG. 12 and FIG. 1 to FIG. 12 As shown, one end of the third sub-fan-out wiring 232 can be connected to the third output terminal P3, and the other end of the third sub-fan-out wiring 232 can be connected to the bent fan-out wiring 410. That is, the third sub-fan-out wiring 232 can be electrically connected to the third main fan-out wiring 231 through the bent fan-out wiring 410. The third sub-fan-out wiring 232 can be disposed in the same layer as the layer in which the third main fan-out wiring 231 is disposed. That is, the third sub-fan-out wiring 232 may include the second conductive layer 200.

[0112] In addition, such as FIG. 4 and FIG. 5 to FIG. 12 As shown, one end of the fourth sub-fan-out wiring 142 can be connected to the fourth output terminal P4, and the other end of the fourth sub-fan-out wiring 142 can be connected to the bent fan-out wiring 410. That is, the fourth sub-fan-out wiring 142 can be electrically connected to the fourth main fan-out wiring 141 through the bent fan-out wiring 410. The fourth sub-fan-out wiring 142 can be disposed in the same layer as the layer in which the fourth main fan-out wiring 141 is disposed. That is, the fourth sub-fan-out wiring 142 may include a first conductive layer 100.

[0113] The curved fan-out wiring 410 can be set in the curved region BR. The curved fan-out wiring 410 can extend in the first direction DR1 and can be arranged sequentially at specific intervals along the second direction DR2.

[0114] One end of the bent fan-out wiring 410 can extend to the non-display area NDA of the main region MR and can be connected to the main fan-out wirings 211, 121, 231, and 141 described above. The other end of the bent fan-out wiring 410 can extend to the sub-region SR and can be connected to the sub-fan-out wirings 212, 122, 232, and 142 described above. That is, the main fan-out wirings 211, 121, 231, and 141 and the sub-fan-out wirings 212, 122, 232, and 142 can be connected to each other via the bent fan-out wiring 410.

[0115] The curved fan-out wiring 410 can be disposed in a different layer than the layer in which the main fan-out wirings 211, 121, 231, and 141 and the sub-fan-out wirings 212, 122, 232, and 142 are disposed, and an insulating layer can be disposed between the curved fan-out wiring 410 and the main fan-out wirings 211, 121, 231, and 141 and the sub-fan-out wirings 212, 122, 232, and 142. The curved fan-out wiring 410 can also be disposed in the same layer as the layer in which the aforementioned connecting wiring DM is disposed. That is, the curved fan-out wiring 410 may include a fourth conductive layer 400.

[0116] In an exemplary embodiment, such as FIG. 4 to FIG. 12 and FIG. 4 to FIG. 12 As shown, for example, the bent fan-out wire 410 of the first fan-out wire F1 can connect the first main fan-out wire 211 to the first sub-fan-out wire 212. A third insulating layer IL3 and a fourth insulating layer IL4 can be disposed between the bent fan-out wire 410 and the first main fan-out wire 211 and the first sub-fan-out wire 212. One end of the bent fan-out wire 410 can be connected to the first main fan-out wire 211 through a contact hole passing through the third insulating layer IL3 and the fourth insulating layer IL4 and exposing one end of the first main fan-out wire 211. Additionally, the other end of the bent fan-out wire 410 can be connected to the first sub-fan-out wire 212 through a contact hole passing through the third insulating layer IL3 and the fourth insulating layer IL4 and exposing one end of the first sub-fan-out wire 212.

[0117] In addition, such as FIG. 6 and FIG. 5As shown, the bent fan-out wiring 410 of the second fan-out wiring F2 can connect the second main fan-out wiring 121 to the second sub-fan-out wiring 122. A second insulating layer IL2, a third insulating layer IL3, and a fourth insulating layer IL4 can be arranged between the bent fan-out wiring 410 and the second main fan-out wiring 121 and the second sub-fan-out wiring 122. One end of the bent fan-out wiring 410 can be connected to the second main fan-out wiring 121 through a contact hole passing through the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4 and exposing one end of the second main fan-out wiring 121. The other end of the bent fan-out wiring 410 can be connected to the second sub-fan-out wiring 122 through a contact hole passing through the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4 and exposing one end of the second sub-fan-out wiring 122.

[0118] In addition, such as FIG. 7 and FIG. 8 As shown, the bent fan-out wiring 410 of the third fan-out wiring F3 can connect the third main fan-out wiring 231 to the third sub-fan-out wiring 232. A third insulating layer IL3 and a fourth insulating layer IL4 can be disposed between the bent fan-out wiring 410 and the third main fan-out wiring 231 and the third sub-fan-out wiring 232. One end of the bent fan-out wiring 410 can be connected to the third main fan-out wiring 231 through a contact hole passing through the third insulating layer IL3 and the fourth insulating layer IL4 and exposing one end of the third main fan-out wiring 231. Furthermore, the other end of the bent fan-out wiring 410 can be connected to the third sub-fan-out wiring 232 through a contact hole passing through the third insulating layer IL3 and the fourth insulating layer IL4 and exposing one end of the third sub-fan-out wiring 232.

[0119] In addition, such as FIG. 8 to FIG. 12 and FIG. 8 As shown, the bent fan-out wiring 410 of the fourth fan-out wiring F4 can connect the fourth main fan-out wiring 141 to the fourth sub-fan-out wiring 142. The second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4 can be arranged between the bent fan-out wiring 410 and the fourth main fan-out wiring 141 and the fourth sub-fan-out wiring 142. One end of the bent fan-out wiring 410 can be connected to the fourth main fan-out wiring 141 through a contact hole passing through the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4 and exposing one end of the fourth main fan-out wiring 141. Furthermore, the other end of the bent fan-out wiring 410 can be connected to the fourth sub-fan-out wiring 142 through a contact hole passing through the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4 and exposing one end of the fourth sub-fan-out wiring 142.

[0120] As described above, the second fan-out wiring F2 and the third fan-out wiring F3 can intersect and overlap each other in the thickness direction. In this case, the second fan-out wiring F2 and the third fan-out wiring F3 can intersect each other in the main region MR. When the second fan-out wiring F2 and the third fan-out wiring F3 intersect each other, fan-out wiring including the same conductive layer can be applied to sub-pixels R, G, and B that emit the same color. In an exemplary embodiment, for example, fan-out wiring F1 and F3 including the second conductive layer 200 can be applied to the first sub-pixel R and the third sub-pixel B of the first pixel PX1 and the second pixel PX2, and fan-out wiring F2 and F4 including the first conductive layer 100 can be applied to the second sub-pixel G of the first pixel PX1 and the second pixel PX2. Therefore, since the fan-out wiring connected to the same sub-pixels R, G, and B includes different types of conductive layers to prevent CD skew differences, the brightness difference and color deviation between the same sub-pixels R, G, and B can be improved. That is, the display quality of the display device can be improved.

[0121] The aforementioned sub-pixels R, G, and B, signal routing DL, connection routing DM, and fan-out routing F are not limited to... FIG. 9 As shown, various modifications can be made within the same sub-pixels R, G, and B of each pixel in pixels PX1 and PX2, including fan-out wiring with the same conductive layer applied.

[0122] The cross-sectional structures of the aforementioned subpixels R, G, and B will be described in detail below. (Refer to...) FIG. 8 To describe in detail the cross-sectional structure of subpixels R, G, and B. FIG. 10 In this context, for some components, those identical to the aforementioned components will be given new additional reference numerals and will be placed in parallel with existing reference numerals to clarify interlayer components.

[0123] refer to FIG. 8 The sub-pixels R, G, and B may include: a substrate 101; a buffer layer BF; a semiconductor layer ACT; a first insulating layer IL1; a first conductive layer 100; a second insulating layer IL2; a second conductive layer 200; a third insulating layer IL3; a third conductive layer 300; a fourth insulating layer IL4; a fourth conductive layer 400; a fifth insulating layer IL5; a first electrode layer 710; a pixel defining film 800, wherein an opening portion is defined to expose the first electrode layer 710; an emission layer 720 disposed in the opening portion of the pixel defining film 800; a second electrode layer 730 disposed on the emission layer 720 and the pixel defining film 800; and a passivation layer 900.

[0124] Each of the above layers may comprise a single membrane or a deposited membrane comprising multiple membranes. Further layers may be disposed between these layers.

[0125] The substrate 101 can support the various layers disposed thereon. The substrate 101 may include an insulating material. In an exemplary embodiment, the substrate 101 may include inorganic materials such as glass or quartz, or may include organic materials such as polyimide. The substrate 101 may be a rigid substrate or a flexible substrate.

[0126] A buffer layer BF is disposed on the substrate 101. The buffer layer BF can prevent the diffusion of ionic impurities, prevent moisture penetration, and perform surface planarization. In an exemplary embodiment, the buffer layer BF may include silicon nitride, silicon oxide, silicon oxynitride, etc.

[0127] A semiconductor layer ACT is disposed on the buffer layer BF. The semiconductor layer ACT forms the channels of multiple transistors for sub-pixels R, G, and B. In an exemplary embodiment, the semiconductor layer ACT may include polycrystalline silicon. In an exemplary embodiment, the polycrystalline silicon may be formed, for example, by crystallizing amorphous silicon.

[0128] When the semiconductor layer ACT comprises polycrystalline silicon, the ion-doped semiconductor layer ACT can become conductive when ions are incorporated into it. Therefore, the semiconductor layer ACT can include not only the channel regions of multiple transistors, but also their source and drain regions. The source and drain regions can be connected to both sides of each channel region.

[0129] In another exemplary embodiment, the semiconductor layer ACT may include monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. In an exemplary embodiment, the oxide semiconductor may include, for example, a two-component compound (AB) comprising indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), and three-component compounds (AB) x C y ) and four-component based compounds. In an exemplary embodiment, the semiconductor layer ACT may include indium tin zinc oxide (“ITZO”) or indium gallium zinc oxide (“IGZO”).

[0130] A first insulating layer IL1 is disposed on the semiconductor layer ACT. The first insulating layer IL1 can typically be disposed on the entire surface of the substrate 101. The first insulating layer IL1 can be a gate insulating film with gate insulation function. The first insulating layer IL1 can include silicon compounds, metal oxides, etc. In an exemplary embodiment, the first insulating layer IL1 can include, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide (Al), tantalum oxide (Ta), hafnium oxide (Hf), zirconium oxide (Zr), titanium oxide (Ti), etc. The first insulating layer IL1 can be a single film or a multilayer film comprising deposited films of different materials.

[0131] A first conductive layer 100 is disposed on a first insulating layer IL1. In an exemplary embodiment, the first conductive layer 100 may include at least one metal selected from molybdenum (Mo), Al, platinum (Pt), palladium (Pd), silver (Ag), Mg, gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), Ti, Ta, tungsten (W), and copper (Cu). The first conductive layer 100 may be a single film or a multilayer film.

[0132] The first conductive layer 100 may include a second main fan-out wiring 121, a second sub-fan-out wiring 122, a fourth main fan-out wiring 141, and a fourth sub-fan-out wiring 142. Furthermore, the first conductive layer 100 may include the gate electrode of a transistor and the first electrode of a holding capacitor.

[0133] A second insulating layer IL2 is disposed on the first conductive layer 100. The second insulating layer IL2 can typically be disposed on the entire surface of the substrate 101. The second insulating layer IL2 insulates the first conductive layer 100 from the second conductive layer 200.

[0134] The second insulating layer IL2 may be an interlayer insulating film. The second insulating layer IL2 may include the same material as the first insulating layer IL1, or may include one or more materials selected from the materials exemplified above as component materials of the first insulating layer IL1.

[0135] The second conductive layer 200 is disposed on the second insulating layer IL2. In an exemplary embodiment, the second conductive layer 200 may include at least one metal selected from Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, and Cu.

[0136] The second conductive layer 200 may include, but is not limited to, the same material as the first conductive layer 100. The second conductive layer 200 may be a single film or a multilayer film.

[0137] The second conductive layer 200 may include a first main fan-out wiring 211, a first sub-fan-out wiring 212, a third main fan-out wiring 231, and a third sub-fan-out wiring 232. Furthermore, the second conductive layer 200 may include a second electrode of a holding capacitor. The second conductive layer 200 can be overlapped with the first conductive layer 100 to form a holding capacitor, with a second insulating layer IL2 present therebetween.

[0138] The third insulating layer IL3 covers the second conductive layer 200. The third insulating layer IL3 insulates the second conductive layer 200 from the third conductive layer 300. The third insulating layer IL3 may include the same material as the first insulating layer IL1, or may include one or more materials selected from those exemplified above as component materials of the first insulating layer IL1.

[0139] The third conductive layer 300 is disposed on the third insulating layer IL3. In an exemplary embodiment, the third conductive layer 300 may include at least one metal selected from Al, Mo, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, and Cu. The third conductive layer 300 may be a single film or a multilayer film. In an exemplary embodiment, the third conductive layer 300 may have, for example, a deposition structure such as Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0140] The third conductive layer 300 may include the signal wiring DL and the source electrode SE described above. The source electrode SE can be connected to the source region of the semiconductor layer ACT through contact holes passing through the third insulating layer IL3, the second insulating layer IL2, and the first insulating layer IL1.

[0141] The fourth insulating layer IL4 covers the third conductive layer 300. The fourth insulating layer IL4 may be a via layer. In an exemplary embodiment, the fourth insulating layer IL4 may include an organic insulating material, such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene, etc.

[0142] A fourth conductive layer 400 is disposed on a fourth insulating layer IL4. The fourth insulating layer IL4 may include the same material as the third conductive layer 300, or may include one or more materials selected from the materials exemplified above as component materials of the third conductive layer 300.

[0143] The fourth conductive layer 400 may include the aforementioned connection wiring DM and bent fan-out wiring 410. Furthermore, the fourth conductive layer 400 may include a first conductive pattern CP1. The first conductive pattern CP1 can be connected to the source electrode SE through a contact hole passing through the fourth insulating layer IL4.

[0144] The fifth insulating layer IL5 covers the fourth conductive layer 400. The fifth insulating layer IL5 may be a via layer. The fifth insulating layer IL5 may include the same material as the fourth insulating layer IL4, or may include one or more materials selected from the materials exemplified above as component materials of the fourth insulating layer IL4.

[0145] The first electrode layer 710 is disposed on the fifth insulating layer IL5. In an exemplary embodiment, the first electrode layer 710 may have a deposition film structure in which layers of materials with high work functions, such as indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO) and indium oxide (In2O3), are deposited; and reflective material layers, such as Ag, Mg, Al, Pt, Pb, Au, Ni, Nd, Ir, Cr, lithium (Li), Ca and combinations thereof, are deposited, but are not limited thereto. The layer with high work function may be disposed above the reflective material layer close to the emitting layer 720. In an exemplary embodiment, the first electrode layer 710 may have a multilayer structure such as ITO / Mg, ITO / MgF, ITO / Ag and ITO / Ag / ITO, but is not limited thereto. The anode electrode of each of the sub-pixels R, G and B may include the first electrode layer 710. The anode electrode may be connected to the first conductive pattern CP1 through a contact hole through the fifth insulating layer IL5.

[0146] A pixel defining film 800 may be disposed on the first electrode layer 710. In an exemplary embodiment, the pixel defining film 800 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide (Hf), aluminum oxide (Al), titanium oxide (Ti), tantalum oxide (Ta), and zinc oxide (Zn), or organic insulating materials such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene (“BCB”). The pixel defining film 800 may be a single film or a multilayer film comprising deposited films of different materials.

[0147] An opening portion exposing the first electrode layer 710 can be defined in the pixel-defining film 800. The opening portion can define the emission region of each of the sub-pixels R, G, and B. An emission layer 720 is disposed in the opening portion of the pixel-defining film 800. The emission layer 720 may include an organic emission layer, a hole injection / transport layer, and an electron injection / transport layer.

[0148] The second electrode layer 730 is disposed on the emitter layer 720 and the pixel defining film 800. A cathode electrode may include the second electrode layer 730. The cathode electrode may be disposed throughout the entire display area DA. In an exemplary embodiment, the second electrode layer 730 may include a material layer having a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, compounds thereof, or combinations thereof (e.g., a combination of Ag and Mg). The second electrode layer 730 may further include a transparent metal oxide layer disposed on the material layer having a low work function.

[0149] A passivation layer 900 may be disposed on the second electrode layer 730. The passivation layer 900 prevents moisture, oxygen, etc., from penetrating into the emitter layer 720. In an exemplary embodiment, the passivation layer 900 may include at least one inorganic film and / or an organic film. In an exemplary embodiment, the inorganic film may include, for example, a film derived from Al. x O y TiO x ZrO x SiO x AlO x N y Al x N y SiO x N y Si x N y ZnO x and Ta x O y One or more inorganic materials are used. In an exemplary embodiment, the organic membrane can be manufactured by polymerization of at least one monomer selected from the group consisting of pentabromophenyl acrylate, 2-(9H-carbazole-9-yl)ethyl methacrylate, N-vinylcarbazole, bis(methacryloylthiophenyl) sulfide, and zirconium acrylate. The organic membrane may be a planarized membrane.

[0150] Other exemplary embodiments will be described below. In the following, the same reference numerals will be used to denote the same components as described above, and repeated descriptions will be omitted or simplified.

[0151] FIG. 11 This is a plan view illustrating another exemplary embodiment of the signal wiring, connection wiring, and fan-out wiring of a display device according to the present invention. FIG. 8 It is shown FIG. 12 A magnified plan view of region C. FIG. 8 It is along FIG. 9 A sectional view taken from line XV-XV'. FIG. 8 It is along FIG. 10 A sectional view taken by line XVI-XVI'.

[0152] refer to FIG. 8 The display device 1_1 in the exemplary embodiment has the same as FIG. 11 The difference in the exemplary embodiment is that the fan-out wiring F intersects each other in the sub-region SR.

[0153] In detail, the main fan-out wirings 211, 121_1, 231_1, and 141 of the fan-out wiring F can be arranged in the non-display area NDA of the main region MR. The main fan-out wirings 211, 121_1, 231_1, and 141 can extend along a first direction DR1 and can be arranged sequentially at specific intervals along a second direction DR2. That is, multiple such main fan-out wirings 211, 121_1, 231_1, and 141 can be arranged spaced apart from each other. Specifically, the multiple main fan-out wirings 211, 121_1, 231_1, and 141 can be arranged without overlapping each other in the thickness direction.

[0154] Since the main fan-out wirings 211, 121_1, 231_1 and 141 are arranged to be spaced apart from each other, they have the same characteristics as the above references. FIG. 8 The interlayer components of the main fan-out wirings 211, 121, 231 and 141 described are substantially the same, so repeated descriptions will be omitted.

[0155] Sub-fanout routes 212, 122_1, 232_1, and 142 of the fanout route F can be arranged in the sub-region SR. Some of the sub-fanout routes 212, 122_1, 232_1, and 142 can intersect each other and can overlap in the thickness direction.

[0156] In detail, the first sub-fanout wiring 212 can be connected to the first sub-pixel R and the third sub-pixel B of the first pixel PX1, the second sub-fanout wiring 122_1 can be connected to the second sub-pixel G of the first pixel PX1, the third sub-fanout wiring 232_1 can be connected to the first sub-pixel R and the third sub-pixel B of the second pixel PX2, and the fourth sub-fanout wiring 142 can be connected to the second sub-pixel G of the second pixel PX2.

[0157] The second sub-fan-out wiring 122_1 and the third sub-fan-out wiring 232_1 can intersect each other and overlap in the thickness direction. When the second sub-fan-out wiring 122_1 and the third sub-fan-out wiring 232_1 intersect each other, fan-out wiring including the same conductive layer can be applied to sub-pixels R, G, and B that emit the same color. In an exemplary embodiment, fan-out wirings F1 and F3_1 including the second conductive layer 200 can be applied to the first sub-pixel R and the third sub-pixel B of the first pixel PX1 and the second pixel PX2, and fan-out wirings F2_1 and F4 including the first conductive layer 100 can be applied to the second sub-pixel G of the first pixel PX1 and the second pixel PX2. Therefore, as described above, since the fan-out wirings connected to the same sub-pixels R, G, and B include different types of conductive layers to prevent CD skew differences, the brightness difference and color deviation between the same sub-pixels R, G, and B can be improved.

[0158] Since it has already been referenced FIG. 12The first sub-fanout wiring 212 and the fourth sub-fanout wiring 142 are described, so their repeated descriptions will be omitted.

[0159] The bent fan-out wiring 410 of the fan-out wiring F can be disposed in the bent region BR. One end of the bent fan-out wiring 410 can extend to the non-display region NDA of the main region MR and can be connected to the main fan-out wirings 211, 121_1, 231_1 and 141 mentioned above. The other end of the bent fan-out wiring 410 can extend to the sub-region SR and can be connected to the sub-fan-out wirings 212, 122_1, 232_1 and 142 mentioned above. That is, the main fan-out wirings 211, 121_1, 231_1 and 141 and the sub-fan-out wirings 212, 122_1, 232_1 and 142 can be connected by the bent fan-out wiring 410 respectively.

[0160] Since it has already been referenced FIG. 8 The curved fan-out wiring 410 is described, so its repeated description will be omitted.

[0161] The aforementioned sub-pixels R, G, and B, signal routing DL, connection routing DM, and fan-out routing F are not limited to... FIG. 9 As shown, various modifications can be made within the range of the same sub-pixels R, G, and B of each pixel in pixels PX1 and PX2 that emit the same color, including fan-out wiring with the same conductive layer.

[0162] FIG. 8 This is a perspective view of another exemplary embodiment of the display device according to the present invention. FIG. 10 yes FIG. 8 An expanded view of the display device. FIG. 11 It is shown FIG. 8 An expanded view of the signal cabling, connection cabling, and fan-out cabling of the display device.

[0163] refer to FIG. 12 The display device 1_2 in this exemplary embodiment has the same as FIG. 1 to FIG. 12 The difference in the exemplary embodiment is that the main area MR of the display panel 10_1 includes a front display area DA0, side display areas DA1, DA2, DA3 and DA4, and corner areas C1, C2, C3 and C4.

[0164] The front display area DA0 and the side display areas DA1, DA2, DA3 and DA4 can be display areas DA for displaying images. The corner areas C1, C2, C3 and C4 are non-display areas NDA for not displaying images, and can provide space for signal wiring DL, connection wiring DM, etc. to pass through them.

[0165] The front display area DA0 can have a rectangular shape, which includes two long sides extending in the first direction DR1 and two short sides extending in the second direction DR2. However, the front display area DA0 is not limited to this and can also have a polygonal shape with rounded corners, where the short sides intersect the long sides.

[0166] The side display areas DA1, DA2, DA3 and DA4 may include the first side display area DA1, the second side display area DA2, the third side display area DA3 and the fourth side display area DA4.

[0167] The first side display area DA1 can extend from the edge of the front display area DA0 in the direction opposite to the first direction DR1, the second side display area DA2 can extend from the edge of the front display area DA0 in the direction opposite to the second direction DR2, the third side display area DA3 can extend from the edge of the front display area DA0 in the first direction DR1, and the fourth side display area DA4 can extend from the edge of the front display area DA0 in the second direction DR2.

[0168] The first to fourth side display areas DA1, DA2, DA3, and DA4 may have substantially the same functions or components, except for their positions. In the following description, the common features of the first to fourth side display areas DA1, DA2, DA3, and DA4 will be based on the first side display area DA1, and repeated descriptions will be omitted.

[0169] The first side display area DA1 may extend outward from the edge of the front display area DA0 and bend at a predetermined angle. In an exemplary embodiment, the first side display area DA1 may bend from the front display area DA0 at an angle of, for example, more than about 90 degrees (°) and less than about 150 degrees.

[0170] The first side display area DA1 can be connected to the curved area BR. For example... FIG. 5 As shown, when the first side display area DA1 is bent or flexed vertically based on the front display area DA0, the curved area BR is bent or flexed vertically again based on the first side display area DA1 (that is, bent or flexed at an angle of approximately 180° based on the front display area DA0), such that the sub-area SR disposed on one side of the curved area BR can be disposed below the front display area DA0 in the thickness direction of the front display area DA0. The sub-area SR can overlap with the front display area DA0 and can be configured to be parallel to the front display area DA0.

[0171] Corner areas C1, C2, C3, and C4 can be located between side display areas DA1, DA2, DA3, and DA4. Corner areas C1, C2, C3, and C4 can each comprise a first to fourth corner area C1, C2, C3, and C4 located between the first to fourth side display areas DA1, DA2, DA3, and DA4. The first to fourth corner areas C1, C2, C3, and C4 can be arranged close to the four corners, with the long and short sides of the front display area DA0 intersecting each other at these four corners. The first to fourth corner areas C1, C2, C3, and C4 can have substantially the same function or components, except for their location. In the following description, the common features of the first to fourth corner areas C1, C2, C3, and C4 will be described based on the first corner area C1, and repeated descriptions will be omitted.

[0172] The first corner area C1 can be located between the first side display area DA1 and the second side display area DA2. One end of the first corner area C1 can contact the first side display area DA1, and the other end of the first corner area C1 can contact the second side display area DA2.

[0173] The first corner region C1 can extend from the front display region DA0 and is formed to be rounded with a predetermined curvature. The curvature formed by the first corner region C1 and the front display region DA0 can be greater than the curvature formed by the front display region DA0 and each of the first side display region DA1 and the second side display region DA2.

[0174] The first corner area C1 can provide space where signal cabling DL can be connected to connection cabling DM.

[0175] Multiple signal wirings DL can extend from the first corner area C1 and be arranged in the side display areas DA1, DA2, DA3 and DA4 and the front display area DA0. Furthermore, signal wiring DL can extend from the non-display area NDA between the first side display area DA1 and the curved area BR, and be arranged in the side display areas DA1, DA2, DA3 and DA4 and the front display area DA0.

[0176] Multiple connection cables DM can extend from the non-display area NDA between the first side display area DA1 and the bending area BR to the first corner area C1 via the first side display area DA1, the front display area DA0, or the second side display area DA2.

[0177] Multiple connection cables DM can be electrically connected to multiple signal cables DL in the first corner area C1. Additionally, the connection cables DM can be electrically connected to multiple signal cables DL in the non-display area NDA between the first side display area DA1 and the curved area BR.

[0178] As described above, the display device 1_2 may include a connection cable DM that runs through the display area DA, and image signals can be provided to the signal cable DL through the connection cable DM. Therefore, as described above, the additional invalid area required to directly connect the signal cable DL to the fan-out cable F may be unnecessary.

[0179] Multiple fan-out wirings F can extend from the driver chip 20 of the sub-region SR to the non-display region NDA of the main region MR.

[0180] Multiple fan-out cables F can be electrically connected to multiple signal cables DL respectively. Some of the multiple fan-out cables F can be directly connected to some of the multiple signal cables DL, and others of the multiple fan-out cables F can be directly connected to the connecting cable DM, and are electrically connected to the signal cables DL through the connecting cable DM.

[0181] Some of the multiple fan-out wirings F can intersect each other and overlap in the thickness direction. When some of the fan-out wirings F intersect each other, fan-out wirings with the same conductive layer can be applied to each sub-pixel that emits the same color. Therefore, as described above, since the fan-out wirings connected to the same sub-pixels R, G, and B include different types of conductive layers to prevent CD skew differences, the brightness difference and color deviation between the same sub-pixels R, G, and B can be improved.

[0182] Although the accompanying drawings show multiple fan-out wirings F intersecting each other in the non-display area NDA of the main region MR, the invention is not limited thereto. That is, as shown... FIG. 5 As shown, multiple fan-out wirings F can intersect each other in sub-regions SR.

[0183] In addition, since it has already been referenced FIG. 5 FIG. 13 FIG. 14 FIG. 13 FIG. 15 FIG. 14 FIG. 16 FIG. 14 FIG. 13 to FIG. 16 FIG. 1 to FIG. 12 FIG. 1 to FIG. 12 FIG. 1 to FIG. 12 FIG. 1 to FIG. 12 FIG. 13 to FIG. 16 FIG. 17 FIG. 18 FIG. 17 FIG. 19 FIG. 17 FIG. 17 to FIG. 19 FIG. 1 to FIG. 12 FIG. 19 FIG. 13 FIG. 1 to FIG. 12 The signal routing (DL), connection routing (DM), and fan-out routing (F) are described, so repeated descriptions will be omitted.

[0184] According to some exemplary embodiments, a display device can minimize its non-display area by arranging connection wiring in the display area.

[0185] Furthermore, by allowing fan-out wiring connected to connection wiring to intersect with fan-out wiring connected to signal wiring, fan-out wiring including the same conductive layer can be applied to sub-pixels that emit the same color. Therefore, since fan-out wiring connected to the same sub-pixel includes different types of conductive layers to prevent CD skew differences, brightness differences and color deviations between the R, G, and B of the same sub-pixel can be improved. In other words, the display quality of the display device can be improved.

[0186] Although exemplary embodiments of the invention have been described with reference to the accompanying drawings, those skilled in the art will understand that the invention may be practiced in other specific forms without departing from its spirit and essential characteristics. Therefore, it should be understood that the above exemplary embodiments are illustrative and should not be construed as limiting the invention.

[0187] The effects of exemplary embodiments of the present invention are not limited to the above examples, and various effects are included in the specification.

Claims

1. A display device, comprising: The display panel includes a display area and a non-display area; Multiple signal cables are arranged in the display area; Multiple fan-out wirings are arranged in the non-display area and electrically connected to the multiple signal wirings; as well as Multiple connection cabling connects the multiple signal cabling to the multiple fan-out cabling. Among these, some of the fan-out wirings intersect each other and overlap each other in the plan view, and Wherein, the first fan-out wiring in the plurality of fan-out wirings does not overlap with the other fan-out wirings in the plurality of fan-out wirings.

2. A display device, comprising: The display panel includes a display area and a non-display area; Multiple signal cables are arranged in the display area; Multiple fan-out wirings are arranged in the non-display area and electrically connected to the multiple signal wirings; as well as Multiple connection cabling connects the multiple signal cabling to the multiple fan-out cabling. Among these, some of the fan-out wirings intersect each other and overlap each other in the plan view, and The display panel further includes a curved region, and some of the fan-out wires of the plurality of fan-out wires intersect each other in the non-display region between the display region and the curved region.

3. The display device according to claim 2, wherein, One of the fan-out wires that intersects with each other in the plurality of fan-out wires contacts the signal wire, and another of the fan-out wires that intersects with each other in the plurality of fan-out wires contacts the connection wire.

4. The display device according to claim 3, wherein, The fan-out wiring that contacts the connecting wiring among the plurality of fan-out wirings includes a first conductive layer. The fan-out wiring that is in contact with the signal wiring includes a second conductive layer. The signal wiring includes a third conductive layer, and The second conductive layer is disposed between the first conductive layer and the third conductive layer.

5. The display device according to claim 4, wherein, The connection wiring includes a fourth conductive layer, and the connection wiring is electrically connected to the signal wiring through a contact hole that passes through an insulating layer disposed between the connection wiring and the signal wiring and exposes one end of the signal wiring.

6. The display device according to claim 5, wherein, The connection wiring includes: The first part extends in the first direction; The second portion extends from one end of the first portion in a second direction intersecting the first direction; and The third part extends from one end of the second part in a direction opposite to the first direction, and The first part is spaced apart from the third part.

7. A display device, comprising: The display panel includes a display area and a non-display area; Multiple signal cables are arranged in the display area; Multiple fan-out wirings are arranged in the non-display area and electrically connected to the multiple signal wirings; as well as Multiple connection cabling connects the multiple signal cabling to the multiple fan-out cabling. Among these, some of the fan-out wirings intersect each other and overlap each other in the plan view, and The display panel further includes a curved region, a main region arranged on one side of the curved region, and a sub-region extending from the other side of the curved region, wherein some of the fan-out wirings intersect each other in the sub-region.

8. A display device comprising a display area and a non-display area, the display device comprising: The first signal wiring, the second signal wiring, the third signal wiring, and the fourth signal wiring are arranged in the display area; The first fan-out wiring, the second fan-out wiring, the third fan-out wiring, and the fourth fan-out wiring are arranged in the non-display area and are electrically connected to the first signal wiring, the second signal wiring, the third signal wiring, and the fourth signal wiring, respectively. A first connection cable is disposed in the display area, and the first signal cable is connected to the first fan-out cable; as well as A second connection cable is disposed in the display area, and the second signal cable is connected to the second fan-out cable. The second fan-out wiring and the third fan-out wiring intersect and overlap each other in the plan view.

9. The display device according to claim 8, comprising a first pixel and a second pixel disposed in the display area. in, The first signal wiring and the second signal wiring are connected to the first pixel, and The third signal wiring and the fourth signal wiring are connected to the second pixel.

10. The display device according to claim 9, wherein, The first pixel and the second pixel each include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit different colors from each other. The first signal wiring is connected to the first sub-pixel and the third sub-pixel of the first pixel. Wherein, the second signal wiring is connected to the second sub-pixel of the first pixel. The third signal wiring is connected to the first sub-pixel and the third sub-pixel of the second pixel, and The fourth signal wiring is connected to the second sub-pixel of the second pixel.

11. The display device according to claim 8, wherein, The first fan-out wiring, the second fan-out wiring, the third fan-out wiring, and the fourth fan-out wiring include: The first main fan-out wiring, the second main fan-out wiring, the third main fan-out wiring, and the fourth main fan-out wiring are respectively connected to the first connecting wiring and the second connecting wiring, as well as the third signal wiring and the fourth signal wiring; and The first sub-fanout wiring, the second sub-fanout wiring, the third sub-fanout wiring, and the fourth sub-fanout wiring are respectively spaced apart from the first main fanout wiring, the second main fanout wiring, the third main fanout wiring, and the fourth main fanout wiring.

12. The display device according to claim 11, wherein, The first fan-out wiring, the second fan-out wiring, the third fan-out wiring, and the fourth fan-out wiring further include: The fan-out wiring is bent, and the first main fan-out wiring, the second main fan-out wiring, the third main fan-out wiring and the fourth main fan-out wiring are respectively connected to the first sub-fan-out wiring, the second sub-fan-out wiring, the third sub-fan-out wiring and the fourth sub-fan-out wiring.

13. The display device according to claim 12, wherein, The curved fan-out wiring is arranged in the same layer as the first connection wiring and the second connection wiring.

14. The display device according to claim 11, wherein, The second main fan-out wiring and the third main fan-out wiring intersect and overlap each other in the thickness direction.

15. The display device according to claim 14, wherein, The second main fan-out wiring and the third main fan-out wiring are located in different layers.

16. The display device according to claim 15, wherein, The second main fan-out wiring and the second sub-fan-out wiring are arranged in the same layer.

17. The display device according to claim 15, wherein, The third main fan-out wiring and the third sub-fan-out wiring are arranged in the same layer.

18. The display device according to claim 11, wherein, The second sub-fanout wiring and the third sub-fanout wiring intersect and overlap each other in the thickness direction.

19. The display device according to claim 18, wherein, The second sub-fanout wiring and the third sub-fanout wiring are located in different layers.

20. The display device according to claim 11, wherein, The second main fan-out wiring and the fourth main fan-out wiring both include a first conductive layer. The first main fan-out wiring and the third main fan-out wiring both include a second conductive layer. Wherein, the first signal wiring, the second signal wiring, the third signal wiring, and the fourth signal wiring include a third conductive layer, and The second conductive layer is disposed between the first conductive layer and the third conductive layer.

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