Digital capacitor isolator test and sorting system and sorting device

Abstract

A digital capacitor isolator testing and sorting system comprises a multi-channel isolator test adapter integrated box, wherein a detection circuit is provided in the integrated box for connecting a chip under test; a test system and a communication-connected sorting system; the test system comprises a test machine and a test system PC; the test machine tests the chip under test in the integrated box; the test system PC controls the test process by controlling the opening or closing of the test machine's test input signal and / or test output signal channels; the test machine is further used to detect detection information during the test process; the test system PC outputs corresponding test results based on the test information; the sorting system comprises an automatic sorting machine, a sorting system industrial control programmable logic controller (PLC) and the sorting system PC; the test machine obtains a judgment result based on a feedback signal and transmits an instruction to the sorting system industrial control programmable logic controller (PLC); the industrial control programmable logic controller (PLC) controls the automatic sorting machine to classify the tested products according to their quality.

Description

Technical Field

[0001] The present invention relates to the technical field of universal single / dual / quadruple unit digital capacitor isolator testing and sorting, and in particular to a digital capacitor isolator testing and sorting system and a sorting device thereof. Background Art

[0002] In the field of integrated circuit design, packaging, and testing, digital capacitor isolators are generally available in three combinations: one unit, two units, and four units. Five popular package types include narrow-body SOP8L, narrow-body SOP16L, wide-body SOP8W and SOP16W, and DFN3*3-8L. The corresponding high-speed digital-analog testers used to test digital capacitor isolators vary widely, including the S100, J750, CHROMA 3380, T2000, and Advantest V93000. To ensure consistent test methods, principles, and implementation standards, universal test equipment, stable and reliable performance, and easy maintenance, a multi-channel digital capacitor isolator test and sorting system was developed in accordance with national standards. Summary of the Invention

[0003] In order to solve the above problems, the digital capacitor isolator testing and sorting system and the sorting device thereof provided by the present invention solve the technical problem in the prior art that digital capacitor isolators cannot be tested in a standard and consistent manner.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions: a digital capacitor isolator test and sorting system and a sorting device thereof, comprising a multi-channel isolator test adapter integrated box, wherein a detection circuit is provided in the integrated box for connecting the chip under test;

[0005] It also includes a testing system and a sorting system with communication connections;

[0006] The test system includes a test machine and a test system PC. The test machine tests the chip under test in the integrated box. The test system PC controls the test process by controlling the opening or closing of the test input signal and / or test output signal channel of the test machine.

[0007] The test machine is also used to detect the test information during the test process, and the test system PC outputs the corresponding test results according to the test information;

[0008] The sorting system includes an automatic sorting machine, a sorting system industrial control PLC and a sorting system PC. The testing machine draws a judgment result based on the feedback signal and transmits the instruction to the industrial control PLC of the sorting system. The industrial control PLC controls the automatic sorting machine to classify the tested products according to quality.

[0009] Furthermore, the test input signal and / or test output signal channel of the test machine includes:

[0010] VDDA detection channel, VDDB detection channel, ENA detection channel, ENB detection channel and at least one group of input and output detection channels.

[0011] Furthermore, it also includes a programmable power supply, which includes a voltage source group, a current source group and a signal source group; the multi-channel isolator test adapter integrated box includes a gold finger;

[0012] The VDDA detection channel includes a VDDA pin end and a first electronically controlled switch group, wherein the VDDA pin end is respectively connected to the voltage source group and the current source group through the first electronically controlled switch group; the control signal of the first electronically controlled switch group is connected to the test system PC; the VDDA pin end is connected to the gold finger for connecting the detection signal to the chip;

[0013] The VDDB detection channel includes a VDDB pin end and a second electric control switch group. The VDDB pin end is connected to the

[0014] The second electronically controlled switch group is respectively connected to the voltage source group and the current source group; the control signal of the second electronically controlled switch group is connected to the test system PC; the VDDB pin end is connected to the gold finger for connecting the detection signal to the chip;

[0015] The ENA detection channel includes an ENA pin end and a third electronically controlled switch group. The ENA pin end is respectively connected to the voltage source group and the current source group through the third electronically controlled switch group. The control signal of the third electronically controlled switch group is connected to the test system PC. The ENA pin end is connected to the gold finger for connecting the detection signal to the chip.

[0016] The ENB detection channel includes an ENB pin end and a fourth electronically controlled switch group. The ENB pin end is respectively connected to the voltage source group and the current source group through the fourth electronically controlled switch group. The control signal of the fourth electronically controlled switch group is connected to the test system PC; the ENB pin end is connected to the gold finger for connecting the detection signal to the chip.

[0017] Furthermore, the input and output detection channels include an input detection channel and an output detection channel;

[0018] The input detection channel includes IN1, IN2, IN3, IN4 pin ends and IN1 input electronically controlled switch group, IN2 input electronically controlled switch group, IN3 input electronically controlled switch group, IN4 input electronically controlled switch group;

[0019] The IN1, IN2, IN3, and IN4 pins are connected to the voltage source group, the current source group, and the signal source group respectively through the IN1 input electronic control switch group, the IN2 input electronic control switch group, the IN3 input electronic control switch group, and the IN4 input electronic control switch group;

[0020] The control signals of the IN1 input electronic control switch group, the IN2 input electronic control switch group, the IN3 input electronic control switch group and the IN4 input electronic control switch group are respectively connected to the test system PC; the IN1, IN2, IN3 and IN4 pin ends are all connected to the gold fingers for connecting the detection signals to the chip;

[0021] The output detection channel includes OUT1, OUT2, OUT3 and OUT4 pin ends and OUT1 input electronically controlled switch group, OUT2 input electronically controlled switch group, OUT3 input electronically controlled switch group, OUT4 input electronically controlled switch group;

[0022] The OUT1, OUT2, OUT3 and OUT4 pin ends are respectively connected to the voltage source group, the current source group and the signal source group through the OUT1 input electronic control switch group, the OUT2 input electronic control switch group, the OUT3 input electronic control switch group and the OUT4 input electronic control switch group;

[0023] The control signals of the OUT1 input electronic control switch group, OUT2 input electronic control switch group, OUT3 input electronic control switch group and OUT4 input electronic control switch group are respectively connected to the test system PC; the OUT1, OUT2, OUT3 and OUT4 pin ends are all connected to gold fingers for connecting the detection signals to the chip.

[0024] Specifically, the model of the chip under test is IS374X.

[0025] The present invention also provides a digital capacitor isolator testing device, comprising a testing mechanism and an automatic sorting mechanism, wherein the testing mechanism comprises a testing machine and a testing system PC;

[0026] The test machine includes a test machine board card integration box, and a test source lead-out board card is provided on the outside of the test machine board card integration box;

[0027] The automatic sorting mechanism includes an automatic sorting machine, the outer side of the automatic sorting machine is provided with a tested product fixing slot facing the test machine board card integration box, and a gold finger fixing plate is provided near the tested product fixing slot;

[0028] It also includes a multi-channel isolator test adapter integrated box, which is fixed on the gold finger fixing plate.

[0029] Furthermore, an automatic blanking chute is provided on the automatic sorting machine just above the fixed chute for the tested product.

[0030] Furthermore, the multi-channel isolator test adapter integrated box and the test source lead-out board are connected through multiple groups of high-speed signal coaxial shielded cables and DC signal source connection cables.

[0031] Furthermore, a press joint for the product to be tested is provided on the automatic sorting machine at a position corresponding to the fixing groove of the product to be tested.

[0032] Furthermore, the test machine and the test system PC are connected by a 25-core cable and parallel data communication is used.

[0033] Way.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] 1. This practical digital capacitor isolator test system adopts an overshoot voltage protection circuit, which can protect the relay drive circuit on the baseboard and the operational amplifier loop board and extend its service life.

[0036] 2. The digital capacitor isolator test system of the present invention adopts a shielded reed relay to prevent interference from external environmental signals and crosstalk from its own loop operation, making the transmission and acquisition of frequency signals above 100 MHz quite stable, thereby ensuring the accuracy of the measured data.

[0037] 3. The digital capacitor isolator test system of the present invention uses a double-sided tape shielding layer connection, so that the test box can test PA-level leakage and UV-level output voltage, fully meeting the quality requirements of industrial finished products.

[0038] 4. The test circuit of the digital capacitor isolator test system of the present invention uses relay switches for physical connection and isolation to ensure the independence and stability of each port. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Attached drawings:

[0040] Figure 1 This is a principle block diagram of the present invention;

[0041] Figure 2 This is a test circuit diagram of the present invention;

[0042] Figure 3 A schematic diagram of the invention structure;

[0043] Figure 4 for Figure 3 Side view of

[0044] Figure 5 It is a structural schematic diagram of another angle of the present invention;

[0045] Figure 6 It is a structural diagram of the automatic sorting mechanism of the present invention;

[0046] Figure 7 This is a structural diagram of the automatic sorting mechanism from another angle.

[0047] In the figure: automatic sorting machine 1, test system PC 2, test machine board integration box 3, DC signal source connection cable 4, tested product crimping joint 5, test source lead-out board 6, multi-channel isolator test adapter integration box 7, tested product fixing slot 8, gold finger fixing plate 9, automatic blanking chute 10, transmission belt 11, transmission motor 12, test good product tube 13, test bad classification tube 14. DETAILED DESCRIPTION

[0048] The present invention will be further described in detail below through specific embodiments:

[0049] See also Figure 1-2 , a digital capacitor isolator test and sorting system and a sorting device thereof, including a multi-channel isolator test adapter integrated box 7, the integrated box is provided with a detection circuit for connecting the chip under test; also including a test system PC2 and a communication connection sorting system;

[0050] The test system PC2 includes a test machine and a test system PC2. The test machine tests the chip under test in the integrated box. The test system PC2 controls the test process by controlling the opening or closing of the test input signal and / or test output signal channel of the test machine; the test machine is also used to detect the detection information during the test process, and the test system PC2 outputs the corresponding test results based on the test information; the sorting system includes an automatic sorting machine 1, a sorting system industrial control PLC and a sorting system PC. The test machine draws a judgment result based on the feedback signal and transmits the instruction to the industrial control PLC of the sorting system. The industrial control PLC controls the automatic sorting machine 1 to classify the tested products according to quality.

[0051] Furthermore, the test input signal and / or test output signal channel of the test machine includes:

[0052] The device also includes a VDDA detection channel, a VDDB detection channel, an ENA detection channel, an ENB detection channel, and at least one set of input and output detection channels. The device also includes a programmable power supply, which includes a voltage source group, a current source group, and a signal source group. The multi-channel isolator test adapter integrated box 7 includes a gold finger. The VDDA detection channel includes a VDDA pin end and a first electronically controlled switch group, and the VDDA pin end is connected to the voltage source group and the current source group respectively through the first electronically controlled switch group.

[0053] The control signal of the first electric control switch group is connected to the test system PC2; the VDDA pin end is connected to the gold finger for connecting the detection signal to the chip; the VDDB detection channel includes the VDDB pin end and the second electric control switch group, the VDDB The pin ends are respectively connected to the voltage source group and the current source group through the second electronically controlled switch group; the control signal of the second electronically controlled switch group is connected to the test system PC2; the VDDB pin end is connected to the gold finger for connecting the detection signal to the chip; the ENA detection channel includes an ENA pin end and a third electronically controlled switch group, the ENA pin end is respectively connected to the voltage source group and the current source group through the third electronically controlled switch group, and the control signal of the third electronically controlled switch group is connected to the test system PC2; the ENA pin end is connected to the gold finger for connecting the detection signal to the chip; the ENB detection channel includes an ENB pin end and a fourth electronically controlled switch group, the ENB pin end is respectively connected to the voltage source group and the current source group through the fourth electronically controlled switch group, and the control signal of the fourth electronically controlled switch group is connected to the test system PC2; the ENB pin end is connected to the gold finger for connecting the detection signal to the chip.

[0054] The input and output detection channels include an input detection channel and an output detection channel; the input detection channel includes IN1, IN2, IN3, and IN4 pin ends and the IN1 input electronically controlled switch group, IN2 input electronically controlled switch group, IN3 input electronically controlled switch group, and IN4 input electronically controlled switch group; the IN1, IN2, IN3, and IN4 pin ends are respectively connected to the voltage source group, the current source group, and the signal source group through the IN1 input electronically controlled switch group, the IN2 input electronically controlled switch group, the IN3 input electronically controlled switch group, and the IN4 input electronically controlled switch group; the control signals of the IN1 input electronically controlled switch group, the IN2 input electronically controlled switch group, the IN3 input electronically controlled switch group, and the IN4 input electronically controlled switch group are respectively connected to the test system PC2; the IN1, IN2, IN3, and IN4 pin ends are all connected to the gold finger for connecting the detection signal to the chip; the output detection channel includes OUT1, OUT2, OUT3, and OUT4 pin ends and the OUT1 input electronically controlled switch group, OUT2 input electronically controlled switch group, OUT3 input electronically controlled switch group, and OUT4 input electronically controlled switch group;

[0055] The OUT1, OUT2, OUT3 and OUT4 pin ends are respectively connected to the voltage source group, current source group and signal source group through the OUT1 input electronic control switch group, OUT2 input electronic control switch group, OUT3 input electronic control switch group and OUT4 input electronic control switch group; the control signals of the OUT1 input electronic control switch group, OUT2 input electronic control switch group, OUT3 input electronic control switch group and OUT4 input electronic control switch group are respectively connected to the test system PC2; the OUT1, OUT2, OUT3 and OUT4 pin ends are all connected to gold fingers for connecting the detection signal to the chip. Specifically, the model of the chip under test is IS374X. The programmable power supply provides each group of power supply for the test machine's range application range, including ±48V / 10A, ±24V / 5A, ±12V / 5A, ±5V / 10A, etc.; the programmable power supply and the test system PC2 are both powered by AC220V, 50HZ.

[0056] According to national standards, the design parameter performance test items of general digital capacitor isolators are as follows:

[0057] 1. OS (open short circuit test) test steps and methods

[0058] As shown in the test schematic, the 6 ports VDDA, IN1, IN2, IN3, IN4, and ENA on the left side of the device under test (DUT) are connected to the V1 current source, V3 current source, V6 current source, V9 current source, V12 current source, and V15 current source through relays K1, K3, K6, K9, K12, and K15.

[0059] Draw 100uA from GNDA (set to 0V) and test the voltage value of each pin within the indicator range (-0.9V, -0.2V). If the test value is lower than -0.9V, it is judged as open circuit (OPEN) state. If the test value is higher than -0.2V, it is judged as short circuit (SHORT) state.

[0060] Similarly, the VDDB, OUT1, OUT2, OUT3, OUT4, and ENB ports on the right side of the device under test (DUT) are connected to the V01 current source, V03 current source, V06 current source, V09 current source, V012 current source, and V015 current source by connecting relays K01, K03, K06, K09, K012, and K015.

[0061] Draw 100uA from GNDB (set to 0V) and test the voltage value of each pin within the indicator range (-0.9V, -0.2V). If the test value is lower than -0.9V, it is judged as open circuit (OPEN) state. If the test value is higher than -0.2V, it is judged as short circuit (SHORT) state.

[0062] 2. VOUT (default output level test) test steps and methods:

[0063] As shown in the schematic diagram, the device under test (DUT) is connected to the relays K01, K03, K06, K09, K012, and K015.

[0064] V01 current source, V03 current source, V06 current source, V09 current source, V012 current source, V015 current source connection

[0065] Principle: Under the specified power supply voltage, VDDB port is set to 0V, and the DC voltage output by the OUT port of the device under test is measured.

[0066] 2.1 The VDDB input voltage of the DUT is in the range of 2.375V-5.5V through the V02 voltage source.

[0067] 2.2 Measure the voltage values ​​of the current sources V03, V06, V09 and V012 corresponding to the OUT1-OUT4 terminals of the DUT.

[0068] 2.3 The output voltage value of the DUT OUT terminal should be close to the V02 voltage source to be judged as a good product, otherwise it is judged as a defective product.

[0069] 3. UVLO start voltage and stop working voltage test steps and methods:

[0070] As shown in the schematic diagram, the device under test (DUT) VDDA is connected to the V2 voltage source by turning on relay K2.

[0071] Principle: The voltage of VDDA increases from 0V to 5.5V and decreases from 5.5V to 0V. When the current value of the voltage source connected to the VDDA of the device under test suddenly increases, the corresponding voltage values ​​are the start-up voltage and the stop working voltage.

[0072] 3.1 The voltage at the DUT power supply terminal VDDA is applied with a voltage that gradually increases from small to large through the V2 voltage source.

[0073] 3.2 Monitor the current value of the V2 voltage source. When the current value of the V2 voltage source is ≥1mA, the voltage value of the V2 voltage source is the starting voltage.

[0074] 3.3 The voltage at the DUT power supply terminal VDDA is applied with a voltage that gradually decreases through the V2 voltage source.

[0075] 3.4 Monitor the current value of the V2 voltage source. When the current value of the V2 voltage source is ≤1mA, the voltage value of the V2 voltage source is the starting voltage.

[0076] Similarly:

[0077] 3.5 The VDDB terminal of the DUT is applied with a variable voltage from 0V to 5.5V through the V02 voltage source.

[0078] 3.6 Monitor the current value of the V02 voltage source. When the current value of the V02 voltage source is ≥1mA, the voltage value of the V02 voltage source is the starting voltage.

[0079] 3.7 The V02 voltage source applies a variable voltage to the DUT power supply terminal VDDB, which changes from 5.5V to 0V.

[0080] 3.8 Monitor the current value of the V02 voltage source. When the current value of the V02 voltage source is ≤1mA, the voltage value of the V02 voltage source is the stop working voltage.

[0081] 4. VO1 (output voltage logic high and low levels)

[0082] As shown in the schematic diagram, the device under test (DUT) is connected to the relevant voltage source by turning on relays K2, K4, K7, K10, K13, K02, K03, K06, K09, and K012.

[0083] Principle: Under the specified power supply voltage and input IN terminal at the specified voltage, the device OUT terminal SINK or SOURCE has a certain current value, and the maximum value that the device can output (flow out of / into the device).

[0084] 4.1 Apply the specified power supply voltages VDDA and VDDB to the DUT power supply terminal through the V2 voltage source and the V02 voltage source.

[0085] 4.2 The IN input voltage is at the same level as the power supply voltage.

[0086] 4.3 The voltage value at the OUT terminal when 4mA flows out of the OUT terminal.

[0087] The voltage value at the OUT terminal when 4mA flows into the OUT terminal.

[0088] VINT_H (positive input threshold voltage)

[0089] As shown in the test schematic, the device under test (DUT) switches on relay K2.

[0090] K4, K7, K10, K13, K02, K04, K07, K010, K013 are connected to the relevant voltage source

[0091] Principle: Under the specified power supply voltage (VDDB and VDDA ports), the voltage of the IN input port changes from low to high, and the level of the monitored OUT port changes from low to high;

[0092] 5.1 Apply the specified power supply voltage (2.375V-5.5V) to the DUT power supply terminals (VDDB and VDDA ports) through the V2 voltage source and the V02 voltage source.

[0093] 5.2 The voltage of the V4, V7, V10, and V13 voltage sources varies from 0V to 5.5V.

[0094] 5.3 When the level of the monitoring V04, V07, V010, and V013 voltage sources changes from low to high, the voltage of the corresponding V4, V7, V10, and V13 voltage sources is the positive input threshold voltage.

[0095] VINT_L (negative input threshold voltage)

[0096] As shown in the test schematic, the device under test (DUT) switches on relay K2.

[0097] K4, K7, K10, K13, K02, K04, K07, K010, K013 are connected to the relevant voltage source

[0098] Principle: Under the specified power supply voltage (VDDB and VDDA ports), the voltage of the IN input port changes from high to low, and the level of the monitored OUT port changes from low to high;

[0099] 6.1 Apply the specified power supply voltage (2.375V-5.5V) to the DUT power supply terminals (VDDB and VDDA ports) through the V2 voltage source and the V02 voltage source.

[0100] 6.2 The voltage of the V4, V7, V10, and V13 voltage sources varies from 5.5V to 0V.

[0101] 6.3 When the levels of the monitoring voltage sources V04, V07, V010, and V013 change from high to low, the voltages of the corresponding voltage sources V4, V7, V10, and V13 are the negative input threshold voltages.

[0102] 7 IIH (input high level current)

[0103] As shown in the test schematic, the device under test (DUT) is connected to the relevant voltage source by connecting relays K2, K4, K7, K10, K13, and K02.

[0104] Principle: Under the specified power supply voltage (VDDB and VDDA ports), when the IN input port voltage is at the power supply voltage value, the current value flowing into the port;

[0105] 7.1 Apply the specified power supply voltage (2.375V-5.5V) to the DUT power supply terminals (VDDB and VDDA ports) through the V2 voltage source and the V02 voltage source.

[0106] 7.2 The voltage of the V4, V7, V10, and V13 voltage sources varies from (2.375V to 5.5V).

[0107] 7.3 Read the current value of the V4, V7, V10, and V13 voltage sources as IIH.

[0108] 8. IIL (input low level current)

[0109] As shown in the test schematic, the device under test (DUT) is connected to the relevant voltage source by connecting relays K2, K4, K7, K10, K13, and K02.

[0110] Principle: Under the specified power supply voltage (VDDB and VDDA ports), when the IN input port voltage is at the power supply voltage value, the current value flowing into the port;

[0111] 8.1 Apply the specified power supply voltage (2.375V-5.5V) to the DUT power supply terminals (VDDB and VDDA ports) through the V2 voltage source and the V02 voltage source.

[0112] 8.2 Set the voltage of V4, V7, V10, and V13 voltage sources to 0V.

[0113] 8.3 Read the current value of the V4, V7, V10, and V13 voltage sources as IIL.

[0114] 9. ROUT (output impedance)

[0115] As shown in the test schematic, the device under test (DUT) switches on relay K2.

[0116] K4, K7, K10, K13, K02, K04, K07, K010, K013 are connected to the relevant voltage source

[0117] Principle: Under the specified power supply voltage (VDDB and VDDA ports), the specified current flows into the OUT port, the OUT port voltage is monitored, and the output impedance ROUT is calculated;

[0118] 9.1 Apply the specified power supply voltage (2.375V-5.5V) to the DUT power supply terminals (VDDB and VDDA ports) through the V2 voltage source and the V02 voltage source.

[0119] 9.2 The voltages of the V4, V7, V10, and V13 voltage sources are set to the same value as the power supply voltage.

[0120] 9.3 The sink current of current sources V03, V06, V09, and V012 is 4 mA, and the test voltage value is VOUTn.

[0121] 9.4 ROUTn=VOUTn / 4mA.

[0122] 10. IDD_DC (DC signal power supply current)

[0123] As shown in the schematic diagram, the device under test (DUT) is connected to the relevant voltage source by connecting relays K2, K4, K7, K10, K13, and K02.

[0124] Principle: When the power supply voltage (VDDB and VDDA ports) is specified and the voltage of the IN input port is at the H / L level, the current value flowing into the VDDB and VDDA ports;

[0125] 10.1 Apply the specified power supply voltage (2.375V-5.5V) to the DUT power supply terminals (VDDB and VDDA ports) through the V2 voltage source and the V02 voltage source.

[0126] 10.2 Set the voltage of V4, V7, V10, and V13 voltage sources to 0V or synchronize with the voltages of VDDB and VDDA.

[0127] 10.3 Read the current value of the V2 and V02 voltage sources as IDD DC.

[0128] 11. IDD_AC_500KHZ (AC signal 500K power supply current)

[0129] As shown in the schematic diagram, the device under test (DUT) is connected to the relevant square wave signal generator by connecting relays K2, K5, K8, K11, K14, and K02.

[0130] Principle: Under the specified power supply voltage (VDDB and VDDA ports), the specified square wave clock signal is applied to the IN input port, and the current value flowing into the VDDB and VDDA ports;

[0131] 11.1 Apply the specified power supply voltage (2.375V-5.5V) to the DUT power supply terminals (VDDB and VDDA ports) through the V2 voltage source and the V02 voltage source.

[0132] 11.2 Apply a 500KHZ signal to the square wave clock signal source of V5, V8, V11, and V14.

[0133] 11.3 Read the current value of the V2 and V02 voltage sources as IDD_AC_500KHZ.

[0134] 12. IDD_AC_20MHZ (AC signal 5M power supply current)

[0135] As shown in the test schematic, the device under test (DUT) is connected to the relevant square wave signal generator by connecting relays K2, K5, K8, K11, K14, and K02.

[0136] Principle: Under the specified power supply voltage (VDDB and VDDA ports), the specified square wave clock signal is applied to the IN input port, and the current value flowing into the VDDB and VDDA ports;

[0137] 12.1 Apply the specified power supply voltage (2.375V-5.5V) to the DUT power supply terminals (VDDB and VDDA ports) through the V2 voltage source and the V02 voltage source.

[0138] 12.2 The square wave clock signal source of V5, V8, V11, and V14 applies a 20 MHz signal.

[0139] 12.3 Read the current value of the V2 and V02 voltage sources as IDD_AC_5MHZ.

[0140] 13. IDD_AC_100MHZ (AC signal 50M power supply current)

[0141] As shown in the test schematic, the device under test (DUT) is connected to the relevant square wave signal generator by connecting relays K2, K5, K8, K11, K14, and K02.

[0142] Principle: Under the specified power supply voltage (VDDB and VDDA ports), the specified square wave clock signal is applied to the IN input port, and the current value flowing into the VDDB and VDDA ports;

[0143] 13.1 The DUT power supply terminals (VDDB and VDDA ports) are supplied with the specified power supply voltage (2.375 V to 5.5 V) through the V2 voltage source and the V02 voltage source.

[0144] 13.2 Apply a 100 MHz signal to the square wave clock signal source of V5, V8, V11, and V14.

[0145] 13.3 Read the current value of the V2 and V02 voltage sources as IDD_AC_100MHZ.

[0146] 14. SER (High-speed transmission bit error rate)

[0147] As shown in the test schematic, the device under test (DUT) is connected to the relevant square wave signal generation source by connecting relays K2, K5, K8, K11, K14, and K02; at the same time, relays K05, K08, K011, and K014 are connected to the relevant square wave signal measurement source;

[0148] Principle: At the specified power supply voltage (VDDB and VDDA ports), apply a specified square wave clock signal to the IN input port and measure the output square wave clock signal at the OUT port;

[0149] 14.1 The DUT power supply terminals (VDDB and VDDA ports) are supplied with the specified power supply voltage (2.375 V to 5.5 V) through the V2 voltage source and the V02 voltage source.

[0150] 14.2 The square wave clock signal source of V5, V8, V11, and V14 sends a 100 MHz signal to the IN port.

[0151] 14.3 The square wave clock signal measurement source of V05, V08, V011, and V014 measures the output signal of the OUT port.

[0152] Sampling and measuring.

[0153] 11.4 Calculate the percentage of the number of input clock signals at the IN end to the number of output clock signals at the OUT end, which is SER.

[0154] See also Figure 3-7 The present invention also proposes a digital capacitor isolator test device, including a test mechanism and an automatic sorting mechanism 1, the test mechanism includes a test machine and a test system PC2PC; the test machine includes a test machine board integrated box

[0155] 3. The test source lead-out board 6 is provided on the outside of the test machine board integrated box 3; the automatic sorting machine 1 includes an automatic sorting machine

[0156] 1. The automatic sorting machine 1 has a test product fixing slot 8 on the outside, facing the test machine board integration box 3. A gold finger fixing plate 9 is located near the test product fixing slot 8. The automatic sorting machine 1 also includes a multi-channel isolator test adapter integration box 7, which is fixed to the gold finger fixing plate 9. An automatic blanking chute 10 is located directly above the test product fixing slot 8 on the automatic sorting machine 1. A test product crimping head 5 is located on the automatic sorting machine 1 at a position corresponding to the test product fixing slot 8. The test adapter integrated box is directly fixed on the product positioning position of the sorting system through the gold finger fixing plate 9. The tested product falls freely to the product positioning position through the material tube on the sorting system, and then the tested product crimping head 5 of the sorting system is actuated to allow the tested product to contact the gold finger, so that the applied voltage or current signal of the test machine is transmitted to the tested product, and at the same time, the processed signal of the tested product is also fed back to the test machine; the test machine determines whether the product is good or defective according to the feedback signal, and sends the corresponding instructions to the industrial control PLC of the sorting system through the communication cable, so that it commands the automatic sorting machine 1 to take corresponding actions, so that good and defective products enter different BIN boxes.

[0157] The automatic sorting machine 1 also includes a material guide track, a transmission belt 11, a transmission motor 12, a test good product tube 13 and a test bad product classification tube 14. See the figure. The tested product in the product material strip to be tested is transported to the test station and the pressure head by the mechanical automatic transmission mechanism and fixed. The tested product is connected to the test system PC2 through the gold finger contact. At this time, the manipulator sends an SOT signal (an electrical signal telling the tester to start) to the test system PC2. After receiving this signal, the test system PC2 performs various parameter tests such as voltage, current, clock signal, frequency signal and efficiency on the tested product according to the predetermined electrical performance program. If the various parameters of the product meet the specification requirements, the tester will give the manipulator a PASS signal, and the manipulator will pass through the material guide track, and the transmission belt 11 and the transmission motor 12 will make the tested product enter the test good product tube 13; if the product has parameters that are not within the specification requirements, the tester will give the manipulator a FAIL signal, and the manipulator will pass through the material guide track, the transmission belt 11 , the transmission motor 12 sends the tested product into the test defective classification tube 14; finally, the test system PC2 will send EOT (test end signal) to the robot, indicating that the test and sorting process of a product is completed; the robot will then proceed to the next test process, and the cycle will continue.

[0158] The multi-isolator test adapter integrated box 7 and the test source lead-out board 6 are connected via multiple sets of high-speed signal coaxial shielded cables and a DC signal source connection cable 4. This facilitates high-speed signal transmission, minimizes interference, and reduces signal reflection delay. The test machine and the test system PC2PC are connected via a 25-core cable, employing parallel data communication.

[0159] The method for making a test transfer integrated box in a universal single / dual / quadruple unit digital capacitor isolator test and sorting system is as follows: first draw the PCB diagram as required and then make the printed circuit board. The technical requirements are as follows: 1) the characters are printed in white; 2) the board material is

[0160] The thickness is 1.6mm, and the copper foil thickness is greater than or equal to 35um. 3) Add a tin spraying process to the printed circuit board to prevent oxidation and ensure good welding; then assemble the PCBA. Before soldering the components, use a multimeter to check the basic electrical performance of the PCB. If the performance is good, solder the components on the printed circuit board in order from small to large. During soldering, confirm whether the polarity and installation position of the components are correct; after all connectors are soldered, turn on the power, and connect the input and output channels in series with an Agilent voltage and dual-channel oscilloscope for preliminary electrical inspection; then use screws to fix all the printed circuit board assemblies in the housing, and then perform vibration tests and high and low temperature aging tests, and finally perform EMC anti-interference and group pulse tests. After all experiments are completed, turn on the power and test their accuracy with standard samples.

[0161] When using the test adapter integrated box, first determine whether the signal channels defined in the product correspond one-to-one with the channels of the test machine signal source.

[0162] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art will be able to modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein with equivalents. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. Digital capacitor isolator test and sorting system, characterized by: The invention comprises a multi-channel isolator test adapter integrated box (7), wherein a detection circuit is provided in the multi-channel isolator test adapter integrated box (7) for connecting the chip to be tested; and further comprises a test system PC and a communication connection sorting system; The test system PC includes a test machine, a multi-channel isolator test adapter integrated box (7), and a chip under test. The test system PC controls the test process by controlling the opening or closing of the test input signal and / or test output signal channel of the test machine; The test machine is also used to detect the test information during the test process, and the test system PC outputs the corresponding test results according to the test information; The sorting system comprises an automatic sorting machine (1), a sorting system industrial control PLC and a sorting system PC, wherein the test machine applies a voltage or current signal to the product under test, and at the same time, the signal processed by the product under test is fed back to the test machine; the test machine determines whether the product is good or bad based on the feedback signal, and sends the corresponding instruction to the sorting system industrial control PLC through a communication cable, so that the PLC instructs the automatic sorting machine (1) to take corresponding action, so that the good and bad products are placed in different BIN boxes; The test input signal and / or test output signal channels of the test machine include: VDDA detection channel, VDDB detection channel, ENA detection channel, ENB detection channel and at least one group of input and output detection channels; It also includes a program-controlled power supply, which includes a voltage source group, a current source group, and a signal source group; the multi-channel isolator test adapter integrated box (7) includes a gold finger; The VDDA detection channel includes a VDDA pin end and a first electronically controlled switch group, wherein the VDDA pin end is respectively connected to the voltage source group and the current source group through the first electronically controlled switch group; the control signal of the first electronically controlled switch group is connected to the test system PC; the VDDA pin end is connected to the gold finger for connecting the detection signal to the chip; The VDDB detection channel includes a VDDB pin end and a second electronically controlled switch group, wherein the VDDB pin end is respectively connected to the voltage source group and the current source group through the second electronically controlled switch group; the control signal of the second electronically controlled switch group is connected to the test system PC; the VDDB pin end is connected to the gold finger for connecting the detection signal to the chip; The ENA detection channel includes an ENA pin end and a third electronically controlled switch group. The ENA pin end is respectively connected to the voltage source group and the current source group through the third electronically controlled switch group. The control signal of the third electronically controlled switch group is connected to the test system PC. The ENA pin end is connected to the gold finger for connecting the detection signal to the chip. The ENB detection channel includes an ENB pin end and a fourth electronically controlled switch group. The ENB pin end is respectively connected to the voltage source group and the current source group through the fourth electronically controlled switch group. The control signal of the fourth electronically controlled switch group is connected to the test system PC; the ENB pin end is connected to the gold finger for connecting the detection signal to the chip.

2. The digital capacitor isolator testing and sorting system according to claim 1, characterized in that: The input and output detection channels include an input detection channel and an output detection channel; The input detection channel includes IN1, IN2, IN3, IN4 pin ends and IN1 input electronically controlled switch group, IN2 input electronically controlled switch group, IN3 input electronically controlled switch group, IN4 input electronically controlled switch group; The IN1, IN2, IN3, and IN4 pins are connected to the voltage source group, the current source group, and the signal source group respectively through the IN1 input electronic control switch group, the IN2 input electronic control switch group, the IN3 input electronic control switch group, and the IN4 input electronic control switch group; The control signals of the IN1 input electronic control switch group, the IN2 input electronic control switch group, the IN3 input electronic control switch group and the IN4 input electronic control switch group are respectively connected to the test system PC; the IN1, IN2, IN3 and IN4 pin ends are all connected to the gold fingers for connecting the detection signals to the chip; The output detection channel includes OUT1, OUT2, OUT3 and OUT4 pin ends and OUT1 input electronically controlled switch group, OUT2 input electronically controlled switch group, OUT3 input electronically controlled switch group, OUT4 input electronically controlled switch group; the OUT1, OUT2, OUT3 and OUT4 pin ends are respectively connected to the voltage source group, the current source group and the signal source group through the OUT1 input electronically controlled switch group, the OUT2 input electronically controlled switch group, the OUT3 input electronically controlled switch group and the OUT4 input electronically controlled switch group; The control signals of the OUT1 input electronic control switch group, OUT2 input electronic control switch group, OUT3 input electronic control switch group and OUT4 input electronic control switch group are respectively connected to the test system PC; the OUT1, OUT2, OUT3 and OUT4 pin ends are all connected to gold fingers for connecting the detection signals to the chip.

3. The digital capacitor isolator testing and sorting system according to any one of claims 1-2, characterized in that: The model of the chip under test is IS374X.

4. The digital capacitor isolator testing and sorting system according to claim 1, wherein: The test machine and the test system PC are connected by a 25-core cable and adopt a parallel data communication method.

5. The test device used in a digital capacitor isolator test system according to claim 3, characterized in that: The invention comprises a testing mechanism and an automatic sorting mechanism, wherein the testing mechanism comprises a testing machine and a testing system PC; the testing machine comprises a testing machine board card integration box (3), and a test source lead-out board card (6) is provided on the outside of the testing machine board card integration box (3); the automatic sorting mechanism comprises an automatic sorting machine (1), and a tested product fixing slot (8) is provided on the outside of the automatic sorting machine (1) facing the side of the testing machine board card integration box (3), and a gold finger fixing plate (9) is provided near the tested product fixing slot (8); and the invention also comprises a multi-channel isolator test transfer integration box (7), and the multi-channel isolator test transfer integration box (7) is fixed on the gold finger fixing plate (9).

6. The test device used in the digital capacitor isolator test system according to claim 5, characterized in that: An automatic blanking chute (10) is provided directly above the fixed chute (8) for the product to be tested on the automatic sorting machine (1).

7. The test device used in the digital capacitor isolator test system according to claim 6, characterized in that: The multi-channel isolator test adapter integrated box (7) and the test source lead-out board (6) are connected via multiple groups of high-speed signal coaxial shielded wires and DC signal source connection cables (4).

8. The test device used in the digital capacitor isolator test system according to claim 7, characterized in that: A product-to-be-tested crimping joint (5) is provided on the automatic sorting machine (1) at a position corresponding to the product-to-be-tested fixing groove (8).

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