Apparatus and method for processing floating point numbers

Abstract

Circuits and associated methods are disclosed for processing two floating-point numbers (A, B) to generate a sum (A+B) and a difference (A-B) of the two numbers. The method includes using a same-sign floating-point adder (1020) to compute (806) a sum of the absolute values of the two floating-point numbers (|A|+|B|) to produce a first result. The method also includes computing (808) a difference of the absolute values (|A|-|B|) to produce a second result. The sum (A+B) and the difference (A-B) are generated (810, 812) based on the first result (|A|+|B|), the second result (|A|-|B|), and the sign of each floating-point number.

Description

TECHNICAL FIELD

[0001] The present application relates to apparatuses and methods for processing floating-point numbers. BACKGROUND

[0002] Floating-point arithmetic is useful in a wide variety of applications, including but not limited to graphics, data processing, image processing, signal processing, control algorithms, scientific programming, and many others. Adding floating-point numbers together is one of the most fundamental operations in floating-point arithmetic, and is ubiquitous in a wide variety of different applications and implementations.

[0003] Floating-point addition can be implemented in software, e.g., by executing a suitable instruction on a general-purpose processing unit. Alternatively, floating-point addition can be implemented in hardware, e.g., by suitably configuring a fixed-function circuit. Generally speaking, a software implementation allows for greater flexibility (e.g., in terms of changing the addition operation after design time, e.g., changing the number of numbers to be added together) compared to a hardware implementation; however, generally speaking, a hardware implementation provides more efficient operation (e.g., in terms of lower latency and lower power consumption) compared to a software implementation. Thus, a hardware implementation can be more suitable than a software implementation if efficiency of operation is considered more important than flexibility (e.g., if it is known that a particular type of addition operation needs to be performed many times in a device where power consumption and latency are very important, such as a battery-powered mobile device (e.g., a smartphone, tablet, or laptop)). SUMMARY

[0004] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the DETAILED DESCRIPTION. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0005] When implementing any functionality (e.g., floating-point addition) in dedicated hardware, hardware size is a consideration, especially when using the hardware in size-constrained devices such as mobile devices. Therefore, when designing hardware for a processing unit, trade-offs must be made regarding (i) power consumption, (ii) processing performance, and (iii) size (also referred to as "semiconductor area" or "silicon area"). Improving one of these factors (e.g., reducing power consumption, increasing processing performance, or reducing silicon area) can lead to a deterioration of one or both of the other factors (e.g., increasing power consumption, decreasing processing performance, or increasing silicon area). This paper describes adder circuitry and associated methods for processing a set of at least three floating-point numbers to be added together, which can provide improvements in one or more of these factors without necessarily causing a deterioration in one or more of the other factors. The method involves identifying at least two numbers with the same sign from at least three numbers, i.e., at least two numbers that are both positive or both negative. The identified at least two numbers are added together using one or more floating-point adders with the same sign. A floating-point adder with the same sign includes circuitry configured to add floating-point numbers with the same sign, but excludes circuitry configured to add numbers with different signs.

[0006] According to one aspect, a machine-implemented method is provided for processing an input set comprising at least three floating-point numbers to be summed, the input set including one or more positive numbers and one or more negative numbers, the method comprising:

[0007] It accepts at least three floating-point numbers from the input set;

[0008] Identify at least two numbers in the input set that have the same sign; and

[0009] Use one or more floating-point adders with the same sign to add together at least two identified numbers to produce one or more partial sums.

[0010] One or more floating-point adders with the same sign are implemented in a fixed-function circuit configured to add floating-point numbers with the same sign together, and one or more floating-point adders with the same sign do not include circuitry configured to add numbers with different signs together.

[0011] The inventors have recognized two points. First, it is easier to add floating-point numbers together if it is known in advance that they have the same sign. Second, in any set of three numbers, there must be at least two numbers with the same sign (or more generally, in any set of (2n) or (2n-1) numbers, there must be at least n numbers with the same sign). This combination of identifiers can be used to simplify the process of adding any set of at least three floating-point numbers together by first identifying and then adding the numbers with the same sign.

[0012] A 2:1 same-sign adder (i.e., an same-sign adder with two inputs and one output) can be used to add two numbers with the same sign together.

[0013] Two 2:1 adders with the same sign can be used to add three numbers with the same sign, where the output of the first adder provides one of its inputs to the second adder. Alternatively, a single 3:1 adder with the same sign (i.e., an adder with the same sign that has three inputs and one output) can be provided to add three numbers with the same sign. Efficiently adding three numbers with the same sign can be useful, for example, when it is desired to add five numbers (with arbitrary signs) together, because in any set of five numbers, there are at least three numbers that share the same sign.

[0014] When using multiple floating-point adders with the same sign to add numbers with the same sign, at least some of the adders can be arranged in series (i.e., the outputs of one or more adders provide input to one or more other adders). The series arrangement of adders can include a tree with multiple levels, where each level of the tree has many inputs and produces fewer intermediate results than the number of inputs, with the intermediate results being provided as input to the next level.

[0015] Preferably, a mixed-sign adder is not used to produce one or more partial summation results.

[0016] The method may also include outputting one or more partial summations and each remaining number from the input set. Here, "remaining number" means any number other than the at least two numbers identified as having the same sign.

[0017] The method may further include: adding one or more partial summation results together with each remaining number from the input set to calculate the sum of the input set, wherein adding one or more partial summation results together with each remaining number from the input set includes using at least one mixed-sign floating-point adder implemented in a fixed-function circuit configured to add floating-point numbers having the same or different signs together.

[0018] The method may further include: using a mixed-sign floating-point adder to add together multiple numbers derived from an input set, wherein at least one of the multiple numbers is a partial summation result produced by a same-sign floating-point adder, thereby calculating the sum of the input set, wherein the mixed-sign floating-point adder is implemented in a fixed-function circuit configured to add together floating-point numbers having the same or different signs.

[0019] One or more floating-point adders with the same sign may include a first array of floating-point adders with the same sign and a second array of floating-point adders with the same sign, wherein identifying at least two numbers having the same sign includes: evaluating at least the sign bit of each floating-point number in the input set; passing the floating-point number to the corresponding input of the first array only if the sign bit of each floating-point number in the input set is zero; passing the floating-point number to the corresponding input of the second array only if the sign bit of each floating-point number in the input set is one; the method further includes combining the output of the second array with the output of the first array.

[0020] Combining may include subtracting the output of the second array from the output of the first array using a floating-point subtractor (particularly if the output of the second array is represented as a positive number). Alternatively, combining may include adding the output of the second array to the output of the first array (particularly if the output of the second array is represented as a negative number).

[0021] In this method, positive numbers from the input set are added together in the first array, and negative numbers from the input set are added together in the second array.

[0022] The number of inputs to the first array can be equal to the number of floating-point numbers in the input set. The number of inputs to the second array can be equal to the number of floating-point numbers in the input set.

[0023] The first and second arrays can be implemented using two different arrays. The two different arrays can operate simultaneously.

[0024] The first array and the second array can be implemented by a single array, which is operated as the first array at a first time and as the second array at a different second time.

[0025] Identifying at least two numbers with the same sign can include classifying the input set into positive and negative numbers.

[0026] One or more identically signed floating-point adders may include an array of identically signed floating-point adders having a plurality of inputs, wherein adding at least two identified numbers together may include: passing some or all positive numbers to a corresponding first subset of the plurality of inputs; and passing some or all negative numbers to a corresponding second subset of the plurality of inputs, such that each identically signed floating-point adder in the array receives an input having the same sign.

[0027] Identifying at least two numbers with the same sign can include determining that two or more numbers have the same sign; and identifying at least two numbers with the smallest absolute value among two or more numbers with the same sign.

[0028] According to another aspect, an adder circuit is provided, the adder circuit being configured to process an input set comprising at least three floating-point numbers to be summed, the input set including one or more positive numbers and one or more negative numbers, the circuit comprising:

[0029] The input is configured to receive at least three floating-point numbers from the input set;

[0030] Multiplexing logic configured to identify at least two numbers with the same sign in the input set; and

[0031] One or more floating-point adders with the same sign, configured to add at least two identified numbers together to produce one or more partial sums.

[0032] One or more floating-point adders with the same sign are implemented in a fixed-function circuit configured to add floating-point numbers with the same sign together, and one or more floating-point adders with the same sign do not include circuitry configured to add numbers with different signs together.

[0033] The adder circuit may further include: a first output configured to output one or more partial summation results; and a second output configured to output each remaining number from the input set, rather than at least two numbers identified as having the same sign.

[0034] The adder circuit may further include at least one mixed-sign floating-point adder implemented in a fixed-function circuit configured to add floating-point numbers having the same or different signs together, wherein a first input of the at least one mixed-sign floating-point adder is coupled to the output of one or more identical-sign floating-point adders, and a second input of the at least one mixed-sign floating-point adder is configured to receive at least one remaining number from the input set, rather than the identified at least two numbers.

[0035] The adder circuit may also include at least one mixed-sign floating-point adder implemented in a fixed-function circuit configured to add floating-point numbers having the same or different signs together, wherein at least one mixed-sign floating-point adder is configured to add together multiple numbers derived from the input set to calculate the sum of the input set, wherein at least one of the multiple numbers is a partial summation result produced by a floating-point adder with the same sign.

[0036] A composite adder circuit is also provided, which includes multiple circuits (of the same or different types, combined in any way) as outlined herein, wherein the output of one adder circuit is coupled to the input of another adder circuit.

[0037] In some examples, one or more identically signed floating-point adders include a first array of identically signed floating-point adders and a second array of identically signed floating-point adders, wherein multiplexing logic is configured to: evaluate at least the sign bit of each floating-point number in the input set; pass the floating-point number to the corresponding input of the first array only if the sign bit of each floating-point number in the input set is zero; and pass the floating-point number to the corresponding input of the second array only if the sign bit of each floating-point number in the input set is one. The adder circuitry also includes a floating-point subtractor or a mixed-sign floating-point adder configured to combine the output of the second array with the output of the first array. As described above, the combination can include subtraction or addition.

[0038] Each of the first and second arrays may include a logarithmic tree of floating-point adders with the same sign.

[0039] The first and second arrays can be two different physical arrays in the hardware. In particular, these two arrays can be arranged to operate in parallel with each other.

[0040] The first and second arrays can be provided by a single physical array in the hardware, wherein the multiplexing logic is configured to: pass floating-point numbers with a sign bit of zero to the single array in a first time interval; and pass floating-point numbers with a sign bit of one to the single array in a second, different time interval.

[0041] The reuse logic can be configured to classify the input set into positive and negative numbers.

[0042] One or more identically signed floating-point adders may include an array of identically signed floating-point adders having multiple inputs, wherein the multiplexing logic includes a rotation multiplexer configured to align the boundary between positive and negative numbers with the boundary between two identically signed floating-point adders in the array, such that each identically signed floating-point adder in the array receives an input with the same sign.

[0043] Other circuits and associated methods are also disclosed for processing two floating-point numbers to generate a sum and a difference between the two numbers. The method includes using a floating-point adder with the same sign to calculate the sum of the absolute values ​​of the two floating-point numbers to produce a first result. The method also includes calculating the difference of the absolute values ​​to produce a second result. The sum and difference are generated based on the first result, the second result, and the sign of each floating-point number.

[0044] The inventors have recognized that calculating the sum and difference of two numbers always involves adding two numbers with the same sign. Therefore, in this context, a floating-point adder with the same sign can also be used.

[0045] According to one aspect, a machine-implemented method is provided for processing an input set comprising two floating-point numbers, each floating-point number having a sign, to generate the sum of the two floating-point numbers and the difference between the two floating-point numbers, the method comprising:

[0046] Receives two floating-point numbers from the input set;

[0047] Use a floating-point adder with the same sign to calculate the sum of the absolute values ​​of the two floating-point numbers to produce the first result;

[0048] Use a floating-point subtractor to calculate the difference between the absolute values ​​of two floating-point numbers to produce a second result; and

[0049] Generate the sum and difference of two floating-point numbers based on the following: a first result, a second result, and the sign of each floating-point number.

[0050] The same-sign floating-point adders are implemented in a fixed-function circuit that is configured to add floating-point numbers with the same sign together, and the same-sign floating-point adders do not include circuitry configured to add numbers with different signs together.

[0051] Generating the sum of two floating-point numbers and the difference between two floating-point numbers can include: generating the sum of two floating-point numbers from one of the first result and the second result; and generating the difference between two floating-point numbers from the other of the first result and the second result.

[0052] Generating the sum and difference of two floating-point numbers can include correcting the sign of the first result and the sign of the second result based on the sign of each of the two floating-point numbers.

[0053] According to another aspect, a circuit is provided, configured to process an input set comprising two floating-point numbers, each floating-point number having a sign, to generate the sum of the two floating-point numbers and the difference between the two floating-point numbers, the circuit comprising:

[0054] The input is configured to receive two floating-point numbers from a set of inputs;

[0055] A floating-point adder with the same sign, configured to calculate the sum of the absolute values ​​of two floating-point numbers to produce a first result;

[0056] A floating-point subtractor, used to calculate the difference between the absolute values ​​of two floating-point numbers to produce a second result; and

[0057] Multiplexing and sign correction logic is configured to generate the sum and difference of two floating-point numbers based on the following: a first result, a second result, and the sign of each floating-point number.

[0058] The same-sign floating-point adders are implemented in a fixed-function circuit that is configured to add floating-point numbers with the same sign together, and the same-sign floating-point adders do not include circuitry configured to add numbers with different signs together.

[0059] The floating-point subtractor is preferably implemented in a fixed-function circuit.

[0060] In some implementations, a floating-point subtractor can be implemented using a mixed-sign floating-point adder.

[0061] The multiplexing and sign correction logic can be configured to: generate the sum of two floating-point numbers from one of the first and second results; and generate the difference of two floating-point numbers from the other of the first and second results.

[0062] The multiplexing and sign correction logic can be configured to correct the sign of the first result and the sign of the second result based on the sign of each of the two floating-point numbers.

[0063] A processing system is also provided, which includes one of the circuits described above. A processing system is also provided, configured to perform the methods described above. In some embodiments, the processing system may be a graphics processing system or an artificial intelligence accelerator system. Such systems may be embodied in hardware on an integrated circuit.

[0064] A method of manufacturing is also provided using an integrated circuit manufacturing system, a circuit as described above, or a processing system as described above. The manufacturing method includes: using a layout processing system to process a computer-readable description of the circuit or processing system to generate a circuit layout description of an integrated circuit embodying the circuit or processing system; and using an integrated circuit generation system to manufacture the circuit or processing system according to the circuit layout description.

[0065] An integrated circuit definition dataset is also provided, which, when processed in an integrated circuit manufacturing system, configures the system to manufacture the circuits or processing systems outlined above. The integrated circuit definition dataset can be stored on a computer-readable storage medium, preferably on a non-transitory computer-readable storage medium.

[0066] A computer-implemented method is also provided, which processes a computer-readable description of an integrated circuit to generate a representation of the integrated circuit, the method comprising: receiving a computer-readable description of the integrated circuit; identifying in the computer-readable description of the integrated circuit a description of one or more functional blocks for summing at least three floating-point numbers; and generating a representation of the integrated circuit, wherein the one or more functional blocks are represented in the representation of the integrated circuit as a representation of an adder circuit as outlined above.

[0067] A computer-implemented method is also provided, which processes a computer-readable description of an integrated circuit to generate a representation of the integrated circuit, the method comprising: receiving a computer-readable description of the integrated circuit; identifying in the computer-readable description of the integrated circuit a description of one or more functional blocks for calculating the sum of two floating-point numbers and the difference between the two floating-point numbers; and generating a representation of the integrated circuit, wherein the one or more functional blocks are represented in the representation of the integrated circuit as a representation of a circuit as outlined above.

[0068] Also provided is computer program code configured to, when executed on one or more processors, cause one or more processors to perform the computer-implemented methods as outlined above. The computer program code may be stored on a non-transitory computer-readable storage medium.

[0069] A computer-readable description of a circuit or processing system as outlined above is also provided, which, when processed in an integrated circuit manufacturing system, enables the integrated circuit manufacturing system to produce an integrated circuit embodying the circuit or processing system. The computer-readable description may be stored on a computer-readable storage medium, preferably on a non-transitory computer-readable storage medium.

[0070] A non-transitory computer-readable storage medium is also disclosed, on which a computer-readable description of a circuit or processing system as described above is stored. When processed in an integrated circuit manufacturing system, the integrated circuit manufacturing system performs the following operations: processes the computer-readable description using a layout processing system to generate a circuit layout description of an integrated circuit embodying the circuit or processing system; and manufactures the circuit or processing system using an integrated circuit generation system based on the circuit layout description.

[0071] As will be apparent to those skilled in the art, the above features can be appropriately combined, and can be combined with any aspect of the examples described herein. Attached Figure Description

[0072] The example will now be described in detail with reference to the accompanying drawings, in which:

[0073] Figure 1 This is a schematic block diagram of the adder circuit according to the first embodiment;

[0074] Figure 2 It is a schematic block diagram of an adder circuit for adding three floating-point numbers together according to the second embodiment;

[0075] Figure 3 This is a flowchart illustrating the method according to the implementation scheme;

[0076] Figure 4 It is a schematic block diagram of an adder circuit for adding any number of floating-point numbers together, according to the third embodiment;

[0077] Figure 5 It is a schematic block diagram of an adder circuit for adding any number of floating-point numbers together according to the fourth embodiment;

[0078] Figure 6 This is a schematic block diagram of an adder circuit according to another implementation scheme;

[0079] Figure 7 This is a schematic block diagram of a composite adder circuit for adding six floating-point numbers together, according to another embodiment.

[0080] Figure 8 This illustrates a computer system that implements a graphics processing system;

[0081] Figure 9 An integrated circuit manufacturing system for generating integrated circuits that embody a graphics processing system is shown;

[0082] Figure 10 This is a flowchart illustrating a method for processing a computer-readable description of an integrated circuit to generate a representation of the integrated circuit;

[0083] Figure 11 It is a schematic block diagram of a circuit for calculating the sum and difference of two floating-point numbers according to the implementation scheme; and

[0084] Figure 12 It is based on an implementation plan that can be... Figure 11 The flowchart shows the method of circuit execution.

[0085] The accompanying drawings illustrate various examples. Those skilled in the art will understand that the element boundaries (e.g., boxes, groups of boxes, or other shapes) shown in the drawings represent one example of a boundary. In some examples, it may be that one element can be designed as multiple elements, or multiple elements can be designed as one element. Where appropriate, common reference numerals are used throughout the figures to indicate similar features. Detailed Implementation

[0086] In the description of the preferred embodiments below, the following terms are used:

[0087] A "same-sign floating-point adder" is a component that can only add floating-point numbers with the same sign, but not floating-point numbers with different signs. In other words, if a same-sign floating-point adder is given inputs with different signs, it will generally produce an incorrect result (although there may be a finite number of combinations of input values ​​that can still produce the correct result). In the accompanying drawings, a same-sign floating-point adder is indicated by the label "SS add". In the examples described herein, the same-sign floating-point adder is implemented in a fixed-function circuit configured to add floating-point numbers with the same sign, but the same-sign floating-point adder does not include circuitry configured to add numbers with different signs.

[0088] A "mixed-sign floating-point adder" is a component capable of adding floating-point numbers with the same sign and also capable of adding floating-point numbers with different signs. That is, when a mixed-sign floating-point adder is given inputs with the same or different signs, it will produce the correct result. In the accompanying drawings, mixed-sign floating-point adders are indicated by the label "Add" (because they are regular floating-point adders capable of adding signed floating-point numbers). In the example described herein, the mixed-sign floating-point adder is implemented in a fixed-function circuit configured to add floating-point numbers with the same or different signs.

[0089] A floating-point subtractor is a component that can subtract one floating-point number from another. In the examples described herein, the floating-point subtractor is implemented in a fixed-function circuit. In some examples, the floating-point subtractor can be implemented using a mixed-sign floating-point adder (because a mixed-sign floating-point adder can perform both addition and subtraction operations).

[0090] The following description is presented with the aid of examples to enable those skilled in the art to make and use the invention. The invention is not limited to the embodiments described herein, and various modifications to the disclosed embodiments will be readily apparent to those skilled in the art.

[0091] The implementation scheme will now be described using examples only.

[0092] Figure 1 An adder circuit 100 according to a first embodiment is shown. The adder circuit 100 is configured to process an input set consisting of three floating-point numbers A, B, and C to be summed. It is assumed that the input set includes a mixture of positive and negative numbers (but the adder circuit also functions correctly when the numbers are all positive or all negative). The adder circuit 100 includes inputs configured to receive numbers A, B, and C; multiplexing logic 110 configured to identify two numbers in the input set that have the same sign; and a floating-point adder 120 with the same sign configured to add the identified two numbers with the same sign together to produce a partial summation result. Figure 1 In this implementation, a portion of the summation result is output via a first output terminal (“Output 1”) of the circuit. A second output terminal (“Output 2”) is configured to output the remaining number from the input set, that is, a third number besides the two numbers identified as having the same sign. Thus, Figure 1 The adder circuit 100 is used as a "reducer" to reduce the three floating-point inputs that need to be summed to two floating-point outputs that need to be summed. As will be discussed in more detail below, this reducer can be used as a building block to construct larger adder circuits.

[0093] Multiplexing logic 110 includes three multiplexers 102, 104, and 106. The first multiplexer 102 has two inputs configured to receive numbers A and B, respectively. The second multiplexer 104 also has two inputs configured to receive numbers B and C, respectively. The third multiplexer 106 has three inputs configured to receive three numbers A, B, and C, respectively. Each multiplexer has one output. The output of the first multiplexer 102 is coupled to one input of a floating-point adder 120 with the same sign. The output of the second multiplexer 104 is coupled to the other input of the same-sign floating-point adder 120. The output of the third multiplexer 106 is directly coupled to the second output of circuit 100.

[0094] When numbers A and B have the same sign, the first multiplexer 102 is controlled to output A, and the second multiplexer 104 is controlled to output B. Therefore, the same-sign floating-point adder 120 adds A and B together. When numbers A and C have the same sign, the first multiplexer 102 is controlled to output A, and the second multiplexer 104 is controlled to output C. Therefore, the same-sign floating-point adder 120 adds A and C together. Similarly, when numbers B and C have the same sign, the first multiplexer 102 is controlled to output B, and the second multiplexer 104 is controlled to output C. Therefore, the same-sign floating-point adder 120 adds B and C together. In each case, the third multiplexer 106 is controlled to output the third of the three numbers, i.e., the remaining number, which is neither selected by the first multiplexer 102 nor by the second multiplexer 104. For the sake of clarity and simplicity, Figure 1 The control logic of the multiplexer is not shown. However, it is straightforward to implement this using simple logic operations on the sign bits of the three numbers A, B, and C.

[0095] According to one example, multiplexers 102 to 106 can be controlled as follows. Let Sa, Sb, and Sc be the sign bits of A, B, and C, respectively.

[0096] ●If (Sa XOR Sb), then the second multiplexer 104 selects C.

[0097] ●If (Sa XOR Sc) and (Sa XOR Sb) are equal, then the first multiplexer 102 selects B.

[0098] In other words, if the signs of A and B are different, the second multiplexer 104 selects C; otherwise, it selects B. If the signs of A and C are different and the signs of A and B are also different, the first multiplexer 102 selects B; otherwise, it selects A. The control signals for the third multiplexer 106 can be generated from the control signals of the other two multiplexers. Alternatively, as described below, they can be generated from Sa, Sb, and Sc. Assume that the third multiplexer 106 is implemented as two dual-input multiplexers 106a and 106b.

[0099] ●If the (Sb XOR Sc) multiplexer 106a selects B instead of A

[0100] ●If (Sa XOR Sb) multiplexer 106b selects the output of multiplexer 106a instead of C

[0101] Note that the XOR term (Sa XOR Sb) is used three times, thus allowing a single XOR gate to be shared. The truth table for the control logic summarized above is provided below. Here, m102 and m104 are the control bits for the first multiplexer 102 and the second multiplexer 104, respectively; m106a and m106b are the control bits for multiplexers 106a and 106b that form the third multiplexer 106.

[0102]

[0103] As stated above, in any set of three-digit inputs, there will always be at least two digits with the same sign. In some cases, all three digits may simultaneously have the same sign. In this case, for Figure 1 In this circuit, it is not particularly important which two numbers are provided to the same-sign floating-point adder 120. However, according to a modification of the first embodiment, in this case, the multiplexing logic can select the two numbers with the smallest absolute value and provide them to the same-sign adder 120. This is advantageous because floating-point precision can sometimes be improved by prioritizing the addition of smaller numbers rather than adding smaller numbers to larger numbers. In some embodiments, the two smallest numbers can be conveniently identified by comparing the exponents of the three numbers. When the numbers have different exponents, this approximation will correctly identify the two smallest numbers. When the numbers have the same exponent, the two smallest numbers may not be correctly identified, but this is not a significant drawback—in this case, the numbers are roughly of the same order of magnitude, and the precision of the calculation should be less sensitive to the order of the addition operations.

[0104] Figure 2 An adder circuit 130 according to a second embodiment is shown. The adder circuit includes... Figure 1 The first embodiment includes a "reducer" adder circuit 100 and a mixed-sign floating-point adder 132. The inputs of the mixed-sign floating-point adder 132 are coupled to the outputs of the adder circuit 100 of the first embodiment. Thus, the adder circuit 130 of the second embodiment is configured to add three numbers A, B, and C together using a single-sign floating-point adder 120 and a mixed-sign floating-point adder 132. The mixed-sign floating-point adder 132 receives the following as inputs: (i) a partial summation result generated by the single-sign floating-point adder 120 and provided at the first output of the adder circuit 100; and (ii) the remaining number provided at the second output of the adder circuit 100. The output of the mixed-sign floating-point adder 132 is provided as the output of the adder circuit 130 and represents the result of the sum of the input numbers (A, B, and C).

[0105] A naive approach to adding three numbers together is to use two mixed-sign floating-point adders without multiplexing logic. The first mixed-sign floating-point adder is arranged to add two of the input numbers (e.g., A and B). The second mixed-sign floating-point adder is arranged to add the remaining input number (e.g., C) and the result from the first mixed-sign floating-point adder to provide a result representing the sum of the three input numbers. In contrast to this naive approach, the adder circuit 130 of the second embodiment replaces one of the mixed-sign floating-point adders in the mixed-sign floating-point adder circuit 100, which includes the same sign floating-point adder 120 and some multiplexing logic 110. As described below, the same-sign floating-point adder 120 is easier to implement (e.g., with reduced silicon area) than the mixed-sign floating-point adder 132, thus allowing the addition of three numbers to be implemented more efficiently (e.g., with reduced power consumption and / or reduced latency). For example, the inventors have found that the reduction in semiconductor area achieved by using the same-sign floating-point adder 120 (instead of the mixed-sign floating-point adder) can significantly outweigh the additional area occupied by the multiplexing logic 110. Therefore, the adder circuit 130 using the second embodiment can be significantly more efficient (e.g., in terms of silicon area, power consumption, and / or latency) compared to a naive adder circuit with two mixed-sign floating-point adders.

[0106] Figure 3 This is a flowchart of a method performed by adder circuits according to the implementation scheme. In step 604, adder circuits 100 and 130 receive three floating-point numbers A, B, and C from the input set. In step 606, multiplexing logic 110 identifies two numbers with the same sign in the input set. In step 608, the same-sign floating-point adder 120 adds the identified two numbers together to produce a partial sum. Figure 1 In the "reducer" adder circuit 100, in step 610, the adder circuit 100 outputs a partial summation result and the remaining number among the three numbers. Figure 2 In the adder circuit 130, in step 612, the mixed-sign floating-point adder 132 adds the partial summation result generated by the same-sign floating-point adder 120 to the remaining numbers, thereby calculating the sum of the three input numbers A, B, and C. After step 612, in step 614, the adder circuit 130 outputs the result of the sum of the three numbers A, B, and C.

[0107] As those skilled in the art will understand from the above description, the scope of this disclosure is not limited to adding three floating-point numbers together. The same principle can be extended to any large set of inputs. For example, the “reducer” adder circuit 100 and / or adder circuit 130 can be implemented in a tree structure, with or without additional hybrid sign adders, to provide improvements over similar circuits implemented using only hybrid sign adders (e.g., reduced semiconductor area). In the discussion below, many further examples of possible architectures for extending the principle to any large set of inputs will be provided.

[0108] Figure 4 An architecture for adding floating-point numbers according to a third embodiment is shown. The adder circuitry of this embodiment comprises an array of identically signed floating-point adders arranged in a logarithmic tree. For simplicity and clarity, only the first layer 220a of the identically signed adders in the tree is shown. The multiplexing logic includes a classification block 214 configured to classify the set of input numbers A, B, C…N into positive and negative numbers according to their signs. In general, the size of the set (N) can be arbitrarily large. Within the subset of positive numbers, it is not necessary to classify the numbers. Similarly, within the subset of negative numbers, it is not necessary to classify the numbers. The classification block 214 is configured to output a vector of numbers, wherein the positive numbers of the input set are located at one end of the vector, and the negative numbers are located at the other end of the vector. The multiplexing logic also includes rotating multiplexers 212a, 212b… formed by an array of individual multiplexers. These individual multiplexers are arranged in layers, with one layer 212a, 212b of the multiplexers located at the input of each layer 220a of the same-sign floating-point adders in the tree. The multiplexers are configured to align the boundary between positive and negative numbers with the boundary between two same-sign floating-point adders in the array, such that each same-sign floating-point adder in the array always receives input with the same sign. See the first layer 212a of the multiplexers; this can be achieved by either passing the categorized numbers directly to the adders or by cyclically shifting the numbers one bit to the left, depending on whether the number of positive numbers is odd or even. This ensures that at most one computation is needed at each layer of the tree to operate on two floating-point numbers with different signs, and that this computation is located at a predictable position on the right side of the tree. A mixed-sign floating-point adder 232a is positioned at this position to operate on mixed-sign numbers. The same process is repeated in successive layers of multiplexers and adders until the final mixed-sign floating-point adder 232n is provided at the end of the tree. The mixed-sign adder 232n receives a partial summation result from the end output of the same array of signed floating-point adders at one of its inputs. At its other input, the mixed-sign adder receives the output of the mixed-sign adder in the previous layer.

[0109] Control signals for controlling the cyclic shift at each layer 212a, 212b of the multiplexer can be generated by counting the number of positive (or negative) numbers in the input set. Therefore, the multiplexing logic can include a counting block 216 configured to count positive (or negative) numbers. The count output provides control bits, thus allowing control bits to be generated early in the computation before reaching the lower layers of the tree. The least significant bit of the count controls the multiplexer at the first layer 212a of the rotation multiplexer. The second least significant bit controls the multiplexer at the second layer 212b, and so on. In this way, the rotation multiplexers 212a, b, ... ensure that at most one mixed-symbol computation is performed at each layer, and is performed by a mixed-symbol floating-point adder on the right side of the tree at that layer.

[0110] As mentioned above, Figure 4 The architecture includes a mixed-sign floating-point adder at each level. This is slightly more expensive. This can be avoided by eliminating the mixed-sign floating-point adders from all levels except the last one, and instead simply passing the mixed-sign numbers to the next level until the last level, where a single mixed-sign floating-point adder 232n is provided. In this case, to avoid increasing the number of mixed-sign numbers at each level, it is preferable to add multiplexing logic to allow cyclic shifts that shift the numbers one bit to the left and one bit to the right at each level. By shifting appropriately to the left or right at each level, this ensures that at most two mixed-sign numbers exist, which are always on the right side of the tree at each level.

[0111] It has been found that implementing classification block 214 can be costly. In some cases, the cost of implementing classification block 214 (in terms of semiconductor area) can outweigh the benefit of reduced area occupied by the same sign floating-point adder 220a. If the inputs are known to be pre-classified for some reason (at least classified into positive and negative subsets), then classification block 214 is not necessary, which would reduce the cost of this implementation in terms of semiconductor area, power consumption, and latency. A classification-independent architecture is desired. Figure 5 One such architecture is shown.

[0112] Figure 5This is a block diagram of an adder circuit according to a fourth embodiment. In this embodiment, the adder circuit includes a first array 320 of floating-point adders with the same sign and a second array 325 of floating-point adders with the same sign. Multiplexing logic is provided in the form of blocks 317a-n and 318a-n. The circuit includes one block 317a-n and one block 318a-n for each input floating-point number. Each array 320, 325 has a number of inputs equal to the number of floating-point numbers in the input set (to be added together). Therefore, for each array, each input of the array corresponds to a corresponding floating-point number in the input set. Blocks 317a-n control the inputs to the first array 320, while blocks 318a-n control the inputs to the second array 325.

[0113] Each block 317 is configured to evaluate the sign bit of the corresponding floating-point number in the input set. If the sign bit is zero, block 317 passes the number to the corresponding input of the first array 320. If the sign bit is one, block 317 does not pass the number to the corresponding input of array 320. Figure 5 In the implementation scheme, when the sign bit is one, block 317 passes the floating-point number zero to the corresponding input of array 320. This means that the first array 320 receives all positive numbers in the input set and receives the floating-point value zero at the position corresponding to the negative numbers in the input set.

[0114] Each block 318 is configured to evaluate the sign bit of the corresponding floating-point number in the input set and perform the opposite operation of block 317. That is, if the sign bit is one, block 318 passes the number to the corresponding input of the second array 325. If the sign bit is zero, block 318 does not pass the number to the corresponding input of array 325. Instead, when the sign bit is zero, it passes the floating-point number zero to the corresponding input of array 325. In this way, the second array 325 receives all negative numbers in the input set and receives the floating-point value zero in the position corresponding to the positive numbers in the input set.

[0115] The first array 320 comprises a logarithmic tree of floating-point adders of the same sign. Since all inputs are positive or zero, no additional multiplexing logic is required within this tree. Similarly, the second array 325 comprises a second logarithmic tree of floating-point adders of the same sign, without additional multiplexing logic because all inputs are negative or zero. The adder circuitry also includes a floating-point subtractor 332. One input of subtractor 332 is coupled to the output of the final floating-point adder of the same sign in the first array 320. The other input of subtractor 332 is coupled to the output of the final floating-point adder of the same sign in the second array 325. Therefore, subtractor 332 is configured to combine the partial summation result produced by the first array with the partial summation result produced by the second array. In particular, subtractor 332 is configured to subtract the absolute value of the sum of negative numbers from the sum of positive numbers. Subtractor 332 can be implemented as a mixed-sign floating-point adder, where adding a positive and a negative number corresponds to subtracting the absolute value of the negative number from the positive number. Alternatively, since subtractor 332 is always guaranteed to have one positive (or zero) input and one negative (or zero) input, it can be optimized for this purpose.

[0116] Note that (for input sets of the same size) and Figure 4 Compared to the adder circuit, Figure 5 The adder circuit requires a larger number of floating-point adders with the same sign. However, surprisingly, it has been found that by eliminating... Figure 4 The area saved by the 214-classification block can exceed Figure 5 The additional area required for the two arrays 320 and 325 in the diagram. Figure 5 Further optimization of the architecture is also possible. For example, for any given set of inputs, some of the adders in each array 320, 325 may have one zero input, and some adders may have zero at both inputs. Providing bypass circuitry to handle these cases to reduce power consumption can be beneficial. By detecting zero inputs and supplying zero outputs by bypassing floating-point adders of the same sign, addition of 0+0=0 can be avoided. Similarly, by detecting zero inputs and supplying the output of X by bypassing floating-point adders of the same sign, addition of X+0=X can be avoided. Of course, this optimization saves energy but not semiconductor area, because it still needs to be implemented for the case where the inputs of the adders in each array are non-zero.

[0117] exist Figure 5 In this case, both arrays are the same size. Figure 5 In variations of the implementation, one array may be larger than the other. One such example includes a first array whose size is... Figure 5The first array has the same size as the second array; and the second array is half that size. That is, the first array has N inputs, while the second array has N / 2 inputs (rounded to the next integer if N is odd). This is based on the observation that in any set of (2n-1) or (2n) numbers, there must exist at least n numbers with the same sign. In this variant, not all positive numbers are provided to the first array (e.g., ...). Figure 5 Instead of providing a single input array (as shown), the larger subset is provided to the first array, and the smaller subset to the second array. For the first array, the worst-case scenario is that all numbers have the same sign (either all positive or all negative). In other words, in the worst case, the larger set contains the complete set of input numbers. This means the first array needs to be of "full" size with N inputs. The worst-case scenario for the second array is that the smaller set contains half the numbers of the input set. Therefore, the second array needs N / 2 inputs. In this variant, some additional logic is needed to identify which subset of numbers is the larger set and which is the smaller set; that is, to identify whether the number of positive numbers is greater than the number of negative numbers, and vice versa. The cost of this additional logic can be weighed against the area savings achieved by halving the size of the second array.

[0118] because Figure 5 The similarity between the two arrays 320 and 325 in the architecture suggests another way to balance area and speed. Figure 5 In an alternative implementation, the first and second arrays can be provided by a single array. The multiplexing logic is then configured to pass floating-point numbers with a sign bit of 0 to that single array in a first time interval (e.g., a first clock cycle) and floating-point numbers with a sign bit of 1 to that single array in a second time interval (e.g., a subsequent clock cycle). The output of the array in the first interval (clock cycle) can be stored in a register so that the result generated in the second interval (clock cycle) can be subtracted from it later. (Naturally, the first and second time intervals do not have to be in this order—positive or negative numbers in the input set can be processed first.)

[0119] In such Figure 4 and Figure 5In the example shown, using one or more arrays or trees, it is not necessary to propagate the computation throughout the entire array or tree in a single clock cycle. Instead, it may be beneficial to implement each array or tree as a pipeline, where the results generated by a given layer (or set of layers) in one clock cycle are stored in registers at the end of that clock cycle. In the next clock cycle, these results are read from the registers into the input of the next layer (or set of layers) in the array. In this way, one computation follows another throughout the array, and even if the array requires several clock cycles to perform the entire computation, it can still produce output values ​​in each clock cycle.

[0120] The concept of pipelines can also be applied to the discussions above. Figure 5 An alternative implementation, in which the first and second arrays are provided by a single physical array. For example, a single pipelined array can be configured with positive and negative numbers respectively in alternating clock cycles. The computation propagates through the single array in subsequent clock cycles until it reaches the end of the array. The subtractors at the end of the array are controlled to recombine positive and negative sums from the same input set (depending on whether the positive or negative numbers in the input set enter the pipeline first). Thus, Figure 5 The pipelined implementation of a single array can produce one output value every two clock cycles.

[0121] In the example above, it is assumed that each identically signed floating-point adder is capable of adding two inputs with the same sign together to produce a single output. However, this is not necessary. It is also possible to design an identically signed floating-point adder that adds a large number of inputs together in an integrated manner. Figure 6 An adder circuit 400 is shown built around a floating-point adder 420 of the same sign, which takes three floating-point inputs of the same sign and adds them together to produce a single output. Figure 6 In this context, it serves as the basis for a 5:3 reducer, which sums the five floating-point inputs and outputs three floating-point outputs. This is similar to... Figure 1 The 3:2 reducer operates. Of the five floating-point inputs, multiplexing logic 410 selects three inputs with the same sign. (There will always be at least three.) These three inputs are added together by a 3:1 same-sign floating-point adder 420. The remaining two inputs are passed to the reducer's output (adder circuit 400).

[0122] The three numbers provided at the output of the reducer (adder circuit 400) can then be added together—for example, using... Figure 2 The adder circuit 130 shown provides a five-input adder. This step is not required.

[0123] The basic concepts of 3:2 and 5:3 reducers can be summarized as (2n-1):n reducers, because in any set of 2n-1 numbers, there must be at least n numbers with the same sign. However, this is a trade-off, as the reuse logic becomes more complex (and takes up more space) as the number n increases.

[0124] As described above, adder circuits according to the examples, such as the adder circuits described above, can be combined to form a composite adder circuit. Figure 7 An embodiment of such a composite adder circuit is shown. It includes a 6:4 reducer adder circuit 500; as... Figure 1 The 3:2 reducer adder circuit 100 shown; and as shown in the figure Figure 2 The adder circuit 130 shown is similar to the 6:4 reducer adder circuit 500. Figure 6 The circuit 400 is a 5:3 adder. It is built around the same 3:1 same-sign floating-point adder 420, but multiplexed logic 510 takes six inputs; three of them with the same sign are passed to adder 420; and the remaining three are passed to the output. The remaining three inputs passed to the output of circuit 500 are fed into multiplexed logic 110 of circuit 100. This identifies two of them with the same sign and feeds them into same-sign floating-point adder 120. Note that multiplexed logic blocks 510 and 110 can be implemented with a relatively simple and fast arrangement of logic gates. Therefore, in practice, when adder 420 begins its calculation, adder 120 can, for example, begin its calculation simultaneously with or shortly thereafter within the same clock cycle. This can be advantageous for the overall latency of the circuit and is therefore likely better than other methods that connect the inputs and outputs of various component circuits together. In particular, this may be preferred when designing pipeline implementations, as the goal in this case is typically to maximize the amount of computational work that can be completed at each stage of the pipeline per clock cycle. However, this connectivity configuration is not essential in all implementations.

[0125] It should be noted that the 6:4 reducer adder circuit 500 is not an example of the general principle of (2n-1):n mentioned above. However, it belongs to a closely related general category of reducers, where (2n-1+m) inputs are reduced to (n+m) outputs by constructing a (2n-1):n reducer and passing an additional m inputs to the output.

[0126] Any of the circuits described above can be combined in mixed configurations. For example, a partial array can be constructed that has fewer layers than the entire array and multiple outputs. The outputs of the partial array can be used as inputs to provide circuits similar to... Figure 7Composite circuits. Similarly, similar to... Figure 6 or Figure 7 Many circuits, in which the outputs of these circuits are fed as inputs to a circuit similar to... Figure 4 or Figure 5 Array.

[0127] For completeness, the design of a same-sign floating-point adder will now be discussed to show how the method can be simplified to be more efficient in terms of silicon area, power consumption, and latency compared to a mixed-sign floating-point adder. The algorithm implemented by the same-sign floating-point adder is as follows. To compute Y, the sum of two floating-point numbers A and B has the same sign:

[0128] ●Identifier A', the larger number. A' = max(A, B)

[0129] ● Identify B', the smaller number. B' = min (A, B)

[0130] ● Align the mantissa of B' with the mantissa of A'. This can be done by shifting the mantissa of B' to the right by a number of bits equal to the difference between the exponents of A and B.

[0131] ● The phases of the two mantissas (e.g., aligned) are added to produce Y', thereby including an additional carry bit c on the left. It should be understood that the carry bit c is either 0 or 1. Importantly, this carry alone encodes the magnitude change of the output value Y with respect to the larger input value A'.

[0132] ● If the carry bit c=1, then set the mantissa of Y to Y'[M:1]]; if there is no carry (carry bit c=0), then set the mantissa of Y to Y'[M-1:0], where M is the number of mantissas to be included in the result Y.

[0133] ● Set the exponent of Y to be equal to the exponent of A' plus c.

[0134] ● Set the sign bit of Y to be equal to the sign bit of A (and in any case, the same as the sign bit of B).

[0135] Assume an adder that truncates the addition result (i.e., always rounds to zero). If you expect the result to be rounded to the nearest floating-point number, some additional logic is needed. Further logic can be added to handle exceptions (NaN, inf, underflow, overflow, etc.).

[0136] Compared to a mixed-sign floating-point adder, the algorithm described above eliminates several (potentially costly) operations. In a mixed-sign floating-point adder, first, a two's complement inversion is required to reverse the mantissa of the negative input. Second, the difference between the two numbers may be much smaller than either of the two numbers themselves. This means that the magnitude of the result may be very different from the magnitude of the input numbers (unlike an identically signed adder where the exponent of the result is known to be equal to the exponent of the larger of the two input numbers or one larger). For a mixed-sign floating-point adder, a leading zero count is required for Y' to determine the exponent of Y. Third, Y' needs to be left-shifted by an amount equal to the number of leading zero counts (a variable number of bits unknown beforehand) to produce the mantissa of Y. By eliminating these operations, an identically signed floating-point adder can be significantly simpler than a mixed-sign floating-point adder (e.g., significantly smaller in area). For an exemplary implementation, based on 32-bit floating-point numbers and a 1ns clock cycle, the inventors have found that, in terms of on-chip area, an identically signed floating-point adder can be about one-third the size of a mixed-sign floating-point adder.

[0137] An implementation can be useful in any situation where it is desired to add three or more floating-point numbers together. This need arises in many practical applications. For example, it is a crucial step in inner product calculation. The inner product (also known as the scalar product or dot product) of two numeric vectors is produced by multiplying corresponding elements in each vector in pairs and summing the results of these multiplications. Inner product calculation appears in applications including implementations in graphics and neural networks. For example, graphics processing systems used to render 3D scenes can often perform the addition of three numbers (e.g., as part of the dot product between three-dimensional vectors), so adder circuitry can be included in graphics processing systems configured in fixed-function circuitry specifically for (e.g., using...) Figure 2 The adder circuit 130 shown adds three numbers together. Similarly, a neural network accelerator can be configured to perform the addition of large sets of numbers (e.g., 64, 128, or 256 numbers), for example, as part of a large weighted sum, and therefore, an adder circuit can be included in a neural network accelerator configured in a fixed-function circuit specifically designed to add a particular number of numbers (e.g., 64, 128, or 256 numbers) together, for example using... Figure 5 The adder circuit shown is similar to Figure 7 The composite adder circuit shown is illustrated. Therefore, the implementation can find specific utility in processing systems such as graphics processing systems or artificial intelligence accelerator systems (e.g., including neural network accelerators).

[0138] Figure 8A computer system in which such a graphics processing system can be implemented is shown. The computer system includes a CPU 902, a GPU 904, a memory 906, and other devices 914, such as a display 916, a speaker 918, and a camera 919. A processing block 910 (corresponding to one of the adder circuits 100, 130, 400, and 500 described above) is implemented on the GPU 904. The components of the computer system can communicate with each other via a communication bus 920.

[0139] Although Figure 8 An implementation of the graphics processing system is shown, but it should be understood that a similar block diagram can be drawn for an artificial intelligence accelerator system—for example, by replacing the GPU 904 with a neural network accelerator (NNA), thereby implementing the processing block 910 in the NNA.

[0140] Figure 1 , Figure 2 and Figure 4 to Figure 7 The adder circuit is shown as comprising a number of functional blocks. This is merely illustrative and is not intended to define a strict division between the different logic elements of such an entity. Each functional block may be provided in any suitable manner. It should be understood that the intermediate values ​​described herein as being formed by the adder circuit do not need to be physically generated by the adder circuit at any point in time, and may only represent logical values ​​that conveniently describe the processing performed by the adder circuit between its inputs and outputs.

[0141] The adder circuit described herein is implemented in hardware on an integrated circuit. The adder circuit described herein can be configured to perform any of the methods described herein. Examples of computer-readable storage media include random access memory (RAM), read-only memory (ROM), optical disk, flash memory, hard disk storage, and other memory devices that can use magnetic, optical, and other techniques to store instructions or other data and can be accessed by a machine.

[0142] As used herein, the terms computer program code and computer-readable instructions refer to any kind of executable code for a processor, comprising code expressed in machine language, interpreted language, or scripting language. Executable code includes binary code, machine code, bytecode, code defining integrated circuits (e.g., hardware description languages ​​or netlists), and code expressed in programming languages ​​such as C, Java, or OpenCL. Executable code can be, for example, any kind of software, firmware, script, module, or library that, when properly executed, processed, interpreted, compiled, or run in a virtual machine or other software environment, causes the processor of a computer system that supports the executable code to perform tasks specified by said code.

[0143] A processor, computer, or computer system can be any kind of device, machine, or special-purpose circuit, or a collection or part thereof, that has the processing power to execute instructions. A processor can be any kind of general-purpose or special-purpose processor, such as a CPU, GPU, NNA, system-on-a-chip, state machine, media processor, application-specific integrated circuit (ASIC), etc. A computer or computer system may include one or more processors.

[0144] The term "computer-readable description of a circuit" is intended to encompass software, such as HDL (Hardware Description Language) software, that defines hardware configurations as described herein for designing integrated circuits or configuring programmable chips to perform desired functions. That is, a computer-readable storage medium may be provided on which computer-readable program code in the form of an integrated circuit definition dataset is encoded, which, when processed (i.e., executed) in an integrated circuit manufacturing system, configures the system to manufacture adder circuits configured to perform any of the methods described herein, or to manufacture adder circuits including any of the devices described herein. The integrated circuit definition dataset may, for example, be an integrated circuit description.

[0145] Therefore, a method for manufacturing an adder circuit as described herein can be provided at an integrated circuit manufacturing system. Furthermore, an integrated circuit definition dataset can be provided, which, when processed in the integrated circuit manufacturing system, enables the method for manufacturing the adder circuit to be executed.

[0146] Integrated circuit definition datasets can be in the form of computer code, such as netlists, code for configuring programmable chips, or hardware description languages ​​suitable for manufacturing at any level in integrated circuits, including register-transfer level (RTL) code, high-level circuit representations (such as Verilog or VHDL), and low-level circuit representations (such as OASIS (RTM) and GDSII). Higher-level representations (such as RTL) that logically define hardware suitable for manufacturing in integrated circuits can be processed on a computer system configured to generate manufacturing definitions of integrated circuits within the context of a software environment that includes definitions of circuit elements and rules for combining these elements to generate the manufacturing definition of the integrated circuit defined by that representation. As is typically the case where software executes at a computer system to define a machine, one or more intermediate user steps (e.g., providing commands, variables, etc.) may be required to configure the computer system to generate the manufacturing definition of the integrated circuit, executing code that defines the integrated circuit in order to generate the manufacturing definition of the integrated circuit.

[0147] The following is about Figure 9This describes an example of processing integrated circuit definition datasets at an integrated circuit manufacturing system in order to configure the system for manufacturing adder circuits.

[0148] Figure 9 An example of an integrated circuit (IC) manufacturing system 1002 configured to manufacture adder circuits as described in any of the examples herein is shown. Specifically, the IC manufacturing system 1002 includes a layout processing system 1004 and an integrated circuit generation system 1006. The IC manufacturing system 1002 is configured to receive an IC definition dataset (e.g., defining adder circuits as described in any of the examples herein), process the IC definition dataset, and generate an IC (e.g., embodying adder circuits as described in any of the examples herein) based on the IC definition dataset. The processing of the IC definition dataset configures the IC manufacturing system 1002 to manufacture integrated circuits embodying adder circuits as described in any of the examples herein.

[0149] The layout processing system 1004 is configured to receive and process an IC definition dataset to determine a circuit layout. Methods for determining a circuit layout based on an IC definition dataset are known in the art and may involve, for example, synthesizing RTL code to determine the gate-level representation of the circuit to be generated, for example, in relation to logic components (e.g., NAND, NOR, AND, OR, MUX, and FLIP-FLOP components). By determining the location information of the logic components, the circuit layout can be determined based on the gate-level representation of the circuit. This can be done automatically or with user intervention to optimize the circuit layout. When the layout processing system 1004 has determined the circuit layout, it can output the circuit layout definition to the IC generation system 1006. The circuit layout definition may be, for example, a circuit layout description.

[0150] As is known in the art, IC generation system 1006 generates ICs according to a circuit layout definition. For example, IC generation system 1006 can implement a semiconductor device manufacturing process for generating ICs, which may involve a multi-step sequence of photolithography and chemical processing steps, during which electronic circuits are gradually formed on a wafer made of semiconductor material. The circuit layout definition may be in the form of a mask, which can be used in the photolithography process to generate ICs according to the circuit definition. Alternatively, the circuit layout definition provided to IC generation system 1006 may be in the form of computer-readable code, which IC generation system 1006 can use to form a suitable mask for generating ICs.

[0151] The various processes performed by the IC manufacturing system 1002 can all be implemented in one location, for example, by one party. Alternatively, the IC manufacturing system 1002 can be a distributed system, allowing some processes to be performed in different locations and by different parties. For example, some of the following stages can be performed in different locations and / or by different parties: (i) synthesizing RTL code representing an IC definition dataset to form a gate-level representation of the circuit to be generated; (ii) generating a circuit layout based on the gate-level representation; (iii) forming a mask based on the circuit layout; and (iv) using the mask to manufacture the integrated circuit.

[0152] In other examples, the processing of the integrated circuit definition dataset at the integrated circuit manufacturing system can configure the system to manufacture adder circuits in which the IC definition dataset is not processed in order to determine the circuit layout.

[0153] In some implementations, when processed in an integrated circuit manufacturing system, the integrated circuit definition dataset can enable the integrated circuit manufacturing system to generate devices as described herein. For example, the integrated circuit definition dataset, as described above... Figure 9 The described method configures an integrated circuit manufacturing system to produce devices as described herein.

[0154] In some examples, an integrated circuit definition dataset can contain software running on hardware defined at the dataset, or software running in combination with hardware defined at the dataset. Figure 9 In the example shown, the IC generation system can be further configured by the integrated circuit definition dataset to load firmware onto the integrated circuit according to the program code defined at the integrated circuit definition dataset during the manufacturing of the integrated circuit, or otherwise provide the integrated circuit with program code for use with the integrated circuit.

[0155] Figure 10 An example of a computer-implemented method for processing a computer-readable description of an integrated circuit to generate a representation of the integrated circuit is shown. This method can be performed by a synthesis tool that synthesizes RTL code to determine a gate-level representation of the circuit to be generated, for example, in terms of logic components (e.g., NAND, NOR, AND, OR, MUX, and FLIP-FLOP components). During this synthesis process, the synthesis tool can optimize the circuit by implementing the floating-point sum using one of the above-described adder circuits, or by using a circuit similar to that described below to implement the floating-point sum and floating-point difference, referencing... Figure 11 and Figure 12In step 702, the synthesis tool receives a computer-readable description of the integrated circuit. This computer-readable description may include RTL code. In step 704, the synthesis tool identifies in the RTL code a description of one or more functional blocks used for summing three (or more) floating-point numbers, or for calculating the sum of two floating-point numbers and the difference between the two floating-point numbers. In step 706, the synthesis tool generates a representation of the integrated circuit. The synthesis tool optimizes the representation by representing the identified functional blocks as circuits as described herein. The synthesis tool may select which type of circuit to use based on factors such as the number of inputs and outputs of the identified functional blocks and / or design parameters to be prioritized (e.g., speed or area). The generated integrated circuit representation may include a netlist—that is, a gate-level representation. This gate-level representation may be further processed in subsequent steps to generate a circuit layout.

[0156] Figure 11 The diagram shows a circuit configured to calculate the sum and difference of two floating-point numbers A and B. That is, Figure 11 The circuit is configured to calculate A+B and AB. Regardless of the signs of A and B, one of these calculations can be performed by a floating-point adder of the same sign, as described above. Other calculations require a subtractor or a mixed-sign floating-point adder. Figure 11In the example, the circuit includes: a floating-point adder 1020; a floating-point subtractor 1032; and multiplexing and sign correction logic 1010. Each of the adder 1020 and subtractor 1032 is implemented in a fixed-function circuit. Each of the adder 1020 and subtractor 1032 has two inputs. Numbers A and B are provided to the corresponding inputs of the adder 1020 and subtractor 1032. The same-sign floating-point adder 1020 is configured to calculate the sum of the absolute values ​​of the two numbers (|A| + |B|) to produce a first result. For example, this can be achieved by forcing the sign bits of the two numbers to zero (indicating positive numbers) and then adding the resulting two positive numbers together. In an alternative example, the same-sign floating-point adder 1020 may ignore the sign bits of the two numbers, or it may force the sign bits of the two numbers to one (indicating negative numbers) and then add the resulting two numbers together. Subtractor 1032 is configured to calculate the difference of the absolute values ​​of two floating-point numbers (|A| - |B|) to produce a second result. For example, it can do this by forcing the sign bit of A to zero (indicating a positive number) and forcing the sign bit of B to one (indicating a negative number). In an alternative example, subtractor 1032 can forcibly set the sign bit of A to one (indicating a negative number) and forcibly set the sign bit of B to zero (indicating a positive number). The outputs of the same-sign floating-point adder 1020 and subtractor 1032 are provided as inputs to multiplexing and sign correction logic 1010. Multiplexing and sign correction logic 1010 is configured to generate the sum (A + B) and the difference (AB) of the two floating-point numbers based on: the first result, the second result, and the sign of each floating-point number A and B.

[0157] Figure 12 It shows that it can be made by Figure 11The circuit executes the following method. In step 804, the circuit receives floating-point numbers A and B. In step 806, a floating-point adder 1020 with the same sign calculates the sum of the absolute values ​​of A and B, thereby producing a first result. In step 808, a subtractor 1032 calculates the difference between the absolute values ​​of A and B, thereby producing a second result. In step 810, multiplexing and sign correction logic 1010 corrects the sign of the first result and the sign of the second result based on the sign of each of the two floating-point numbers A and B. In this context, “correcting” the sign of the first and second results means that the multiplexing and sign correction logic 1010 ensures that the sign of the sum / difference is correctly set based on the sign of each of the two floating-point numbers. In other words, the sign correction logic determines the sign of the sum / difference based on the sign of each of the two floating-point numbers. Depending on the sign of the floating-point numbers, the correct sign of the sum (A+B) or difference (AB) may be the same as or different from the sign of the first result or the second result. Therefore, in some cases, the sign of the first / second result can be changed by the multiplexing and sign correction logic 1010; simultaneously, in other cases, the sign of the first / second result is already correct without being changed. This is described in further detail below. In step 812, the multiplexing and sign correction logic 1010 selects one of the (sign-corrected) first result and the (sign-corrected) second result to generate the sum of the two floating-point numbers (A+B). In the same step, the multiplexing and sign correction logic 1010 selects the other (sign-corrected) result to generate the difference of the two floating-point numbers (AB). Finally, in step 814, the sum and difference are output from the circuit.

[0158] The following is a truth table of operations performed by the multiplexing and sign correction logic 1010 according to an example of the present invention. In this table, Sa represents the sign bit of the first number A, and Sb represents the sign bit of the second number. The two columns on the right indicate which result is selected to produce the relevant output of the circuit, and how sign correction is performed.

[0159]

[0160] For example, referring to the third row of the reference table, when A is negative and B is positive, the sum of the two floating-point numbers A+B is given by -(|A|-|B|); therefore, the multiplexing and sign correction logic 1010 selects the second result (|A|-|B|) and changes the sign bit (changing it to zero if it is one, and to one if it is zero). Meanwhile, the difference between the two numbers AB is given by -(|A|+|B|); therefore, the multiplexing and sign correction logic 1010 selects the first result (|A|+|B|) and changes the sign bit. This changes the sign bit to one (because the first result is always positive, thus making the sign bit equal to zero).

[0161] The subtractor 1032 can be implemented as a mixed-sign floating-point adder because it is capable of subtracting floating-point numbers. Alternatively, the subtractor can be simplified because it is known in advance that the first input A of the subtractor will always force its sign bit to zero, and the second input B of the subtractor will always force its sign bit to one. (The two's complement inversion will always be performed on the second input B, and never on the first input A.)

[0162] In the example above, refer to Figure 12 Before selecting an output in step 812, the signs of the first and second results are corrected in step 810. However, as those skilled in the art will understand, selection and sign correction can be performed in the same reverse order.

[0163] Compared to known implementations, the implementation of the concepts set forth in this application in devices, apparatuses, modules, and / or systems (and the methods implemented herein) can result in performance improvements. Performance improvements may include one or more of increased computational performance, reduced latency, increased throughput, and / or reduced power consumption. During the manufacture of such devices, apparatuses, modules, and systems (e.g., in integrated circuits), trade-offs can be made between performance improvements and physical implementations, thereby improving manufacturing methods. For example, a trade-off can be made between performance improvements and layout area, thereby matching the performance of known implementations but using less silicon. This can be accomplished, for example, by reusing functional blocks in a serial manner or sharing functional blocks among elements of a device, apparatus, module, and / or system. Conversely, the concepts set forth in this application that result in improvements to the physical implementations of devices, apparatuses, modules, and systems (e.g., reduced silicon area) can be traded off for performance improvements. This can be accomplished, for example, by manufacturing multiple instances of modules within a predefined area budget.

[0164] The applicant has independently disclosed each individual feature described herein, as well as any combination of two or more such features, to the extent that such features or combinations can be implemented based on the specification as a whole, in accordance with the common knowledge of those skilled in the art, regardless of whether such features or combinations of features solve any problem disclosed herein. In view of the foregoing description, those skilled in the art will understand that various modifications can be made within the scope of this invention.

Claims

1. A machine-implemented method for processing an input set, the input set comprising two floating-point numbers (A, B), each floating-point number having a sign, to generate a sum (A+B) of the two floating-point numbers and a difference (AB) of the two floating-point numbers, the method comprising: Receive the two floating-point numbers from the input set (804); The sum of the absolute values ​​of the two floating-point numbers (806) is calculated using a floating-point adder with the same sign (1020) to produce a first result; The floating-point subtractor (1032) is used to calculate (808) the difference between the absolute values ​​of the two floating-point numbers to produce a second result; as well as Generate (810, 812) the sum (A+B) and the difference (AB) of the two floating-point numbers based on the following: the first result, the second result, and the sign of each floating-point number. The same-sign floating-point adder (1020) is implemented in a fixed-function circuit configured to add floating-point numbers with the same sign, and the same-sign floating-point adder does not include circuitry configured to add numbers with different signs. The generation of the sum (A+B) and difference (AB) of the two floating-point numbers includes correcting (810) the sign of the first result and the sign of the second result. If the first floating-point number (A) of the two floating-point numbers is positive, then the sign of the first result remains unchanged, and the sign of the second result remains unchanged as well. If the first floating-point number (A) of the two floating-point numbers is negative, the sign of the first result is set to represent a negative number, and the sign of the second result is changed.

2. The method of claim 1, wherein generating the sum (A+B) and the difference (AB) of the two floating-point numbers comprises: Generate (812) the sum of the two floating-point numbers (A+B) from one of the first result and the second result; as well as (812) The difference (AB) between the two floating-point numbers is generated from the other of the first result and the second result.

3. A circuit configured to process an input set comprising two floating-point numbers (A, B), each floating-point number having a sign, to generate a sum (A+B) and a difference (AB) between the two floating-point numbers, the circuit comprising: Input, the input being configured to receive (804) the two floating-point numbers of the input set; A floating-point adder with the same sign (1020), the floating-point adder with the same sign is configured to calculate (806) the sum of the absolute values ​​of the two floating-point numbers to produce a first result; A floating-point subtractor (1032) is configured to calculate (808) the difference between the absolute values ​​of the two floating-point numbers to produce a second result; as well as Multiplexing and sign correction logic (1010) is configured to generate the sum (A+B) and the difference (AB) of the two floating-point numbers based on: the first result, the second result, and the sign of each floating-point number (A, B). The same-sign floating-point adders are implemented in fixed-function circuitry configured to add floating-point numbers with the same sign, and the same-sign floating-point adders do not include circuitry configured to add numbers with different signs. The multiplexing and symbol correction logic (1010) is configured to correct the symbol of the first result and the symbol of the second result. If the first floating-point number (A) of the two floating-point numbers is positive, then the sign of the first result remains unchanged, and the sign of the second result remains unchanged as well. If the first floating-point number (A) of the two floating-point numbers is negative, the sign of the first result is set to represent a negative number, and the sign of the second result is changed.

4. The method of claim 1 or the circuit of claim 3, wherein the floating-point subtractor (1032) is implemented in a fixed-function circuit.

5. The method of claim 1 or 4, or the circuit of claim 3 or 4, wherein the floating-point subtractor (1032) is implemented by a mixed-sign floating-point adder.

6. The circuit of any one of claims 3 to 5, wherein the multiplexing and symbol correction logic (1010) is configured as follows: Generate the sum of the two floating-point numbers (A+B) from one of the first and second results; and The difference (AB) between the two floating-point numbers is generated from the other of the first and second results.

7. A processing system comprising the circuitry claimed in any one of claims 3 to 6.

8. A processing system configured to perform the method as claimed in claim 1, 2, 4 or 5.

9. The processing system of claim 7 or 8, wherein the processing system is a graphics processing system or an artificial intelligence accelerator system.

10. A method for manufacturing a circuit as described in any one of claims 3 to 6 or a processing system as described in any one of claims 7 to 9 using an integrated circuit manufacturing system, the method comprising: A layout processing system is used to process a computer-readable description of the circuit or processing system to generate a circuit layout description of an integrated circuit embodying the circuit or processing system. as well as The circuit or processing system is manufactured using an integrated circuit manufacturing system, based on the circuit layout description.

11. A non-transitory computer-readable storage medium storing a computer-readable description of a circuit or processing system as described in any one of claims 3 to 9, which, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to perform the following operations: The computer-readable description is processed using a layout processing system to generate a circuit layout description of an integrated circuit embodying the circuit or processing system; and The circuit or processing system is manufactured using an integrated circuit manufacturing system, based on the circuit layout description.

12. A computer-implemented method for processing a computer-readable description of an integrated circuit to generate a representation of the integrated circuit, the method comprising: Receive the computer-readable description of the integrated circuit; In the computer-readable description of the integrated circuit, a description identifies one or more functional blocks for calculating the sum of two floating-point numbers and the difference between the two floating-point numbers; and Generate the representation of the integrated circuit, wherein one or more functional blocks are represented in the representation of the integrated circuit as a representation of a circuit according to any one of claims 3 to 6.

13. A non-transitory computer-readable storage medium storing computer program code on the non-transitory computer-readable storage medium, the computer program code being configured to cause the one or more processors to perform the method of claim 12 when the code is run on the one or more processors.

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