Non-volatile memory device and programming method thereof

Abstract

A programming method of a non-volatile memory device is disclosed. The non-volatile memory device includes cell strings having memory cells stacked perpendicular to a surface of a substrate. The method includes: performing a first programming stage including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line; and performing a second programming stage including programming a second memory cell after completely programming the first memory cell. The second memory cell is connected to a second word line closer to the substrate than the first word line. A second pass voltage is applied to a first group of word lines below the second word line and a third pass voltage is applied to a second group of word lines above the second word line. The second pass voltage is lower than the third pass voltage.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0086948, filed with the Korean Intellectual Property Office on July 18, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Some example embodiments disclosed herein relate to semiconductor memory devices, and more particularly, to non - volatile memory devices and programming methods thereof. Background Art

[0004] Semiconductor memory devices are classified into volatile semiconductor memory devices and non - volatile semiconductor memory devices. Volatile semiconductor memory devices have fast read and write speeds, but when power is cut off from a volatile semiconductor memory device, the volatile semiconductor memory device loses the data stored therein. In contrast, a non - volatile semiconductor memory device retains the data stored therein even when power is cut off from the non - volatile semiconductor memory device. For this reason, non - volatile semiconductor memory devices are used to store information that is desired to be retained regardless of whether power is supplied to them.

[0005] Flash memory devices can be examples of non - volatile semiconductor memory devices. Flash memory devices are used to store voice and image data of information devices. Examples of such information devices include one or more of the following: computers, cellular phones, smart phones, personal digital assistants (PDAs), handheld personal computers (PCs), game consoles, fax machines, scanners, and printers. Semiconductor memory devices having three - dimensional stacked memory cells are being developed to increase the integration degree of semiconductor memory devices.

[0006] Three - dimensional semiconductor memory devices can include cell strings implemented by stacking memory cells in a direction perpendicular to a substrate to increase the integration degree. However, it is necessary to maintain the reliability of three - dimensional semiconductor memory devices while increasing the integration degree. Specifically, due to an etching process, the size of the channel holes of the cell strings of three - dimensional semiconductor memory devices varies according to the position of the channel holes. Considering such geometric characteristics in three - dimensional semiconductor memory devices, it is desirable to develop a method for programming memory cells. Summary of the Invention

[0007] Some example embodiments provide a non - volatile memory device and a programming method thereof that perform a programming operation in consideration of the geometric structure of a cell string.

[0008] According to some example embodiments, a programming method of a non-volatile memory device is provided. The non-volatile memory device includes cell strings in which a plurality of memory cells are stacked in a direction perpendicular to the surface of a substrate. The method includes: performing a first programming phase including programming a first memory cell among the plurality of memory cells. The first memory cell is connected to a first word line among the plurality of word lines of the cell string. The first programming phase includes: applying a first pass voltage to other word lines above or below the first word line among the plurality of word lines; and performing a second programming phase including programming a second memory cell among the plurality of memory cells after the first memory cell is fully programmed. The second memory cell is connected to a second word line closer to the substrate than the first word line among the plurality of word lines. The second programming phase includes: applying a second pass voltage to a first group of word lines below the second word line among the plurality of word lines and applying a third pass voltage to a second group of word lines above the second word line among the plurality of word lines, and the second pass voltage is lower than the third pass voltage.

[0009] According to some example embodiments, a programming method of a non-volatile memory device is provided. The non-volatile memory device includes cell strings in which a plurality of memory cells are stacked in a direction perpendicular to the surface of a substrate. The method includes: performing a programming verification phase including applying a verification voltage to a selected word line among the plurality of word lines of the cell string and applying a read pass voltage to a plurality of unselected word lines among the plurality of word lines to verify whether a selected memory cell among the plurality of memory cells is programmed, and programming the selected word line before a first word line closer to the substrate among the plurality of word lines or after a second word line farther from the substrate among the plurality of word lines; performing a first recovery phase including applying a first recovery voltage to the selected word line and the plurality of unselected word lines and applying a precharge voltage to a common source line of the cell string; and performing a second recovery phase including discharging at least one unselected word line among the plurality of unselected word lines to a ground voltage.

[0010] According to some example embodiments, a non-volatile memory device is provided, including: a memory cell array including cell strings in which a plurality of memory cells are stacked in a direction perpendicular to the surface of a substrate; an address decoder configured to select a word line among the plurality of word lines included in the cell string to program the plurality of memory cells; a page buffer configured to control bit lines of the cell string; and control logic circuitry configured to control the address decoder and the page buffer such that in a programming operation, a word line farthest from the substrate among the plurality of word lines is programmed first, and a recovery phase is performed after a programming verification operation. The recovery phase includes applying a recovery voltage to a selected word line among the plurality of word lines and unselected word lines among the plurality of word lines, and the recovery phase includes applying a precharge voltage to a common source line of the cell string. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features will become apparent by describing some example embodiments with reference to the accompanying drawings.

[0012] Figure 1 is a block diagram showing a non-volatile memory device according to some example embodiments.

[0013] Figure 2 is a diagram showing a memory block according to some example embodiments.

[0014] Figure 3A is a diagram showing Figure 2 the structure of a cell string in a memory block of.

[0015] Figure 3B is a diagram showing Figure 3A the structure of one memory cell of.

[0016] Figure 4 is a diagram showing memory cells included in a cell string and their programming order according to some example embodiments.

[0017] Figure 5 is a waveform diagram showing programming operations according to some example embodiments.

[0018] Figure 6 is a diagram showing how the word line voltage changes during a recovery operation according to some example embodiments.

[0019] Figure 7 briefly shows Figure 6 the channel initialization effect in the first recovery stage of.

[0020] Figure 8A and Figure 8B is a waveform diagram showing some example embodiments of a recovery operation.

[0021] Figures 9A to 9D is a waveform diagram showing some example embodiments of a recovery operation.

[0022] Figure 10 is a diagram showing a threshold voltage distribution associated with 3-bit memory cells to describe some example embodiments.

[0023] Figure 11A and Figure 11B is a diagram showing the characteristics of the voltage applied to a word line during a programming execution stage according to some example embodiments.

[0024] Figure 12A is a waveform diagram showing the word line voltage of a first pass condition applied to a word line above a reference word line during a programming operation.

[0025] Figure 12B It is a waveform diagram of the word line voltage showing the second pass condition applied to the word line located above the reference word line during a programming operation.

[0026] Figure 13 It is shown with reference Figure 12B It is a waveform diagram of the word line voltage showing the third pass condition applied when the driving temperature of the non-volatile memory device is lower than the reference temperature compared to the second pass condition described.

[0027] Figure 14 It is a flowchart showing a method of providing a pass voltage for each condition during the programming execution phase of some example embodiments.

[0028] Figure 15 It is a diagram showing another example of a cell array structure to which a programming method according to some example embodiments can be applied. Detailed Description

[0029] It should be understood that the foregoing general description and the following detailed description are provided as examples and should be considered as providing additional description. Reference numerals will be detailed in some example embodiments, and examples of the example embodiments are shown in the drawings. As much as possible, the same reference numerals are used in the drawings and the description to refer to the same or similar components.

[0030] Hereinafter, for ease of description, the names of word lines may be defined according to their positions. In a memory block or a cell string, the word line selected for a programming operation is referred to as the "selected word line". The remaining word lines other than the selected word line in the word lines are referred to as "unselected word lines". In addition, all or a part of the unselected word lines located above the selected word line with respect to the substrate among the unselected word lines is referred to as the "first word line group". The unselected word lines located below the selected word line with respect to the substrate among the unselected word lines are referred to as the "second word line group".

[0031] Figure 1 It is a block diagram showing a non-volatile memory device according to some example embodiments. Reference Figure 1, the non-volatile memory device 100 may include a memory cell array 110, an address decoder 120, a page buffer 130, an input / output (I / O) buffer 140, a control logic circuit 150, a voltage generator 160, and / or a temperature sensor 170. According to some example embodiments, the operations described herein as being performed by the non-volatile memory device 100, the address decoder 120, the page buffer 130 (e.g., operating as a write driver and / or a read amplifier), the control logic circuit 150, the voltage generator 160, and / or the temperature sensor 170 may be performed by a processing circuit. As used in the present disclosure, the term "processing circuit" may refer to, for example: hardware including logic circuits; a hardware / software combination such as a processor executing software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to: a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0032] The memory cell array 110 may be connected to the address decoder 120 through word lines WL, select lines SSL and GSL, and / or a common source line CSL. The memory cell array 110 may be connected to the page buffer 130 through bit lines BL. The memory cell array 110 may include a plurality of NAND cell strings. The channels of the NAND cell strings may be formed in a vertical direction. The word lines of the memory cell array 110 may be stacked in a direction perpendicular to the substrate.

[0033] In a programming operation, characteristic differences may occur between memory cells corresponding to the stacked word line layers. In order to stack memory cells in a vertical structure, channels may be formed by vertically penetrating the word lines using an etching process. For example, in the case where the aspect ratio of the pillar is not large, when an etching process is performed to form channels, the diameter of each channel hole may decrease as the depth of each channel hole increases. That is, as the etching process is performed, the size of the memory cells may vary for each layer. This may mean that the size of the tunneling insulation layer or the floating gate of each memory cell varies according to the channel depth.

[0034] Even if the same programming voltage or a similar programming voltage can be applied to the memory cells under the above conditions, different magnitudes of electric fields may be applied to the floating gates of the memory cells having different sizes. Under the same programming voltage condition or a similar programming voltage condition, a relatively larger electric field may be formed at the floating gate of the memory cell having a relatively smaller size. Therefore, the programming speed of the memory cell having a relatively smaller diameter may be relatively faster.

[0035] According to some example embodiments, to solve the problems caused by such geometric characteristics of the cell string, memory cells far from the substrate may be programmed first. However, in the case of programming the memory cells in this programming order, when programming the memory cells close to the substrate, the channel of the cell string may be separated and boosted. A potential difference in the boosted channel may occur, thereby causing hot electron injection. However, some example embodiments may provide a word line voltage application method for preventing such hot carrier injection (HCI) problems from occurring during a programming operation or reducing the occurrence of HCI problems.

[0036] The address decoder 120 may select one memory block among a plurality of memory blocks of the memory cell array 110 in response to the address ADD. The address decoder 120 may select one word line among the plurality of word lines of the selected memory block. The address decoder 120 may provide a word line voltage from the voltage generator 160 to the selected word line of the selected memory block. During a programming operation, the address decoder 120 may provide a programming / verification voltage Vpgm / Vfy to the selected word line and a pass voltage Vpass to the unselected word lines. When the position of the selected word line is closer to the substrate than a reference position, the address decoder 120 may change the level of the pass voltage Vpass. For example, the address decoder 120 may increase the level of the pass voltage Vpass to be provided to some word lines (e.g., a first word line group) located above the selected word line and may decrease the level of the pass voltage Vpass to be provided to some word lines (e.g., a second word line group) located below the selected word line.

[0037] The address decoder 120 may select word lines such that the memory cells close to the string select line SSL are programmed first during a programming operation. To satisfy this programming order, the starting position of the programming operation is not limited to the position of any one memory cell in the cell string (or the programming operation may start regardless of the position of the memory cells). In particular, in the case of programming the memory cells adjacent to the string select line SSL first, it may be impossible or difficult to initialize the channel by using the string select line SSL and the bit line. Therefore, the address decoder 120 may perform various channel initialization operations based on the above programming order. For example, the address decoder 120 may determine the time to apply a voltage to the string select line, the ground select line, and / or the common source line to perform a channel initialization operation corresponding to the programming order of the memory cells.

[0038] The page buffer 130 may operate as a write driver and / or a read amplifier according to an operation mode. In a programming operation, the page buffer 130 may provide a bit line voltage corresponding to data “DATA” to be programmed to the bit lines of the memory cell array 110. In a read operation, the page buffer 130 may sense data stored in the selected memory cells through the bit lines. The page buffer 130 may latch and output the sensed data “DATA”. The page buffer 130 may include a plurality of page buffers respectively connected to the bit lines. According to some example embodiments, when performing a programming and / or a read operation, for example, the input / output (I / O) buffer 140 may buffer data received outside the non-volatile memory device 100 and / or data to be transmitted (e.g., data from / to a host device).

[0039] The control logic circuit 150 may control the address decoder 120, the page buffer 130, and / or the voltage generator 160 in response to a command CMD and / or an address ADD from outside (e.g., from a host device). The control logic circuit 150 may control the address decoder 120, the page buffer 130, and / or the voltage generator 160 such that memory cells far from the substrate are programmed first in a programming operation.

[0040] The control logic circuit 150 may control the address decoder 120, the page buffer 130, and / or the voltage generator 160 to perform a recovery operation and a programming execution operation after a programming verification operation. The recovery operation (or, recovery phase) of some example embodiments includes a first recovery operation RCV1 (or a first recovery phase) and a second recovery operation RCV2 (or a second recovery phase). In the first recovery operation RCV1, a recovery voltage Vrcv may be applied to all word lines. In the second recovery operation RCV2 after the first recovery operation RCV1, the recovery voltage Vrcv may be provided to the selected word lines and some word lines adjacent to the selected word lines (e.g., a first word line group and a second word line group), and the remaining word lines may be discharged to a ground level. This will be described in detail with reference to the drawings to be described below. The control logic circuit 150 may control the address decoder 120, the page buffer 130, and / or the voltage generator 160 to perform this recovery operation.

[0041] The control logic circuit 150 may control the address decoder 120, the page buffer 130, and / or the voltage generator 160 such that a pass voltage according to some example embodiments is applied to the word lines in a programming execution operation. The control logic circuit 150 may reduce the level of the pass voltage to be provided to some word lines (e.g., a first word line group) located below the selected word line, and may increase the level of the pass voltage to be provided to some word lines (e.g., a second word line group) located above the selected word line.

[0042] Specifically, the control logic circuit 150 may refer to the temperature information Temp_Info provided by the temperature sensor 170 to allow the address decoder 120 to adjust (or regulate) the level of the pass voltage Vpass to be provided in a programming operation. The operation of the address decoder 120 may be performed such that the level of the pass voltage Vpass to be provided to some word lines located above the selected word line at a specific position (or height) is increased, and the level of the pass voltage Vpass to be provided to some word lines located below the selected word line is decreased. However, at a specific driving temperature or lower driving temperature, the control logic circuit 150 allows the address decoder 120 to additionally increase the level of the pass voltage Vpass to be provided to some word lines located above the selected word line. At a specific driving temperature or lower driving temperature, the control logic circuit 150 allows the address decoder 120 to additionally decrease the level of the pass voltage Vpass to be provided to some word lines located below the selected word line. According to some example embodiments, the specific driving temperature may be a design parameter determined through empirical research.

[0043] Under the control of the control logic circuit 150, the voltage generator 160 may generate various word line voltages to be provided to the word lines and / or voltages to be provided to the blocks (e.g., well regions) in which memory cells are formed. The word line voltages to be provided to the word lines may include a programming voltage Vpgm, a pass voltage Vpass, select and non-select read voltages VRD and Vread, etc. The voltage generator 160 may generate a select line voltage VSSL and a select line voltage VGSL to be provided to the select line SSL and the select line GSL in a read operation and a programming operation.

[0044] The temperature sensor 170 may provide the sensed temperature information Temp_Info of the non-volatile memory device 100 to the control logic circuit 150. The temperature sensor 170 may measure the internal temperature of the non-volatile memory device 100 and may generate the temperature information Temp_Info obtained by converting the measured temperature into numerical information. For example, the following sensors may be used as the temperature sensor 170: a thermoelectromotive force (or thermocouple) sensor using an electromotive force that changes according to temperature, a pyroelectric conductivity sensor that senses a resistance value that changes according to temperature, etc. However, the temperature measurement method of the temperature sensor 170 is not limited thereto. For example, it can be well understood that various methods may be applied to the temperature sensor 170.

[0045] Some non - volatile memory devices 100 of example embodiments include memory blocks in which cell strings are formed in a direction perpendicular to a substrate. The non - volatile memory device 100 may first program memory cells far from the substrate. Additionally, in this programming sequence, when programming memory cells located below a specific word line (or a reference word line), the pass voltage to be provided to at least one unselected word line located above the selected word line may be controlled to increase. When programming memory cells located below a specific word line, the pass voltage to be provided to at least one unselected word line located below the selected word line may be controlled to decrease.

[0046] Figure 2 is a diagram showing a memory block BLKa according to some example embodiments. According to some example embodiments, the memory block BLKa may be the same as or similar to the memory cell array 110. Refer to Figure 2 , a plurality of cell strings CS may be arranged in rows and columns on a substrate SUB. The cell strings CS may be commonly connected to a common source line CSL formed on (or in) the substrate SUB. In Figure 2 , an exemplary position of the substrate SUB is depicted to facilitate understanding of the structure of the memory block BLKa. In Figure 2 an example is shown in which the common source line CSL is connected to the lower end of the cell string CS. However, the common source line CSL may be electrically connected to the lower end of the cell string CS, and some example embodiments are not limited to the case where the common source line CSL is physically located at the lower end of the cell string CS. In some example embodiments, Figure 2 a 4×4 matrix of cell strings CS is shown. However, some example embodiments are not limited thereto.

[0047] Each row of cell strings CS may be connected to a corresponding one of a first ground selection line GSL1 to a fourth ground selection line GSL4 (e.g., the first ground selection line GSL1, the second ground selection line GSL2, the third ground selection line GSL3, and the fourth ground selection line GSL4) or a corresponding one of a first string selection line SSL1 to a fourth string selection line SSL4 (e.g., the first string selection line SSL1, the second string selection line SSL2, the third string selection line SSL3, and the fourth string selection line SSL4). However, the first ground selection line GSL1 to the fourth ground selection line GSL4 may be commonly connected to each other. Each column of cell strings CS may be connected to a corresponding one of a first bit line BL1 to a fourth bit line BL4 (e.g., the first bit line BL1, the second bit line BL2, the third bit line BL3, and the fourth bit line BL4). For ease of illustration, the cell strings CS connected to the second ground selection line GSL2 and the third ground selection line GSL3 or the second string selection line SSL2 and the third string selection line SSL3 are depicted as blurred.

[0048] Each cell string CS may include: at least one ground selection transistor GST connected to a corresponding ground selection line; a plurality of memory cells MC respectively connected to a plurality of word lines WL; and at least one (or two) string selection transistors SST connected to corresponding string selection lines. In each cell string CS, the ground selection transistor GST, the memory cells MC, and the string selection transistors SST may be connected in series with each other in a direction perpendicular to the substrate SUB and may be sequentially stacked in a direction perpendicular to the substrate SUB. In addition, the memory cells MC may include dummy memory cells that do not store data. The dummy memory cells may be used for various purposes.

[0049] Memory cells of the cell string CS located at the same height or a similar height from the substrate SUB or the ground selection transistor GST may be connected to the same word line or a similar word line. Memory cells of the cell string CS located at different heights from the substrate SUB or the ground selection transistor GST may be connected to different word lines.

[0050] The memory block BLKa may be implemented with a three-dimensional (3D) memory array. The 3D memory array may be monolithically formed in one or more physical levels of an array of memory cells MC having active regions disposed above a silicon substrate and circuitry associated with the operation of these memory cells MC. The circuitry associated with the operation of the memory cells MC may be located above or within such a substrate. The term "monolithic" means that the layers of each level of the array are directly deposited on the layers of each lower level of the 3D memory array.

[0051] In some example embodiments, the 3D memory array may include vertically oriented vertical NAND strings (or cell strings) such that at least one memory cell is located above another memory cell. At least one memory cell may include a charge trapping layer. Each vertical NAND string may also include at least one selection transistor disposed above the memory cells MC. The at least one selection transistor may have the same structure or a similar structure as the memory cells MC and may be formed uniformly with the memory cells MC.

[0052] The following patent documents (incorporated herein by reference) describe suitable configurations for three-dimensional memory arrays, where the three-dimensional memory arrays are configured as multiple levels and share word lines and / or bit lines between the levels: U.S. Patent No. 7,679,133; No. 8,553,466; No. 8,654,587; No. 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0053] Figure 3A and Figure 3B shows Figure 2View of the structure of a cell string in memory block BLKa.

[0054] Reference Figure 2 、 Figure 3A and Figure 3B , a column PL extending in a direction perpendicular to the substrate SUB and in contact with the substrate SUB is provided on the substrate SUB. The ground selection line GSL, word line WL, and string selection line SSL can be formed of a conductive material (e.g., a metal material) parallel to the substrate SUB. The column PL can be in contact with the substrate SUB through the conductive material forming the string selection line SSL, word line WL, and ground selection line GSL. In addition, the word line WL can include a dummy word line connected to a dummy memory cell that does not store data. The dummy word line can be used for various purposes.

[0055] Figure 3B Shows a cross-sectional view taken along line A-A'. Figure 3A The cross-sectional view of the memory cell MCa corresponding to one word line is shown. The column PL can include a cylinder BD. An air gap AG can be defined inside the main body BD. The main body BD can include P-type silicon and can be a region where a channel will be formed. The column PL can also include: a cylindrical tunneling insulating layer TI that surrounds or partially surrounds the main body BD; and a cylindrical charge trapping layer CT that surrounds or partially surrounds the tunneling insulating layer TI. A blocking insulating layer BI can be provided between the word line and the column PL. The main body BD, tunneling insulating layer TI, charge trapping layer CT, blocking insulating layer BI, and one word line can constitute (or be included in) a charge trapping type transistor formed in a direction perpendicular to the substrate SUB or the upper surface of the substrate SUB. Each memory cell in the string selection transistor SST, ground selection transistor GST, and memory cell MC can have the same structure or a similar structure to the memory cell MCa.

[0056] In the process of manufacturing the cell string CS, the shorter the distance from the substrate SUB, the smaller the width of the column PL or the cross-sectional area parallel to the upper surface of the substrate SUB. Therefore, when the same voltage or a similar voltage is applied to the main bodies of the ground selection transistor GST, memory cell MC, and string selection transistor SST and the same voltage or a similar voltage is applied to the ground selection line GSL, word line WL, and string selection line SSL, the electric field formed at the memory cell adjacent to the substrate SUB or the ground selection transistor GST is greater than the electric field formed at the memory cell far from the substrate SUB or the string selection transistor SST. The above characteristics have an impact on the programming interference that occurs during the execution of the programming operation. To solve the problems caused by the geometric characteristics of the cell string CS, as described above, the programming order can be determined such that the memory cells far from the substrate SUB are programmed first.

[0057] Figure 4 is a diagram showing memory cells in a cell string and their programming sequence according to some example embodiments. Here, a cell string CS1 may include a plurality of memory cells MC0 to MCn-1 (n is a natural number of 1 or greater) (e.g., memory cell MC0, memory cell MC1, ……, memory cell MCn-2, and memory cell MCn-1). For example, memory cell MC0 may be closest to the substrate SUB, and memory cell MCn may be farthest from the substrate SUB (or may be closest to the string select line SSL).

[0058] Reference Figure 4 , in the first cell string CS1, the size of the memory cells may increase as the distance from the substrate SUB increases. According to some example embodiments, the memory cell with a relatively slow programming speed (or with a relatively large channel hole diameter) may be programmed first. For example, the non-volatile memory device 100 may first select the word line WLn-1 of the memory cell MCn-1 for the programming operation. The remaining word lines WLn-2, WLn-3, ……, WL1, and WL0 may be selected sequentially from top to bottom. According to some example embodiments, any one or all of the cell strings CS may be the same as or similar to the first cell string CS1.

[0059] Figure 5 is a waveform diagram showing the programming operations of some example embodiments. Reference Figure 5 , the programming operations of some example embodiments may include a programming verification period VFY, a recovery period RCV, and / or a programming execution period PGM_EXE.

[0060] Programming pulses Vpgm1 and programming pulse Vpgm2 may be provided to the selected word line for the programming operation in the form of stepwise incremental step pulses (e.g., incremental step pulse programming (ISPP)). First, after applying the programming pulse Vpgm1 to the selected word line, verification voltages Vfy1, Vfy2, and Vfy3 of different levels are sequentially provided to the selected word line. In Figure 5 three verification voltages Vfy1, Vfy2, and Vfy3 are shown, but some example embodiments are not limited thereto. It can be well understood that at least one verification voltage among various levels of verification voltages may be applied to the selected word line in the form of a pulse during the programming verification period VFY.

[0061] The operations of restoring and initializing word lines can be performed in parallel during the recovery period RCV. That is, the recovery voltage Vrcv can be applied to all word lines to which the read pass voltage Vread or the verify voltages Vfy1, Vfy2, and Vfy3 are applied. After that, the recovery voltage Vrcv can be provided to the selected word line and the word lines adjacent to the selected word line, and the remaining word lines can be discharged to the ground level. Additionally, the precharge voltage Vprch can be applied to the common source line CSL of the cell string. Thus, the channels of the cell string can be initialized to a level corresponding to the precharge voltage Vprch. In this case, hot electron injection caused by the negative boost that can occur in the worst case can be prevented or reduced. This will be described in detail with reference to the accompanying drawings to be described below. According to some example embodiments, when the driving temperature of the non-volatile memory device (e.g., non-volatile memory device 100) is lower than the reference temperature TH or when the number of unprogrammed memory cells in the cell string is less than or equal to a reference value, the precharge voltage Vprch can be increased or made higher. According to some example embodiments, the reference value can be a design parameter determined through empirical research.

[0062] During the programming execution period PGM_EXE, the level of the pass voltage to be applied to the unselected word lines can vary according to the position of the selected word line. In the case where the selected word line is above the reference position, the first pass voltage Vpass1 can be applied to the unselected word lines. Additionally, in this case, the second pass voltage Vpass2 having a level lower than the level of the first pass voltage Vpass1 can be applied to the unselected word lines adjacent to the selected word line. According to some example embodiments, the reference position can be a design parameter determined through empirical research.

[0063] However, in the case where the position of the selected word line corresponds to the reference position or the selected word line is below the reference position, the third pass voltage Vpass3 (here, Vpass3 > Vpass1) can be applied to some of the unselected word lines (e.g., the second word line group) that are above the selected word line. The second pass voltage VPass2 or a voltage lower than the second pass voltage Vpass2 can be applied to some of the unselected word lines (e.g., the first word line group) that are below the selected word line. Additionally, in the case where the driving temperature of the non-volatile memory device 100 is lower than the reference temperature TH, the level of the third pass voltage Vpass3 can become higher, and the level of the second pass voltage Vpass2 can become lower. According to some example embodiments, the reference temperature can be a design parameter determined through empirical research.

[0064] Figure 6is a diagram showing how the word line voltage changes during the recovery operation in some example embodiments. Refer to Figure 6 , the recovery operation of some example embodiments includes a first recovery operation RCV1 and a second recovery operation RCV2. Here, it is assumed that the selected word line for the programming operation is word line WL2 (or the third word line WL2 starting from the ground selection line GSL).

[0065] Before the recovery operation (①), a programming verification operation VFY is performed. A verification voltage Vfy for verifying whether the memory cell is successfully programmed is applied to the selected word line WL2. Simultaneously or concurrently, a read pass voltage Vread is applied to the remaining word lines. The read pass voltage Vread has a voltage level sufficient to fully turn on the memory cells in all programming states.

[0066] Then, the recovery operation of some example embodiments can be performed. The recovery operation of some example embodiments may include a first recovery phase RCV1 (②) and a second recovery phase RCV2 (③). Here, it is assumed that a cell string is connected to 91 word lines WL0 to WL90 (e.g., word line WL0, word line WL1, word line WL2, word line WL3, word line WL4, word line WL5, word line WL6, word line WL7, word line WL8, word line WL9, word line WL10,..., word line WL90). However, it can be well understood that the number of word lines is not limited to the above example.

[0067] In the first recovery phase RCV1, a recovery voltage Vrcv can be applied to all word lines WL0 to WL90. A precharge voltage Vprch can be provided through the common source line CSL to initialize the channel of the cell string. To initialize the channel through the common source line CSL, a ground voltage GND for turning off the string selection transistor SST can be provided to the string selection line SSL. Additionally, a recovery voltage Vrcv can be applied to the ground selection line GSL to turn on the ground selection transistor GST. In some example embodiments, the recovery voltage Vrcv can be a voltage lower than the read pass voltage Vread and higher than 0V. Furthermore, in some example embodiments, the precharge voltage Vprch can be a voltage lower than the power supply voltage VDD and higher than 0V.

[0068] In the second recovery stage RCV2, the pre-charge voltage Vprch provided for initializing the channel through the common source line CSL can be maintained. The recovery voltage Vrcv can be continuously provided to the selected word line WL2 and the second word line group G2. The second word line group G2 refers to one or more word lines located above the selected word line WL2. However, the ground voltage GND or the recovery voltage Vrcv can be provided to the first word line group G1. The first word line group G1 refers to one or more word lines located below the selected word line WL2. In some example embodiments, the recovery voltage Vrcv can be applied to the word line WL1 of the first word line group G1, and the ground voltage GND can be applied to the word line WL0 of the first word line group G1. However, in some example embodiments, the ground voltage GND can be applied to all word lines WL0 and WL1 of the first word line group G1. Additionally, the ground voltage GND can be applied to the third word line group G3. The third word line group G3 refers to the remaining word lines other than the first word line group G1 and the second word line group G2.

[0069] Figure 7 briefly shows Figure 6 the channel initialization effect in the first recovery stage RCV1. For ease of description, in Figure 7 , it is assumed that the memory cells of the selected word line WL2 and the first word line group G1 are in the erased state "E" and several memory cells of the second word line group G2 are in a specific programmed state. That is, it is assumed that the memory cell connected to the word line WL3 is in the programmed state P7, the memory cell connected to the word line WL4 is in the programmed state P2, and the memory cell connected to the word line WL5 is in the erased state "E".

[0070] In the case of the first recovery stage RCV1 without applying the recovery voltage Vrcv that can be used in some example embodiments, a channel cutoff region (i.e., a local boost region) can be formed in the channel corresponding to the memory cells of the second word line group G2 (depicted as the channel CH). In the case of performing a general recovery operation, after providing the read-pass voltage Vread to the upper word lines WL3 to WL90 of the selected word line WL2 during the verification operation, the upper word lines WL3 to WL90 can be discharged to the level of the ground voltage GND. In this way, the boosted channel cutoff region may experience negative downward coupling. This is called "negative boost". Therefore, the negative charge in the channel cutoff region may increase.

[0071] However, since the channel is local, there may be no path through which the increased negative charge can be discharged. In this case, the voltage of the channel cutoff region can be a negative voltage by negative boosting, and the voltage of the channel corresponding to the memory cells connected to the lower word lines WL0 and WL1 of the selected word line WL2 can be the ground voltage GND (e.g., 0V) because the channel is connected to the common source line CSL. Thus, the difference between the negative voltage of the channel cutoff region and the ground voltage (e.g., 0V) becomes larger, and thus the memory cells connected to the selected word line WL2 and having the erase state "E" can be programmed due to hot carrier injection (HCI).

[0072] Conversely, the non-volatile memory device 100 according to some example embodiments can float all the word lines WL0 to WL90 by using the recovery voltage Vrcv to reduce read interference caused by negative boosting in the recovery operation. That is, the word lines WL0 to WL90 are discharged from the read pass voltage Vread to the recovery voltage Vrcv higher than 0V. In this way, no channel cutoff region is formed in the channel. This means that interference caused by hot carrier injection (HCI) can be prevented or reduced.

[0073] In some example embodiments, the recovery voltage Vrcv is lower than the read pass voltage Vread and higher than 0V. The recovery voltage Vrcv can be a positive voltage sufficient to turn on the memory cells having the highest state (e.g., P7 in the case of a triple-level cell (TLC)). For example, the recovery voltage Vrcv can be the drive voltage VDD for driving the non-volatile memory device 100.

[0074] The non-volatile memory device 100 according to some example embodiments can prevent or reduce read interference by floating the word lines at the recovery voltage Vrcv during the recovery operation.

[0075] Figure 8A and Figure 8B are waveform diagrams showing the recovery operations of some example embodiments. Referring to Figure 7 and Figure 8A , the recovery operations of some example embodiments can be performed after the programming verification phase VFY. The recovery operations of some example embodiments can be divided into a first recovery stage RCV1 and a second recovery stage RCV2.

[0076] The programming verification phase VFY can be performed from time t0 to time t1. To determine whether the programming is successful, the verification voltage Vfy can be applied to the selected word line WL2, and the read pass voltage Vread can be applied to the unselected word lines WL0, WL1, and WL3 to WL90. The ground select voltage VGSL can be applied to the ground select line GSL, and the common source line CSL can be maintained in the grounded state.

[0077] A first recovery phase RCV1 can be performed from time t1 to time t2. During the first recovery phase RCV1, a recovery voltage Vrcv can be applied to all word lines WL0 to WL90. A ground selection voltage VGSL can be applied to the ground selection line GSL. In particular, a pre-charge voltage Vprch for channel initialization can be applied to the common source line CSL.

[0078] A second recovery phase RCV2 can be performed from time t2 to time t4. During the second recovery phase RCV2, the recovery voltage Vrcv can be continuously supplied to the selected word line WL2 and a second word line group G2 located above the selected word line WL2. Conversely, the word lines WL0 and WL1 of the first word line group G1 and the word lines WL6 to WL90 of the third word line group G3 located below the selected word line WL2 can be discharged to the ground level GND.

[0079] After that, during the programming execution phase PGM_EXE, the ground selection line GSL can be discharged to the ground level at time t4. A programming voltage Vpgm can be applied to the selected word line WL2, and a pass voltage Vpass can be applied to the unselected word lines WL0, WL1, and WL3 to WL90.

[0080] As described above, a negative boost that can occur in the channel during the recovery operation can be prevented or reduced by the recovery operations of some example embodiments that can be performed during the channel initialization operation.

[0081] Reference Figure 8B , the recovery operations of some example embodiments can be performed after the programming verification phase VFY. The recovery operations of some example embodiments can be divided into a first recovery phase RCV1 and a second recovery phase RCV2. The programming verification phase VFY and the first recovery phase RCV1 from time t0 to time t2 are the same as or substantially the same as those of Figure 8A , so additional descriptions will be omitted to avoid redundancy.

[0082] The second recovery phase RCV2 can be performed from time t2 to time t4. In some example embodiments, during the second recovery phase RCV2, a second recovery voltage Vpre can be supplied to the selected word line WL2 and a second word line group G2 located above the selected word line WL2. The level of the second recovery voltage Vpre can be lower than the level of the recovery voltage Vrcv (hereinafter referred to as "the first recovery voltage Vrcv") supplied during the first recovery phase RCV1. For example, the second recovery voltage Vpre can be 0V or higher than 0V and lower than the first recovery voltage Vrcv. Conversely, the first word line group G1 and the third word line group G3 located below the selected word line WL2 can be discharged to the ground level GND.

[0083] Thereafter, the ground selection line GSL can be discharged to the ground level GND at time t4 for the programming execution stage PGM_EXE. A programming voltage Vpgm can be applied to the selected word line WL2, and a pass voltage Vpass can be applied to the unselected word lines WL0, WL1, and WL3 to WL90.

[0084] As described above, the negative boost that can occur in the channel during the recovery operation can be prevented or reduced by the recovery operation of some example embodiments that can be performed during the channel initialization operation.

[0085] Figures 9A to 9D is a waveform diagram showing some example embodiments of the recovery operation.

[0086] Reference Figure 9A , the recovery operation according to some example embodiments includes a first recovery operation RCV1 and a second recovery operation RCV2. In some example embodiments, the programming verification stage VFY, the first recovery stage RCV1, and the programming execution stage PGM_EXE are the same as or similar to those described in reference Figure 8A That is, the operations from time t0 to time t2 are the same as or similar to those of Figure 8A , so additional descriptions will be omitted to avoid redundancy. The second recovery stage RCV2 will be described more comprehensively.

[0087] The second recovery stage RCV2 can be performed from time t2 to time t3. In the second recovery stage RCV2, a recovery voltage Vrcv can be continuously provided to the selected word line WL2 and the word lines WL3 to WL5 of the second word line group G2 above the selected word line WL2. Conversely, the word lines WL0 and WL1 of the first word line group G1 below the selected word line WL2 and the word lines WL6 to WL90 of the third word line group G3 can be discharged to the ground level GND.

[0088] At time t3, the selected word line WL2 can be discharged to the ground level GND. By discharging the selected word line WL2, the accuracy of the programming voltage Vpgm provided in the programming execution stage PGM_EXE can be improved. At time t4, the programming voltage Vpgm can be applied to the selected word line WL2, and the pass voltage Vpass can be applied to the unselected word lines WL0, WL1, and WL3 to WL90.

[0089] Reference Figure 9B , the recovery operation according to some example embodiments includes a first recovery operation RCV1 and a second recovery operation RCV2. In some example embodiments, the programming verification stage VFY, the first recovery stage RCV1, and the programming execution stage PGM_EXE are the same as or similar to those described in referenceFigure 9A Those described stages are the same or similar. That is, the operations from time t0 to time t2 are the same or similar to Figure 8A the operations of, and thus additional descriptions will be omitted to avoid redundancy.

[0090] A second recovery stage RCV2 can be performed from time t2 to time t3. In the second recovery stage RCV2, a second recovery voltage Vpre can be provided to the selected word line WL2 and word lines WL3 to WL5 of a second word line group G2 located above the selected word line WL2. The level of the second recovery voltage Vpre can be lower than the level of the first recovery voltage Vrcv provided in the first recovery stage RCV1. For example, the second recovery voltage Vpre can be 0V or higher than 0V and lower than the first recovery voltage Vrcv. Conversely, word lines WL0 and WL1 of the first word line group G1 and word lines WL6 to WL90 of the third word line group G3 can be discharged to the ground level GND.

[0091] At time t3, the selected word line WL2 can be discharged to the ground level GND. In this case, the second recovery voltage Vpre can be continuously provided to word lines WL3 to WL5 of the second word line group G2, and word lines WL0 and WL1 of the first word line group G1 and word lines WL6 to WL90 of the third word line group G3 can be maintained at the ground level GND.

[0092] At time t4, the ground selection line GSL can be discharged to the ground level GND for the programming execution stage PGM_EXE. A programming voltage Vpgm can be applied to the selected word line WL2, and a pass voltage Vpass can be applied to unselected word lines WL0, WL1, and WL3 to WL90.

[0093] As described above, negative boost that can occur in the channel during the recovery operation can be effectively prevented or reduced through the recovery operations of some example embodiments performed in the channel initialization operation.

[0094] Reference Figure 9C , the recovery operations according to some example embodiments include a first recovery operation RCV1 and a second recovery operation RCV2. In some example embodiments, the programming verification stage VFY, the first recovery stage RCV1, and the programming execution stage PGM_EXE are the same or similar to Figure 9A those described. That is, the operations from time t0 to time t2 are the same or similar to Figure 9A those of (except for the unselected word line WL3, as further discussed below), and thus additional descriptions will be omitted to avoid redundancy. The second recovery stage RCV2 will be described more comprehensively.

[0095] The second recovery phase RCV2 can be performed from time t2 to time t3. During the second recovery phase RCV2, a recovery voltage Vrcv can be continuously supplied to the selected word line WL2 and a second word line group G2 located above the selected word line WL2. Conversely, word lines WL0 and WL1 of the first word line group G1 and word lines WL6 to WL90 of the third word line group G3 located below the selected word line WL2 can be discharged to the ground level GND.

[0096] At time t3, the selected word line WL2 and the unselected word line WL3 (which is an upper word line adjacent or neighboring to the selected word line WL2) can be discharged to the ground level GND. Discharging the selected word line WL2 and the unselected word line WL3 can improve the accuracy of the programming voltage Vpgm provided during the programming execution phase PGM_EXE.

[0097] At time t4, the programming voltage Vpgm can be applied to the selected word line WL2, and the pass voltage Vpass can be applied to the unselected word lines WL0, WL1, and WL3 to WL90. According to some example embodiments, from time t1 to time t2 and at time t4, the unselected word line WL3 can be subjected to the same voltage or a similar voltage as the voltage applied to the unselected word lines WL4 to WL5 of the second word line group G2. From time t2 to time t4, the unselected word line WL3 can be subjected to the same voltage or a similar voltage as the voltage applied to the selected word line WL2.

[0098] Reference Figure 9D According to some example embodiments, the recovery operation includes a first recovery operation RCV1 and a second recovery operation RCV2. In some example embodiments, the programming verification phase VFY, the first recovery phase RCV1, and the programming execution phase PGM_EXE are the same as or similar to those described in reference Figure 9A That is, the operations from time t0 to time t2 are the same as or similar to those of Figure 9A (except for the unselected word line WL3, as further discussed below), so additional descriptions will be omitted to avoid redundancy. The second recovery phase RCV2 will be described more comprehensively.

[0099] The second recovery phase RCV2 can be performed from time t2 to time t3. In the second recovery phase RCV2, a second recovery voltage Vpre can be provided to the selected word line WL2 and the word lines WL3 to WL5 of the second word line group G2 located above the selected word line WL2. Conversely, the word lines WL0 and WL1 of the first word line group G1 and the word lines WL6 to WL90 of the third word line group G3 can be discharged to the ground level GND. Here, the level of the second recovery voltage Vpre can be lower than the level of the first recovery voltage Vrcv provided in the first recovery phase RCV1. For example, the second recovery voltage Vpre can be 0V or higher than 0V and can be lower than the first recovery voltage Vrcv.

[0100] From time t3 to time t4, the selected word line WL2 and the unselected word line WL3 (which is the upper word line adjacent or next to the selected word line WL2) can be discharged to the ground level GND. In this case, the second recovery voltage Vpre can be continuously provided to the remaining word lines WL4 and WL5 of the second word line group G2 other than the unselected word line WL3. Conversely, the word lines WL0 and WL1 of the first word line group G1 and the word lines WL6 to WL90 of the third word line group G3 can be maintained at the ground level GND.

[0101] At time t4, a programming voltage Vpgm can be applied to the selected word line WL2, and a pass voltage Vpass can be applied to the unselected word lines WL0, WL1, and WL3 to WL90. According to some example embodiments, from time t1 to time t2 and at time t4, the unselected word line WL3 can be subjected to the same voltage or a similar voltage as the voltage applied to the unselected word lines WL4 to WL5 of the second word line group G2. From time t2 to time t4, the unselected word line WL3 can be subjected to the same voltage or a similar voltage as the voltage applied to the selected word line WL2.

[0102] Figure 10 is a diagram showing a threshold voltage distribution associated with a 3-bit memory cell according to some example embodiments. Refer to Figure 10 , a memory cell can be programmed to an erase state "E" and one of a plurality of programming states P1 to P7.

[0103] The above verification voltage Vfy can include voltages for identifying the plurality of programming states P1 to P7 (e.g., verification voltage Vfy4, verification voltage Vfy6, etc.). For example, the verification voltage Vfy4 can have a voltage level for identifying whether a memory cell for the programming state P4 has been successfully programmed.

[0104] The recovery voltage Vrcv of some example embodiments may be lower than the read pass voltage Vread and may be higher than the upper limit of the highest programming state P7. However, the level of the recovery voltage Vrcv is not limited to the above examples. The recovery voltage Vrcv may be adjusted in consideration of negative boosting and / or read interference. For example, the recovery voltage Vrcv may be the driving voltage VDD that serves as the power supply voltage of the non-volatile memory device 100.

[0105] Figure 11A and Figure 11B is a diagram showing the characteristics of the voltage applied to a word line during the programming execution phase of some example embodiments. Figure 11A shows the channel and word line voltages when the word line selected for the programming operation is above the reference word line RWL. Figure 11B shows the channel and word line voltages when the selected word line is below the reference word line RWL.

[0106] Here, it is assumed that the reference word line RWL is the word line WL15 in the sequence of programming performed in the order from the upper word line to the lower word line. The reference word line RWL refers to the word line where hot electron injection (HCI) becomes severe or harmful due to the potential difference of the local boosted channel and thus changes the conditions for applying the pass voltage during the programming operation. The condition for applying the pass voltage to the word line above the reference word line RWL during the programming operation is referred to as the "first pass condition". The condition for applying the pass voltage to the reference word line RWL and the word lines below the reference word line RWL during the programming operation is referred to as the "second pass condition". As will be described later, a third pass condition in which an offset can be added to the second pass condition can be considered based on the degree of hot electron injection that varies according to temperature.

[0107] Figure 11AShows a first pass condition that can be applied when a programming operation is performed on a word line located above a reference word line RWL. For example, when word line WL47 is selected for the programming operation, the selected word line WL47 is much farther or farther from the substrate than the reference word line RWL. In this case, the pass voltage applied in the programming operation can be determined according to the first pass condition. According to the first pass condition, the first pass voltage Vpass1 or the second pass voltage Vpass2 (Vpass2 < Vpass1) can be applied to word lines WL48 to WL90 located above the selected word line WL47. The first pass voltage Vpass1 or the second pass voltage Vpass2 (Vpass2 < Vpass1) can be applied to word lines WL0 to WL46 located below the selected word line WL47. In particular, the second pass voltage Vpass2 lower than the first pass voltage Vpass1 can be applied to word lines WL46 and WL48 adjacent or neighboring to the selected word line WL47, and the first pass voltage Vpass1 can be applied to the remaining word lines WL0 to WL45 and WL49 and WL50 to WL90.

[0108] Figure 11B Shows a second pass condition that can be applied when a programming operation is performed on a word line located below a reference word line RWL. For example, when word line WL2 is selected for the programming operation, the selected word line WL2 is closer or nearer to the substrate than the reference word line RWL. In this case, the pass voltage applied in the programming operation can be determined according to the second pass condition. According to the second pass condition, the third pass voltage Vpass3 (Vpass3 > Vpass1) can be applied to a second word line group WL3 to WLj (j is a natural number: 4 < j < 90) located above the selected word line WL2. The second pass voltage Vpass2 (Vpass2 < Vpass1) is applied to a first word line group WL0 to WL1 located below the selected word line WL2. Here, the number of word lines belonging to the second word line group (e.g., WL3 to WLj) under the second pass condition is greater than the number of word lines belonging to the second word line group under the first pass condition. In addition, the level change of the pass voltage under the first pass condition and the second pass condition is not limited to the above examples.

[0109] Figure 12A Is a waveform diagram of the word line voltage showing the first pass condition, and the word line voltage of the first pass condition can be applied to the word lines located above the reference word line RWL during the programming operation. Refer to Figure 12A , when word line WL47 is selected for the programming operation, the selected word line WL47 can be much farther from the substrate than the reference word line RWL. In this case, the pass voltage applied in the programming operation can be determined according to the first pass condition.

[0110] At time T0, a second bit line voltage VBL2 can be applied to an unselected bit line (or a bit line for which programming is prohibited). For example, the second bit line voltage VBL2 can be a power supply voltage VDD. According to this biasing condition, programming of memory cells connected to the unselected bit line can be prohibited. During a programming operation, the selected bit line can be maintained at the level of a first bit line voltage VBL1. For example, the first bit line voltage VBL1 can be a ground voltage GND. Additionally, at time T0, a second string select voltage VSSL2 can be applied to the selected string select line, and a first string select voltage VSSL1 can be applied to the unselected string select line. For example, the second string select voltage VSSL2 can be a power supply voltage VDD.

[0111] At time T1, a pass voltage Vpass1 and a pass voltage Vpass2 can be applied to the word lines. Here, either the first pass voltage Vpass1 or the second pass voltage Vpass2 (Vpass2 < Vpass1) can be applied to word lines WL48 to WL90 located above the selected word line WL47. That is, the first pass voltage Vpass1 can be applied to word lines WL49 to WL90, and the second pass voltage Vpass2 can be applied to the word line WL48 adjacent or next to the selected word line WL47. The second pass voltage Vpass2 can be applied to the selected word line WL47. Further, either the first pass voltage Vpass1 or the second pass voltage Vpass2 can be applied to word lines WL0 to WL46 located below the selected word line WL47. In particular, the second pass voltage Vpass2 lower than the first pass voltage Vpass1 can be applied to the word lines WL46 and WL48 adjacent or next to the selected word line WL47, and the first pass voltage Vpass1 can be applied to the remaining word lines WL0 to WL45 and WL49 to WL90.

[0112] At time T2, a programming voltage Vpgm can be applied to the selected word line WL47. There can be programmed memory cells in the selected string, where the selected string is connected to the selected word line WL47. According to a first pass condition, the above biasing conditions associated with the unselected word lines WL0 to WL46 and WL48 to WL90 can be continuously maintained. In this case, from time T1 to time T3, the channels of the cell strings connected to the unselected string select lines are maintained in a boosted state. Therefore, in the unselected cell strings, programming of the memory cells connected to the selected word line WL47 can be prohibited.

[0113] At time T3, the programming voltage Vpgm and the pass voltages Vpass1 and Vpass2 supplied to the word lines can be restored.

[0114] The word line voltage of the first pass condition that can be applied to the word line located above the reference word line RWL in a programming operation has been described above.

[0115] Figure 12B is a waveform diagram showing the word line voltage of the second pass condition, and the word line voltage of the second pass condition can be applied to the word line located above the reference word line RWL in a programming operation. Refer to Figure 12B , when the word line WL2 is selected for a programming operation, the selected word line WL2 can be closer to or nearer to the substrate than the reference word line RWL. In this case, the pass voltage applied in the programming operation can be determined according to the second pass condition.

[0116] The bit line voltage and the string select voltage from time T0 to time T1 are the same as or similar to those of Figure 12A Therefore, additional descriptions will be omitted to avoid redundancy.

[0117] At time T1, the pass voltage Vpass1, the pass voltage Vpass2, and the pass voltage Vpass3 can be applied to the word line. Here, the third pass voltage Vpass3 higher than the first pass voltage Vpass1 can be applied to the word lines WL3 to WL(i - 1) (i is a natural number: 4 < i < 90) of the second word line group located above the selected word line WL2. In addition, the first pass voltage Vpass1 lower than the third pass voltage Vpass3 can be applied to the word lines WLi to WL90 of the third word line group located above the second word line group WL3 to WL(i - 1). The second pass voltage Vpass2 lower than the first pass voltage Vpass1 can be applied to the word lines WL0 to WL1 of the first word line group located below the selected word line WL2. In this case, one of the pass voltages of the first pass voltage Vpass1, the second pass voltage Vpass2, and / or the third pass voltage Vpass3 can be applied to the selected word line WL2.

[0118] Here, memory cell interference and hot electron injection (HCI) can be considered to appropriately select the number of word lines of the second word line group to which a third pass voltage Vpass3 higher than the first pass voltage Vpass1 can be applied. As the number of word lines of the second word line group increases, the potential of the locally boosted first channel CH1 can become higher, and thus the possibility of hot electron injection (HCI) can become lower. However, the interference of the memory cells caused by the third pass voltage Vpass3 may increase up to the increased potential of the channel. According to some example embodiments, the number of word lines included in the second word line group can vary according to the sensed driving temperature of the non-volatile memory device (e.g., non-volatile memory device 100). For example, when the driving temperature is lower than the reference temperature, the number of word lines included in the second word line group can be greater than the number of word lines included in the second word line group when the driving temperature is equal to or higher than the reference temperature.

[0119] At time T2, a programming voltage Vpgm can be applied to the selected word line WL2. There can be programmed memory cells of the selected string, and the selected string can be connected to the selected word line WL2. The voltage of the second pass condition provided at time T1 can be continuously provided to the unselected word lines WL0, WL1, and WL3 to WL90. In this case, from time T1 to time T3, the channels CH1 and CH2 of the cell strings connected to the unselected string select lines can maintain the boosted state. Therefore, in the unselected cell strings, programming of the memory cells connected to the selected word line WL2 can be prohibited.

[0120] At time T3, the programming voltage Vpgm and the pass voltages Vpass1, Vpass2, and Vpass3 provided to the word lines can be restored.

[0121] The word line voltage of the second pass condition described above can be applied to the word lines located above the reference word line RWL during a programming operation.

[0122] Figure 13 is a waveform diagram showing the word line voltage of the third pass condition that can be applied when the driving temperature of the non-volatile memory device is lower than the reference temperature TH compared to the second pass condition described with reference Figure 12B . Referring to Figure 13 , when the word line WL2 is selected for a programming operation, the selected word line WL2 is closer to or nearer to the substrate than the reference word line RWL (e.g., WL15). When the current driving temperature included in the temperature information Temp_Info provided from the temperature sensor 170 (refer to Figure 1 ) is the reference temperature TH or lower than the reference temperature TH, the reference Figure 12BThe described second pass condition is applied to the programming operation. However, when it is determined that the current driving temperature is the reference temperature TH or higher than the reference temperature TH, the third pass condition to be described below can be applied to the programming operation.

[0123] The bit line voltage and the string select voltage from time T0 to time T1 are the same as or similar to Figure 12A those voltages, so additional description will be omitted to avoid redundancy.

[0124] At time T1, the pass voltage Vpass1, the pass voltage Vpass2 - β, and the pass voltage Vpass3 + α can be applied to the word line. Here, the fifth pass voltage Vpass3 + α higher than the third pass voltage Vpass3 can be applied to the word lines WL3 to WLi - 1 (i is a natural number: 4 < i < 90) of the second word line group located above the selected word line WL2. Here, α can be an offset depending on the current temperature. The third pass voltage Vpass3 or the first pass voltage Vpass1 can be applied to the word lines WLi to WL90 of the third word line group located above the selected word line WL2. The fourth pass voltage Vpass2 - β lower than the second pass voltage Vpass2 can be applied to the word lines WL0 to WL1 of the first word line group located below the selected word line WL2. Here, β can be an offset depending on the current temperature. In this case, one of the pass voltages among the first pass voltage Vpass1, the second pass voltage Vpass2, and / or the third pass voltage Vpass3 can be applied to the selected word line WL2.

[0125] At time T2, the programming voltage Vpgm can be applied to the selected word line WL2. The memory cells of the selected string connected to the selected word line WL2 can be programmed. The voltages of the third pass condition provided at time T1 can be continuously provided to the unselected word lines WL0, WL1, and WL3 to WL90. In this case, from time T1 to time T3, the channels CH1 and CH2 of the cell strings connected to the unselected string select lines can maintain the boosted state. Therefore, in the unselected cell strings, programming of the memory cells connected to the selected word line WL2 can be prohibited.

[0126] At time T3, the programming voltage Vpgm and the pass voltages Vpass1, Vpass2 - β, and Vpass3 + α provided to the word lines can be restored.

[0127] The word line voltages of the third pass condition that can be applied when it is determined that the current driving temperature is the reference temperature TH are described above.

[0128] Figure 14is a flowchart showing a method of providing a pass voltage for each condition during a programming execution phase of some example embodiments. Refer to Figure 1 and Figure 14 , the optimal or improved pass voltage condition can be selected according to the position of the selected word line and / or the driving temperature during the programming operation. Here, the order of selecting the word lines of the cell string for the programming operation is limited to the case where the word line far from the substrate is selected first.

[0129] In operation S110, the word line WL to which the programming voltage Vpgm is to be applied can be selected by controlling the logic circuit 150 (refer to Figure 1 ). The word line selected in operation S110 is referred to as the "selected word line". In some example embodiments, the word line far from the substrate can be selected first to provide the programming voltage thereto.

[0130] In operation S120, the control logic circuit 150 can perform an operation branch according to the relative position of the selected word line with respect to the reference word line RWL. When (e.g., in response to a determination that) the selected word line is above the reference word line RWL or farther from the substrate (yes), the process can proceed to operation S130. When (e.g., in response to a determination that) the selected word line is below the reference word line RWL or the selected word line is closer to the substrate than the reference word line RWL (no), the process can proceed to operation S140. For example, the reference word line RWL can be the word line WL15, and the word line WL15 is the sixteenth word line starting from the substrate among the 91 word lines WL0 to WL90. However, it can be well understood that the position of the reference word line RWL can be determined differently according to the number of layers of the three-dimensional semiconductor memory and / or the process characteristics.

[0131] In operation S130, the control logic circuit 150 can apply a pass voltage to the unselected word lines according to the first pass condition. In this case, the programming voltage Vpgm can be applied to the selected word line. In Figure 12A an example level of the pass voltage for the first pass condition is shown. That is, the first pass voltage Vpass1 or the second pass voltage Vpass2 (Vpass2 < Vpass1) can be applied to the unselected word lines.

[0132] In operation S140, the control logic circuit 150 may obtain the current temperature for driving the non-volatile memory device 100 based on the temperature information Temp_Info provided from the temperature sensor 170. The control logic circuit 150 may compare the current temperature with a reference temperature TH (e.g., may determine whether the current temperature is lower than the reference temperature TH) to perform an operation branch for selecting a pass condition. When the current temperature is higher than or equal to the reference temperature TH (No), the process may proceed to operation S160. When the current temperature is lower than the reference temperature TH (Yes), the process may proceed to operation S150.

[0133] In operation S150, the control logic circuit 150 may determine that the driving temperature is not high enough to cause hot carrier injection (HCI), and may apply a pass voltage to the unselected word lines according to a second pass condition. A programming voltage Vpgm may be applied to the selected word line. In Figure 12B An example level of the pass voltage for the second pass condition is shown. That is, a third pass voltage Vpass3 higher than the first pass voltage Vpass1 is applied to a second word line group including unselected word lines located above the selected word line among the unselected word lines. A second pass voltage Vpass2 lower than the first pass voltage Vpass1 is applied to a first word line group including unselected word lines located below the selected word line among the unselected word lines. In addition, the first pass voltage Vpass1 may be applied to the remaining unselected word lines (e.g., a third word line group) located above the second word line group.

[0134] In operation S160, the control logic circuit 150 may determine that the driving temperature is high enough to cause hot carrier injection (HCI), and may apply a pass voltage to the unselected word lines according to a third pass condition. In this case, a programming voltage Vpgm may be applied to the selected word line. In Figure 13 An example level of the pass voltage for the third pass condition is shown. That is, a pass voltage Vpass3+α higher than the third pass voltage Vpass3 is applied to a second word line group including unselected word lines located above the selected word line among the unselected word lines. A pass voltage Vpass2-β lower than the second pass voltage Vpass2 is applied to a first word line group including unselected word lines located below the selected word line among the unselected word lines. In addition, the first pass voltage Vpass1 may be applied to the remaining unselected word lines (e.g., a third word line group) located above the second word line group.

[0135] The process for providing an optimal or improved pass voltage based on the position of the selected word line and / or the driving temperature during a programming operation has been described above.

[0136] Figure 15is a diagram showing another example of a cell array structure to which a programming method according to some example embodiments can be applied. Refer to Figure 15 , the cell string CS2 may include two cell groups CG1 and CG2, and in each cell group, the size of the memory cells increases as the distance from the substrate SUB increases.

[0137] The first cell group CG1 may include memory cells MC0 to MCm, and the sizes of the memory cells MC0 to MCm increase in order (e.g., memory cell MC0, memory cell MC2, memory cell MC3, ……, memory cell MCm-1, and memory cell MCm). The second cell group CG2 may include memory cells MCm+1 to MCn-1, and the sizes of the memory cells MCm+1 to MCn-1 increase in order (e.g., memory cell MCm+1, memory cell MCm+2, memory cell MCm+3, ……, memory cell MCn-2, and memory cell MCn-1). The programming order may follow such an order that the memory cell MCn-1 farthest or farther from the substrate SUB is programmed first, and the memory cell MC0 is programmed last. According to some example embodiments, any one or all of the cell strings CS may be the same as or similar to the cell string CS2.

[0138] However, the cell string CS2 may be formed in such a shape that the size of the channel hole decreases uniformly until the center of the channel hole and then increases again. Thus, the recovery operation RCV and the programming execution operation PGM_EXE described with reference to Figure 5 can be applied to a word line range in which the size of the channel hole is a reference or smaller (e.g., a word line range selected from word lines WL0, WLm1, ……, WLm-1, WLm, WLm+1, WLm+2, ……, WLn-1, and WLn).

[0139] According to some example embodiments, the potential difference of the local channel may be reduced during the programming operation, thereby preventing or reducing the reliability degradation caused by hot electron injection.

[0140] For ease of description, in this document, spatial relative terms such as "under", "below", "lower", "above", "upper", etc. may be used to describe the relationship of one element or feature to another element or feature as shown in the figure. For example, as used herein, the terms "upper", "higher than", "on", "above", and / or "top" may refer to the vertical direction (such as Figure 2elements or features that are further away on the device shown), and the terms "lower", "below" and / or "beneath" may refer to elements or features that are further away in a direction opposite to the vertical direction relative to another element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features will be oriented "above" the other elements or features. Thus, the term "below" can encompass both the orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0141] It will be understood that when an element is referred to as being "adjacent" to another element, the element may be in immediate contact with or adjacent to the other element, or there may be intervening elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0142] Some example embodiments are described herein with reference to cross-sectional views of schematic diagrams that are ideal examples. Thus, for example, variations in the illustrated shapes due to manufacturing techniques and / or tolerances are to be expected. Accordingly, some example embodiments should not be construed as being limited to the particular shapes of the regions shown herein, but should include, for example, shape deviations caused by manufacturing.

[0143] Some example embodiments may be described with reference to acts and symbolic representations of operations (e.g., in the form of flowcharts, process diagrams, data flow diagrams, structure diagrams, block diagrams, etc.) that may be implemented in connection with units and / or devices discussed in more detail hereinafter. Although discussed in a particular manner, the functions or operations specified in a particular block may be performed differently than the processes specified in the flowcharts, process diagrams, etc. For example, functions or operations shown to be performed serially in two consecutive blocks may actually be performed simultaneously, at the same instant, or in some cases in the reverse order.

[0144] Although some example embodiments have been described, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made without departing from the spirit and scope of some example embodiments as set forth in the appended claims.

Claims

1. A programming method for a non-volatile memory device, the non-volatile memory device including cell strings in which a plurality of memory cells are stacked in a direction perpendicular to the surface of a substrate, the programming method comprising: Performing a first programming phase including programming a first memory cell among the plurality of memory cells, the first memory cell being connected to a first word line among a plurality of word lines of the cell string, the first programming phase including applying a first pass voltage to other word lines among the plurality of word lines that are above or below the first word line with respect to the substrate; And Performing a second programming phase including programming a second memory cell among the plurality of memory cells after completely programming the first memory cell, the second memory cell being connected to a second word line among the plurality of word lines that is closer to the substrate than the first word line, the second programming phase including applying a second pass voltage to a first group of word lines among the plurality of word lines that are below the second word line with respect to the substrate and applying a third pass voltage to a second group of word lines among the plurality of word lines that are above the second word line with respect to the substrate, the second pass voltage being lower than the third pass voltage, wherein the number of word lines included in the second group of word lines varies according to the driving temperature.

2. The programming method according to claim 1, wherein the second word line is closer to the substrate than a reference word line among the plurality of word lines.

3. The programming method according to claim 1, wherein the second programming phase includes applying a fourth pass voltage to a third group of word lines among the plurality of word lines that are above the second group of word lines with respect to the substrate, the fourth pass voltage being higher than the second pass voltage and lower than the third pass voltage.

4. The programming method according to claim 1, further comprising: Sensing the driving temperature of the non-volatile memory device; And Adjusting the second pass voltage or the third pass voltage according to the driving temperature.

5. The programming method according to claim 4, wherein the adjustment increases the third pass voltage based on a first temperature offset in response to the driving temperature being higher than a reference temperature.

6. The programming method according to claim 4, wherein the adjustment decreases the second pass voltage based on a second temperature offset in response to the driving temperature being higher than a reference temperature.

7. The programming method according to claim 4, wherein the number of word lines included in the second group of word lines when the driving temperature is lower than the reference temperature is greater than the number of word lines included in the second group of word lines when the driving temperature is equal to or higher than the reference temperature.

8. The programming method according to claim 1, wherein the channel hole of the first memory cell is larger than the channel hole of the second memory cell.

Images