Method and system for making fiducials using selective region growing

Abstract

A method for forming an alignment mark, comprising: providing a III-V compound substrate having a device region and an alignment mark region; forming a hard mask layer, the hard mask layer having a first group of openings on the alignment mark region exposing a first surface portion of the III-V compound substrate and a second group of openings on the device region exposing a second surface portion of the III-V compound substrate; etching the surface of the exposed III-V compound substrate using the hard mask layer as a mask to form a plurality of grooves; and epitaxially regrowing a semiconductor layer in the grooves to form an alignment mark extending to a predetermined height above a processed surface of the III-V compound substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 875,443, filed on July 17, 2019, entitled “Method and System for Fabricating Fiducials Using Selective Area Growth,” the entire contents of which are incorporated herein by reference for all purposes. Background Art

[0003] A series of photolithography steps are usually required in the manufacture of semiconductor devices. Therefore, in order to provide alignment between the previously processed layer and the current layer, one or more fiducials (also called alignment marks) can be formed in the processed layer as topographic steps or depressions. A protective layer (e.g., silicon oxide) can be formed over the topographic features to prevent damage to the fiducials (alignment marks) during subsequent processing. However, such a protective layer will limit the resolution of the fiducials and increase cost and processing time.

[0004] For example, some semiconductor manufacturing processes that require fiducials (alignment marks) require at least one and sometimes two or more additional mask steps. These additional fiducials (alignment masks) and associated processes increase processing costs, cycle time, and potential defects in process flow. Therefore, there is a need in the art for improved methods and systems related to fiducials. Summary of the invention

[0005] The present invention relates to semiconductor manufacturing technology, and more specifically, to a method of forming an alignment mark and to a semiconductor device having such an alignment mark. In particular, in some semiconductor manufacturing processes, at certain steps in the process, the surface of the semiconductor can be made substantially flat. One process in the process is selective area regrowth to form a semiconductor layer embedded in an existing pattern. An example of such regrowth providing a substantially flat surface is given in US9,117,839 (Kizilyalli et al.). In such a selective area regrowth process, it is desirable to simultaneously form an alignment structure having a topographic relief relative to the flat regrowth surface.

[0006] In one aspect of the present invention, a method for forming an alignment mark comprises: providing a III-V compound substrate having a device region and an alignment mark region; forming a hard mask layer, the hard mask layer having a first group of openings on the alignment mark region exposing a first surface portion of the III-V compound substrate and a second group of openings on the device region exposing a second surface portion of the III-V compound substrate; etching the surface of the exposed III-V compound substrate using the hard mask layer as a mask to form a plurality of grooves; and epitaxially regrowing a semiconductor layer in the grooves to form an alignment mark extending to a predetermined height above a processed surface of the III-V compound substrate.

[0007] In another aspect of the present invention, a semiconductor device may include: a III-V compound substrate including a device region and an alignment mark region, and a plurality of three-dimensional and three-dimensional alignment marks in the alignment mark region. Each of the alignment marks may include a protruding portion extending above a surface of the III-V compound substrate. In one embodiment, the III-V compound substrate includes an N-type GaN epitaxial layer, and the alignment mark includes a P-type GaN epitaxial layer.

[0008] Many benefits can be obtained through the present invention compared to conventional techniques. For example, embodiments of the present invention utilize the enhanced growth rate of the metal organic chemical vapor deposition (MOCVD) epitaxial film adjacent to the large area of ​​the hard mask to produce raised features during the P-type GaN regrowth process, even when the regrowth in the device array itself is flattened to the level of the fin top surface. Embodiments of the present invention can utilize a first selective area re-growth definition mask to produce alignment structures that are visible to a deep UV (DUV) aligner in a subsequent alignment step after the P-type GaN regrowth. In one embodiment, the selective area regrowth definition mask is a source definition mask that is also the first mask in the process flow according to embodiments of the present invention. According to some embodiments, other types of alignment marks (e.g., i-line alignment marks) can be subsequently created in a subsequent metal mask patterning step for subsequent mix and match alignment.

[0009] In addition, embodiments of the present invention provide methods and systems for simultaneously generating alignment features (marks) during epitaxial regrowth of the gate region of a vertical fin-based FET device, potentially avoiding the use of additional mask layers. This new method utilizes the enhanced growth rate of the MOCVD epitaxial film adjacent to a large area of ​​a hard mask to produce raised features during the P-type GaN regrowth step, even when the regrowth in the device array is flattened to the level of the top surface of the fin. In some embodiments, the regrowth of the alignment features is self-limiting, so that the height of the alignment features (marks) can be predetermined by the opening width of the patterned mask layer. These and other embodiments of the present invention and their many advantages and features will be described in more detail in conjunction with the following content and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a graph illustrating measured and simulated growth rate enhancement (GRE) distributions of GaN around different hard mask widths in accordance with an embodiment of the present invention.

[0011] Figure 2A is a top plan view of a partially patterned hard mask layer including an alignment mask layout and a fin layout according to an embodiment of the present invention.

[0012] Figure 2B is along Figure 2A Partial cross-sectional view of the patterned hard mask layer taken along line AA in FIG.

[0013] Figure 2C FIG. 4 is a top view of P-type GaN regrowth in a trench according to an embodiment of the present invention.

[0014] Figure 2D According to an embodiment of the present invention, Figure 2C Cross-sectional view of P-type GaN regrowth in the trench and hard mask removal, taken along line BB in FIG.

[0015] Figure 3 is a simplified flow chart illustrating a method of forming fiducials (alignment marks) during the formation of integrated circuits on a semiconductor wafer according to some embodiments of the present invention.

[0016] Figure 4 is a FIB cross section showing different growth on a 0.7 / 3 array for a 400 nm regrowth wafer according to an embodiment of the present invention.

[0017] Figure 5A is an oblique-view SEM image of a 0.7 / 3 array on a 600 nm regrown wafer according to an embodiment of the present invention.

[0018] Figure 5B yes Figure 5A An enlarged section of the end of the regrowth zone in FIG.

[0019] Figure 6 is a FIB cross section of a 0.7 / 3 array on an 800 nm regrown wafer according to an embodiment of the present invention.

[0020] 7A to 7F Results of regrowth profiles on corresponding 200 nm, 400 nm, 500 nm, 550 nm, 600 nm and 650 nm regrowth wafers according to embodiments of the present invention are shown.

[0021] Figure 8 is an oblique-view SEM image of a 0.3 μm×25 μm long fin array with a 2 μm pitch on a 500 nm regrown wafer according to an embodiment of the present invention.

[0022] Fig. 9 The PECVD nitride hard mask sidewall angle for a 0.3 μm hard mask width for a 0.3 μm×25 μm long fin array with a 2 μm pitch in accordance with an embodiment of the present invention is shown.

[0023] Fig.10 A top view of an alignment mark set designed to form fiducials over a hard mask when the fin array is planar is shown in accordance with an embodiment of the present invention.

[0024] Fig.11A A top view of an alignment mark group that may be used as an alignment mark pattern according to some embodiments of the present invention is shown.

[0025] Fig. 11B A portion of an alignment mask result on a 500 nm regrown wafer according to an embodiment of the present invention is shown.

[0026] Fig. 12A A top view of a hexagonal ring pattern with regrown over a hard mask is shown in accordance with an embodiment of the present invention.

[0027] Fig. 12B Shows Fig. 12A A magnified portion of the hexagonal ring pattern in the image.

[0028] Fig. 12C According to an embodiment of the present invention Fig. 12A Oblique SEM image of a magnified portion of the hexagonal ring pattern in FIG.

[0029] Fig.13A is an array of hexagonal pyramidal protrusions showing regrown over a hard mask in accordance with an embodiment of the present invention.

[0030] Fig. 13B Shows Fig.13A A magnified portion of the array in . DETAILED DESCRIPTION

[0031] Some semiconductor devices include one or more layers of epitaxially grown semiconductor material. Selective area metal-organic vapor phase epitaxy (SA-MOVPE) is one of the methods used to manufacture vertical fin field effect transistor (FinFET) devices.

[0032] Figure 1 is a graph illustrating measured and simulated growth rate enhancement (GRE) distributions of GaN (gallium nitride) around different mask widths that may be used in embodiments of the present invention. Figure 1 Described in "Selective Area Metal-Organic Vapor Phase Epitaxy of Nitride Semiconductors for Multicolor Emission" by Tomonari Shioda et al., published in the IEEE Journal of Selected Topics in Quantum Electronics in 2009. The width of the mask pair is increased stepwise. The entire content of this document is incorporated herein by reference. The measured value of GRE is obtained by normalizing the thickness at a given position with the thickness at a flat position. Reference Figure 1 , the mask opening is 60 μm (micrometers), and the mask width of the mask pair varies from 30 μm at position 1 (positions are shown in μm on the x-axis) to 240 μm at position 8 in increments of 30 μm at each subsequent position. The growth temperature is 1150°C, and the pressure is 100 mbar (millibar) in the case of H2 carrier gas. In the schematic diagram of the mask pattern, the solid line represents the experimental (i.e. measured) GRE values ​​for different mask widths along the mask pair (indicated by arrows 1 to 8), and the dashed line represents the experimental (i.e. measured) GRE values ​​at D / k s = 50 μm, where D is the mass diffusivity in the gas phase (m 2 / s), and k sis the surface reaction rate constant (m / s). The selective area MOCVD growth of GaN is affected by the selective growth hard mask. Gallium that reaches the hard mask surface preferentially diffuses to the nearby GaN surface, where it is incorporated into the growing film. As a result, the growth rate of GaN near the large area hard mask region is enhanced by the flow of gallium species from the hard mask surface.

[0033] refer to Figure 2A , Figure 2B , Figure 2C and Figure 2D A method of manufacturing a semiconductor device will be described. Figure 2A is a top plan view of a partially patterned hard mask layer according to an embodiment of the present invention, the partially patterned hard mask layer including an alignment mask layout and a semiconductor active device area fin layout. A method for manufacturing a semiconductor device may include providing a semiconductor substrate, such as a Group III nitride compound substrate. In one embodiment, the Group III nitride compound substrate is an N-type GaN substrate, on which is grown an N-type GaN epitaxial layer, a second N-type GaN epitaxial layer having a graded dopant concentration, and a third N-type GaN epitaxial layer having a higher dopant concentration than the first epitaxial layer. The method also includes forming a patterned hard mask layer on the semiconductor substrate. As used herein, the terms "fiducials" and "alignment mark" are used interchangeably. The terms "alignment fiducials" and "alignment mark" are used interchangeably. As Figure 2A As shown, the patterned hard mask layer has an alignment mark area and a device area, the alignment mark area includes a plurality of alignment mark openings 203, and the device area includes a plurality of fins, which are protected by a hard mask separated by openings 205. In some embodiments, each of the plurality of alignment mark openings 203 has a width of about 0.7 μm, and the spacing measured from the center to the center of two adjacent alignment mark openings is about 3 μm. In some embodiments, each of the plurality of alignment mark openings 203 has a width of 0.6 μm to 2.0 μm, and the spacing measured from the center to the center of two adjacent alignment mark openings is about 8 μm. In some embodiments, each of the plurality of fin openings 205 has a width of about 1.8 μm, each fin has a width of about 0.2 μm, and the spacing measured from the center to the center of two adjacent fin openings is about 2.0 μm. For the width and center-to-center spacing of the alignment mark openings and the width and center-to-center spacing of the fin openings, other embodiments may also adopt other values, and these values ​​are merely exemplary. A person skilled in the art would appreciate many variations, modifications, and substitutions.

[0034] refer to Figure 2B , a hard mask layer 201 is formed on a semiconductor substrate 200. The hard mask layer may include one or more dielectrics, such as oxides and nitrides, or other suitable materials (including, for example, refractory metals, metal alloys, or metal compounds) that can be deposited, patterned, subjected to an etching process, and subjected to a high temperature regrowth process. The hard mask has a main lateral surface that is consistent with the (0001) plane of the semiconductor substrate. In some embodiments, the semiconductor substrate may be formed from <0001> The direction deviates at a certain angle. The method also includes removing a first portion in the alignment mark area and a second portion in the device area of ​​the semiconductor substrate by etching using a patterned hard mask layer as a mask to form a first group of alignment mask grooves 207 in the alignment mask area, and forming a second group of fin grooves 209 in the device area. In one embodiment, each groove may have a depth of 0.8 μm. In order to have a uniform groove depth, good controllability of the etching process is required. In some embodiments, the etching process may include a chlorine-based chemical treatment method using RIE to form a groove, and a TMAH solution may be used to perform a cleaning process after etching the semiconductor substrate. The groove includes sidewalls substantially perpendicular to the main surface of the semiconductor substrate. In some embodiments, the groove sidewalls in the device area are substantially parallel to the m-plane of GaN.

[0035] The method further includes epitaxially regrowing a semiconductor layer in the trench until the semiconductor layer is substantially coplanar with a base of the hard mask in the device region. Meanwhile, a protruding portion of the semiconductor layer extending on the upper surface of the semiconductor substrate reaches a predetermined height. Figure 2C is a top plan view of P-type GaN regrowth in a trench according to an embodiment of the present invention. In one embodiment, the P-type GaN regrowth may be metal organic vapor phase epitaxy (MOVPE), which allows good in-plane control of thickness, stress and bandgap energy.

[0036] Figure 2D According to an embodiment of the present invention, after the epitaxial regrowth of the semiconductor layer (eg, P-type GaN), Figure 2C A cross-sectional view of the P-type GaN regrowth in the trench and the removal of the hard mask layer taken along line BB in FIG. Figure 2D , the epitaxial regrowth of the semiconductor layer in the quasi-mark trench has a portion 211 protruding above the hard mask, while the regrowth of the semiconductor layer in the fin opening has an upper surface 213 below the hard mask, and the upper surface 213 of the semiconductor layer is substantially flat. The dotted line indicates the bottom of the trench 209 that has been covered by the regrowth of the semiconductor layer. Figure 1As discussed, since the width of the alignment mark opening is smaller than the width of the fin opening, as a result of GRE, the MOCVD growth rate in the alignment mark opening is higher than the MOCVD growth rate in the fin opening. It should be noted that in the case where the protrusion above the hard mask is characterized as a triangular shape, the growth of the semiconductor layer in the alignment mark opening can be self-limiting. In one embodiment, the plane of the sidewall of the alignment mark opening is substantially parallel to the m-plane of GaN, and the protrusion 211 above the hard mask has a height approximately equal to the alignment mark opening width Wtr multiplied by the square root of 3 divided by 2 ((√3 / 2)×Wtr). In one embodiment, a smooth surface of the regrown surface can be obtained at a growth temperature in the range of 800°C to 1150°C and using H2 carrier gas at a pressure of about 100 mbar. In one embodiment, the growth temperature is in the range of 850°C to 1100°C, preferably between 900°C and 1050°C, and more preferably between about 930°C to about 970°C, for example, 950°C in one embodiment. Therefore, embodiments of the present invention utilize a mask having a two-dimensional shape to grow a three-dimensional alignment mark. The growth surface (ie, Figure 2D The regrown surface shown in FIG. 1 is surrounded by crystal planes that produce what may be called multi-directional (e.g., six-directional) alignment marks. For example, the growth surface may be aligned parallel to the m-plane of the substrate, i.e. <1000> , <0010> and <0100> axis.

[0037] Figure 3 is a simplified flow chart illustrating a method 300 for forming a reference point (alignment mark) during the formation of an integrated circuit on a semiconductor wafer according to some embodiments of the present invention. The method 300 may include: providing a III-V compound substrate (301) having a device area (also called an active area) and an alignment mark area. In one embodiment, the substrate may include a GaN material. The method 300 may further include: forming a patterned hard mask layer on the III-V compound substrate. The patterned hard mask layer includes a first set of openings on the alignment area and a second set of openings on the device area (box 303). In one embodiment, the hard mask layer includes silicon nitride and may be formed on the substrate by a PECVD or LPCVD process. The hard mask layer is then patterned by lithography, the etching method including forming a patterned photoresist on the hard mask layer and then etching the hard mask layer to form a patterned hard mask layer. In one embodiment, as Figure 2AAs shown, the patterned hard mask layer has a first group of openings exposing a first surface portion of the substrate on the alignment mark area, and a second group of openings exposing a second surface portion of the substrate on the device area. In one embodiment, each of the first group of openings has a width of about 0.7 μm and a length of about 35 μm. The spacing between two adjacent openings in the first group of openings is about 3 μm. The first group of openings is also referred to herein as a 0.7 / 3 array, that is, the opening width of the 0.7 / 3 array is about 0.7 μm, and the spacing of the 0.7 / 3 array is about 3 μm. In one embodiment, each of the second group of openings has a width of about 1.8 μm and a length that can be the same or different from the length of the first group of openings. The spacing between two adjacent openings in the second opening is about 2.0 μm. The second group of openings is also referred to as a 1.8 / 2.0 array, that is, the width and spacing of the 1.8 / 2.0 array are 1.8 μm and 2.0 μm, respectively. For the width of these openings and the center-to-center spacing, other embodiments may also adopt other values, and these values ​​are merely exemplary. A person skilled in the art would appreciate many variations, modifications, and substitutions.

[0038] The method 300 further includes: etching the exposed first surface portion and the second surface portion of the substrate to form a plurality of trenches (305). In one embodiment, each trench has a depth of about 0.8 μm. The method 300 further includes: epitaxially regrowing a semiconductor layer (307) in the trenches until a portion of the semiconductor layer in the second portion of the substrate becomes substantially planar relative to a lower surface of the hard mask layer, such as Figure 2D At the same time, the protruding portion of the semiconductor layer in the first portion of the substrate reaches a predetermined height above the upper surface of the hard mask layer. The predetermined height may be determined by the width of the trench. In one embodiment, the protruding portion may be self-limiting and have an isosceles triangle or trapezoid shape, the base of which isosceles triangle or trapezoid shape is flush with the substrate. For example, Figure 2D As shown, the protrusion may have a height equal to the product of the width of the base and √3 / 2. Figure 1 As explained, because the width of the first group of openings (e.g., 0.7 μm) is smaller than the width of the second group of openings (e.g., 1.8 μm), and the hard mask width of the first group of openings (e.g., 3-0.7=2.3 μm) is larger than the hard mask width of the second group of openings (e.g., 2.0-1.8=0.2 μm), the regrowth rate of a portion of the semiconductor layer in the first group of trenches is greater than the regrowth rate of a portion of the semiconductor layer in the second group of trenches, as shown in FIG. Figure 2D The method 300 may further include: removing the hard mask after the epitaxial regrowth process.

[0039] In some embodiments, the epitaxial regrowth of the semiconductor layer in the device region may include: regrowing the GaN layer and implanting P-type ions (e.g., magnesium, Mg). In one embodiment, the implantation of P-type ions may be performed simultaneously with the regrowth process. In another embodiment, the implantation of P-type ions may be performed after the regrowth process. In some embodiments, the dopant concentration is about 1×10 19 Atom / cm 3 Magnesium is used to dope the P-type GaN.

[0040] Figure 4 4 is a focused ion beam (FIB) cross section according to an embodiment of the present invention, which shows different growth on a 0.7 / 3 array (alignment mask array) and a 1.8 / 2.0 fin array (insert 401) for a 400 nm (nanometer) regrown wafer. Figure 4 , for the 400nm regrown wafer, all the trench openings in the 0.7 / 3 array show growth above the level of the hard mask, while the fin array shows non-planar growth with growth surfaces (valleys) below the hard mask (see insert 401). As shown in insert 401, the regrown semiconductor layer shows valleys in the large trenches (large trench width and small hard mask width) between two adjacent fins in the active device area, while the overgrowth in the alignment mask area (small trench width and large hard mask width) is almost complete. It can be expected that the self-limiting alignment mark in the alignment mark area reaches a predetermined height before the re-growth of the semiconductor layer has a planarized surface (the valley between two adjacent fins is completely filled).

[0041] Figure 5A is an oblique SEM image of a 0.7 / 3 array on a 600 nm regrown wafer according to an embodiment of the present invention. Figure 5A , the P-type GaN region (bright stripe) re-grows above the hard mask (dark region). The different contrasts between different P-type GaN regions are caused by the different top surfaces. The hard mask (dark region) corresponds to the hard mask layer disposed on the substrate surface, and the bright stripes between the hard masks correspond to the protrusions 211 extending above the hard mask surface, as shown in FIG. Figure 2D The regrowth extends over the hard mask and forms a triangle.

[0042] Figure 5B yes Figure 5A An enlarged portion of the end of the regrown zone is shown in FIG. Figure 5B , the regrown triangle (indicated by the dotted ellipse) extends above the hard mask (flat surface). Figure 2DAs discussed, the epitaxially grown GaN layer in the trench has a protruding portion extending above the hard mask surface. The protruding portion has a triangular shape, which allows the height of the protruding portion to be precisely controlled. Figure 2D , when the regrowing faces intersect at the vertices of the triangle, the regrowing process will stop. In other words, the re-growth of the GaN layer is self-limiting, and the re-growth is substantially stopped when the height or thickness of the protrusion extending above the hard mask surface reaches a predetermined value, which is determined by the width of the trench opening. In one embodiment, the protrusion above the hard mask has a height approximately equal to the square root of 3 divided by 2 times the width of the alignment mark opening. In one embodiment, a smooth surface of the regrowing face can be obtained at a growth temperature in the range of 850°C to 1100°C, preferably between 900°C and 1050°C, more preferably between about 930°C and about 970°C, and using H2 carrier gas at a pressure in the range of about 100mbar to about 800mbar. Therefore, according to some embodiments of the present invention, an alignment feature (mark, reference point) can be formed by forming a protruding member on a III-nitride substrate. The three-dimensional (3D) nature of the protrusion of the alignment feature improves visibility relative to the flat device area and allows alignment in the x-direction and the y-direction.

[0043] Figure 6 is a FIB cross section of a 0.7 / 3 array on an 800 nm regrown wafer according to an embodiment of the present invention. Figure 6 , the regrowth of the alignment mark in the trench has a triangular portion 701 extending above the hard mask. The alignment mark is self-limiting, as will be described below with reference to 7A to 7F As described, it is shown that the regrown layer between adjacent fins has a planarized (flat) surface at the 650nm regrown. It should be noted that layer 603 is a protective layer required only to protect the structure for the FIB process. Layer 603 does not exist in the normal process, it is required due to the preparation measurement of the FIB process.

[0044] Fig. 7A is an SEM image showing a vertical regrowth profile of a semiconductor layer in a depression between adjacent semiconductor fins on a 200nm regrowth substrate in a 1.8 / 2.0 fin array. During the 200nm regrowth process, there are gaps 710 below the lateral portion. These gaps 710 are located in a protective layer that only needs to protect the structure for the FIB process. The gaps 710 and the protective layer do not exist in the normal process, but are generated due to the preparation measurement of the FIB process.

[0045] Figure 7B701 is a SEM image showing a vertical regrowth profile of a semiconductor layer in a trench between adjacent semiconductor fins on a 400nm regrowth substrate in a 1.8 / 2.0 fin array. For this 400nm regrowth, there is a valley 712 between adjacent semiconductor fins. It should be noted that there is a layer 701 above the hard mask. Layer 701 is a protective layer that is only required to protect the structure for the FIB process. Layer 701 does not exist during the regrowth process, it is only required due to the preparation measurement of the FIB process.

[0046] Figure 7C is a SEM image showing a vertical regrowth profile of a semiconductor layer in a trench between adjacent semiconductor fins on a 500 nm regrowth substrate in a 1.8 / 2.0 fin array. There is a divot 714 between adjacent semiconductor fins.

[0047] Fig.7D is a SEM image showing a vertical regrowth profile of a semiconductor layer in a trench between adjacent semiconductor fins on a 550nm regrowth substrate in a 1.8 / 2.0 fin array. A depression 718 can still be seen between adjacent semiconductor fins. Figure 7C Compared with the depression 714 in FIG. 1 , the depression 716 is shallower. It can also be seen that Figure 7C and Fig.7D The depth of the recesses 714, 716 shown in FIG. 1 is greater in the lateral and vertical directions than in FIG. Figure 7B The valley 712 shown in FIG. 7 is smaller. The regrown layer between the fins on the 550 nm regrown substrate achieves an almost flat surface. Layer 701 is a protective layer for the FIB process. According to an embodiment of the present invention, the artifact layer 701 is not required.

[0048] Fig. 7E is a SEM image showing a vertical regrowth profile of a semiconductor layer in a recess between adjacent semiconductor fins on a 600 nm regrowth substrate in a 1.8 / 2.0 fin array. The upper surface of the regrowth semiconductor layer is substantially flat and flush with the lower surface of the hard mask.

[0049] Figure 7Fis an SEM image showing a vertical regrowth profile of a semiconductor layer in a trench between adjacent semiconductor fins on a 650nm regrowth substrate in a 1.8 / 2.0 fin array. The upper surface of the regrowth semiconductor layer is substantially flat and above the lower surface of the hard mask. Therefore, the inventors believe that in this example, for the initial etched trench depth, a regrowth thickness between 550nm and 650nm can provide an acceptable flat surface for the semiconductor layer. Of course, a person of ordinary skill in the art can appreciate a variety of variations, modifications, and substitutions. In one embodiment, the regrowth thickness in the active device area depends on the etch depth and the width ratio between the hard mask and the trench. In another embodiment, the flatness of the regrowth of the semiconductor layer in the active device area depends on the trench depth and the ratio between the fin width and the trench width. In one embodiment, the active device region has a trench depth of approximately 0.8 μm, a trench width of approximately 1.8 μm, and a hard mask width of approximately 0.2 μm (i.e., the fin width is approximately 0.2 μm), such that a width ratio between the trench in the active device region and the hard mask is 0.9 (1.8 / 0.2), thereby obtaining a flat surface of the regrown semiconductor layer at a regrown thickness of 550 nm to 650 nm.

[0050] According to an embodiment of the present invention, the hard mask material may include silicon dioxide, silicon nitride, aluminum nitride, aluminum oxide, titanium nitride, hafnium oxide, and combinations thereof. The thickness of the hard mask material may vary from a few nanometers to about four hundred nanometers. Conventional photolithography semiconductor process, for example, includes spin coating photoresist on the hard mask material, selectively exposing the photoresist, developing the photoresist, and etching the hard mask material using the photoresist as a mask. In one embodiment, the hard mask material may be deposited by PECVD. In one embodiment, the hard mask material may be deposited by LPCVD.

[0051] Figure 8 is an oblique SEM image showing a 0.3 μm wide×25 μm long fin array (0.3 / 2 array) with a 2 μm pitch on a 500 nm regrown wafer according to an embodiment of the present invention. Figure 8 , the epitaxial regrowth of the semiconductor layer (eg, gate layer) between the fins has a substantially flat surface and no non-uniformity. In other words, a fin array can be formed in the recess, which is surrounded by a gate layer having a substantially flat surface.

[0052] Fig. 9is an SEM image showing the PECVD nitride hard mask sidewall angle for a 0.3 μm hard mask width for a 0.3 μm×25 μm long fin array (0.3 / 2 array) with a 2 μm pitch according to an embodiment of the present invention. Fig. 9 , the nitride hard mask layer has a thickness of about 249.7 μm and an angle ranging from 78 degrees to about 82 degrees at a hard mask width of 0.3 μm. In one embodiment, the average hard mask angle is about 80 degrees. In contrast, the vertical sidewall angle of the nitride hard mask by LPCVD is about 83 degrees and more (not shown). In other words, the sidewall erosion of the PECVD nitride hard mask is more than the sidewall erosion of the LPCVD nitride hard mask, making the sidewalls of the PECVD nitride hard mask less perpendicular to the lateral surface of the substrate than the sidewalls of the LPCVD nitride hard mask. The inventors concluded that the LPCVD process is superior to the PECVD process.

[0053] Fig.10 A top plan view of a plurality of alignment mark groups having different geometries designed to produce topographical regrowth features protruding above the hard mask when the device fin array is substantially flush with the bottom of the hard mask according to an embodiment of the present invention is shown. Fig.10 , multiple alignment mark groups can be formed at the source metal mask patterning step (for example, the first step in the process flow of forming a vertical FinFET device). Different alignment mark groups may include: a plurality of alignment marks for forming strip grooves in the alignment mark area along the direction of multiple fins in the device area in a direction different from the direction of the fins in the device area, and a plurality of alignment marks for forming polygons in the alignment mark area. For example, the upper portion 1011 includes an alignment mark group having strips, the strips having different opening sizes, arranged parallel to each other, and spaced from each other by the hard mask width. The lower portion 1012 includes alignment mark groups having polygonal shapes (for example, square, rectangular, honeycomb, hexagonal, etc.) and different sizes.

[0054] Included Fig.11A and Fig. 11B FIG. 11 shows a top view of an alignment mark group having different geometries of an alignment mark pattern that can be used as a hard mask according to some embodiments of the present invention. Fig.11A, the upper part of the alignment mark group includes a plurality of strips having different geometric shapes arranged in the vertical direction and the horizontal direction. These strips have different widths and are spaced apart from each other at different distances. The lower part of the alignment mark group includes discrete small geometric shapes, which can be square or hexagonal in the transparent part 1101, the semi-transparent (not completely transparent) part 1102 or the opaque part 1103. Fig. 11B 1 shows the alignment mask result on a 500nm regrown wafer according to an embodiment of the present invention. The inventors also found that Fig.11A The hexagonal and hexagonal ring patterned alignment mark groups 1104 in FIG. 1 are not affected by stress and show significant growth over the hard mask.

[0055] Fig. 12A A top plan view of a hexagonal annular pattern that can be formed on a semiconductor substrate according to an embodiment of the present invention is shown. In one embodiment, the hexagonal annular pattern includes an array of substantially hexagonal alignment marks. The hard mask layer can be formed by covering the hard mask layer with a patterned photoresist. Fig. 12A The patterned photoresist may include a plurality of openings, the plurality of openings having a plurality of first openings corresponding to an array of hexagonal alignment marks in the alignment mark region and a plurality of second openings corresponding to an array of semiconductor fins disposed in the device region. A photolithography process is then performed to generate an array of hexagonal openings (hexagonal ring openings) in the hard mask in the alignment mark region and an array of fins in the device region, such as Figure 2A and Figure 2B As shown. A hard mask is used as a mask to etch the underlying semiconductor substrate to form grooves in the alignment mark area and the device area. In one embodiment, each side of the hexagonal ring-shaped opening has a width of approximately 0.7 μm and a length of approximately 11.5 μm. In one embodiment, each opening in the device area has a width of 1.8 μm and a length of 25 μm. An epitaxial regrowth process of the semiconductor layer is then performed in the trench to form a protruding portion of the semiconductor layer extending to a predetermined height above the upper surface of the semiconductor substrate. In one embodiment, the hexagonal edges are aligned parallel to the intersection of the c-plane and the m-plane of the substrate (i.e., along the

[1000] ,

[0100] , and

[0010] directions). As Figure 2D As described, the epitaxial regrowth process is self-limiting. In one embodiment, the epitaxial regrowth process may be a P-type GaN regrowth. In one embodiment, the P-type GaN regrowth may be a MOVPE process.

[0056] Fig. 12B Shows Fig. 12A A magnified portion of the hexagonal ring pattern in the image. Fig. 12C According to an embodiment of the present invention Fig. 12A Oblique SEM image of a magnified portion of the hexagonal ring pattern in FIG. It should be noted that the hexagonal ring patterned alignment mark has significant growth above the hard mask (dark background) and has well-defined triangular sides. Fig. 12C As shown, the growth of the alignment mark is carried out along six directions aligned with the m-plane of the hexagonal crystal structure that constrains the growth. Therefore, the outer surface (i.e., the growth surface) of the hexagonal ring pattern defines six directions, so that the hexagonal ring pattern can be called a multi-directional alignment mark, for example, at least a three-dimensional growth surface. For example, the outer surface of the hexagonal ring includes (10-11), (01-11), (-1101), (-1011), (0-111) and (1-101) planes. It should be noted that the inner surface of the hexagonal ring pattern is aligned with the corresponding outer surface.

[0057] Fig.13A An array of hexagonal pyramids that may be used as fiducials (alignment marks) according to an embodiment of the present invention is shown. Fig. 13B Shows Fig.13A An enlarged portion of an array of hexagonal pyramids in FIG. Problems during the photolithography process may result in irregular sizes of the pyramids. The regrowth of the hexagonal pyramids is self-limiting, and the growth essentially stops when the six sides of the hexagonal pyramids intersect each other. Therefore, an embodiment of the present invention provides three-dimensional and six-directional alignment marks, wherein the alignment marks are defined by a three-dimensional shape formed by the six sides of the hexagonal pyramids, wherein each hexagonal pyramid has a different growth direction. In one embodiment, the six sides of the hexagonal pyramids are (10-11), (01-11), (-1101), (-1011), (0-111) and (1-101) planes.

[0058] The above-mentioned embodiment has a vertically regrown semiconductor layer in both the alignment mark region and the device (active) region. The alignment mark region includes an alignment mark array, which may include Fig.10The pattern shown. The device area or active area may include a plurality of semiconductor fins arranged parallel to each other. The alignment mark and the semiconductor fin may be arranged in the same direction or in different directions. In some embodiments, the alignment mark may be set at the periphery of the wafer (substrate), the periphery of the device boundary, or in the cutting line of the wafer (substrate). The regrown portion of the semiconductor layer in the alignment mark area protrudes above the upper surface of the hard mask layer. In one embodiment, the regrown portion of the semiconductor layer in the device area has an upper surface that is substantially flush with the lower surface of the hard mask layer, that is, when the hard mask layer is removed, the upper surface is substantially flush with the upper surface of the substrate. In one embodiment, the surface of the substrate is in the c-plane, and the regrown portion of the semiconductor layer is oriented along the m-plane direction (that is, the regrown edge intersecting the c-plane is in one of the

[1000] ,

[0100] or

[0010] directions).

[0059] like Fig.10 and Fig.11A As shown, many possible alignment mark patterns can be used. In one embodiment, the alignment marks may include Fig. 12A In one embodiment, each side of the hexagonal ring pattern is aligned with the m-plane of the substrate. In one embodiment, the alignment mark may include Fig.13A An array of hexagonal patterns is shown. In one embodiment, each side of the lower surface of the hexagonal pattern is aligned with the m-plane of the substrate. In one embodiment, the substrate is a III-V compound substrate. In one embodiment, the substrate comprises GaN.

[0060] In one embodiment, the protruding portion of the semiconductor layer in the alignment region is self-limiting and has a thickness of height H=(√3 / 2)×W, where W is the width of the trench opening defined by the hard mask layer.

[0061] In one embodiment, the protruding portion of the semiconductor layer in the alignment region is an isosceles triangle or a trapezoid having a base angle in the range of 58 to 65 degrees in a cross-sectional view.

[0062] In one embodiment, the alignment mark region has a plurality of trenches, each trench having a depth of about 0.8 μm, a width of about 0.7 μm, and a width of the hard mask layer of about 3 μm between two adjacent openings.

[0063] In some embodiments, the ratio of the width of the opening in the alignment mark area to the width of the hard mask layer is less than 1, while the ratio of the width of the opening in the device area to the width of the hard mask layer is much greater than 1. In one embodiment, the ratio of the width of the opening for epitaxial growth of the alignment mark to the width of the hard mask layer disposed between two adjacent openings is approximately 0.233. In one embodiment, the ratio of the width of the opening for epitaxial growth of the flat epitaxial area in the device area to the width of the hard mask layer disposed between two adjacent openings is between 6 and 10, for example, approximately 9. In one embodiment, each opening may include a hexagonal ring pattern. In one embodiment, each side of the hexagonal ring pattern is aligned with the m-plane of the III-V (e.g., III-nitride) compound substrate.

[0064] In one embodiment, the hard mask layer in the device or active area includes an array of elongated openings arranged parallel to each other and configured to form a plurality of semiconductor fins. In one embodiment, each of the elongated openings has a width in the range of about 0.2 μm to about 0.3 μm, a length in the range of about 25 μm to about 1000 μm, and a spacing between two adjacent elongated openings in the range of about 1.9 μm to about 10 μm. The scope of the present invention is not limited to the arrangement of the fins in the drawings associated with the alignment marks.

[0065] In one embodiment, the substrate is a III-V compound substrate including an N-type GaN epitaxial layer, and the semiconductor layer includes a P-type GaN regrown epitaxial layer.

[0066] The embodiments disclosed herein are not limited in scope by the specific embodiments described herein. In addition to the embodiments described herein, various modifications of these embodiments of the present invention will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. In addition, although some embodiments of the present invention have been described in the context of being specifically implemented in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that their applicability is not limited thereto, and embodiments of the present invention may be advantageously implemented in any environment for any purpose.

Claims

1. A method for forming an alignment mark, the method comprising: providing a III-V compound substrate having a device region and an alignment mark region, wherein the III-V compound substrate is characterized by a processed surface; forming a hard mask layer having a first set of openings over the alignment mark region exposing a first surface portion of the processed surface of the III-V compound substrate and a second set of openings over the device region exposing a second surface portion of the processed surface of the III-V compound substrate; etching the first surface portion and the second surface portion of the III-V compound substrate using the hard mask layer as a mask to form a plurality of trenches; as well as Without removing the hard mask layer, a semiconductor layer is epitaxially regrown in the trench to form alignment marks, wherein each of the alignment marks extends to a predetermined height above the processed surface of the III-V compound substrate.

2. The method according to claim 1, wherein: The III-V compound substrate includes GaN.

3. The method according to claim 1, wherein: Each of the trenches has a depth of about 0.8 μm.

4. The method according to claim 1, wherein: Each of the trenches has a width of about 0.7 μm, and a width of the hard mask layer between two adjacent openings is about 3 μm.

5. The method according to claim 1, wherein: A ratio of a width of an opening to a width of the hard mask layer between two adjacent openings is about 0.

233.

6. The method according to claim 1, wherein: The first set of openings includes an array of hexagonal annular patterns.

7. The method according to claim 6, wherein: Each side of the hexagonal ring pattern is aligned with the m-plane of the III-V compound substrate.

8. The method according to claim 1, wherein: The predetermined height is determined using the following formula: H=(√3 / 2)×W, Wherein H is the predetermined height, and W is the width of the trench opening.

9. The method according to claim 1, wherein: The alignment mark is characterized by an isosceles triangle shape having a base angle in a range of 58 to 65 degrees in a cross-sectional view.

10. The method according to claim 1, wherein: The second set of openings includes an array of elongated openings arranged parallel to one another configured to form a plurality of semiconductor fins.

11. The method according to claim 10, wherein: Each of the elongated openings has a width in the range of about 0.2 μm to about 0.3 μm, a length in the range of about 100 μm to about 1000 μm, and a spacing between two adjacent elongated openings in the range of about 1.9 μm to about 10 μm.

12. The method according to claim 1, wherein: The III-V compound substrate includes an N-type GaN epitaxial layer, and the semiconductor layer includes a P-type GaN epitaxial layer.

13. The method according to claim 1, wherein: Epitaxially regrowth of the semiconductor layer is self-limiting in the alignment mark region.

14. A semiconductor device comprising: A III-V compound substrate including a device region and an alignment mark region having a plurality of grooves; as well as A plurality of three-dimensional alignment marks, each of the plurality of three-dimensional alignment marks is disposed in one of the plurality of grooves in the alignment mark region, and each of the plurality of three-dimensional alignment marks includes a protruding portion extending above a surface of the III-V compound substrate.

15. The semiconductor device according to claim 14, wherein: Each of the three-dimensional alignment marks comprises a hexagonal, ring-shaped alignment mark in plan view having a predetermined height and characterized by at least a three-dimensional growth surface.

16. The semiconductor device according to claim 15, wherein: The protrusion portion has an isosceles triangle or trapezoid shape having a base angle in the range of 58 to 65 degrees in a cross-sectional view.

17. The semiconductor device according to claim 15, wherein: The protruding portion has an isosceles triangle or trapezoid shape having a bottom side substantially flush with a surface of the III-V compound substrate in a cross-sectional view.

18. The semiconductor device according to claim 17, wherein: The protrusion has an isosceles triangle shape, and the predetermined height is determined using the following formula: H=(√3 / 2)×W, Wherein H is the predetermined height, and W is the width of the base of the isosceles triangle.

19. The semiconductor device according to claim 14, wherein: The III-V compound substrate includes an N-type GaN epitaxial layer, and the plurality of three-dimensional alignment marks include a P-type GaN epitaxial layer.

20. The semiconductor device according to claim 14, wherein The device region includes a plurality of semiconductor fins arranged in parallel with each other, wherein a regrown layer between each of the plurality of semiconductor fins has a regrown surface lower than the protruding portion of each of the plurality of three-dimensional alignment marks.

21. A method for forming an alignment mark array, the method comprising: providing a III-V compound substrate having a device region and an alignment mark region, wherein the III-V compound substrate is characterized by a processed surface; forming a hard mask layer having a first set of openings over the alignment mark region exposing a first surface portion of the processed surface of the III-V compound substrate and a second set of openings over the device region exposing a second surface portion of the processed surface of the III-V compound substrate, wherein each of the first set of openings corresponds to an alignment mark in the alignment mark array; etching the first surface portion and the second surface portion of the III-V compound substrate using the hard mask layer as a mask to form a plurality of trenches; as well as A semiconductor layer is epitaxially regrown in the trench to form an alignment mark extending to a predetermined height above the processed surface of the III-V compound substrate to provide the alignment mark as a plurality of three-dimensional alignment marks.

22. The method according to claim 21, wherein: Each of the first set of openings has a polygonal shape.

23. The method according to claim 22, wherein: Each of the first set of openings has a hexagonal shape.

24. The method according to claim 23, wherein: Each of the alignment marks has a hexagonal shape and the alignment mark array is a two-dimensional array.

25. The method according to claim 22, wherein: Each of the first set of openings has a rectangular shape.

26. The method of claim 22, wherein: Each of the first set of openings has a honeycomb shape.

27. The method of claim 21, wherein: The first set of openings are of different sizes; Epitaxially regrowing the semiconductor layer includes epitaxially regrowing without removing the hard mask layer; and The predetermined height is higher than the hard mask layer.

28. The method of claim 21, wherein: The predetermined height is determined using the following formula: H=(√3 / 2)×W, Wherein H is the predetermined height, and W is the width of the trench opening.

29. The method according to claim 21, wherein: The second set of openings includes an array of elongated openings arranged parallel to one another configured to form a plurality of semiconductor fins.

30. The method of claim 21, wherein: The III-V compound substrate includes GaN.

31. A semiconductor device comprising: A III-V compound substrate comprising a device region and an alignment mark region, wherein the alignment mark region comprises a plurality of recesses; as well as An alignment mark group includes a plurality of three-dimensional alignment marks, each of the plurality of recesses being filled by a single three-dimensional alignment mark of the plurality of three-dimensional alignment marks, and each of the plurality of three-dimensional alignment marks including a protruding portion extending above a surface of the III-V compound substrate.

32. The semiconductor device according to claim 31, wherein Each of the plurality of three-dimensional alignment marks is a polygon in a plan view.

33. The semiconductor device according to claim 32, wherein: Each of the plurality of three-dimensional alignment marks has a hexagonal shape in a plan view.

34. The semiconductor device according to claim 33, wherein: The alignment mark group includes a two-dimensional array of the plurality of three-dimensional alignment marks.

35. The semiconductor device according to claim 32, wherein: Each of the plurality of three-dimensional alignment marks is rectangular in a plan view.

36. The semiconductor device according to claim 32, wherein: Each of the plurality of three-dimensional alignment marks has a honeycomb shape in a plan view.

37. The semiconductor device according to claim 31, wherein: The plurality of three-dimensional alignment marks have different sizes.

38. The semiconductor device according to claim 31, wherein The protrusion portion has an isosceles triangle or trapezoid shape having a base angle in the range of 58 to 65 degrees in a cross-sectional view.

39. The semiconductor device according to claim 31, wherein: The III-V compound substrate includes an N-type GaN epitaxial layer, and the plurality of three-dimensional alignment marks include a P-type GaN epitaxial layer.

40. The semiconductor device according to claim 31, wherein The device region includes a plurality of semiconductor fins arranged in parallel with each other, wherein a regrown layer between the plurality of semiconductor fins has a regrown surface lower than the protruding portion of each of the plurality of three-dimensional alignment marks.

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