Display device

Abstract

A display device is provided. The display device includes pixels connected to scan lines and data lines intersecting the scan lines, wherein each of the pixels includes a light emitting element, a drive transistor that controls a drive current supplied to the light emitting element according to a data voltage applied from the data line, and a switching transistor that applies the data voltage of the data line to the drive transistor according to a scan signal applied from the scan line. The drive transistor includes a first active layer having an oxide semiconductor and a first gate electrode below the first active layer. The switching transistor includes a second active layer having an oxide semiconductor that is the same as the oxide semiconductor of the first active layer and a second gate electrode below the second active layer. At least one of the drive transistor and the switching transistor includes an oxide layer over each of the active layers.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2019-0087678, filed on July 19, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to a display device and a method of manufacturing the display device, and for example, to a display device including a thin-film transistor comprising an oxide layer. Background Technology

[0003] With the development of multimedia technology, display devices have become increasingly important. Therefore, various types of display devices are currently in use, such as organic light-emitting diode (OLED) devices and liquid crystal display (LCD) devices.

[0004] Display devices are used to display images and include display panels such as organic light-emitting display panels or liquid crystal display panels. Among them, the light-emitting display panel may include light-emitting elements. For example, light-emitting diodes (LEDs) may include organic light-emitting diodes (OLEDs) that use organic materials as fluorescent materials and inorganic light-emitting diodes that use inorganic materials as fluorescent materials.

[0005] Such a display device includes a display panel, a gate driver, a data driver, and a timing controller. The display panel includes data lines, gate lines, and pixels formed at the intersections of the data lines and the gate lines. When a gate signal is supplied to the gate lines using a thin-film transistor as a switching element, each pixel receives a data voltage from the data lines. Each pixel emits light with a set (e.g., predetermined) brightness according to the data voltage.

[0006] Display devices capable of displaying images at ultra-high definition (UHD) resolution have already been released. Recently, a display device capable of displaying images at 8K ultra-high definition (UHD) resolution is under development. UHD refers to a resolution of 3840×2160, and 8K UHD refers to a resolution of 7680×4320.

[0007] In high-resolution display devices, the number of pixels increases, thus reducing the drive current of each pixel. Consequently, the drive voltage range of the drive transistors in each pixel decreases. Summary of the Invention

[0008] This disclosure provides a display device including a driving transistor and a switching transistor, the driving transistor and the switching transistor including an active layer having an oxide semiconductor and an oxide layer.

[0009] It should be noted that the purpose of this disclosure is not limited to the purposes mentioned above, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0010] According to some embodiments, the display device may include a driving transistor and a switching transistor, both having gate electrodes below the active layer, and at least one of them may include an oxide layer above the active layer as an oxygen supply layer. When the switching transistor includes an oxide layer, the device characteristics and reliability of the display device can be improved. When the driving transistor includes an oxide layer, a wide range of driving voltages can be achieved.

[0011] It should be noted that the aspects and / or effects of this disclosure are not limited to those described above, and other aspects and / or effects of this disclosure will be apparent to those skilled in the art from the following description.

[0012] According to some embodiments of the present disclosure, a display device includes: a substrate including a display area and a pad area; a first conductive layer located on the substrate, the first conductive layer including a gate electrode in the display area and a pad electrode in the pad area; a buffer layer located on the first conductive layer, the buffer layer covering the gate electrode and exposing portions of the pad electrode; a first semiconductor layer located on the buffer layer and including an oxide semiconductor, the first semiconductor layer including a first active layer and a second active layer in the display area; a second conductive layer located on the first semiconductor layer, the second conductive layer including a source electrode and a drain electrode in the display area; a first protective layer located on the second conductive layer, the first protective layer covering the source electrode and the drain electrode and exposing portions of the pad electrode; a second semiconductor layer located on the first protective layer and including an oxide semiconductor, the second semiconductor layer including at least one oxide layer in the display area; a first planarization layer located on the second semiconductor layer; and a third conductive layer located on the first planarization layer, the third conductive layer including a first electrode electrically connected to one of the source electrodes through a contact hole penetrating the first planarization layer and the first protective layer, wherein at least one oxide layer of the second semiconductor layer is located above at least one selected from the first active layer and the second active layer.

[0013] In some embodiments, the oxide semiconductor of the first semiconductor layer and the second semiconductor layer may include at least one selected from indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf).

[0014] In some embodiments, the second conductive layer may include: a first source electrode located on a first side of the first active layer; a first drain electrode located on a second side of the first active layer; a second source electrode located on a first side of the second active layer; and a second drain electrode located on a second side of the second active layer.

[0015] In some embodiments, one side of the first source electrode may be aligned with one side of the first active layer, and one side of the first drain electrode may be aligned with the other side of the first active layer, and the other side of the first source electrode and the other side of the first drain electrode may be located on the first active layer.

[0016] In some embodiments, one side of the second source electrode may be located on the buffer layer, and one side of the second drain electrode may be located on the buffer layer, and the other side of the second source electrode and the other side of the second drain electrode may be located on the second active layer.

[0017] In some embodiments, the first protective layer may include a plurality of grooves, a portion of the upper surface of the first protective layer being recessed in the plurality of grooves, and the grooves may include a first groove between the first source electrode and the first drain electrode and a second groove between the second source electrode and the second drain electrode.

[0018] In some embodiments, the oxide layer of the second semiconductor layer can contact the gate electrode through a contact hole that penetrates the first protective layer and the buffer layer to expose a portion of the upper surface of the gate electrode.

[0019] In some embodiments, the oxide layer may include a first oxide layer above the first active layer.

[0020] In some embodiments, the first groove may be stacked with the first active layer in the thickness direction, and the first oxide layer may be located in the first groove.

[0021] In some embodiments, the second groove may be stacked with the second active layer in the thickness direction, and the oxide layer may be a second oxide layer in the second groove above the second active layer.

[0022] In some embodiments, the first protective layer may include a first contact hole that penetrates the first protective layer to expose a portion of the upper surface of the first source electrode and a second contact hole that penetrates the first protective layer to expose a portion of the upper surface of the first drain electrode.

[0023] In some embodiments, the second semiconductor layer may include a first oxide pattern that contacts the first source electrode through a first contact hole and a second oxide pattern that contacts the first drain electrode through a second contact hole.

[0024] In some embodiments, the first planarization layer may include a third contact hole that penetrates the first planarization layer and the first protective layer to expose the upper surface of the second source electrode, and a fourth contact hole that penetrates the first planarization layer and the first protective layer to expose the upper surface of the second drain electrode.

[0025] In some embodiments, the third conductive layer may include a first electrode pattern that contacts the second source electrode through a third contact hole and a second electrode pattern that contacts the second drain electrode through a fourth contact hole.

[0026] In some embodiments, the buffer layer may include a fifth contact hole that penetrates the buffer layer to expose a portion of the upper surface of the pad electrode, the second semiconductor layer may be located in the pad region and may also include a third oxide pattern that contacts the pad electrode through the fifth contact hole.

[0027] In some embodiments, the first protective layer may further include a sixth contact hole that penetrates the first protective layer to expose a portion of the third oxide pattern and a portion of the upper surface of the buffer layer, and the third conductive layer may further include a third electrode pattern located in the pad region and in contact with the third oxide pattern through the sixth contact hole.

[0028] According to some embodiments of the present disclosure, a display device includes pixels connected to scan lines and data lines intersecting the scan lines, wherein each of the pixels includes: a light-emitting element; a driving transistor that controls a driving current supplied to the light-emitting element according to a data voltage applied from the data lines; and a switching transistor that applies the data voltage of the data lines to the driving transistor according to a scan signal applied from the scan lines, wherein the driving transistor includes a first active layer having an oxide semiconductor and a first gate electrode below the first active layer, wherein the switching transistor includes a second active layer having an oxide semiconductor of the same type as the first active layer and a second gate electrode below the second active layer, and wherein at least one selected from the driving transistor and the switching transistor includes an oxide layer above each of the active layers of the selected transistor.

[0029] In some embodiments, the oxide layer comprises an oxide semiconductor, and the oxide semiconductor of the oxide layer may include at least one selected from indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf).

[0030] In some embodiments, the first protective layer may be located on the first active layer of the driving transistor and on the second active layer of the switching transistor, and the driving transistor may further include a first oxide layer located on the first protective layer and stacked with the first active layer in the thickness direction.

[0031] In some embodiments, the switching transistor may further include a second oxide layer located on the first protective layer and stacked with the second active layer in the thickness direction. Attached Figure Description

[0032] Some aspects and features of this disclosure will become more apparent from the description of some embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0033] Figure 1 This is a plan view of a display device according to some embodiments of the present disclosure;

[0034] Figure 2 This is a plan view illustrating examples of display devices according to some embodiments of the present disclosure;

[0035] Figure 3 yes Figure 2 The equivalent circuit diagram of one of the pixels;

[0036] Figure 4 It is shown Figure 2 The equivalent circuit diagram of one of the pixels;

[0037] Figure 5 This is a plan view illustrating a driving transistor according to some embodiments of the present disclosure;

[0038] Figure 6 This is a plan view illustrating a switching transistor according to some embodiments of the present disclosure;

[0039] Figure 7 This is a cross-sectional view of a display device according to some embodiments of the present disclosure;

[0040] Figures 8 to 10 This is a graph showing the drive current based on the gate voltage of the switching transistor according to some embodiments of the present disclosure;

[0041] Figure 11 It is along Figure 6 A cross-sectional view taken by line Q1-Q1';

[0042] Figure 12 This is a flowchart illustrating the process steps for manufacturing a display device according to some embodiments of the present disclosure;

[0043] Figures 13 to 25 This is a cross-sectional view illustrating the process steps for manufacturing a display device according to some embodiments of the present disclosure;

[0044] Figure 26 This is a plan view illustrating a driving transistor according to some embodiments of the present disclosure;

[0045] Figure 27 It shows including Figure 26 A cross-sectional view of a display device with driving transistors according to some embodiments of the present disclosure;

[0046] Figure 28 This is a cross-sectional view of a display device according to some embodiments of the present disclosure;

[0047] Figure 29 and Figure 30This is a cross-sectional view illustrating an example of a display device according to some embodiments of the present disclosure;

[0048] Figures 31 to 33 It shows the manufacturing process. Figure 30 A cross-sectional view of some processing steps in a method of a display device according to some embodiments of the present disclosure;

[0049] Figure 34 This is a plan view illustrating a switching transistor according to some embodiments of the present disclosure;

[0050] Figure 35 It shows including Figure 34 A cross-sectional view of a display device with switching transistors according to some embodiments of the present disclosure; and

[0051] Figure 36 This is a cross-sectional view of a display device according to some embodiments of the present disclosure. Detailed Implementation

[0052] Some embodiments of this disclosure will now be described more fully below with reference to the accompanying drawings, in which some embodiments of this disclosure are illustrated. However, the subject matter of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are described so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0053] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on said other layer or substrate, or there may be an intermediate layer. Throughout the specification, the same reference numerals indicate the same or similar components (e.g., features).

[0054] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure. Similarly, the second element may also be referred to as the first element.

[0055] In the following description, some embodiments of this disclosure will be described with reference to the accompanying drawings.

[0056] Figure 1 This is a plan view illustrating a display device according to some embodiments of the present disclosure.

[0057] Reference Figure 1The display device 1 displays moving or still images. The display device 1 can refer to (e.g., it may be) any electronic device that includes a display screen. For example, the display device 1 may include a television, laptop computer, monitor, electronic billboard, Internet of Things device, mobile phone, smartphone, tablet PC, electronic watch, smartwatch, watch phone, head-mounted display device, mobile communication terminal, electronic notebook, e-book reader, portable multimedia player (PMP), navigation device, game console, digital camera, camcorder, etc.

[0058] The display device 1 includes a display panel 10 for providing a display screen. Examples of the display panel 10 may include an LED display panel, an organic light-emitting display panel, a quantum dot light-emitting display panel, a plasma display panel, a field emission display panel, etc. In the following description, the display panel 10 is used as (e.g., assumed to be) an LED display panel, but this disclosure is not limited thereto. Any other suitable display panel may be used.

[0059] The shape of the display device 1 can be modified in various ways. For example, the display device 1 can have shapes such as a rectangle with a longer horizontal (e.g., horizontal) side, a rectangle with a longer vertical side, a square, a quadrilateral with rounded corners (vertices), other polygons, a circle, etc. The shape of the display area DPA of the display device 1 can be similar to the overall shape of the display device 1. For example, Figure 1 The display device 1 and the display area DPA are shown, both of which are rectangular in shape with a longer horizontal side.

[0060] Display device 1 may include a display area DPA and a non-display area NDA. An image may be displayed in the display area DPA. No image is displayed in the non-display area NDA. The display area DPA may be referred to as the active area, and the non-display area NDA may be referred to as the inactive area.

[0061] The display area DPA can occupy approximately the center of the display device 1. The display area DPA can include a plurality of pixels PX. When viewed from above (e.g., when the display device 1 is viewed from above, making the display device 1 visible in a plane), the plurality of pixels PX can be arranged in a matrix. When viewed from above, the shape of each pixel PX can be, but is not limited to, a rectangle or a square. In some embodiments, each pixel PX can be a rhombus shape with sides inclined relative to a first direction DR1.

[0062] A non-display area NDA may surround the display area DPA. The non-display area NDA may completely or partially surround the display area DPA (e.g., completely or partially around the display area DPA). The display area DPA may have a rectangular shape, and the non-display area NDA may be adjacent to the sides (e.g., four sides) of the display area DPA. The non-display area NDA may provide (e.g., define) a border for the display device 1. The non-display area NDA may include a first non-display area NDA1, a second non-display area NDA2, a third non-display area NDA3, and a fourth non-display area NDA4.

[0063] In the non-display area NDA, driving circuitry or driving elements for driving the display area DPA may be included. According to some embodiments of this disclosure, the pad (“pad”, or “solder pad”) unit is located on the first longer side of the display device 1 (e.g., ...). Figure 1 The first non-display area NDA1 adjacent to the lower side of the display device 1 and the second longer side of the display device 1 (e.g., the lower side of the display device 1) Figure 1 The second non-display area NDA2, adjacent to the upper edge of the display unit, is located on the display substrate of the display device 1. External devices EXD can be mounted on the pad electrodes of each of the pad cells. Some examples of external devices EXD may include connection films, printed circuit boards, driver chips DIC, connectors, wire connection films, etc. The scan driver SDR, directly on the display substrate of the display device 1, can be located adjacent to the first shorter edge of the display device 1 (e.g., the upper edge of the display unit). Figure 1 The third non-display area NDA3 is located on the left side of the image.

[0064] Figure 2 This is a plan view illustrating an example of a display device according to some embodiments of the present disclosure.

[0065] Reference Figure 2 The display device 1 may include a display panel 10 and multiple lines on the display panel 10. The multiple lines may include a scan line SCL, a sensing signal line SSL, a data line DTL, a reference voltage line RVL, a first power supply voltage line ELVDL, etc.

[0066] Display panel 10 may include a display area DPA in which pixels PX display an image and a non-display area NDA that is a peripheral area of ​​display area DPA. When display panel 10 includes a curved portion, display area DPA may be on the curved portion. In some embodiments, the image of display panel 10 may be seen on the curved portion (e.g., from the curved portion, through the curved portion, etc.).

[0067] In some embodiments, pixels PX, along with scan lines SCL, data lines DTL, and power lines connected to pixels PX, can be arranged in a display area DPA. Scan lines SCL can be arranged on a second direction DR2 intersecting a first direction DR1 and extending along the first direction DR1, while data lines DTL can be arranged on the first direction DR1 and extending along the second direction DR2. Each pixel PX can be connected to at least one scan line SCL and at least one data line DTL.

[0068] Each pixel PX may include a driving transistor, at least one switching transistor, a light-emitting element, and a capacitor. Because the switching transistor turns on in response to a scan signal from the scan line SCL, a data voltage from the data line DTL can be applied to the gate electrode of the driving transistor. When the data voltage is applied to the gate electrode, the driving transistor can supply a driving current to the light-emitting element, thereby emitting light. The driving transistor and at least one switching transistor may be thin-film transistors. The light-emitting element can emit light proportionally to the driving current from the driving transistor. The light-emitting element may be an organic light-emitting diode comprising a first electrode, an organic emitting layer, and a second electrode. The capacitor can keep the data voltage applied to the gate electrode of the driving transistor constant (e.g., substantially constant).

[0069] The non-display area NDA can be defined as the region extending from the outer edge (e.g., outer edge) of the display area DPA to the outer edge of the display panel 10. The scan driver SDR, used to apply scan signals to the scan line SCL, can be located on one side of the non-display area NDA. Furthermore, the pad area PDA can be as follows: Figure 2 The ground shown is located above and below the non-display area NDA (e.g., as shown in the image). Figure 1 As shown in the diagram, this occurs in the first non-display area NDA1 and the second non-display area NDA2. The pad area PDA may include multiple pads WPDs that are electrically connected to lines on the display panel 10.

[0070] The scan line SCL and the sensing signal line SSL can extend along the first direction DR1. The scan line SCL and the sensing signal line SSL can be connected to the scan driver SDR. The scan driver SDR can include driving circuitry. The scan driver SDR can be located in the third non-display area NDA3 on the display panel 10, but embodiments of this disclosure are not limited thereto. For example, the scan driver SDR can be in the fourth non-display area NDA4 or both the third non-display area NDA3 and the fourth non-display area NDA4. The scan driver SDR can be connected to the signal connection wiring CWL. At least one end of the signal connection wiring CWL can include a pad WPD_CW in the first non-display area NDA1 and / or the second non-display area NDA2. The signal connection wiring CWL can be connected to an external device EXD.

[0071] The data line DTL and the reference voltage line RVL may extend in a second direction DR2, intersecting the first direction DR1. The first power supply voltage line ELVDL may include a portion extending in the second direction DR2. The first power supply voltage line ELVDL may also include a portion extending in the first direction DR1. The first power supply voltage line ELVDL may have, but is not limited to, a mesh structure. The second power supply voltage line ELVSL (see...) Figure 3 It can be displayed on the display panel 10.

[0072] The pad WPD can be located at at least one end of the data line DTL, the reference voltage line RVL, and the first power supply voltage line ELVDL. Each of the pads WPD can be located in the pad region PDA of the non-display area NDA. According to some embodiments of this disclosure, the pad of the data line DTL (hereinafter referred to as the data pad) WPD_DT can be located in the pad region PDA below the non-display area NDA (e.g., at the first non-display area NDA1). The pad of the reference voltage line RVL (hereinafter referred to as the reference voltage pad) WPD_RV and the pad of the first power supply voltage line ELVDL (hereinafter referred to as the first power supply voltage pad) WPD_ELVD can be located in the pad region PDA above the non-display area NDA (e.g., at the second non-display area NDA2). As another example, the data pad WPD_DT, the reference voltage pad WPD_RV, and the first power supply voltage pad WPD_ELVD can all be located in the same area, such as in the pad region PDA below the non-display area NDA (e.g., at the first non-display area NDA1). External components (EXDs) can be mounted on each of the pads in the WPD. The external components (EXDs) can be mounted on the pads in the WPD via methods such as anisotropic conductive films, ultrasonic bonding, etc.

[0073] Each of the pixels PX in the display panel 10 includes a pixel driving circuit. The lines described above may pass through (e.g., may be connected to) each of the pixels PX or its periphery to apply a driving signal to the pixel driving circuit. The pixel driving circuit may include transistors and capacitors. The number of transistors and capacitors in each pixel driving circuit may vary. In some of the embodiments described below, the pixel driving circuit has a 3T1C structure including three transistors and one capacitor. However, embodiments of this disclosure are not limited thereto. For example, embodiments of the pixel driving circuit may have a 2T1C structure, a 7T1C structure, a 6T1C structure, or any other suitable structure.

[0074] Figure 3 According to some embodiments Figure 2 A circuit diagram of one of the pixels.

[0075] Reference Figure 3 A pixel PX may include a driving transistor DRT, a switching transistor SCT, a light-emitting element EL, and a capacitor Cst. Although Figure 3 The illustration shows a pixel PX with a 2T1C structure comprising a driving transistor DRT, a switching transistor SCT, and a capacitor Cst; however, embodiments of this disclosure are not limited thereto. The pixel PX may include any suitable number of transistors (e.g., more than two transistors) and any suitable number of capacitors (e.g., more than one capacitor).

[0076] Each of the driving transistor (DRT) and the switching transistor (SCT) may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other may be a drain electrode.

[0077] Each of the driving transistor DRT and the switching transistor SCT can be implemented as a thin-film transistor. Although Figure 3 The driving transistor DRT and the switching transistor SCT are shown to be n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), but embodiments of this disclosure are not limited thereto. The driving transistor DRT and the switching transistor SCT may also be p-type MOSFETs. In some such embodiments, the positions of the source and drain electrodes of each of the driving transistor DRT and the switching transistor SCT can be varied. In the following description, the driving transistor DRT and the switching transistor SCT are employed as (e.g., assumed to be) n-type MOSFETs.

[0078] When a data voltage is applied to the gate electrode of the driving transistor DRT, the driving transistor DRT can supply a driving current to the light-emitting element EL, thereby emitting light. Therefore, the driving transistor DRT can be a driving transistor. The gate electrode of the driving transistor DRT can be connected to the source electrode of the switching transistor SCT, the source electrode of the driving transistor DRT can be connected to the first electrode of the light-emitting element EL, and the drain electrode of the driving transistor DRT can be connected to the first power supply voltage line ELVDL from which the first power supply voltage is applied.

[0079] The switching transistor SCT turns on in response to the scan signal from the scan line SCL, allowing the data voltage from the data line DTL to be applied to the gate electrode of the driving transistor DRT. Therefore, the switching transistor SCT can be a switching transistor. The gate electrode of the switching transistor SCT can be connected to the scan line SCL, the source electrode of the switching transistor SCT can be connected to the gate electrode of the driving transistor DRT, and the drain electrode of the switching transistor SCT can be connected to the data line DTL.

[0080] A capacitor Cst can be connected between the gate electrode and the source electrode of the driving transistor DRT. Therefore, the capacitor Cst can keep the data voltage applied to the gate electrode of the driving transistor DRT constant (e.g., substantially constant).

[0081] The light-emitting element EL can emit light proportionally to the drive current from the driving transistor DRT. The light-emitting element EL can be an organic light-emitting diode including a first electrode, an organic emitting layer, and a second electrode. The first electrode of the light-emitting element EL can be connected to the source electrode of the driving transistor DRT, and the second electrode can be connected to a second power supply voltage line ELVSL from which a second power supply voltage lower than the first power supply voltage is applied.

[0082] Figure 4 This illustrates some embodiments. Figure 2 A circuit diagram of one of the pixels.

[0083] Reference Figure 4 A pixel PX may include a driving transistor DRT, a switching transistor SCT, a sensing transistor SST, a light-emitting element EL, and a capacitor Cst. Figure 4 Some embodiments of the pixel PX shown have a 3T1C structure containing a driving transistor DRT, a switching transistor SCT, a sensing transistor SST, and a capacitor Cst.

[0084] According to some embodiments, Figure 4 The circuit shown may further include a compensation circuit comprising a sensing transistor SST and a reference voltage line RVL. The compensation circuit compensates for the threshold voltage of the driving transistor DRT, which acts as the driving transistor.

[0085] The source electrode of the sensing transistor SST can be connected to the source electrode of the driving transistor DRT and the first electrode of the light-emitting element EL. The gate electrode of the sensing transistor SST can be connected to the sensing signal line SSL, the drain electrode of the sensing transistor SST can be connected to the reference voltage line RVL, and the source electrode of the sensing transistor SST can also be connected to one end of the capacitor Cst. The sensing transistor SST is turned on by the sensing signal of the sensing signal line SSL and supplies a reference voltage to the source electrode of the driving transistor DRT through the reference voltage line RVL, or senses the voltage or current at the source electrode of the driving transistor DRT (e.g., from the source electrode of the driving transistor DRT).

[0086] A reference voltage line RVL can be connected to a scan driver SDR. The scan driver SDR can sense the source electrode of the driving transistor DRT of each pixel PX in real time during the non-display period of n frames or images (where n is an integer of 1 or greater). For example, the scan driver SDR can sense the source electrode of the driving transistor DRT of each pixel PX while the pixel PX is experiencing a non-display period or while n frames of the image are being displayed (e.g., substantially simultaneously). The switching transistor SCT and the sensing transistor SST can be turned on simultaneously. In some embodiments, the sensing operation via the reference voltage line RVL and the data output operation via the data line DTL for outputting data signals are separated from each other according to the time-division scheme of the scan driver SDR (e.g., timely separation).

[0087] Digital data signals, analog data signals, or gamma signals can be compensated based on the sensing results. Furthermore, compensation circuitry for generating compensation signals based on sensing results can be implemented in the scan driver SDR, the timing controller, or it can be implemented as a separate circuit.

[0088] However, the embodiments disclosed herein are not limited thereto. For example, although references to Figure 3 and Figure 4 The described pixel PX has a 2T1C structure and a 3T1C structure, but the pixel PX in other embodiments may include a greater number of transistors or capacitors.

[0089] The structure and arrangement of the transistors in each of the pixels PX will be described in more detail below.

[0090] Figure 5 This is a plan view illustrating a driving transistor according to some embodiments of the present disclosure. Figure 6 This is a plan view illustrating a switching transistor according to some embodiments of the present disclosure. Figure 7 This is a cross-sectional view of a display device according to some embodiments of the present disclosure.

[0091] Figure 7 The diagram shows a portion of the display area DPA and a portion of the pad area PDA of the non-display area NDA. The cross-section of the display area DPA shows the drive transistor DRT and the switching transistor SCT of each pixel PX.

[0092] Reference Figures 5 to 7 The display device 1 may include multiple conductive layers and multiple semiconductor layers. The display device 1 includes a first substrate 110, a buffer layer 120, a first protective layer 170, a first planarization layer 180, a first electrode PXE, an organic emitter layer EML, a second electrode CME, and a pixel defining layer PDL. Furthermore, the display device 1 includes a first conductive layer, a first semiconductor layer, a second conductive layer, a second semiconductor layer, and a third conductive layer, which serve as multiple conductive layers and multiple semiconductor layers. The conductive layers and semiconductor layers may include a driving transistor DRT and a switching transistor SCT.

[0093] According to some embodiments of this disclosure, the display device 1 may include a driving transistor DRT and a switching transistor SCT having a bottom gate structure (e.g., arranged) in which the gate electrode is below the active layer. Figures 5 to 7 As shown, in the driving transistor DRT and the switching transistor SCT, gate electrodes 310 and 410 are located below the active layers 350 and 450, respectively. At least one of the driving transistor DRT and the switching transistor SCT may also include an oxide layer on the active layer 350 or 450. In some embodiments where the driving transistor DRT and the switching transistor SCT of the display device 1 have a bottom-gate structure and also include an oxide layer, excellent device characteristics can be obtained.

[0094] According to some embodiments of this disclosure, a driving transistor DRT may include a first gate electrode 310, a first active layer 350, a first source electrode 330, and a first drain electrode 340. A switching transistor SCT may include a second gate electrode 410, a second active layer 450, a second source electrode 430, a second drain electrode 440, and a second oxide layer 470. At least one selected from the driving transistor DRT and the switching transistor SCT includes an oxide layer on the active layer. Although Figure 7 The diagram shows a switching transistor SCT including a second oxide layer 470, but embodiments of this disclosure are not limited thereto. For example, the driving transistor DRT may also include, for instance, a second oxide layer 470. Figure 27 The first oxide layer 370_1 is shown in the figure. The driving transistor DRT and the switching transistor SCT will be described in more detail below.

[0095] The first substrate 110 may include a region comprising a driving transistor DRT and a switching transistor SCT. The first substrate 110 may comprise plastic or glass.

[0096] The first conductive layer is on the first substrate 110. The first conductive layer includes a first gate electrode 310 of the driving transistor DRT, a second gate electrode 410 of the switching transistor SCT, and a pad electrode 500 of the pad region PDA. The scan line SCL and the sensing signal line SSL described above may also be included in the first conductive layer.

[0097] The first gate electrode 310 may be stacked with a portion of the first active layer 350, and a buffer layer 120 is located between the first gate electrode 310 and a portion of the first active layer 350. The second gate electrode 410 may be stacked with a portion of the second active layer 450, and a buffer layer 120 is located between the second gate electrode 410 and a portion of the second active layer 450. For example, as shown in the figures, the first gate electrode 310 and the second gate electrode 410 may each have a width smaller than that of the first active layer 350 and the second active layer 450, respectively. For example, the width of the first gate electrode 310 measured in one direction may be smaller than the width of the first active layer 350 measured in that direction, and the width of the second gate electrode 410 measured in that direction may be smaller than the width of the second active layer 450 measured in that direction. However, embodiments of this disclosure are not limited thereto.

[0098] The pad electrode 500 may be located within the pad region of the PDA, and a hole (e.g., a contact hole CT9) in the buffer layer 120 (e.g., penetrating the buffer layer 120) may expose a portion of the upper surface of the pad electrode 500. A second semiconductor layer or a third conductive layer, which will be described later, may be located on the exposed pad electrode 500 and may be in contact with the pad electrode 500. As used herein, the term "in contact with" may refer to direct contact (e.g., physical contact). An external device EXD may be mounted on the pad electrode 500.

[0099] The first conductive layer may comprise a single layer or multiple layers of at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. However, embodiments of this disclosure are not limited thereto.

[0100] A buffer layer 120 is placed on (e.g., covering) the first conductive layer. The buffer layer 120 may be placed on (e.g., covering) the first gate electrode 310, the second gate electrode 410, and the pad electrode 500. However, in some embodiments, the buffer layer 120 may expose a portion of the upper surface of the pad electrode 500. The buffer layer 120 may protect the drive transistor DRT and switch transistor SCT of the pixel PX from moisture penetration (e.g., penetration) of the first substrate 110. A ninth contact hole CT9 may penetrate a portion of the buffer layer 120 in the pad region PDA and may expose a portion of the upper surface of the pad electrode 500. The pad electrode 500 may contact a portion of the second semiconductor layer through the ninth contact hole CT9.

[0101] Buffer layer 120 may comprise multiple inorganic layers stacked alternately on top of each other. For example, buffer layer 120 may comprise multiple layers, wherein the inorganic layers are derived from silicon oxide (SiO2). x ) layer, silicon nitride (SiN) x One or more inorganic layers, selected from α-layer and β-layer and silicon oxynitride (SiON) layer, are stacked alternately on top of each other.

[0102] The first semiconductor layer is on the buffer layer 120. The first semiconductor layer may include a first active layer 350 and a second active layer 450 located on the buffer layer 120 in the display area DPA. The first active layer 350 and the second active layer 450 may each include (e.g., respectively) active layers for driving transistors DRT and switching transistors SCT. The first active layer 350 may be on the buffer layer 120 above the first gate electrode 310, and the second active layer 450 may be on the buffer layer 120 above the second gate electrode 410. Because the display device 1 according to some embodiments has a bottom-gate structure (e.g., arranged) in which the gate electrodes of the driving transistors DRT and the switching transistors SCT are below the active layers, the number of masks used during the manufacturing process of the display device 1 can be reduced.

[0103] The first semiconductor layer may not be above the pad electrode 500 in the pad region PDA (e.g., it may not be stacked with the pad electrode 500 in the pad region PDA). The second semiconductor layer or the third conductive layer may be on the pad electrode 500.

[0104] The first semiconductor layer may include an oxide semiconductor. In some embodiments, the first active layer 350 and the second active layer 450 may include oxide semiconductors. For example, the oxide semiconductors of the first active layer 350 and the second active layer 450 may include at least one selected from indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf). In some embodiments, the oxide semiconductor may include indium tin oxide (ITO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO). However, embodiments of this disclosure are not limited thereto.

[0105] The second conductive layer is on the first semiconductor layer. The second conductive layer may include a source electrode and a drain electrode. For example, the second conductive layer may include a first source electrode 330 and a first drain electrode 340 of a driving transistor DRT, and a second source electrode 430 and a second drain electrode 440 of a switching transistor SCT. The second conductive layer may also include a data line DTL and power supply voltage lines ELVDL and ELVSL.

[0106] A first source electrode 330 and a first drain electrode 340 are located on the first active layer 350. The first source electrode 330 may contact one side of the first active layer 350, while the first drain electrode 340 may contact the other side of the first active layer 350. For example, one side of the first source electrode 330 may be substantially aligned with one side of the first active layer 350, and one side of the first drain electrode 340 may be substantially aligned with the other side of the first active layer 350. For example, as... Figure 7 As shown, one side (e.g., the left side) of the first source electrode 330 may be aligned with one side (e.g., the left side) of the first active layer 350, while one side (e.g., the right side) of the first drain electrode 340 may be aligned with the other side (e.g., the right side) of the first active layer 350. The other side (e.g., the right side) of the first source electrode 330 and the other side (e.g., the left side) of the first drain electrode 340 may be on the first active layer 350.

[0107] Such a structure can be formed (e.g., fabricated) by patterning portions of the first semiconductor layer and the second conductive layer via (e.g., by) the same process. However, embodiments of this disclosure are not limited thereto. For example, in some embodiments, one side of the first source electrode 330 (e.g., as...) Figure 7 The first source electrode 330 (shown on the left) may extend beyond one side of the first active layer 350 (e.g., the left side), and the first drain electrode 340 may extend beyond the other side of the first active layer 350 (e.g., the right side), such that the first source electrode 330 and the first drain electrode 340 may be on the buffer layer 120. For example, at least a portion of the lower surface of each of the first source electrode 330 and the first drain electrode 340 may be in contact with the buffer layer 120 (e.g., directly on the buffer layer 120).

[0108] The second source electrode 430 and the second drain electrode 440 are located on the second active layer 450. The second source electrode 430 may be in contact with one side of the second active layer 450, while the second drain electrode 440 may be in contact with the other side of the second active layer 450. For example, one side (e.g., the left side) of the second source electrode 430 may be substantially aligned with one side (e.g., the left side) of the second active layer 450, while one side (e.g., the right side) of the second drain electrode 440 may be substantially aligned with the other side (e.g., the right side) of the second active layer 450. The second source electrode 430 and the second drain electrode 440 may be the same as or substantially the same as the first source electrode 330 and the first drain electrode 340, respectively, and their redundant descriptions will not be repeated here.

[0109] In some embodiments, the second conductive layer may not be on the pad electrode 500. A second semiconductor layer or a third conductive layer may be on the pad electrode 500.

[0110] The second conductive layer may comprise a single layer or multiple layers of at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys. However, embodiments of this disclosure are not limited thereto.

[0111] The first protective layer 170 is on top of the second conductive layer (e.g., on the second conductive layer). The first protective layer 170 may be present on the entire surface of the first semiconductor layer, the buffer layer 120, and the second conductive layer. For example, the first protective layer 170 may be present on the entire surface of the first semiconductor layer, the buffer layer 120, and the second conductive layer. For example, the first protective layer 170 may cover the first active layer 350, the second active layer 450, the buffer layer 120, the first source electrode 330, the first drain electrode 340, the second source electrode 430, and the second drain electrode 440. The first protective layer 170 may be made of materials such as silicon oxide (SiO2). x ) and silicon nitride (SiN) x For example, an inorganic material or its stacked structure. Therefore, the upper surface of the first protective layer 170 may include recesses caused by the horizontal difference between the underlying first semiconductor layer and the second conductive layer (e.g., caused by the horizontal difference between the underlying first semiconductor layer and the second conductive layer). For example, the first protective layer 170 may include steps.

[0112] according to Figure 7In some embodiments shown, the recess GP can be in a first protective layer 170, which is recessed due to the level difference between the source electrodes 330 and 430 and the drain electrodes 340 and 440 beneath it. Each of the recesses GP can be above a portion of the active layer located between the spaced-apart source and drain electrodes. The recesses GP can include a first recess GP1 above the first active layer 350 and a second recess GP2 above the second active layer 450. A second semiconductor layer is on the first protective layer 170, and the portion of the second semiconductor layer located in the recesses GP can be an oxide layer of a driving transistor DRT or an oxide layer of a switching transistor SCT.

[0113] Multiple contact holes may be present in the first protective layer 170. The first protective layer 170 may include a first contact hole CT1 that penetrates the first protective layer 170 to expose a portion of the upper surface of the first source electrode 330, a second contact hole CT2 that penetrates the first protective layer 170 to expose a portion of the upper surface of the first drain electrode 340, a third contact hole CT3 that penetrates the first protective layer 170 to expose a portion of the upper surface of the second source electrode 430, and a fourth contact hole CT4 that penetrates the first protective layer 170 to expose a portion of the upper surface of the second drain electrode 440. The source and drain electrodes of the driving transistor DRT and the switching transistor SCT may contact the second semiconductor layer or the third conductive layer through the first contact hole CT1, the second contact hole CT2, the third contact hole CT3, and the fourth contact hole CT4.

[0114] The first protective layer 170 may also be in the pad region PDA. The first protective layer 170 may include a tenth contact hole CT10 that penetrates the protective layer 170 to expose a portion of the upper surface of the pad electrode 500. The ninth contact hole CT9 and the tenth contact hole CT10 may be above the pad electrode 500, such that the pad electrode 500 can contact the second semiconductor layer or the third conductive layer through the contact holes.

[0115] The ninth contact hole CT9 and the tenth contact hole CT10 can be formed via (e.g., by) different processes. In some embodiments of this disclosure, the first width W1, which is the width of the ninth contact hole CT9, can be smaller than the second width W2, which is the width of the tenth contact hole CT10. Because the ninth contact hole CT9 has a smaller width than the tenth contact hole CT10, the sidewall PT of the ninth contact hole CT9 can be further inward than the sidewall of the tenth contact hole CT10. For example, the ninth contact hole CT9 can be centered below the center of the tenth contact hole CT10. However, embodiments of this disclosure are not limited thereto. In some embodiments, the contact holes in the buffer layer 120 and the first protective layer 170 are formed via the same process, such that the sidewalls of the contact holes in the buffer layer 120 can be aligned with the sidewalls of the contact holes in the first protective layer 170. For example, one side (e.g., the left side) of the ninth contact hole CT9 can be aligned with one side (e.g., the left side) of the tenth contact hole CT10.

[0116] The second semiconductor layer may be on the first protective layer 170. The second semiconductor layer may include a plurality of oxide patterns OXP and at least one oxide layer. The oxide layer may be on at least one of the recesses GP of the first protective layer 170 (e.g., in at least one of the recesses GP of the first protective layer 170, or covering at least one of the recesses GP of the first protective layer 170, etc.). For example, the oxide layer may be a second oxide layer 470 on a second recess GP2 of the first protective layer 170 (e.g., in the second recess GP2 of the first protective layer 170, or covering the second recess GP2 of the first protective layer 170, etc.). The second oxide layer 470 may be over the second active layer 450 and stacked with the second active layer 450 in the thickness direction.

[0117] The second oxide layer 470 may be stacked with at least a portion of the second active layer 450 in the thickness direction. In some embodiments of this disclosure, the second oxide layer 470 may cover at least a portion of the second active layer 450 located between the second source electrode 430 and the second drain electrode 440 (e.g., stacked with at least a portion of the second active layer 450 located between the second source electrode 430 and the second drain electrode 440). For example, the width WA of the second oxide layer 470 may be larger than the width WB between the second source electrode 430 and the second drain electrode 440. Therefore, at least a portion of the second oxide layer 470 may be above the second source electrode 430 and the second drain electrode 440. For example, the second oxide layer 470 may be stacked with at least a portion of the second source electrode 430 and the second drain electrode 440 in the thickness direction.

[0118] The oxide layer may be located above the active layer of the switching transistor SCT or the driving transistor DRT, and oxygen may be injected into the active layer. In some embodiments, the second oxide layer 470 has a width WA larger than the width WB between the second source electrode 430 and the second drain electrode 440, such that the second oxide layer 470 at least covers the channel region of the second active layer 450 (e.g., at least overlaps with the channel region of the second active layer 450). Although the second oxide layer 470 in some figures only covers a portion of the second source electrode 430 and the second drain electrode 440, the embodiments of this disclosure are not limited thereto. For example, the second oxide layer 470 may have a larger area.

[0119] Furthermore, the oxide layer may include additional oxide layers. For example, the oxide layer may include an oxide layer located in a first recess GP1 above the first active layer 350 in the thickness direction. At least one selected from the driving transistor DRT and the switching transistor SCT may also include an oxide layer to improve device characteristics.

[0120] The oxide pattern OXP of the second semiconductor layer can contact the second conductive layer. For example, the oxide pattern OXP of the second semiconductor layer can contact the source and drain electrodes of the drive transistor DRT and the switching transistor SCT through contact holes in the first protective layer 170. The oxide pattern OXP can include a first oxide pattern OXP1, a second oxide pattern OXP2, a third oxide pattern OXP3, and a fourth oxide pattern OXP4 in the display area DPA. The oxide pattern OXP can also include a fifth oxide pattern OXP5 in the pad area PDA.

[0121] The first oxide pattern OXP1 can make partial contact with the upper surface of the first source electrode 330 through the first contact hole CT1; the second oxide pattern OXP2 can make partial contact with the upper surface of the first drain electrode 340 through the second contact hole CT2; the third oxide pattern OXP3 can make partial contact with the upper surface of the second source electrode 430 through the third contact hole CT3; and the fourth oxide pattern OXP4 can make partial contact with the upper surface of the second drain electrode 440 through the fourth contact hole CT4. Furthermore, the fifth oxide pattern OXP5 can make partial contact with the upper surface of the pad electrode 500 through the ninth contact hole CT9 and the tenth contact hole CT10. Each of the plurality of oxide patterns OXP can contact and cover at least a portion of the upper surface of the second conductive layer to prevent or reduce damage to the material of the second conductive layer during subsequent processes. Because the first planarization layer 180 is not on the first protective layer 170 in the pad region PDA, the pad electrode 500 can be partially exposed during the manufacturing process of the display device 1. The oxide patterns OXP can cover the exposed second conductive layer or the first conductive layer to protect them. Furthermore, oxide pattern OXP can be electrically connected to the second conductive layer and can be used as a bridging wire to connect them to other lines or components on another layer.

[0122] However, embodiments of this disclosure are not limited thereto. For example, in some embodiments, the oxide pattern OXP may be removed, and the material of the second conductive layer or the first conductive layer may come into contact with the material of the third conductive layer to be protected.

[0123] The second semiconductor layer may also include an oxide semiconductor. For example, the second oxide layer 470 and the oxide pattern OXP may include an oxide semiconductor. For example, the oxide semiconductor of the second oxide layer 470 and the oxide pattern OXP may include at least one selected from indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf). In some embodiments, the oxide semiconductor may include indium tin oxide (ITO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO). However, embodiments of this disclosure are not limited thereto.

[0124] In some embodiments, the second semiconductor layer may comprise the same oxide semiconductor as the first semiconductor layer. In some embodiments, the second semiconductor layer and the first semiconductor layer may comprise oxide semiconductors with different composition ratios.

[0125] According to some embodiments of this disclosure, the oxide layer of the second semiconductor layer may include an oxygen supply layer for injecting oxygen into the active layer 350 or 450 of the driving transistor DRT or the switching transistor SCT. In the oxide semiconductor, oxygen vacancies (Vo) can be partially formed according to the oxygen partial pressure during the deposition process. When the insulating layer is deposited on the oxide semiconductor, hydrogen (H) can be injected into the oxygen vacancies (Vo). Therefore, by providing (e.g., forming) an oxide layer over the active layer, the oxide layer can supply excess oxygen (O) to another adjacent layer (such as an insulating layer, for example). The excess oxygen (O) supplied to the insulating layer can be injected into the channel region of the oxide semiconductor, and the hydrogen (H) permeated into the oxygen vacancies (Vo) can be released back into the insulating layer. According to some embodiments of this disclosure, the driving transistor DRT or the switching transistor SCT may include an oxide layer over the active layer 350 or 450 to adjust the hydrogen or oxygen content included in the active layer 350 or 450, thereby improving device characteristics.

[0126] Figures 8 to 10 This is a graph showing the drive current based on the gate voltage of the switching transistor according to some embodiments.

[0127] Figure 8 This is a graph showing the drive current Ids based on the gate voltage Vgs of the switching transistor SCT in the initial state. Figure 8 In the graph shown, the dashed line represents the drive current Ids based on the gate voltage Vgs of the switching transistor SCT without the oxide layer, while the solid line represents the drive current Ids based on the gate voltage Vgs of the switching transistor SCT including the oxide layer. Figure 9 and Figure 10 The diagram shows the change in drive current Ids after the gate voltage Vgs of the switching transistor SCT has been swept several times. Figure 9 The graph shown illustrates the drive current Ids based on the gate voltage Vgs of the switching transistor SCT excluding the oxide layer. Figure 10 The graph shown illustrates the drive current Ids based on the gate voltage Vgs of the switching transistor SCT, which includes an oxide layer.

[0128] By providing (e.g., forming) an oxide layer above the active layer 450 of the switching transistor SCT, the content of hydrogen (H) introduced from the insulating layer (e.g., the amount of hydrogen (H), the concentration of hydrogen (H), etc.) is reduced, and oxygen is supplied, thereby reducing the concentration of oxygen vacancies (Vo). As a result, device reliability can be ensured (e.g., device characteristics can be reliable). Figure 8As can be seen from the graphs shown, the switching transistor SCT (indicated by the dashed line), which does not include the oxygen supply layer as an oxide layer, has a lower threshold voltage (Vth) on the gate voltage Vgs-drive current Ids curve. Conversely, from... Figure 8 As shown in the graph, the switching transistor SCT (indicated by the solid line), which includes an oxide layer, has a high threshold voltage (Vth) on the gate voltage Vgs-drive current Ids curve. For example, in some embodiments, the switching transistor SCT can exhibit (e.g., have) excellent device characteristics.

[0129] In addition, from Figure 9 and Figure 10 The graph shown illustrates the curve of the drive current Ids of the switching transistor SCT (excluding the oxide layer) after the gate voltage Vgs has been swept several times. Figure 9 ) shift to the left (negative shift). In contrast, from Figure 10 The graph shown illustrates the curve of the drive current Ids of the switching transistor SCT, including the oxide layer, after the gate voltage Vgs has been swept several times. Figure 10 The offset to the left is smaller (negative offset). Therefore, embodiments in which the switching transistor SCT includes an oxide layer can ensure excellent device characteristics.

[0130] In some embodiments, at least one selected from the driving transistor DRT and the switching transistor SCT includes an oxide layer, such that excellent device reliability can be ensured even in embodiments in which their channel regions have short lengths.

[0131] In some embodiments, unlike other oxide patterns OXP, the oxide layer of the second semiconductor layer (e.g., the second oxide layer 470) may be formed in a floating state when it is disposed in the recess GP. However, in some embodiments, because unwanted capacitance may form between the second oxide layer 470 and another conductive layer, the second oxide layer 470 may be electrically connected to another conductive layer (e.g., the first conductive layer).

[0132] Figure 11 It is along Figure 6 A sectional view taken from line Q1-Q1'.

[0133] Reference Figure 6 and Figure 11The second oxide layer 470 can penetrate the first protective layer 170 and the buffer layer 120 to contact the first conductive layer. For example, the second oxide layer 470 can contact the second gate electrode 410 through a contact hole CTO that penetrates the first protective layer 170 and the buffer layer 120 to expose a portion of the upper surface of the first conductive layer. Because the second oxide layer 470 is electrically connected to another conductive layer, unwanted capacitance between the second active layer 450 and the second oxide layer 470 can be prevented or reduced. However, embodiments of this disclosure are not limited thereto. For example, the oxide layer can be electrically connected to another conductive layer (such as power supply voltage lines ELVDL and ELVSL to which the power supply voltage is applied (through which the power supply voltage is applied)).

[0134] Return to reference Figures 5 to 7 The first planarization layer 180 is on the first protective layer 170. The first planarization layer 180 may include a flat surface formed by a thin-film transistor such as a driving transistor DRT and a switching transistor SCT (e.g., formed due to a thin-film transistor such as a driving transistor DRT and a switching transistor SCT, caused by a thin-film transistor such as a driving transistor DRT and a switching transistor SCT, etc.). The first planarization layer 180 may be an organic layer such as an acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0135] Multiple contact holes may be present in the first planarization layer 180. These contact holes may extend through the first planarization layer 180 to expose portions of the second semiconductor layer. Fifth contact hole CT5, sixth contact hole CT6, seventh contact hole CT7, and eighth contact hole CT8 may be present in the first planarization layer 180. Fifth contact hole CT5 may expose a portion of the first oxide pattern OXP1 of the second semiconductor layer, sixth contact hole CT6 may expose a portion of the second oxide pattern OXP2 of the second semiconductor layer, seventh contact hole CT7 may expose a portion of the third oxide pattern OXP3 of the second semiconductor layer, and eighth contact hole CT8 may expose a portion of the fourth oxide pattern OXP4 of the second semiconductor layer. A third conductive layer on the first planarization layer 180 may contact portions of the second semiconductor layer through these contact holes to electrically connect to the second conductive layer.

[0136] In some embodiments, the fifth contact hole CT5, the sixth contact hole CT6, the seventh contact hole CT7, and the eighth contact hole CT8 can penetrate the first planarization layer 180 and the first protective layer 170 to directly expose portions of the second conductive layer. In embodiments where some of the contact holes in the first protective layer 170 are omitted, the first planarization layer 180 and the first protective layer 170 can be etched via the same process to form the fifth contact hole CT5, the sixth contact hole CT6, the seventh contact hole CT7, and the eighth contact hole CT8 that expose portions of the second conductive layer.

[0137] The third conductive layer is located on the first planarization layer 180 in the display area DPA. The third conductive layer may include a first electrode PXE and a plurality of electrode patterns PXP. The electrode patterns PXP may include a first electrode pattern PXP1, a second electrode pattern PXP2, and a third electrode pattern PXP3. The first electrode PXE and the plurality of electrode patterns PXP may be spaced apart from each other and may be arranged in accordance with contact holes in the first planarization layer 180.

[0138] The first electrode PXE can contact the first oxide pattern OXP1 through the fifth contact hole CT5. Therefore, the first electrode PXE can be connected to the first source electrode 330 of the driving transistor DRT. The first electrode pattern PXP1 can contact the second oxide pattern OXP2 through the sixth contact hole CT6, the second electrode pattern PXP2 can contact the third oxide pattern OXP3 through the seventh contact hole CT7, and the third electrode pattern PXP3 can contact the fourth oxide pattern OXP4 through the eighth contact hole CT8. Multiple electrode patterns PXP can prevent or reduce damage to the underlying layer (e.g., oxide pattern OXP), or can be electrically connected to such a layer to serve as a bridging connection.

[0139] Furthermore, the third conductive layer may also include a fourth electrode pattern PXP4 in the pad region PDA. The fourth electrode pattern PXP4 may contact a fifth oxide pattern OXP5 in the pad region PDA. For example, the fourth electrode pattern PXP4 may contact the fifth oxide pattern OXP5 in the tenth contact hole CT10 and the ninth contact hole CT9.

[0140] However, embodiments of this disclosure are not limited thereto. For example, multiple electrode patterns PXP, other than the first electrode PXE, can be omitted from the third conductive layer.

[0141] The light-emitting element EL, including the organic emission layer EML and the second electrode CME, and the pixel definition layer PDL can be further applied to the first planarization layer 180.

[0142] A pixel defining layer (PDL) may cover the edge of the first electrode PXE on the first planarization layer 180 to separate pixels PX from each other. For example, the pixel defining layer (PDL) may define a pixel PX. In each pixel PX, the first electrode PXE, the organic emitting layer (EML), and the second electrode CME are sequentially stacked such that holes from the first electrode PXE and electrons from the second electrode CME combine with each other in the organic emitting layer (EML) to emit light.

[0143] An organic emitting layer (EML) may be located on the first electrode (PXE) and the pixel defining layer (PDL). The organic emitting layer (EML) may include a hole transport layer, a light-emitting layer, and an electron transport layer. Furthermore, the organic emitting layer (EML) may have a structure of two or more stacked elements, with charge-generating layers arranged in series between the stacked elements (e.g., an arrangement). Although the organic emitting layer (EML) is located throughout the display area (DPA) in the figures, embodiments of this disclosure are not limited thereto. In some embodiments, the organic emitting layer (EML) may be partially aligned with the first electrode (PXE) of each pixel (e.g., it may be partially superimposed on the first electrode (PXE) of each pixel (PXE).

[0144] The second electrode CME can be on the organic emitter layer EML. The second electrode CME can be a common layer spanning the pixel PX.

[0145] The light-emitting element (EL) can have a top-emitting type (e.g., structure or arrangement) in which light is emitted upwards. In some embodiments, the first electrode (PXE) can include a metallic material with high reflectivity, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu). Furthermore, the second electrode (CME) can include a transparent conductive material (TCP) (such as ITO and IZO, which can transmit light) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), and an alloy of magnesium (Mg) and silver (Ag). When the second electrode (CME) includes a semi-transmissive conductive material, the light extraction efficiency can be increased by using a microcavity.

[0146] In some embodiments, an encapsulation layer may be present on the second electrode CME to prevent or reduce the permeation (e.g., penetration) of oxygen or moisture into the underlying layer (such as, in the case of the second electrode CME and the organic emitter layer EML). The encapsulation layer may include at least one inorganic layer. The inorganic layer may include at least one selected from silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, and titanium oxide. Furthermore, the encapsulation layer may include at least one organic layer to prevent or reduce particle penetration through the encapsulation layer into the underlying layer (such as, in the case of the organic emitter layer EML and the second electrode CME). The organic layer may include epoxy resin, acrylate, or polyurethane acrylate.

[0147] In some embodiments, the driving transistor DRT and the switching transistor SCT include an active layer having an oxide semiconductor and may have a bottom gate structure (e.g., an arrangement) in which the gate electrode is below the active layer. In some embodiments, because the display device 1 includes a transistor with a bottom gate structure, it is possible to reduce the number of manufacturing process steps (e.g., the number of manufacturing process steps). In some embodiments, at least one selected from the driving transistor DRT and the switching transistor SCT further includes an oxide layer above the active layer, such that even in embodiments in which the channel region of the transistor has a short length, reliable device characteristics can be ensured.

[0148] The method of manufacturing a display device 1 comprising the driving transistor DRT and the switching transistor SCT described above will be described in more detail below.

[0149] Figure 12 This is a flowchart illustrating the processing steps for manufacturing a display device according to some embodiments of the present disclosure.

[0150] Reference Figure 12 The process of manufacturing the display device 1 may include the following steps: forming a first conductive layer including gate electrodes 310 and 410 on a first substrate 110 (step S101); forming a buffer layer 120 on the first conductive layer (step S102); forming a first semiconductor layer including active layers 350 and 450 on the buffer layer 120 (step S103); forming a second conductive layer including source electrodes 330 and 430 and drain electrodes 340 and 440 on the first semiconductor layer (step S104); forming a first protective layer 170 on the second conductive layer (step S105); forming a second semiconductor layer including a second oxide layer 470 on the first protective layer 170 (step S106); and forming a first planarization layer 180, a pixel definition layer (PDL), etc. on the second semiconductor layer (step S107).

[0151] According to some embodiments of this disclosure, during the manufacturing process of the display device 1, the step of forming a first conductive layer including a gate electrode (S101) can be performed before the step of forming a first semiconductor layer including an active layer (S103). By doing so, the driving transistor DRT and the switching transistor SCT can have a bottom-gate structure in which the gate electrode is below the active layer. Furthermore, the step of forming a second semiconductor layer including an oxide layer (S106) can be performed after the step of forming the first semiconductor layer including the active layer (S103), such that at least one selected from the driving transistor DRT and the switching transistor SCT can also include an oxide layer. The switching transistor SCT and / or the driving transistor DRT including an oxide layer can exhibit (e.g., have) improved device characteristics and reliability.

[0152] The manufacturing process steps of the display device 1 will be described in more detail below with reference to the accompanying drawings.

[0153] Figures 13 to 25 This is a cross-sectional view illustrating the processing steps for manufacturing a display device according to some embodiments of the present disclosure.

[0154] Reference Figure 13 A first conductive layer including a gate electrode is formed on the first substrate 110 (step S101), and a buffer layer 120 is formed on the first conductive layer (step S102). The first conductive layer may include a first gate electrode 310 and a second gate electrode 410 in the display area DPA and a pad electrode 500 in the pad area PDA.

[0155] The first conductive layer can be formed by, for example, sputtering a metal layer onto a first substrate 110 and then patterning the metal layer via an etching process using a photoresist pattern. The buffer layer 120 can be formed by, but is not limited to, chemical vapor deposition. However, the embodiments disclosed herein are not limited thereto. For example, processes for forming the conductive layer, buffer layer, and semiconductor layer can be performed by any process commonly available in the relevant art. The following description will focus on the formation sequence and structure of some of the features, without describing in more detail the processes used to form them.

[0156] Reference Figure 14 and Figure 15A first oxide semiconductor layer OXL1 and a first metal layer CHL are formed on buffer layer 120. The first oxide semiconductor layer OXL1 and the first metal layer CHL can be formed entirely on the first substrate 110 and buffer layer 120 (e.g., formed over the entire surface of the first substrate 110 and buffer layer 120). The first oxide semiconductor layer OXL1 and the first metal layer CHL can be patterned during subsequent processes to form active layers 350 and 450, source electrodes 330 and 430, and drain electrodes 340 and 440. In some embodiments, the first oxide semiconductor layer OXL1 can be formed by sputtering to form a monolayer, followed by a patterning process using a photoresist. However, embodiments of this disclosure are not limited thereto. In some embodiments, the first oxide semiconductor layer OXL1 can be formed by atomic layer deposition or any other suitable process generally available.

[0157] Reference Figure 16 and Figure 17 A first photoresist PR1 is formed on the first metal layer CHL, and the first oxide semiconductor layer OXL1 and the first metal layer CHL are patterned to form a first active layer 350, a second active layer 450, and a second metal layer CML. The second metal layer CML can be patterned during subsequent processes to form source and drain electrodes.

[0158] The first photoresist PR1 may be applied over the first gate electrode 310 and the second gate electrode 410 in the display area DPA. The first photoresist PR1 may be used as a mask for patterning the first oxide semiconductor layer OXL1 to form the first active layer 350 and the second active layer 450.

[0159] The two ends of the first photoresist PR1 can be higher than the center portion. The first photoresist PR1 can be formed in such a shape, for example, by using a halftone mask. The first photoresist PR1 can be used as a mask for patterning the first metal layer CHL during subsequent processes, and the source and drain electrodes can be formed simultaneously with a single mask. Therefore, the number of masks used during the manufacturing process of the display device 1 can be reduced.

[0160] Reference Figure 18 and Figure 19The first photoresist PR1 is etched to form a second photoresist PR2, and the second metal layer CML is patterned along the second photoresist PR2 to form source and drain electrodes. Because the two ends and the center of the first photoresist PR1 have different heights, the center of the first photoresist PR1 can be removed first, so that only the two ends of the first photoresist PR1 are retained after the etching process, thereby forming the second photoresist PR2. The second photoresist PR2 can be used as a mask for patterning the second metal layer CML to form the source and drain electrodes.

[0161] By patterning the second metal layer CML along the second photoresist PR2, a first source electrode 330 and a first drain electrode 340 can be formed on the first active layer 350, and a second source electrode 430 and a second drain electrode 440 can be formed on the second active layer 450.

[0162] Reference Figure 20 and Figure 21 The second photoresist PR2 is removed, and a first protective layer 170 is formed on the source and drain electrodes. The step of forming the first protective layer 170 may include forming a first insulating layer 170' on the source and drain electrodes and etching portions of the first insulating layer 170' to form a plurality of contact holes. The first insulating layer 170' may be substantially the same as the first protective layer 170. Due to the source and drain electrodes beneath the first insulating layer 170', a horizontal difference may exist on the upper surface of the first insulating layer 170' (e.g., a horizontal difference on the upper surface of the first insulating layer 170' may exist due to the source and drain electrodes beneath the first insulating layer 170'). For example, a groove GP in which a portion of the upper surface of the first insulating layer 170' is recessed may be formed between the source and drain electrodes.

[0163] The process of forming multiple contact holes by partially etching the first insulating layer 170' (e.g., by etching a portion of the first insulating layer 170') can be performed using any suitable patterning process that is generally available.

[0164] The first protective layer 170 in the display area DPA may include a first contact hole CT1, a second contact hole CT2, a third contact hole CT3, and a fourth contact hole CT4. During the process of forming the first protective layer 170, the first protective layer 170 and the buffer layer 120 in the pad area PDA may be partially etched. Since the first protective layer 170 and the buffer layer 120 have different etch selectivity (e.g., different etch requirements), ninth contact holes CT9 and tenth contact holes CT10 with different diameters can be formed by etching the first protective layer 170 and the buffer layer 120 during different patterning processes. However, the embodiments of this disclosure are not limited thereto.

[0165] Reference Figure 22 and Figure 23 A second oxide semiconductor layer OXL2 is formed on the first protective layer 170, and the second oxide semiconductor layer OXL2 is partially patterned to form the second semiconductor layer. Multiple oxide patterns OXP and oxide layers (e.g., the second oxide layer 470) can be formed by the second semiconductor layer during subsequent processes. The second oxide semiconductor layer OXL2 is completely formed on the first protective layer 170, and portions of the second oxide semiconductor layer OXL2 are patterned and removed during the process of forming the second semiconductor layer. Therefore, the oxide patterns OXP can be spaced apart from each other, and the second oxide semiconductor layer OXL2 formed in the second recess GP2 of the first protective layer 170 can form the second oxide layer 470.

[0166] Reference Figure 24 and Figure 25 A first planarization layer 180 is formed on the second semiconductor layer, and a third conductive layer and a pixel defining layer (PDL) are formed on the first planarization layer 180. The steps for forming the first planarization layer 180 can be substantially the same as those for forming the first protective layer 170. For example, the first planarization layer 180 can be formed by forming a second insulating layer entirely on the first protective layer 170 (e.g., over the entire first protective layer 170) and then partially patterning it to form a plurality of contact holes. Such a structure has already been described above, so a redundant description will not be repeated here.

[0167] An organic emission layer (EML), a second electrode (CME), an encapsulation layer, etc., are formed on the first electrode (PXE) to produce a display device 1.

[0168] By performing the processes described above, a display device 1 according to some embodiments of the present disclosure can be manufactured. In the process of manufacturing the display device 1, a step of forming a first conductive layer including a gate electrode is performed before the step of forming a first semiconductor layer including an active layer, thereby forming a driving transistor DRT and a switching transistor SCT having a bottom gate structure. Furthermore, a step of forming a second semiconductor layer including an oxide layer can be performed after the step of forming the first semiconductor layer including the active layer, thereby at least one selected from the driving transistor DRT and the switching transistor SCT may include an oxide layer.

[0169] In the following text, various structures of the driving transistor DRT and the switching transistor SCT will be described with reference to the accompanying drawings.

[0170] Figure 26 This is a plan view illustrating a driving transistor according to some embodiments of the present disclosure. Figure 27 It shows including Figure 26 A cross-sectional view of an example display device with driving transistors.

[0171] Reference Figure 26 and Figure 27 In the display device 1 according to some embodiments of the present disclosure, the driving transistor DRT_1 may further include a first oxide layer 370_1 on the first active layer 350. Some embodiments are similar to Figure 5 and Figure 7 The difference in some embodiments is that the driving transistor DRT_1 includes a first oxide layer 370_1. Therefore, the description will focus on the differences, and redundant descriptions will not be repeated here.

[0172] In some embodiments, such as Figure 26 and Figure 27 As shown, the driving transistor DRT_1 may further include a first oxide layer 370_1 above the first active layer 350. The first oxide layer 370_1 is located in a first recess GP1 of the first protective layer 170. The width of the first oxide layer 370_1 may be larger than the width between the first source electrode 330 and the first drain electrode 340. At least a portion of the first oxide layer 370_1 may be stacked with the first source electrode 330 and the first drain electrode 340 in the thickness direction.

[0173] Because a larger amount of hydrogen (H) is introduced from the insulating layer on the active layer, the driving transistor DRT_1 can have a higher mobility and therefore a larger number of charge carriers. However, if too many charge carriers are generated in the active layer of the driving transistor DRT_1, it may be difficult to ensure the driving voltage for driving each pixel PX. When the first active layer 350 of the driving transistor DRT_1 has a short channel region, the driving voltage can have a narrower range. Therefore, the display device 1 according to some embodiments also includes a first oxide layer 370_1 above the first active layer 350 of the driving transistor DRT_1, such that even in embodiments where the channel region has a short length, the driving transistor DRT_1 can have a high mobility while ensuring a wide range of driving voltages.

[0174] The structure and materials of the first oxide layer 370_1 are the same or substantially the same as those of the second oxide layer 470, therefore, redundant descriptions will not be repeated here.

[0175] Figure 28 This is a cross-sectional view of a display device according to some embodiments of the present disclosure.

[0176] In some embodiments, such as Figure 28 As shown, the driving transistor DRT_1 may include a first oxide layer 370_1, while the switching transistor SCT_2 may not include a second oxide layer on the second active layer 450. Some embodiments are similar to... Figure 27 The difference in some embodiments is that the second oxide layer 470 of the switching transistor SCT is removed. Other features are the same as or substantially the same as those described above, and therefore, redundant descriptions will not be repeated here.

[0177] In some embodiments, the electrode pattern PXP of the third conductive layer and the oxide pattern OXP of the second semiconductor layer may be removed.

[0178] Figure 29 and Figure 30 This is a cross-sectional view illustrating a display device according to some embodiments of the present disclosure.

[0179] Reference Figure 29 This allows for the removal of the PXP electrode pattern from the third conductive layer. Some embodiments are similar to... Figure 7 The differences in some embodiments shown are: the electrode pattern PXP is removed and the third conductive layer consists only of the first electrode PXE; and the sixth contact hole CT6, the seventh contact hole CT7, and the eighth contact hole CT8 in the first planarization layer 180 are omitted. Other components are the same as those described above. Figure 7 The components described are the same or substantially the same, therefore, redundant descriptions will not be repeated here.

[0180] Reference Figure 30 This allows for the removal of the oxide pattern OXP in the second conductive layer. Some embodiments are similar to... Figure 7 The difference in some embodiments shown is that the oxide pattern OXP is removed, thus the source and drain electrodes of the second conductive layer are in direct contact with the first electrode PXE_4 and the electrode pattern PXP_4 of the third conductive layer. Therefore, the description will focus on the differences, and redundant descriptions will not be repeated here.

[0181] As shown in the attached figures, multiple oxide patterns OXP can be removed, and the first electrode PXE_4 and electrode pattern PXP_4 of the third conductive layer can directly contact the source and drain electrodes of the second conductive layer. For example, the first electrode PXE_4 can contact (e.g., directly contact) the first source electrode 330 of the driving transistor DRT_4, the first electrode pattern PXP1_4 can contact (e.g., directly contact) the first drain electrode 340 of the driving transistor DRT_4, the second electrode pattern PXP2_4 can contact (e.g., directly contact) the second source electrode 430 of the switching transistor SCT_4, and the third electrode pattern PXP3_4 can contact (e.g., directly contact) the second drain electrode 440 of the switching transistor SCT_4. Furthermore, the fourth electrode pattern PXP4_4 in the pad region PDA can directly contact the pad electrode 500.

[0182] In some embodiments, the contact holes in the first protective layer 170_4 in the display area DPA can be omitted, while the contact holes in the first planarization layer 180_4 can extend (e.g., through) the first protective layer 170_4, thereby exposing portions of the second conductive layer. For example, the fifth contact hole CT5, the sixth contact hole CT6, the seventh contact hole CT7, and the eighth contact hole CT8 can penetrate the first planarization layer 180_4 and the first protective layer 170_4 to expose portions of the second conductive layer. These contact holes can be formed via the same process by etching the first protective layer 170_4 and the first planarization layer 180_4. The contact holes in the buffer layer 120_4 in the pad area PDA can be omitted, while the contact holes in the first protective layer 170_4 can extend (e.g., through) the buffer layer 120_4, thereby exposing portions of the first conductive layer. For example, the tenth contact hole CT10 can penetrate the first protective layer 170_4 and the buffer layer 120_4 to expose portions of the first conductive layer. The first protective layer 170_4 and the buffer layer 120_4 can be etched using the same process as that used to etch the first planarization layer 180_4 to form the contact hole CT10.

[0183] Figures 31 to 33 It shows the manufacturing process. Figure 30 A cross-sectional view of some processing steps in the method of the embodiment of the display device shown.

[0184] Reference Figure 31 A second conductive layer is formed, and then a first insulating layer 170'_4 is formed on the second conductive layer. In the process of manufacturing the display device 1 according to some embodiments, a second oxide layer 470 is first formed before forming a plurality of contact holes in the first insulating layer 170'_4. The second oxide semiconductor layer OXL2 formed on the first insulating layer 170'_4 may be formed only on some portions of the first insulating layer 170'_4, thereby forming the second oxide layer 470. However, the embodiments of this disclosure are not limited thereto. For example, in some embodiments, the second oxide semiconductor layer OXL2 may be completely formed on the first insulating layer 170'_4, and portions of the second oxide semiconductor layer OXL2 may be etched and removed to form the second oxide layer 470.

[0185] Reference Figure 32 and Figure 33 The second insulating layer 180'_4 is formed entirely on the first insulating layer 170'_4, and both the first and second insulating layers 170'_4 are etched during the same process to form a plurality of contact holes. In doing so, the first and second insulating layers 170'_4 are etched simultaneously in the display area DPA, and the first insulating layer 170'_4 and the buffer layer 120'_4 can be etched simultaneously in the pad area PDA. Therefore, the contact holes in the display area DPA can penetrate (e.g., pass through) the first planarization layer 180_4 and the first protective layer 170_4 to expose portions of the second conductive layer, and the contact holes in the pad area PDA can penetrate (e.g., pass through) the first protective layer 170_4 and the buffer layer 120_4 to expose portions of the first conductive layer. According to some embodiments of this disclosure, the inner sidewalls of the contact holes in the first planarization layer 180_4 and the first protective layer 170_4 can be aligned with each other. The first planarization layer 180_4 and the first protective layer 170_4 can be patterned using the same etching process, so the inner walls of the contact holes in the first planarization layer 180_4 and the first protective layer 170_4 can be aligned with each other. Furthermore, the inner walls of the contact holes in the first protective layer 170_4 and the buffer layer 120_4 can be aligned with each other. However, the embodiments of this disclosure are not limited thereto.

[0186] In some embodiments, the source electrode and drain electrode are not only on the active layer, but can also be directly on the buffer layer 120.

[0187] Figure 34 This is a plan view illustrating a switching transistor according to some embodiments of the present disclosure. Figure 35 It shows including Figure 34 A cross-sectional view of a display device with switching transistors.

[0188] Reference Figure 34 and Figure 35 In some embodiments, the source electrodes 330_5 and 430_5 and the drain electrodes 340_5 and 440_5 of the driving transistor DRT_5 and the switching transistor SCT_5 may also be on the buffer layer 120. Some embodiments are similar to... Figure 7 The difference in some embodiments lies in the fact that the shapes of the source electrode and the drain electrode of the second conductive layer are different. Therefore, the description will focus on the differences, and redundant descriptions will not be repeated here.

[0189] One side of each of the source electrodes 330_5 and 430_5 and the drain electrodes 340_5 and 440_5 of the second conductive layer may be on the buffer layer 120, while the other side of each may be on the active layers 350_5 and 450_5 of the first semiconductor layer. For example, one side (e.g., the left side) of the first source electrode 330_5 may be on the buffer layer 120, while the other side (e.g., its right side) may be on the first active layer 350_5. One side (e.g., the right side) of the first drain electrode 340_5 may be on the buffer layer 120, while the other side (e.g., its left side) may be located on the first active layer 350_5. Similarly, one side of each of the second source electrode 430_5 and the second drain electrode 440_5 may be on the buffer layer 120, while the other side may be on the second active layer 450_5.

[0190] Such a structure can be formed by patterning portions of the first semiconductor layer and the second conductive layer during different process stages. According to some embodiments of this disclosure, portions of the first semiconductor layer are patterned before the formation of the second conductive layer, allowing the formation of a first active layer 350_5 and a second active layer 450_5. The second conductive layer is then formed such that one side of the source electrode and the other side of the drain electrode of the second conductive layer are not aligned with one side of the active layer of the first semiconductor layer.

[0191] Figure 36 This is a cross-sectional view of a display device according to some embodiments of the present disclosure.

[0192] Reference Figure 36 According to some embodiments of this disclosure, portions of the source electrodes 330_6 and 430_6 and the drain electrodes 340_6 and 440_6 of the driving transistor DRT_6 and the switching transistor SCT_6 may be on the buffer layer 120_6, and the oxide pattern OXP may be omitted. Some embodiments are similar to Figure 35The difference in some embodiments shown is that the oxide pattern OXP is omitted, therefore, the source electrodes 330_6 and 430_6 and the drain electrodes 340_6 and 440_6 of the second conductive layer are in direct contact with the first electrode PXE_4 and the electrode pattern PXP_4 of the third conductive layer. Other features are the same as those described above. Figure 30 and Figure 35 The described features are the same or substantially the same, therefore, redundant descriptions will not be repeated here.

[0193] Those skilled in the art will understand that many variations and modifications can be made to the disclosed embodiments without substantially departing from the principles of this disclosure. Therefore, the disclosed embodiments are not provided for limiting purposes.

Claims

1. A display device, the display device comprising: The substrate includes the display area and the pad area; A first conductive layer is located on the substrate, the first conductive layer including a gate electrode in the display area and a pad electrode in the pad area; A buffer layer is located on the first conductive layer, the buffer layer covering the gate electrode and exposing a portion of the pad electrode; A first semiconductor layer is located on the buffer layer and includes an oxide semiconductor. The first semiconductor layer includes a first active layer and a second active layer in the display area. A second conductive layer is located on the first semiconductor layer, and the second conductive layer includes a source electrode and a drain electrode in the display area; A first protective layer is located on the second conductive layer, the first protective layer covering the source electrode and the drain electrode and exposing a portion of the pad electrode; A second semiconductor layer is located on the first protective layer and includes an oxide semiconductor, wherein the second semiconductor layer includes at least one oxide layer in the display area; A first planarization layer is located on the second semiconductor layer; as well as A third conductive layer is located on the first planarization layer, the third conductive layer including a first electrode electrically connected to one of the source electrodes through contact holes penetrating the first planarization layer and the first protective layer. Wherein, the at least one oxide layer of the second semiconductor layer is located above at least one selected from the first active layer and the second active layer. The second semiconductor layer further includes multiple oxide patterns, which are in contact with the source electrode and the drain electrode. The oxide layer and the plurality of oxide patterns are disposed on different layers from the first electrode, and the first planarization layer is disposed in the thickness direction between the oxide layer and the plurality of oxide patterns and the first electrode. The third conductive layer further includes a plurality of electrode patterns spaced apart from the first electrode, the plurality of electrode patterns being in contact with the plurality of oxide patterns through contact holes penetrating the first planarization layer and the first protective layer.

2. The display device according to claim 1, wherein, The oxide semiconductor of the first semiconductor layer and the second semiconductor layer includes at least one selected from the group consisting of indium, gallium, zinc, tin and hafnium.

3. The display device according to claim 1, wherein, The second conductive layer includes: The first source electrode is located on the first side of the first active layer; The first drain electrode is located on the second side of the first active layer; The second source electrode is located on the first side of the second active layer; and The second drain electrode is located on the second side of the second active layer.

4. The display device according to claim 3, wherein, One side of the first source electrode is aligned with one side of the first active layer, and One side of the first drain electrode is aligned with the other side of the first active layer, and The other side of the first source electrode and the other side of the first drain electrode are located on the first active layer.

5. The display device according to claim 3, wherein, One side of the second source electrode is located on the buffer layer, and One side of the second drain electrode is located on the buffer layer, and The other side of the second source electrode and the other side of the second drain electrode are located on the second active layer.

6. The display device according to claim 3, wherein, The first protective layer includes a plurality of grooves, and a portion of the upper surface of the first protective layer is recessed within the plurality of grooves. The plurality of grooves includes a first groove between the first source electrode and the first drain electrode and a second groove between the second source electrode and the second drain electrode.

7. The display device according to claim 6, wherein, The oxide layer of the second semiconductor layer contacts the gate electrode through a contact hole that penetrates the first protective layer and the buffer layer to expose a portion of the upper surface of the gate electrode.

8. The display device according to claim 6, wherein, The oxide layer includes a first oxide layer above the first active layer.

9. The display device according to claim 8, wherein, The first groove is stacked with the first active layer in the thickness direction, and The first oxide layer is located in the first groove.

10. The display device according to claim 6, wherein, The second groove is stacked with the second active layer in the thickness direction, and The oxide layer includes a second oxide layer in the second groove above the second active layer.

11. The display device according to claim 6, wherein, The first protective layer includes: a first contact hole penetrating the first protective layer to expose a portion of the upper surface of the first source electrode, and The second contact hole penetrates the first protective layer to expose a portion of the upper surface of the first drain electrode.

12. The display device according to claim 11, wherein, The plurality of oxide patterns include: a first oxide pattern, which contacts the first source electrode through the first contact hole, and The second oxide pattern contacts the first drain electrode through the second contact hole.

13. The display device according to claim 6, wherein, The first planarization layer includes: a third contact hole penetrating the first planarization layer and the first protective layer to expose a portion of the upper surface of the oxide pattern among the plurality of oxide patterns that contacts the source electrode; and A fourth contact hole penetrates the first planarization layer and the first protective layer to expose a portion of the upper surface of the oxide pattern among the plurality of oxide patterns that is in contact with the drain electrode.

14. The display device according to claim 13, wherein, The plurality of electrode patterns includes: a first electrode pattern, which contacts the oxide pattern among the plurality of oxide patterns that is in contact with the source electrode through the third contact hole, and The second electrode pattern contacts the oxide pattern among the plurality of oxide patterns that is in contact with the drain electrode through the fourth contact hole.

15. The display device according to claim 1, wherein, The buffer layer includes a fifth contact hole that penetrates the buffer layer to expose a portion of the upper surface of the pad electrode. The second semiconductor layer is located in the pad region, and the second semiconductor layer further includes a third oxide pattern that contacts the pad electrode through the fifth contact hole.

16. The display device according to claim 15, wherein, The first protective layer further includes: a sixth contact hole that penetrates the first protective layer to expose a portion of the third oxide pattern and a portion of the upper surface of the buffer layer, and The third conductive layer further includes a third electrode pattern located in the pad region and in contact with the third oxide pattern through the sixth contact hole.

17. A display device comprising pixels connected to scan lines and data lines intersecting the scan lines. in, Each of the pixels includes: The light-emitting element includes a first electrode, an organic emitting layer, and a second electrode; The driving transistor controls the driving current supplied to the light-emitting element based on the data voltage applied from the data line; and A switching transistor applies the data voltage of the data line to the driving transistor according to the scan signal applied from the scan line. The driving transistor includes a first active layer having an oxide semiconductor, a first gate electrode below the first active layer, and a first source electrode and a first drain electrode above the first active layer. The switching transistor includes a second active layer, a second gate electrode below the second active layer, and a second source electrode and a second drain electrode above the second active layer. The second active layer has the same oxide semiconductor as the oxide semiconductor of the first active layer. Wherein, at least one selected from the driving transistor and the switching transistor is included above each of the active layers of the selected transistor and includes an oxide layer of oxide semiconductor. Each of the pixels further includes multiple oxide patterns, which are located in the same layer as the oxide layer and are in contact with the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode. The oxide layer and the plurality of oxide patterns are disposed on different layers from the first electrode, and a first planarization layer is disposed in the thickness direction between the oxide layer and the plurality of oxide patterns and the first electrode. The first protective layer is located on the first active layer of the driving transistor and on the second active layer of the switching transistor. Each of the pixels further includes a plurality of electrode patterns spaced apart from the first electrode, the plurality of electrode patterns being in contact with the plurality of oxide patterns through contact holes penetrating the first planarization layer and the first protective layer.

18. The display device according to claim 17, wherein, The oxide semiconductor of the oxide layer includes at least one selected from the group consisting of indium, gallium, zinc, tin and hafnium.

19. The display device according to claim 18, wherein, The driving transistor further includes a first oxide layer located on the first protective layer and stacked with the first active layer in the thickness direction.

20. The display device according to claim 19, wherein, The switching transistor further includes a second oxide layer located on the first protective layer and stacked with the second active layer in the thickness direction.

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