Wireless communication circuit with reduced interference

Abstract

The present invention discloses a wireless communication circuit for reducing interference, the wireless communication circuit for reducing interference includes: a circuit board, a chip and a crystal; the circuit board is provided with a first grounding port and at least two second grounding ports; the chip is provided with a third grounding port, the third grounding port is connected to the first grounding port of the circuit board; the chip includes a crystal oscillator; the crystal is provided with a fourth grounding port, the fourth grounding port can be connected to a second grounding port of the circuit board; the crystal can select different second grounding ports, and selecting different second grounding ports can make the external environment interfere with the crystal oscillator differently. The wireless communication circuit for reducing interference proposed by the present invention separates the ground of the chip from the ground of the crystal, flexibly selects the grounding point of the crystal, and finally reduces the interference of the external environment to the crystal oscillator.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits and relates to a wireless communication circuit, and in particular to a wireless communication circuit capable of reducing interference. Background Art

[0002] With the progress of the times, science and technology have developed rapidly and gradually integrated into people's lives. The pursuit of miniaturization and even micro-miniaturization of equipment has become increasingly urgent.

[0003] The miniaturization and even micro-miniaturization of electronic devices has brought unprecedented difficulties and challenges to the design of RF systems. As the area of ​​​​the circuit board becomes smaller, the shortage of routing resources and the rapid increase in the complexity of the layout of electronic components are accompanied. Usually, electronic components that originally have electromagnetic interference have to be placed together in order to improve the integration. Typical miniaturized devices such as wireless Bluetooth headsets have to place Bluetooth chips, power management chips, and even audio chips in an extremely narrow space, not to mention the various passive components such as resistors, capacitors, and inductors that exist to match these chips. What's more challenging is that in order to obtain more functions and better performance, the number of pins on the chip has increased instead of decreased, which has led to more electronic components that need to be accommodated in a narrow space.

[0004] As the size of the printed circuit board PCB decreases, the ground layout of the entire circuit board will become less strong, which will cause the jitter on the ground line to become larger, making the chip more susceptible to interference. In addition, in order to save costs, more and more products use 2-layer boards, and the ground layout will become more difficult.

[0005] In wireless communication systems, in addition to chips, the two most important and indispensable components are crystals or crystal oscillators and antennas or antenna arrays. The mutual interference between them becomes stronger and stronger as the size of the PCB decreases and the number of layers decreases. At the least, it affects the RF performance, such as the sensitivity of the receiver and the error vector amplitude (EVM) of the transmitter, and at the worst, it makes the entire communication system unable to work properly. Of course, digital systems, such as the communication between flash memory devices FLASH and chips, traditional serial communication UART, etc. can also interfere with the RF communication system. Therefore, it is particularly important to effectively reduce the mutual interference between them.

[0006] Because the output signal voltage swing of the power amplifier is very large, usually part of the energy will be transmitted to the ground line of the entire PCB. The disturbance magnitude and phase of the ground line at different locations are different. Figure 1 As shown in the figure, the ① area shows the crystal oscillator circuit inside the chip, and the ② area shows the simplified model of the external crystal. fbIt is the feedback resistor of the inverter, providing a suitable DC bias voltage for the inverter. L1 and C L2 is the on-chip load capacitance of the crystal oscillator. L0, L1 and L2 are the inductances of the connection from the chip internal pad PAD to the corresponding PIN pin of the chip package. The inductance values ​​of these inductors may be different. R1 and R2 are the series resistors added to the two PIN pins of the crystal oscillator on the PCB board. The two resistor values ​​can be different, or there can be only one resistor or no resistor. C p1 ,C p2 It refers to all the capacitances on the two pins of the external crystal oscillator of the chip, including but not limited to the parasitic capacitance of the wiring of the two pins on the PCB board, the external load capacitance and the parasitic capacitance inside the crystal, etc. Interference can usually deteriorate the quality of the final power amplifier output signal through the following situations.

[0007] (1) The interference enters the crystal oscillator through the ground wire GND_0 inside the chip, and generates a spurious frequency related to the power amplifier frequency and the local oscillator frequency at the output of the crystal oscillator. This spurious frequency will affect the quality of the local oscillator output signal, thereby affecting the final EVM.

[0008] (2) The interference enters the crystal oscillator inside the chip through the crystal ground line GND_1, and generates a spurious frequency related to the power amplifier frequency and the local oscillator frequency at the output of the crystal oscillator, thereby affecting the final EVM.

[0009] In order to reduce the impact of the external environment on the crystal oscillator, the crystal is usually placed as close to the chip as possible. Based on this consideration, the ground wire of the crystal and the ground wire of the chip are usually connected together, and the interference to the entire system through these two ground wires will have a certain degree of randomness. For example, different parasitic capacitances, different board sizes, and different thickness and length of the connection between the chip ground wire and the crystal ground wire may cause the quality of the final output RF signal to deteriorate.

[0010] Traditional solutions generally include the following methods:

[0011] (1) Use multi-layer PCB layout and wiring to make the ground line of the entire chip stable enough, thereby reducing the crosstalk of the output signal of the power amplifier to the ground line and reducing its interference with the crystal oscillator. This method significantly increases the hardware cost compared to a two-layer PCB.

[0012] (2) Increase the size of the PCB board so that the antenna feed point is far away from the chip and the crystal, thereby reducing the crosstalk of the power amplifier to the ground wires at the above two points. This method is limited by the size of the PCB board and will become less and less suitable for the overall trend of miniaturization design.

[0013] (3) By adding resistors R1 and R2, interference is blocked from entering the crystal oscillator from the outside, and the impedance seen by the internal nodes of the crystal oscillator chip to the outside of the chip is increased, so that the input and output of the inverter shown in the figure swing with GND_0, turning the interference into common-mode noise and eliminating its influence. Adding resistors to the crystal pins will increase the power consumption of the circuit at best, and cause the crystal oscillator to fail to oscillate at worst, resulting in fatal functional defects.

[0014] (4) By adding external capacitors (as C p1 ,C p2 Part of the circuit), forcing GND_0 and GND_1 to share the same ground can also make the interference of the ground wire appear as common mode noise to the crystal oscillator, thereby eliminating its influence on the output signal. However, the external load capacitor will increase the area of ​​the PCB board and increase the cost of the entire hardware design.

[0015] In view of this, there is an urgent need to design a new wireless communication circuit to overcome at least part of the above-mentioned defects of the existing wireless communication circuit. Summary of the invention

[0016] The present invention provides a wireless communication circuit with reduced interference, which can flexibly select the grounding point of the crystal, ultimately reducing the interference of the external environment on the crystal oscillator, and at the same time can reduce the cost of the product.

[0017] To solve the above technical problem, according to one aspect of the present invention, the following technical solution is adopted:

[0018] A wireless communication circuit for reducing interference, the wireless communication circuit comprising:

[0019] A circuit board is provided with a first grounding port and at least two second grounding ports;

[0020] A chip is provided with a third grounding port, wherein the third grounding port is connected to the first grounding port of the circuit board; the chip includes a crystal oscillator;

[0021] The crystal is provided with a fourth grounding port, which can be connected to a second grounding port of the circuit board; the crystal can select different second grounding ports, and selecting different second grounding ports can cause different interferences of the external environment on the crystal oscillator.

[0022] As an implementation mode of the present invention, after the fourth ground port is connected to the corresponding second ground port through a wire, the connecting wire is equivalent to an inductor and a capacitor connected in parallel;

[0023] The set second ground port is connected to the fourth ground port, so that the interference amount at both ends of the crystal oscillator has the same amplitude and phase as the interference amount on the first ground port.

[0024] As an implementation mode of the present invention, the crystal oscillator includes an inverter and a feedback resistor; the crystal oscillator is provided with an on-chip load capacitor, including a first capacitor and a second capacitor; the inductance of the connection from the internal pad of the chip to the corresponding pin of the chip package includes a first inductance, a second inductance and a third inductance;

[0025] The input end of the inverter is respectively connected to the first end of the feedback resistor, the first end of the first capacitor, and the first end of the first inductor; the output end of the inverter is respectively connected to the second end of the feedback resistor, the first end of the second capacitor, and the first end of the third inductor;

[0026] The second end of the first capacitor and the second end of the second capacitor are respectively connected to the first end of the second inductor; and the second end of the second inductor is grounded.

[0027] As an implementation mode of the present invention, all the capacitors of the two pins of the crystal are the third capacitor and the fourth capacitor respectively; the connecting wire is equivalent to the fifth capacitor and the fourth inductor;

[0028] The first end of the crystal is connected to the first end of the third capacitor, and the second end of the crystal is connected to the first end of the fourth capacitor;

[0029] The second end of the third capacitor is respectively connected to the second end of the fourth capacitor, the first end of the fifth capacitor, and the first end of the fourth inductor; the second end of the fifth capacitor and the second end of the fourth inductor are respectively grounded.

[0030] As an implementation mode of the present invention, the crystal oscillator includes an inverter and a feedback resistor; the crystal oscillator is provided with an on-chip load capacitor, including a first capacitor and a second capacitor; the inductance of the connection from the internal pad of the chip to the corresponding pin of the chip package includes a first inductance, a second inductance and a third inductance;

[0031] All the capacitors of the two pins of the crystal are the third capacitor and the fourth capacitor respectively; the connecting wire is equivalent to the fifth capacitor and the fourth inductor;

[0032] The input end of the inverter is respectively connected to the first end of the feedback resistor, the first end of the first capacitor, and the first end of the first inductor; the output end of the inverter is respectively connected to the second end of the feedback resistor, the first end of the second capacitor, and the first end of the third inductor;

[0033] The second end of the first capacitor and the second end of the second capacitor are respectively connected to the first end of the second inductor; the second end of the second inductor is grounded;

[0034] The second end of the first inductor is respectively connected to the first end of the crystal and the first end of the third capacitor, and the second end of the third inductor is respectively connected to the second end of the crystal and the first end of the fourth capacitor;

[0035] The first end of the crystal is connected to the first end of the third capacitor, and the second end of the crystal is connected to the first end of the fourth capacitor;

[0036] The second end of the third capacitor is respectively connected to the second end of the fourth capacitor, the first end of the fifth capacitor, and the first end of the fourth inductor; the second end of the fifth capacitor and the second end of the fourth inductor are respectively grounded.

[0037] As an implementation manner of the present invention, the wireless communication circuit includes an antenna, the chip is connected to the antenna, and one end of the antenna is grounded.

[0038] As an implementation manner of the present invention, radio frequency signal components having substantially the same amplitude (amplitude difference is within a predetermined range) but different phases exist at a plurality of second ground ports of the circuit board.

[0039] As an implementation manner of the present invention, the chip includes a power amplifier.

[0040] The beneficial effect of the present invention is that the wireless communication circuit for reducing interference proposed by the present invention separates the ground of the chip from the ground of the crystal, flexibly selects the grounding point of the crystal, and ultimately reduces the interference of the external environment on the crystal oscillator.

[0041] The present invention can be applied to any scenario where a crystal oscillator is used, and does not change with the type, number of layers, and size of the PCB board. The present invention is extremely flexible and provides maximum freedom for the design of the PCB board, which will ultimately reduce the size of the PCB board and reduce the cost of the entire solution.

[0042] Compared with the solution of adding resistance to the signal path, the present invention has no effect on the start-up of the crystal oscillator and does not increase power consumption. Compared with the external capacitor solution, the present invention does not require additional material costs, thereby saving PCB wiring resources and reducing solution costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a simplified model diagram of a traditional crystal oscillator circuit.

[0044] Figure 2 FIG. 4 is a schematic diagram of a wireless communication circuit in an embodiment of the present invention.

[0045] Figure 3 It is a schematic diagram of a simplified model of a wireless communication circuit in one embodiment of the present invention. DETAILED DESCRIPTION

[0046] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0048] The description in this section is only for several typical embodiments, and the present invention is not limited to the scope of the embodiments. The same or similar prior art means and some technical features in the embodiments are mutually replaced within the scope of the present invention.

[0049] The term "connection" as used in the specification includes both direct connection and indirect connection, such as connection through some active devices, passive devices or electrically conductive media; it may also include connection through other active devices or passive devices known to those skilled in the art on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits.

[0050] The present invention discloses a wireless communication circuit for reducing interference. Figure 2 is a schematic diagram of a wireless communication circuit in an embodiment of the present invention, Figure 3 This is a simplified model diagram of a wireless communication circuit in one embodiment of the present invention; please refer to Figure 2 , Figure 3 , the wireless communication circuit includes a circuit board (PCB) 1, a chip 2 and a crystal 3. The circuit board 1 is provided with a first ground port and at least two second ground ports. The chip 2 is provided with a third ground port GND_0, and the third ground port GND_0 is connected to the first ground port of the circuit board 1; the chip 2 includes a crystal oscillator 21. The crystal 3 is provided with a fourth ground port GND_1, and the fourth ground port GND_1 can be connected to a second ground port of the circuit board 1; the crystal 3 can select different second ground ports, and selecting different second ground ports can make the external environment interfere with the crystal oscillator differently. In one embodiment, the external environment here refers to a signal outside the crystal oscillator, such as interference entering the crystal oscillator through the internal ground line GND_0 of the chip, such as interference entering the crystal oscillator inside the chip through the ground line GND_1 of the crystal.

[0051] In one embodiment of the present invention, the plurality of second ground ports of the circuit board 1 have radio frequency signal components with substantially consistent amplitudes (amplitude differences are within a predetermined range) but different phases.

[0052] like Figure 2As shown, in one embodiment of the present invention, the wireless communication circuit includes an antenna 4, the chip 2 is connected to the antenna 4, and one end of the antenna 4 is grounded. In addition, the chip 2 may also include a power amplifier.

[0053] In one embodiment of the present invention, after the fourth ground port GND_1 is connected to the corresponding second ground port through a wire, the connecting wire is equivalent to a parallel inductor and capacitor; the set second ground port is connected to the fourth ground port GND_1, so that the interference amount at both ends of the crystal oscillator 21 has the same amplitude and phase as the interference amount on the third ground port GND_0.

[0054] See also Figure 3 In one embodiment of the present invention, the crystal oscillator 21 includes an inverter 210, a feedback resistor R fb The crystal oscillator 21 is provided with an on-chip load capacitor, including a first capacitor C L1 , the second capacitor C L2 The inductors connected from the internal pads of the chip to the corresponding pins of the chip package include a first inductor L1, a second inductor L0 and a third inductor L2. The input ends of the inverter 210 are respectively connected to the feedback resistors R fb The first end of the first capacitor C L1 The output end of the inverter 210 is connected to the feedback resistor R fb The second end of the second capacitor C L2 and the first end of the third inductor L2. The first capacitor C L1 The second end of the second capacitor C L2 The second ends of the second inductors L0 are respectively connected to the first ends of the second inductors L0; and the second ends of the second inductors L0 are grounded.

[0055] Please continue reading Figure 3 In one embodiment, all the capacitors of the two pins of the crystal 3 are respectively the third capacitor C p1 , the fourth capacitor C p2 ; The connecting wire is equivalent to the fifth capacitor C eq And the fourth inductor L eq The second end of the first inductor L1 is connected to the first end of the crystal 3 and the third capacitor C p1 The first end of the third inductor L2 is connected to the second end of the crystal 3 and the fourth capacitor C p2 The third capacitor C p1 The second ends of the fourth capacitors C p2 The second end of the fifth capacitor C eq The first end of the fourth inductor C p2 The first end of the fifth capacitor Ceq The second end of the fourth inductor L eq The second ends of are respectively grounded.

[0056] In summary, the wireless communication circuit for reducing interference proposed by the present invention separates the ground of the chip from the ground of the crystal, flexibly selects the grounding point of the crystal, and ultimately reduces the interference of the external environment on the crystal oscillator.

[0057] The present invention can be applied to any scenario where a crystal oscillator is used, and does not change with the type, number of layers, and size of the PCB board. The present invention is extremely flexible and provides maximum freedom for the design of the PCB board, which will ultimately reduce the size of the PCB board and reduce the cost of the entire solution.

[0058] Compared with the solution of adding resistance to the signal path, the present invention has no effect on the start-up of the crystal oscillator and does not increase power consumption. Compared with the external capacitor solution, the present invention does not require additional material costs, thereby saving PCB wiring resources and reducing solution costs.

[0059] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0060] The description and application of the present invention here are illustrative, and it is not intended to limit the scope of the present invention to the above-mentioned embodiments. The effects or advantages involved in the embodiments may not be embodied in the embodiments due to interference from various factors, and the description of the effects or advantages is not used to limit the embodiments. The deformation and change of the embodiments disclosed here are possible, and the replacement of the embodiments and the various equivalent parts are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential features of the present invention. Other deformations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. A wireless communication circuit for reducing interference, It is characterized in that The wireless communication circuit comprises: A circuit board is provided with a first grounding port and at least two second grounding ports; A chip is provided with a third grounding port, wherein the third grounding port is connected to the first grounding port of the circuit board; the chip includes a crystal oscillator; The crystal is provided with a fourth grounding port, the fourth grounding port can be connected to a second grounding port of the circuit board; the crystal can select different second grounding ports, and selecting different second grounding ports can make the external environment interfere with the crystal oscillator differently; After the fourth ground port is connected to the corresponding second ground port through a wire, the connecting wire is equivalent to an inductor and a capacitor connected in parallel; The second ground port is set to be connected to the fourth ground port so that the interference amount at both ends of the crystal oscillator has the same amplitude and phase as the interference amount on the third ground port; All the capacitors of the two pins of the crystal are the third capacitor and the fourth capacitor respectively; the connecting wire is equivalent to the fifth capacitor and the fourth inductor; The first end of the crystal is connected to the first end of the third capacitor, and the second end of the crystal is connected to the first end of the fourth capacitor; The second end of the third capacitor is respectively connected to the second end of the fourth capacitor, the first end of the fifth capacitor, and the first end of the fourth inductor; the second end of the fifth capacitor and the second end of the fourth inductor are respectively grounded.

2. The wireless communication circuit for reducing interference according to claim 1, Features: The crystal oscillator includes an inverter and a feedback resistor; the crystal oscillator is provided with an on-chip load capacitor, including a first capacitor and a second capacitor; the inductance of the connection from the internal pad of the chip to the corresponding pin of the chip package includes a first inductance, a second inductance and a third inductance; The input end of the inverter is respectively connected to the first end of the feedback resistor, the first end of the first capacitor, and the first end of the first inductor; the output end of the inverter is respectively connected to the second end of the feedback resistor, the first end of the second capacitor, and the first end of the third inductor; The second end of the first capacitor and the second end of the second capacitor are respectively connected to the first end of the second inductor; and the second end of the second inductor is grounded.

3. The wireless communication circuit for reducing interference according to claim 1, Features: The crystal oscillator includes an inverter and a feedback resistor; the crystal oscillator is provided with an on-chip load capacitor, including a first capacitor and a second capacitor; the inductance of the connection from the internal pad of the chip to the corresponding pin of the chip package includes a first inductance, a second inductance and a third inductance; All the capacitors of the two pins of the crystal are the third capacitor and the fourth capacitor respectively; the connecting wire is equivalent to the fifth capacitor and the fourth inductor; The input end of the inverter is respectively connected to the first end of the feedback resistor, the first end of the first capacitor, and the first end of the first inductor; the output end of the inverter is respectively connected to the second end of the feedback resistor, the first end of the second capacitor, and the first end of the third inductor; The second end of the first capacitor and the second end of the second capacitor are respectively connected to the first end of the second inductor; the second end of the second inductor is grounded; The second end of the first inductor is respectively connected to the first end of the crystal and the first end of the third capacitor, and the second end of the third inductor is respectively connected to the second end of the crystal and the first end of the fourth capacitor; The first end of the crystal is connected to the first end of the third capacitor, and the second end of the crystal is connected to the first end of the fourth capacitor; The second end of the third capacitor is respectively connected to the second end of the fourth capacitor, the first end of the fifth capacitor, and the first end of the fourth inductor; the second end of the fifth capacitor and the second end of the fourth inductor are respectively grounded.

4. The wireless communication circuit for reducing interference according to claim 1, Features: The wireless communication circuit comprises an antenna, the chip is connected to the antenna, and one end of the antenna is grounded.

5. The wireless communication circuit for reducing interference according to claim 1, Features: At least two second ground ports of the circuit board have radio frequency signal components with amplitude differences within a predetermined range but different phases.

6. The wireless communication circuit for reducing interference according to claim 1, Features: The chip includes a power amplifier.

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