Display device with a sensor area

Abstract

The present invention discloses a display device having a sensor area. The display device includes a display panel, and the display panel includes a main area and a sensor area. A sensor device overlaps with the sensor area of the display panel in the thickness direction of the display panel. The display panel includes first sub-pixels arranged in the sensor area and second sub-pixels arranged in the main area. The number of transistors of each of the first sub-pixels is different from the number of transistors of each of the second sub-pixels.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a display device having a sensor region. Background Art

[0002] Display devices are becoming more widely used in a variety of different forms. For example, display devices have been adapted for use in various electronic devices such as smart phones, digital cameras, notebook / laptop computers, navigation devices, smart and traditional televisions (TVs). A conventional display device may include a display panel that includes a plurality of pixels connected to scan lines, data lines, and power lines to display an image. The display device may further include various sensor devices, such as a proximity sensor for detecting the presence of a nearby user, an illuminance sensor for detecting brightness, and an iris sensor for identifying a user's iris. The sensor devices may be disposed in a hole provided in front of the display device so as not to overlap with the display panel.

[0003] Meanwhile, as the types and functions of display devices become diversified, the demand for display devices of various designs has increased. For example, for a smart phone, the display device may have a hole or notch in the display area for accommodating various sensor devices, such that the sensor devices do not need to be disposed at the periphery of the display area, thereby providing a widened display area. Some other display devices may avoid the need for holes and notches by arranging the sensors to at least partially overlap the display area. However, if the sensor devices are arranged to at least partially overlap the display panel, the sensing ability of the sensor devices may be reduced because the sensor devices are hidden by the pixels, scan lines, data lines, and power lines of the display panel. Summary of the Invention

[0004] A display device includes a display panel that includes a main region and a sensor region. A plurality of sensor devices at least partially overlap the sensor region of the display panel in a thickness direction of the display panel. The display panel includes first sub-pixels disposed in the sensor region and second sub-pixels disposed in the main region, and the number of transistors of each of the first sub-pixels is different from the number of transistors of each of the second sub-pixels.

[0005] The number of transistors of each of the first sub-pixels may be less than the number of transistors of each of the second sub-pixels.

[0006] The display panel may further include scan lines, data lines, and emission lines. Each of the first sub-pixel and the second sub-pixel may include: a driving transistor configured to control a driving current flowing from a first electrode of the driving transistor to a second electrode according to a data voltage applied to a gate electrode of the driving transistor; a light-emitting element connected to the second electrode of the driving transistor; a first transistor turned on by a scan signal from one of the scan lines to connect the gate electrode of the driving transistor to an initialization voltage line to which an initialization voltage is applied; a second transistor turned on by a scan signal from another one of the scan lines to connect the first electrode of the driving transistor to one of the data lines; a third transistor turned on by a scan signal from yet another one of the scan lines to connect the gate electrode and the second electrode of the driving transistor; a fourth transistor turned on by an emission signal from one of the emission lines to connect the first electrode of the driving transistor to a first driving voltage line to which a first driving voltage is applied; and a fifth transistor turned on by the emission signal to connect the second electrode of the driving transistor to the light-emitting element.

[0007] Each of the second sub-pixels may further include a sixth transistor turned on by a scan signal from still another one of the scan lines to connect a first electrode of the light-emitting element to the initialization voltage line.

[0008] The display panel may further include scan lines that at least partially overlap with the first sub-pixels and the second sub-pixels and to which scan signals are applied. The number of scan lines that at least partially overlap with each of the first sub-pixels may be different from the number of scan lines that at least partially overlap with each of the second sub-pixels.

[0009] The number of scan lines that at least partially overlap with each of the first sub-pixels may be less than the number of scan lines that at least partially overlap with each of the second sub-pixels.

[0010] The display panel may further include a light-transmitting region disposed in a sensor region and not overlapping with the first sub-pixels.

[0011] The light-transmitting region may be at least partially surrounded by the first sub-pixels.

[0012] The display panel may further include a first scan connection line connected to one of the scan lines and disposed in a different layer from the scan lines in a wiring region between the light-transmitting region and the first sub-pixels.

[0013] The display panel may further include an insulating film disposed between the first scan connection line and the scan line connected to the first scan connection line. The first scan connection line may be connected to the scan line to which the first scan connection line is connected through a contact hole penetrating the insulating film.

[0014] The display panel may further include: an initialization voltage line that at least partially overlaps with the first sub-pixel and the second sub-pixel and to which an initialization voltage is applied, a data line that at least partially overlaps with the first sub-pixel and the second sub-pixel and to which a data voltage is applied, and a first driving voltage line that at least partially overlaps with the first sub-pixel and the second sub-pixel and to which a first driving voltage is applied.

[0015] The display panel may further include a power connection line that is connected to one of the first driving voltage lines in a wiring area and is arranged in a different layer from the first driving voltage line.

[0016] One of the data lines may at least partially overlap with one of the initialization voltage lines or the first scan connection line in the wiring area.

[0017] The power connection line may at least partially overlap with one of the scan lines.

[0018] The display panel may further include an insulating film arranged between the power connection line and one of the first driving voltage lines. The power connection line may be connected to the first driving voltage line to which the power connection line is connected through a contact hole penetrating the insulating film.

[0019] The power connection line may be arranged on the data line and the first driving voltage line. The data line and the first driving voltage line may be arranged on the initialization voltage line and the first scan connection line. The initialization voltage line and the first scan connection line may be arranged on the scan line.

[0020] The display panel may further include an initialization connection line that is connected to one of the initialization voltage lines and may be arranged in a different layer from the initialization voltage line.

[0021] One of the data lines may at least partially overlap with the initialization connection line or the first scan connection line in the wiring area.

[0022] The display panel may further include an insulating film arranged between the initialization connection line and one of the initialization voltage lines. The initialization connection line may be connected to the initialization voltage line to which the initialization connection line is connected through a contact hole penetrating the insulating film.

[0023] The power connection line may be arranged on the data line and the first driving voltage line. The data line and the first driving voltage line may be arranged on the scan line. The scan line may be arranged on the initialization connection line and the first scan connection line.

[0024] The display panel may further include a second scan connection line connected to another one of the scan lines and disposed in a different layer from the scan lines, an emission line overlapping at least partially with the first sub-pixel and the second sub-pixel and to which an emission signal is applied, and an emission connection line connected to one of the emission lines and disposed in a different layer from the emission lines.

[0025] In the wiring area, one of the data lines may at least partially overlap with the second scan connection line, and another one of the data lines may at least partially overlap with the emission connection line.

[0026] The second scan connection line and the emission connection line may be disposed in the same layer.

[0027] The power connection line may be disposed on the data line and the first driving voltage line. The data line and the first driving voltage line may be disposed on the initialization voltage line and the first scan connection line. The initialization voltage line and the first scan connection line may be disposed on the scan line and the emission line. The scan line and the emission line may be disposed on the second scan connection line and the emission connection line.

[0028] The display panel may further include a voltage connection line connected to the first driving voltage line.

[0029] The first driving voltage line may mainly extend in a first direction. The voltage connection line may mainly extend in a second direction.

[0030] The voltage connection line may be disposed on the first driving voltage line.

[0031] The first driving voltage line may be disposed on the voltage connection line.

[0032] The voltage connection line may be disposed in the same layer as the initialization voltage line and may be disposed on the scan line.

[0033] The initialization voltage line may be disposed on the voltage connection line and may be disposed in the same layer as the scan line.

[0034] The first driving voltage line may be disposed in the same layer as the voltage connection line.

[0035] The display device includes: a display panel including a main area and a sensor area; and a sensor device at least partially overlapping with the sensor area of the display panel in the thickness direction of the display panel. The display panel includes a first sub-pixel disposed in the sensor area. A second sub-pixel is disposed in the main area. The first driving voltage line overlaps at least partially with the first sub-pixel and the second sub-pixel and is applied with a first driving voltage. The power connection line is connected to the first driving voltage line and is disposed in a different layer from the first driving voltage line.

[0036] The display device includes: a light-transmitting region; a plurality of sub-pixels at least partially surrounding the light-transmitting region; a first wire connected to the sub-pixels; and a second wire connected to the first wire in a wiring region between the light-transmitting region and the sub-pixels. The first wire and the second wire are arranged in different layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] A more complete understanding of the present disclosure will become apparent by specifically describing exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0038] Figure 1 is a perspective view of a display device according to an exemplary embodiment of the present disclosure;

[0039] Figure 2 is a diagrammatic illustration Figure 1 of an exploded perspective view of the display device;

[0040] Figure 3 is a diagrammatic illustration Figure 1 of a plan view of a display panel of the display device;

[0041] Figure 4 is a diagrammatic illustration Figure 1 of a block diagram of a display panel and a display driving circuit of the display device;

[0042] Figure 5 is a diagrammatic illustration Figure 1 of a plan view of a first sub-pixel, a scan line, a data line, and a first driving voltage line in a sensor region of the display device;

[0043] Figure 6 is a diagrammatic illustration Figure 1 of a plan view of a second sub-pixel, a scan line, a data line, and a first driving voltage line in a main region of the display device;

[0044] Figure 7 is a circuit diagram of an exemplary first sub-pixel;

[0045] Figure 8 is a circuit diagram of an exemplary second sub-pixel;

[0046] Figure 9 is a diagrammatic illustration Figure 7 of a plan view of the first sub-pixel;

[0047] Figure 10 is a diagrammatic illustration Figure 8 of a plan view of the second sub-pixel;

[0048] Figure 11 is a cross-sectional view taken along Figure 9 and Figure 10 line I-I' of;

[0049] Figure 12is a sectional view taken along line II-II' of Figure 9 ;

[0050] Figure 13 is a sectional view taken along line III-III' of Figure 10 ;

[0051] Figure 14 is a plan view showing region A of Figure 5 ;

[0052] Figure 15 is a sectional view taken along line IV-IV' of Figure 14 ;

[0053] Figure 16 is a plan view showing region A of Figure 5 ;

[0054] Figure 17 is a sectional view taken along line VIII-VIII' of Figure 16 ;

[0055] Figure 18 is a plan view showing region A of Figure 5 ;

[0056] Figure 19 is a sectional view taken along line V-V' of Figure 18 ;

[0057] Figure 20 is a plan view showing region A of Figure 5 ;

[0058] Figure 21 is a sectional view taken along line VI-VI' of Figure 20 ;

[0059] Figure 22 is a plan view showing pixels, scan lines, data lines, and first driving voltage lines in a sensor region of a display device of Figure 1 ;

[0060] Figure 23 is a plan view showing region B of Figure 22 ; and

[0061] Figure 24 is a sectional view taken along line VII-VII' of Figure 23 ; DETAILED DESCRIPTION

[0062] Exemplary embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. However, the present invention may be embodied in different forms and should not be construed as being uniquely limited to the exemplary embodiments presented herein. Throughout the specification and the drawings, like reference numerals may indicate like or corresponding components, and thus the description of an element may be omitted, assuming that the element is at least similar to the corresponding element described elsewhere in the specification. In the drawings, the sizes and thicknesses of layers and regions may be exaggerated for clarity. Thus, although the relative sizes and thicknesses of layers and regions in the drawings may illustrate a particular embodiment, these elements may also be exaggerated for clarity.

[0063] It will also be understood that when a layer or element is referred to as being "on" another layer or element, the element or layer may be directly on the other layer or element, or there may be intermediate layers or elements.

[0064] Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

[0065] Figure 1 is a perspective view illustrating a display device according to an exemplary embodiment of the present disclosure.

[0066] Referring to Figure 1 and Figure 2 , the display device 10 includes a cover window 100, a display panel 300, a display circuit board 310, a display driving circuit 320, a flexible film 390, a bracket 600, a main circuit board 700, sensor devices (740, 750, 760, and 770), and a lower cover / case 900.

[0067] As used herein, the terms "above", "top", and "top surface" indicate the direction in which the cover window 100 is disposed with respect to the display panel 300, i.e., the Z-axis direction. As used herein, the terms "below", "bottom", and "bottom surface" indicate the direction in which the bracket 600 is disposed with respect to the display panel 300, i.e., the opposite direction of the Z-axis direction. In addition, the terms "left", "right", "up", and "down" as used herein indicate the directions as viewed from above the display panel 300. For example, the term "left" indicates the opposite direction of the X-axis, the term "right" indicates the X-axis direction, the term "up" indicates the Y-axis direction, and the term "down" indicates the opposite direction of the Y-axis direction.

[0068] The display device 10, as a device for displaying moving images or still images, can be used not only in portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, or ultra-mobile PCs (UMPCs), but also in various other products such as televisions (TVs), notebook / laptop computers, computer monitors, electronic billboards, or Internet of Things (IoT) devices.

[0069] In a plan view, the display device 10 may have a substantially rectangular shape. For example, as Figure 1 and Figure 2 shown, the display device 10 may have a substantially rectangular shape having a pair of short sides extending mainly in a first direction (e.g., the X-axis direction) and a pair of long sides extending mainly in a second direction (e.g., the Y-axis direction). The corners where the short sides and long sides of the display device 10 intersect may be rounded to have a predetermined curvature (so as to form a rounded rectangle) or may be right-angled (so as to form a regular rectangle). The shape of the display device 10 is not particularly limited, and the display device 10 may be formed in various other polygonal shapes or in a circular or oval shape.

[0070] The display device 10 may include a first region DR1 formed to be flat and a second region DR2 that may have two portions extending from the left and right sides of the first region DR1. The second region DR2 may be flat or curved downward along the Z-axis. When the second region DR2 is flat, the angle formed by the first region DR1 and the second region DR2 may be an obtuse angle. When the second region DR2 is curved, the second region DR2 may have a uniform or variable curvature.

[0071] Figure 1 It is illustrated that the second region DR2 extends from the left and right sides of the first region DR1, but the present disclosure is not limited thereto. Alternatively, the second region DR2 may extend only from one of the left and right sides of the first region DR1. Yet another alternative is that the second region DR2 may extend not only from the left and right sides of the first region DR1 but also from the upper and lower sides of the first region DR1. For convenience, hereinafter the second region DR2 will be described as being disposed on the left and right sides of the display device 10.

[0072] The cover window 100 may be disposed on the display panel 300 to cover the top surface of the display panel 300. Accordingly, the cover window 100 may protect the top surface of the display panel 300 from impacts and contamination.

[0073] The cover window 100 may be disposed in the first region DR1 and the second region DR2. The cover window 100 may include a first light-transmitting region DA100 corresponding to the display panel 300, a second light-transmitting region SDA100, and a light-shielding region NDA100 corresponding to a region other than the display panel 300. The second light-transmitting region SDA100 may be disposed on one side of the first light-transmitting region DA100, for example, on the upper side of the first light-transmitting region DA100, as shown in Figure 1 and Figure 2 . The first light-transmitting region DA100 and the second light-transmitting region SDA100 may be disposed in the first region DR1 and the second region DR2. The light-shielding region NDA100 may be opaque. The light-shielding region NDA100 may be a decorative layer that can be seen by the user when no image is being displayed.

[0074] The display panel 300 may be disposed below the cover window 100. The display panel 300 may be disposed in both the first region DR1 and the second region DR2. Thus, the image displayed by the display panel 300 can be seen not only in the first region DR1 but also in the second region DR2. For example, through the cover window 100, the image displayed by the display panel 300 can be seen not only on the top surface of the display device 10 but also on the left and right edges of the display device 10.

[0075] The display panel 300 may include a main region MDA and a sensor region SDA. The main region MDA may be disposed to at least partially overlap with the first light-transmitting region DA100 of the cover window 100. The sensor region SDA may be disposed to at least partially overlap with the second light-transmitting region SDA100 of the cover window 100. The sensor region SDA may be disposed on one side of the main region MDA, for example, on the upper side of the main region MDA, as shown in Figure 2 , but the present disclosure is not limited thereto. For example, the sensor region SDA may be disposed adjacent to a corner of the display panel 300 to be at least partially surrounded by the main region MDA. Figure 2 The illustration shows that the display panel 300 includes a single sensor region SDA, but the present disclosure is not limited thereto. Alternatively, the display panel 300 may include multiple sensor regions SDA.

[0076] The display panel 300 may be a light-emitting display panel including light-emitting elements. For example, the display panel 300 may be an OLED display panel using organic light-emitting diodes (OLEDs), an mLED display panel using micro light-emitting diodes (mLEDs), a QLED display panel using quantum dot light-emitting diodes (QLEDs), or an inorganic light-emitting diode (ILED) display panel including an inorganic semiconductor. Hereinafter, the display panel 300 will be described as an OLED display panel.

[0077] The display circuit board 310 and the display driving circuit 320 can each be attached to one side of the display panel 300. One end of the display circuit board 310 can be attached, for example, via an anisotropic conductive film (ACF), to pads provided on one side of the display panel 300. The display circuit board 310 can be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a hybrid PCB (e.g., partially flexible and partially rigid).

[0078] The display driving circuit 320 receives a control signal and a power supply voltage through the display circuit board 310, and generates and outputs signals and voltages for driving the display panel 300. The display driving circuit 320 can be an integrated circuit (IC), and can be attached to the display panel 300 in a chip-on-glass (COG) or chip-on-plastic (COP) manner or by ultrasonic bonding, but the present disclosure is not limited thereto. The display driving circuit 320 can be attached to the display circuit board 310.

[0079] The touch driving circuit 330 can be disposed on the display circuit board 310. The touch driving circuit 330 can be an IC, and can be attached to the top surface of the display circuit board 310. The touch driving circuit 330 can be electrically connected to touch electrodes of a touch sensor layer of the display panel 300 through the display circuit board 310. The touch driving circuit 330 can output touch data including coordinates of a touch input from a user by applying touch driving signals to some of the touch electrodes (e.g., driving electrodes) of the touch sensor layer and detecting a change in charge in a capacitance between the driving electrodes and other touch electrodes (e.g., sensing electrodes) of the touch sensor layer by using the sensing electrodes. As a Figure 3 power supply unit 340 for providing a display driving voltage for driving the display driving circuit 320 can be additionally disposed on the display circuit board 310.

[0080] One side of the flexible film 390 can be attached to the top surface of the display panel 300 from below the display panel 300 via an ACF. The other side of the flexible film 390 can be attached to the top surface of the display circuit board 310 from above the display circuit board 310 via an ACF. The flexible film 390 can be bendable or foldable.

[0081] The flexible film 390 can be not provided, and the display circuit board 310 can be directly attached to one side of the display panel 300. In this case, one side of the display panel 300 can be bent toward the bottom surface of the display panel 300.

[0082] The bracket 600 can be arranged below the display panel 300. The bracket 600 can include plastic, metal, or both. A first camera hole CMH1 into which the first camera sensor 720 is inserted, a cable hole CAH through which a cable 314 connected to the display circuit board 310 passes, and a sensor hole SH in which each of the sensor devices (740, 750, 760, and 770) is arranged can each be formed in the bracket 600. Alternatively, the bracket 600 may not include the sensor hole SH and may be formed to not overlap with the sensor area SDA of the display panel 300.

[0083] The main circuit board 700 and the battery 790 can each be arranged below the bracket 600. The main circuit board 700 can be a PCB or an FPCB.

[0084] The main circuit board 700 can include a main processor 710, a first camera sensor 720, a main connector 730, and sensor devices (740, 750, 760, and 770). The first camera sensor 720 can be arranged on both the top surface and the bottom surface of the main circuit board 700, the main processor 710 can be arranged on the top surface of the main circuit board 700, and the main connector 730 can be arranged on the bottom surface of the main circuit board 700. Each of the sensor devices (740, 750, 760, and 770) can be arranged on the top surface of the main circuit board 700.

[0085] The main processor 710 can control various functions of the display device 10. For example, the main processor 710 can output digital video data to the display driving circuit 320 through the display circuit board 310 so that the display panel 300 can display an image. In addition, the main processor 710 can receive touch data from the touch driving circuit 330, can determine the coordinates of a touch input from a user, and can execute an application pointed to by an icon displayed at the coordinates of the touch input.

[0086] The main processor 710 can control the display device 10 according to sensor signals received from the sensor devices (740, 750, 760, and 770). For example, the main processor 710 can use a proximity sensor signal received from the proximity sensor 740 to determine whether there is an object near the top surface of the display device 10. In a call mode when a user uses the display device 10 for a call, if there is an object near the top surface of the display device 10, the main processor 710 may not execute an application pointed to by the coordinates of a touch input from the user.

[0087] The main processor 710 can determine the brightness at the top surface of the display device 10 according to an illuminance sensor signal received from the illuminance sensor 750. The main processor 710 can control the brightness of an image displayed by the display panel 10 based on the brightness detected at the top surface of the display device 10.

[0088] The main processor 710 may determine whether an iris image from a user is the same as an iris image previously stored in the memory based on an iris sensor signal received from the iris sensor 760. If the iris image from the user is the same as the iris image previously stored in the memory, the main processor 710 may unlock the display device 10 and may display a home screen on the display panel 300.

[0089] The first camera sensor 720 may process a static or moving image obtained by the image sensor and may output the processed image to the main processor 710. The first camera sensor 720 may be a complementary metal oxide semiconductor (CMOS) image sensor or a charge coupled device (CCD) image sensor. Since the first camera sensor 720 is exposed at the bottom surface of the lower cover 900 through the second camera hole CMH2, the first camera sensor 720 may capture an image of an object or a scene at the bottom of the display device 10.

[0090] A cable 314 passing through the cable hole CAH of the bracket 600 may be connected to the main connector 730. As a result, the main circuit board 700 may be electrically connected to the display circuit board 310.

[0091] The sensor devices (740, 750, 760, and 770) may include a proximity sensor 740, an illuminance sensor 750, an iris sensor 760, and a second camera sensor 770. However, other types of sensor devices may be used.

[0092] The proximity sensor 740 is a sensor for determining whether an object exists near the top surface of the display device 10. The proximity sensor 740 may include a light source that outputs light and a light receiver that receives light reflected from the object. The proximity sensor 740 may determine whether an object exists near the top surface of the display device 10 based on the amount of light reflected from the object. Since the proximity sensor 740 is arranged to at least partially overlap with the sensor hole SH, the sensor area SDA of the display panel 300, and the second light transmissive area SDA100 of the cover window 100 in the thickness direction (e.g., the Z-axis direction) of the display panel 300, the proximity sensor 740 may generate a proximity sensor signal according to the presence of an object near the top surface of the display device 10 and may output the proximity sensor signal to the main processor 710.

[0093] The illuminance sensor 750 is a sensor for detecting the brightness at the top surface of the display device 10. The illuminance sensor 750 may include a resistor whose resistance changes according to the brightness of incident light. The illuminance sensor 750 may determine the brightness at the top surface of the display device 10 based on the change in the resistance of the resistor caused by the brightness of incident light. Since the illuminance sensor 750 is arranged to at least partially overlap with the sensor hole SH, the sensor area SDA of the display panel 300, and the second light-transmitting area SDA100 of the cover window 100 in the thickness direction (e.g., the Z-axis direction) of the display panel 300, the illuminance sensor 750 may generate an illuminance sensor signal according to the brightness at the top surface of the display device 10 and may output the illuminance sensor signal to the main processor 710.

[0094] The iris sensor 760 is a sensor for determining whether an image of a user's iris is the same as an iris image previously stored in a memory. The iris sensor 760 may generate an iris sensor signal according to whether an image of a user's iris is the same as an iris image previously stored in a memory and may output the iris sensor signal to the main processor 710.

[0095] The second camera sensor 770 may process a still or moving image obtained by an image sensor and may output the processed image to the main processor 710. The second camera sensor 770 may be a CMOS image sensor or a CCD image sensor. The number of pixels of the second camera sensor 770 may be less than the number of pixels of the first camera sensor 720, and the size of the second camera sensor 770 may be less than the size of the first camera sensor 720. Since the second camera sensor 770 is arranged to at least partially overlap with the sensor hole SH, the sensor area SDA of the display panel 300, and the second light-transmitting area SDA100 of the cover window 100 in the thickness direction (e.g., the Z-axis direction) of the display panel 300, the second camera sensor 770 may capture an image of an object or background at the top of the display device 10.

[0096] The battery 790 may be arranged not to overlap with the main circuit board 700 in a third direction (e.g., the Z-axis direction). The battery 790 may at least partially overlap with the battery hole BH of the bracket 600.

[0097] A mobile communication module capable of exchanging wireless signals with a base station, an external terminal, and / or a server through a mobile communication network may be further provided on the main circuit board 700. The wireless signals may include various types of data associated with the transmission / reception of audio signals, video call signals, or text / multimedia messages.

[0098] The lower cover 900 can be disposed under the main circuit board 700 and the battery 790. The lower cover 900 can be coupled and fixed to the bracket 600. The lower cover 900 can form the bottom appearance of the display device 10. The lower cover 900 can include plastic, metal, or both.

[0099] The second camera hole CMH2 can be formed in the lower cover 900, and the bottom surface of the first camera sensor 720 is exposed through the second camera hole CMH2. There is no particular limitation on the positions of the first camera sensor 720 and the corresponding first camera hole CMH1 and second camera hole CMH2.

[0100] Figure 3 is a diagram Figure 1 of a plan view of the display panel of the display device. Figure 4 is a diagram Figure 1 of a block diagram of the display panel and the display driving circuit of the display device.

[0101] Reference Figure 3 and Figure 4 Referring to and, the display panel 300 can include a sensor region SDA including the first sub-pixel SP1, a main region MDA including the second sub-pixel SP2, and a non-display region NDA that includes neither the first sub-pixel SP1 nor the second sub-pixel SP2. The first sub-pixel SP1 and the second sub-pixel SP2 can be arranged in the sensor region SDA and the main region MDA together with scan lines SL, emission control lines ECL, data lines DL, and a first driving voltage line VDDL connected to the first sub-pixel SP1 and the second sub-pixel SP2. The scan lines SL and the emission control lines ECL can mainly extend in a first direction (e.g., the X-axis direction), and the data lines DL can mainly extend in a second direction (e.g., the Y-axis direction) intersecting the first direction (e.g., the X-axis direction). In the display region DA, the first driving voltage line VDDL can mainly extend in the second direction (e.g., the Y-axis direction). The first driving voltage lines VDDL can be connected to each other in the non-display region NDA.

[0102] Each of the first sub-pixel SP1 and the second sub-pixel SP2 can be connected to at least one of the scan lines SL, at least one of the emission control lines ECL, and one of the first driving voltage lines VDDL. For convenience, Figure 3 and Figure 4 illustrate that each of the first sub-pixel SP1 and the second sub-pixel SP2 is connected to two scan lines SL, one data line DL, one emission control line ECL, and one first driving voltage line VDDL, but the present disclosure is not limited thereto. Alternatively, each of the second sub-pixels SP2 can be connected to three scan lines SL.

[0103] Each of the first sub-pixel SP1 and the second sub-pixel SP2 may include a driving transistor, one or more transistors, a light-emitting element, and a capacitor. The driving transistor may emit light by supplying a driving current to the light-emitting element according to a data voltage applied to its gate electrode. The driving transistor and the transistor may be thin-film transistors (TFTs). The light-emitting element may emit light according to the driving current supplied by the driving transistor. The light-emitting element may be an OLED including a first electrode, an organic light-emitting layer, and a second electrode. The capacitor may uniformly maintain the data voltage applied to the gate electrode of the driving transistor.

[0104] The non-display area NDA may be defined as an area on the display panel 300 other than the main area MDA and the sensor area SDA. Therefore, the non-display area NDA may not include any sub-pixels. The scan driving circuit that applies a scan signal to the scan line SL, the fan-out line FL connected to the data line DL, the display driving circuit 320, and the pad DP connected to the display driving circuit 320 may each be disposed in the non-display area NDA. The display driving circuit 320 and the pad DP may be disposed on one side of the display panel 300. The display driving circuit 320 may be disposed closer to one side of the display panel 300 than the pad DP.

[0105] The scan driver 410 may be connected to the display driving circuit 320 through a plurality of first scan control lines SCL1. The scan driver 410 may receive a scan control signal SCS from the display driving circuit 320 through the first scan control line SCL1. The scan driver 410 may generate a scan signal according to the scan control signal SCS and may sequentially output the scan signal to the scan line SL.

[0106] The emission control driver 420 may be connected to the display driving circuit 320 through a plurality of second scan control lines SCL2. The emission control driver 420 may receive an emission control signal ECS from the display driving circuit 320 through the second scan control line SCL2. The emission control driver 420 may generate an emission signal according to the emission control signal ECS and may sequentially output the emission signal to the emission line ECL.

[0107] As Figure 3 shown, the scan driver 410 may be disposed on one side of each of the main area MDA and the sensor area SDA, and the emission control driver 420 may be disposed on the other side of each of the main area MDA and the sensor area SDA. Alternatively, both the scan driver 410 and the emission control driver 420 may be disposed on the other side of each of the main area MDA and the sensor area SDA.

[0108] The scan driver 410 may include a plurality of TFTs for generating a scan signal in accordance with a scan control signal SCS, and the emission control driver 420 may include a plurality of TFTs for generating an emission signal in accordance with an emission control signal ECS. In this case, the TFTs of the scan driver 410 and the TFTs of the emission control driver 420 may be formed in the same layer as the TFTs of each of the first sub-pixels SP1 and the TFTs of each of the second sub-pixels SP2.

[0109] The display driving circuit 320 may include a timing controller 321 and a data driver 322, as Figure 4 shown.

[0110] The timing controller 321 may receive digital video data DATA and a timing signal from the display circuit board 310. The timing controller 321 may generate a scan control signal SCS for controlling the operation timing of the scan driver 410 in accordance with the timing signal, may generate an emission control signal ECS for controlling the operation timing of the emission control driver 420, and a data control signal DCS for controlling the operation timing of the data driver 322. The timing controller 321 may output the scan control signal SCS to the scan driver 410 through a plurality of scan control lines SCL, and may output the emission control signal ECS to the emission control driver 420. The timing controller 321 may output the digital video data DATA and the data control signal DCS to the data driver 322.

[0111] The data driver 322 may convert the digital video data DATA into positive / negative analog data voltages, and may output the analog data voltages to the data lines DL through the fan-out lines FL. Sub-pixels may be selected by the scan signal from the scan driving circuit, and the data voltages may be provided to the selected sub-pixels.

[0112] The power supply unit 340 may generate a first driving voltage, and may provide the first driving voltage to the first driving voltage line VDDL. In addition, the power supply unit 340 may generate a second driving voltage, and may provide the second driving voltage to the cathode electrode of the OLED of the first sub-pixel SP1 and to the cathode electrode of the OLED of the second sub-pixel SP2. The first driving voltage may be a high-potential voltage for driving the OLED, and the second driving voltage may be a low-potential voltage for driving the OLED. For example, the first driving voltage may have a higher potential than the second driving voltage. The power supply unit 340 may generate driving voltages for driving the display driving circuit 320 and the scan driving circuit, such as a display driving voltage, a gate high voltage, a gate low voltage, etc., and may provide the generated driving voltages to the display driving circuit 320.

[0113] The display driving circuit 320 may be an IC and may be attached to the display panel 300 in a COG or COP manner or by ultrasonic bonding, but the present disclosure is not limited thereto. For example, the display driving circuit 320 may be attached to the display circuit board 310.

[0114] Figure 5 is a diagram Figure 1 of a plan view of a first sub-pixel, a scan line, a data line, and a first driving voltage line in a sensor region of a display device. Figure 6 is a diagram Figure 1 of a plan view of a second sub-pixel, a scan line, a data line, and a first driving voltage line in a main region of a display device.

[0115] For convenience, Figure 5 the (k-1)th scan line Sk-1, the kth scan line Sk, and the (k+1)th scan line Sk+1 (where k is an integer greater than or equal to 2), the jth data line D j the (j+1)th data line D j+1 the (j+2)th data line D j+2 and the (j+3)th data line D j+3 (where j is a positive integer) and the kth emission line Ek and the (k+1)th emission line Ek+1 are illustrated.

[0116] In addition, for convenience, Figure 6 the (p-1)th scan line Sp-1, the pth scan line Sp, the (p+1)th scan line Sp+1, the (p+2)th scan line Sp+2, and the (p+3)th scan line Sp+3 (where p is an integer greater than or equal to 2), the gth data line D g the (g+1)th data line D g+1 the (g+2)th data line D g+2 the (g+3)th data line D g+3 the (g+4)th data line D g+4 the (g+5)th data line D g+5 the (g+6)th data line D g+6 and the (g+7)th data line D g+7 (where g is a positive integer) and the pth emission line Ep, the (p+1)th emission line Ep+1, the (p+2)th emission line Ep+2, and the (p+3)th emission line Ep+3 are illustrated.

[0117] Refer to Figure 5 and Figure 6, the sensor region SDA includes a first sub-pixel SP1 and a light-transmitting region TA that is at least partially surrounded by the first sub-pixel SP1. The main region MDA includes a second sub-pixel SP2. The main region MDA does not include the light-transmitting region TA. Due to the presence of the light-transmitting region TA, the number of first sub-pixels SP1 in the sensor region SDA can be less than the number of second sub-pixels SP2 in the main region MDA.

[0118] In a plan view, each of the first sub-pixels SP1 can have a substantially rectangular shape having a pair of short sides extending mainly in a first direction (e.g., the X-axis direction) and a pair of long sides extending mainly in a second direction (e.g., the Y-axis direction). In a plan view, each of the first sub-pixels SP1 can have a substantially square shape, as Figure 5 shown, but the present disclosure is not limited thereto.

[0119] Each of the second sub-pixels SP2 can include a main pixel portion MP, a first protruding pixel portion PP1, and a second protruding pixel portion PP2. In a plan view, the main pixel portion MP can have a substantially rectangular shape having a pair of short sides extending mainly in a first direction (e.g., the X-axis direction) and a pair of long sides extending mainly in a second direction (e.g., the Y-axis direction). In a plan view, the first protruding pixel portion PP1 and the second protruding pixel portion PP2 can have a substantially rectangular shape. The first protruding pixel portion PP1 can protrude from the upper side of the main pixel portion MP, and the second protruding pixel portion PP2 can protrude from the lower side of the main pixel portion MP. Specifically, the first protruding pixel portion PP1 can protrude from a portion of the upper side of the main pixel portion MP adjacent to the left side of the main pixel portion MP, and the second protruding pixel portion PP2 can protrude from a portion of the lower side of the main pixel portion MP adjacent to the right side of the main pixel portion MP.

[0120] In the sensor region SDA, specifically, in a pixel region PA that at least partially overlaps with the first sub-pixel SP1, an initialization voltage line VIL, a (k - 1)-th scan line Sk-1, a k-th scan line Sk, and a (k + 1)-th scan line Sk+1, and a k-th emission line Ek and a (k + 1)-th emission line Ek+1 can extend mainly in a first direction (e.g., the X-axis direction). In the pixel region PA of the sensor region SDA, a first driving voltage line VDDL, a j-th data line D j , a (j + 1)-th data line D j+1 , a (j + 2)-th data line D j+2 and a (j + 3)-th data line D j+3 can extend mainly in a second direction (e.g., the Y-axis direction).

[0121] In the main area MDA, the initialization voltage line VIL, the (p - 1)-th scan line Sp-1, the p-th scan line Sp, the (p + 1)-th scan line Sp+1, the (p + 2)-th scan line Sp+2, and the (p + 3)-th scan line Sp+3, as well as the p-th emission line Ep, the (p + 1)-th emission line Ep+1, the (p + 2)-th emission line Ep+2, and the (p + 3)-th emission line Ep+3 can mainly extend in the first direction (e.g., the X-axis direction). In the main area MDA, the first driving voltage line VDDL and the g-th data line D g , the (g + 1)-th data line D g+1 , the (g + 2)-th data line D g+2 , the (g + 3)-th data line D g+3 , the (g + 4)-th data line D g+4 , the (g + 5)-th data line D g+5 , the (g + 6)-th data line D g+6 , and the (g + 7)-th data line D g+7 can mainly extend in the second direction (e.g., the Y-axis direction).

[0122] Each in the first sub-pixel SP1 can at least partially overlap with one initialization voltage line VIL, two scan lines SL, and one emission line ECL. For example, each in the first sub-pixel SP1 can at least partially overlap with four lines set in the first direction (e.g., the X-axis direction).

[0123] Each in the second sub-pixel SP2 can at least partially overlap with two initialization voltage lines VIL, three scan lines SL, and one emission line ECL. For example, each in the second sub-pixel SP2 can at least partially overlap with six lines set in the first direction (e.g., the X-axis direction).

[0124] As Figure 7 and Figure 8 shown, the number of transistors provided in each of the first sub-pixels SP1 can be less than the number of transistors provided in each of the second sub-pixels SP2. Therefore, the number of lines set in the first direction (e.g., the X-axis direction) to at least partially overlap with each of the first sub-pixels SP1 can be less than the number of lines set in the first direction (e.g., the X-axis direction) to at least partially overlap with each of the second sub-pixels SP2.

[0125] Each of the first sub-pixel SP1 and the second sub-pixel SP2 can at least partially overlap with one data line and one first driving voltage line VDDL. For example, each of the first sub-pixel SP1 and the second sub-pixel SP2 can at least partially overlap with two lines set in the second direction (e.g., the Y-axis direction).

[0126] The light-transmitting region TA can be at least partially surrounded by the first sub-pixel SP1. Figure 5 It is illustrated that the light-transmitting region TA has a substantially rectangular shape in the plan view, but the present disclosure is not limited thereto. Alternatively, the light-transmitting region TA may have a shape other than the substantially rectangular shape, such as, for example, another polygonal shape, a circular shape, an elliptical shape, or an irregular shape.

[0127] The wiring region LA can be disposed between the light-transmitting region TA and the first sub-pixel SP1. The wiring region LA can be disposed to at least partially surround the light-transmitting region TA.

[0128] As the size of the wiring region LA decreases, the size of the light-transmitting region TA increases. Thus, the distance between each pair of adjacent lines among the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the k-th scan line Sk, the (k + 1)-th scan line Sk+1, and the k-th emission line Ek and the (k + 1)-th emission line Ek+1 can be smaller in the wiring region LA than in the pixel region PA. In addition, the first driving voltage line VDDL and the j-th data line D j , the (j + 1)-th data line D j+1 , the (j + 2)-th data line D j+2 and the (j + 3)-th data line D j+3 among each pair of adjacent lines can be smaller in the wiring region LA than in the pixel region PA.

[0129] The initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the k-th scan line Sk, the (k + 1)-th scan line Sk+1, and the k-th emission line Ek and the (k + 1)-th emission line Ek+1 can be bent at least once in the wiring region LA. For example, the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the k-th scan line Sk, the (k + 1)-th scan line Sk+1, and the k-th emission line Ek and the (k + 1)-th emission line Ek+1 can be bent four times in the wiring region LA.

[0130] The first driving voltage line VDDL and the j-th data line D j , the (j + 1)-th data line D j+1 , the (j + 2)-th data line D j+2 and the (j + 3)-th data line D j+3 can be bent at least once in the wiring region LA. For example, the first driving voltage line VDDL and the j-th data line D j , the (j + 1)-th data line D j+1 , the (j + 2)-th data line D j+2 and the (j + 3)-th data line D j+3 can be bent four times in the wiring region LA.

[0131] The initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the k-th scan line Sk, the (k + 1)-th scan line Sk+1, the k-th emission line Ek, and the (k + 1)-th emission line Ek+1 may each at least partially overlap with at least one of the following lines: the first driving voltage line VDDL and the j-th data line D j , the (j + 1)-th data line D j+1 , the (j + 2)-th data line D j+2 , and the (j + 3)-th data line D j+3 . The first driving voltage line VDDL and the j-th data line D j , the (j + 1)-th data line D j+1 , the (j + 2)-th data line D j+2 , and the (j + 3)-th data line D j+3 may each at least partially overlap with at least one of the following lines: the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the k-th scan line Sk, the (k + 1)-th scan line Sk+1, the k-th emission line Ek, and the (k + 1)-th emission line Ek+1.

[0132] According to Figure 5 and Figure 6 the structure shown in, since the sensor area SDA of the display panel 300 includes a light-transmitting area TA, even if the sensor devices (740, 750, 760, and 770) are arranged to at least partially overlap with the sensor area SDA in the thickness direction of the display panel 300, that is, in the third direction (e.g., the Z-axis direction), light can enter the sensor devices (740, 750, 760, and 770) arranged on the bottom surface of the display panel 300 through the light-transmitting area TA from the top surface of the display device 10. Therefore, deterioration of the sensing ability of the sensor devices (740, 750, 760, and 770) can be prevented or reduced.

[0133] Figure 7 is a circuit diagram of an exemplary first sub-pixel. Specifically, Figure 7 illustrates a first sub-pixel SP1 connected to the (k - 1)-th scan line Sk-1, the k-th scan line Sk, and the j-th data line D j .

[0134] Referring to Figure 7 , the first sub-pixel SP1 may at least partially overlap with the (k - 1)-th scan line Sk-1, the k-th scan line Sk, and the j-th data line D j . In addition, the first sub-pixel SP1 may be connected to the first driving voltage line VDDL provided with the first driving voltage, the initialization voltage line VIL provided with the initialization voltage, and the second driving voltage line VSSL provided with the second driving voltage.

[0135] The first sub-pixel SP1 includes a driving transistor DT, a light-emitting element EL, a switching element, and a first capacitor C1. The switching element may include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, and a fifth transistor ST5.

[0136] The driving transistor DT may include a gate electrode DT_G, a first electrode, and a second electrode. The driving transistor DT controls the drain-source current Ids (hereinafter, the driving current Ids) according to the data voltage applied to the gate electrode DT_G. The driving current Ids flowing through the channel of the driving transistor DT is proportional to the square of the difference between the threshold voltage and the voltage Vgs between the gate electrode DT_G and the source electrode of the driving transistor DT, as shown in Equation (1):

[0137] Ids = k′ × (Vgs - Vth) 2

[0138] where k’ represents a proportionality coefficient determined by the structure and physical characteristics of the driving transistor DT, Vgs represents the gate-source voltage of the driving transistor DT, and Vth represents the threshold voltage of the driving transistor DT.

[0139] The light-emitting element EL emits light according to the driving current Ids. The amount of light emitted by the light-emitting element EL may be proportional to the driving current Ids.

[0140] The light-emitting element EL may be an OLED including an anode electrode, a cathode electrode, and an organic light-emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light-emitting element EL may be an ILED including an anode electrode, a cathode electrode, and an inorganic semiconductor disposed between the anode electrode and the cathode electrode. Yet another alternative is that the light-emitting element EL may be a QLED including an anode electrode, a cathode electrode, and a quantum dot light-emitting layer disposed between the anode electrode and the cathode electrode. Yet another alternative is that the light-emitting element EL may be an mLED.

[0141] The anode electrode of the light-emitting element EL may be connected to the second electrode of the fifth transistor ST5, and the cathode electrode of the light-emitting element EL may be connected to the second driving voltage line VSSL. A parasitic capacitance Cel may be formed between the anode electrode and the cathode electrode of the light-emitting element EL.

[0142] The first transistor ST1 may be a dual transistor including a first (1-1) transistor ST1-1 and a first (1-2) transistor ST1-2. The first (1-1) transistor ST1-1 and the first (1-2) transistor ST1-2 are turned on by a scan signal from the (k-1)th scan line Sk-1 to connect the gate electrode of the driving transistor DT and the initialization voltage line VIL. The gate electrode of the driving transistor DT may be discharged to as low as the initialization voltage of the initialization voltage line VIL. The gate electrode of the first (1-1) transistor ST1-1 may be connected to the (k-1)th scan line Sk-1, the first electrode of the first (1-1) transistor ST1-1 may be connected to the gate electrode of the driving transistor DT, and the second electrode of the first (1-1) transistor ST1-1 may be connected to the first electrode of the first (1-2) transistor ST1-2. The gate electrode of the first (1-2) transistor ST1-2 may be connected to the (k-1)th scan line Sk-1, the first electrode of the first (1-2) transistor ST1-2 may be connected to the second electrode of the first (1-1) transistor ST1-1, and the second electrode of the first (1-2) transistor ST1-2 may be connected to the initialization voltage line VIL.

[0143] The second transistor ST2 is turned on by a scan signal from the kth scan line Sk to connect the first electrode of the driving transistor DT and the jth data line D j . The gate electrode of the second transistor ST2 may be connected to the kth scan line Sk, the first electrode of the second transistor ST2 may be connected to the first electrode of the driving transistor DT, and the second electrode of the second transistor ST2 may be connected to the jth data line D j .

[0144] The third transistor ST3 may be a dual transistor including a (3-1)th transistor ST3-1 and a (3-2)th transistor ST3-2. The (3-1)th transistor ST3-1 and the (3-2)th transistor ST3-2 are turned on by a scan signal from the k-th scan line Sk to connect the gate electrode and the second electrode of the driving transistor DT. For example, when the (3-1)th transistor ST3-1 and the (3-2)th transistor ST3-2 are turned on, the gate electrode and the second electrode of the driving transistor DT are connected, and as a result, the driving transistor DT operates as a diode. The gate electrode of the (3-1)th transistor ST3-1 may be connected to the k-th scan line Sk, the first electrode of the (3-1)th transistor ST3-1 may be connected to the second electrode of the driving transistor DT, and the second electrode of the (3-1)th transistor ST3-1 may be connected to the first electrode of the (3-2)th transistor ST3-2. The gate electrode of the (3-2)th transistor ST3-2 may be connected to the k-th scan line Sk, the first electrode of the (3-2)th transistor ST3-2 may be connected to the second electrode of the (3-1)th transistor ST3-1, and the second electrode of the (3-2)th transistor ST3-2 may be connected to the gate electrode of the driving transistor DT.

[0145] The fourth transistor ST4 is turned on by an emission signal from the k-th emission line Ek to connect the first electrode of the driving transistor DT and the first driving voltage line VDDL. The gate electrode of the fourth transistor ST4 may be connected to the k-th emission line Ek, the first electrode of the fourth transistor ST4 may be connected to the first driving voltage line VDDL, and the second electrode of the fourth transistor ST4 may be connected to the first electrode of the driving transistor DT.

[0146] The fifth transistor ST5 is connected between the second electrode of the driving transistor DT and the anode electrode of the light-emitting element EL. The fifth transistor ST5 is turned on by an emission signal from the k-th emission line Ek to connect the second electrode of the driving transistor DT and the anode electrode of the light-emitting element EL. The gate electrode of the fifth transistor ST5 is connected to the k-th emission line Ek, the first electrode of the fifth transistor ST5 is connected to the second electrode of the driving transistor DT, and the second electrode of the fifth transistor ST5 is connected to the anode electrode of the light-emitting element EL. When both the fourth transistor ST4 and the fifth transistor ST5 are turned on, a driving current Ids may be supplied to the light-emitting element EL.

[0147] The first capacitor C1 is formed between the gate electrode of the driving transistor DT and the first driving voltage line VDDL. The first electrode of the first capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the second electrode of the first capacitor C1 may be connected to the first driving voltage line VDDL.

[0148] When the first electrodes of the first transistor ST1 to the fifth transistor ST5 and the first electrode of the driving transistor DT are source electrodes, the second electrodes of the first transistor ST1 to the fifth transistor ST5 and the second electrode of the driving transistor DT may be drain electrodes. When the first electrodes of the first transistor ST1 to the fifth transistor ST5 and the first electrode of the driving transistor DT are drain electrodes, the second electrodes of the first transistor ST1 to the fifth transistor ST5 and the second electrode of the driving transistor DT may be source electrodes.

[0149] The first transistor ST1 to the fifth transistor ST5 and the driving transistor DT may be formed of one of polysilicon, amorphous silicon, and oxide semiconductor. When the first transistor ST1 to the fifth transistor ST5 and the driving transistor DT are formed of polysilicon, the first transistor ST1 to the fifth transistor ST5 and the driving transistor DT may be formed by a low-temperature polysilicon (LTPS) process.

[0150] Figure 7 It is illustrated that the first transistor ST1 to the fifth transistor ST5 and the driving transistor DT are P-type metal-oxide-semiconductor field-effect transistors (MOSFETs), but the present disclosure is not limited thereto. Alternatively, the first transistor ST1 to the fifth transistor ST5 and the driving transistor DT are N-type MOSFETs.

[0151] Figure 8 is a circuit diagram of an exemplary second sub-pixel. Specifically, Figure 8 illustrates a second sub-pixel SP2 connected to the (p - 1)-th scan line Sp-1, the p-th scan line Sp, and the g-th data line D g of.

[0152] Figure 8 The second sub-pixel SP2 of is different from Figure 7 the first sub-pixel SP1 of in that it further includes a sixth transistor ST6. In the following, the description will mainly focus on the differences from Figure 7 the first sub-pixel SP1 of to describe Figure 8 the second sub-pixel SP2 of. Therefore, it will be assumed that in the sense that certain details of the second sub-pixel SP2 are not described below, these details may be at least similar to the corresponding details of the first sub-pixel SP1 described herein.

[0153] Refer to Figure 8, the sixth transistor ST6 is turned on by a scan signal from the p-th scan line Sp to connect the anode electrode of the light-emitting element EL and the initialization voltage line VIL. The anode electrode of the light-emitting element EL can be discharged to as low a voltage as the initialization voltage of the initialization voltage line VIL. The gate electrode of the sixth transistor ST6 is connected to the p-th scan line Sp, the first electrode of the sixth transistor ST6 is connected to the anode electrode of the light-emitting element EL, and the second electrode of the sixth transistor ST6 is connected to the initialization voltage line VIL.

[0154] According to Figure 7 and Figure 8 In an embodiment, each of the first sub-pixels SP1 includes six transistors, and each of the second sub-pixels SP2 includes seven transistors. For example, the number of transistors provided in each of the first sub-pixels SP1 can be less than the number of transistors provided in each of the second sub-pixels SP2. Accordingly, a wiring area LA can be provided in an area where the sixth transistor ST6 is not provided, and as a result, a light-transmitting area TA can be widened.

[0155] The sixth transistor ST6 of the second sub-pixel SP2 reduces the voltage at the anode electrode of the light-emitting element EL to as low as the initialization voltage. Accordingly, when the light-emitting element EL displays black, the sixth transistor ST6 of the second sub-pixel SP2 can prevent the black from becoming visible to the user during a period when the fifth transistor ST5 of the second sub-pixel SP2 is turned off. However, since the period when the fifth transistor ST5 of the second sub-pixel SP2 is turned off is very short, and the number of first sub-pixels SP1 provided in the sensor area SDA is less than the number of second sub-pixels SP2 provided in the main area MDA, the black becomes almost invisible to the user. Accordingly, the sixth transistor ST6 may not be provided in the first sub-pixel SP1.

[0156] Figure 9 is a plan view of Figure 7 a first sub-pixel.

[0157] Referring to Figure 9 , the first sub-pixel SP1 may include a driving transistor DT, first transistors ST1 to fifth transistors ST5, and a first capacitor C1.

[0158] The driving transistor DT may include an active layer DT_ACT, a gate electrode DT_G, a first electrode DT_S, and a second electrode DT_D. The active layer DT_ACT of the driving transistor DT may at least partially overlap with the gate electrode DT_G of the driving transistor DT. The gate electrode DT_G of the driving transistor DT may be connected to a first connection electrode BE1 through a first contact hole CNT1. The first connection electrode BE1 may be connected to the first electrode S1-1 of the (1-1) transistor ST1-1 and the second electrode D3-2 of the (3-2) transistor ST3-2 through a second contact hole CNT2. The first connection electrode BE1 may intersect with the k-th scan line Sk. The first electrode DT_S of the driving transistor DT may be connected to the first electrode S2 of the second transistor ST2. The second electrode DT_D of the driving transistor DT may be connected to the first electrode S3-1 of the (3-1) transistor ST3-1 and the first electrode S5 of the fifth transistor ST5.

[0159] The first transistor ST1 may be a dual transistor. The first transistor ST1 may include the (1-1) transistor ST1-1 and the (1-2) transistor ST1-2.

[0160] The (1-1) transistor ST1-1 may include an active layer ACT1-1, a gate electrode G1-1, a first electrode S1-1, and a second electrode D1-1. The gate electrode G1-1 of the (1-1) transistor ST1-1 may correspond to a part of the (k-1)-th scan line Sk-1, specifically, the part of the (k-1)-th scan line Sk-1 that at least partially overlaps with the active layer ACT1-1 of the (1-1) transistor ST1-1. The first electrode S1-1 of the (1-1) transistor ST1-1 may be connected to the first connection electrode BE1 through a second contact hole CNT2. The second electrode D1-1 of the (1-1) transistor ST1-1 may be connected to the first electrode S1-2 of the (1-2) transistor ST1-2.

[0161] The (1-2) transistor ST1-2 may include an active layer ACT1-2, a gate electrode G1-2, a first electrode S1-2, and a second electrode D1-2. The gate electrode G1-2 of the (1-2) transistor ST1-2 may correspond to a part of the (k-1)-th scan line Sk-1, specifically, the part of the (k-1)-th scan line Sk-1 that at least partially overlaps with the active layer ACT1-2 of the (1-2) transistor ST1-2. The first electrode S1-2 of the (1-2) transistor ST1-2 may be connected to the second electrode D1-1 of the (1-1) transistor ST1-1. The second electrode D1-2 of the (1-2) transistor ST1-2 may be connected to an initialization connection electrode VIE through a fourth contact hole CNT4.

[0162] The second transistor ST2 may include an active layer ACT2, a gate electrode G2, a first electrode S2, and a second electrode D2. The gate electrode G2 of the second transistor ST2 may correspond to a part of the k-th scan line Sk, specifically, the part of the k-th scan line Sk that at least partially overlaps with the active layer ACT2 of the second transistor ST2. The first electrode S2 of the second transistor ST2 may be connected to the first electrode DT_S of the driving transistor DT. The second electrode D2 of the second transistor ST2 may be connected to the j-th data line D through the third contact hole CNT3 j .

[0163] The third transistor ST3 may be a dual transistor. The third transistor ST3 may include a (3-1) transistor ST3-1 and a (3-2) transistor ST3-2

[0164] The (3-1) transistor ST3-1 may include an active layer ACT3-1, a gate electrode G3-1, a first electrode S3-1, and a second electrode D3-1. The gate electrode G3-1 of the (3-1) transistor ST3-1 may correspond to a part of the k-th scan line Sk, specifically, the part of the k-th scan line Sk that at least partially overlaps with the active layer ACT3-1 of the (3-1) transistor ST3-1. The first electrode S3-1 of the (3-1) transistor ST3-1 may be connected to the second electrode DT_D of the driving transistor DT. The second electrode D3-1 of the (3-1) transistor ST3-1 may be connected to the first electrode S3-2 of the (3-2) transistor ST3-2

[0165] The (3-2) transistor ST3-2 may include an active layer ACT3-2, a gate electrode G3-2, a first electrode S3-2, and a second electrode D3-2. The gate electrode G3-2 of the (3-2) transistor ST3-2 may correspond to a part of the k-th scan line Sk, specifically, the part of the k-th scan line Sk that at least partially overlaps with the active layer ACT3-2 of the (3-2) transistor ST3-2. The first electrode S3-2 of the (3-2) transistor ST3-2 may be connected to the second electrode D3-1 of the (3-1) transistor ST3-1. The second electrode D3-2 of the (3-2) transistor ST3-2 may be connected to the first connection electrode BE1 through the second contact hole CNT2

[0166] The fourth transistor ST4 may include an active layer ACT4, a gate electrode G4, a first electrode S4, and a second electrode D4. The gate electrode G4 of the fourth transistor ST4 may correspond to a part of the k-th emission line Ek, specifically, the part of the k-th emission line Ek that at least partially overlaps with the active layer ACT4 of the fourth transistor ST4. The first electrode S4 of the fourth transistor ST4 may be connected to the second electrode CE12 of the first capacitor C1 through a seventh contact hole CNT7. The second electrode D4 of the fourth transistor ST4 may be connected to the first electrode DT_S of the driving transistor DT.

[0167] The fifth transistor ST5 may include an active layer ACT5, a gate electrode G5, a first electrode S5, and a second electrode D5. The gate electrode G5 of the fifth transistor ST5 may correspond to a part of the k-th emission line Ek, specifically, the part of the k-th emission line Ek that at least partially overlaps with the active layer ACT5 of the fifth transistor ST5. The first electrode S5 of the fifth transistor ST5 may be connected to the second electrode DT_D of the driving transistor DT. The second electrode D5 of the fifth transistor ST5 may be connected to the anode electrode AND of the light-emitting element EL through a sixth contact hole CNT6.

[0168] The first electrode CE11 of the first capacitor C1 may be a part of the gate electrode DT_G of the driving transistor DT. The second electrode CE12 of the first capacitor C1 may be the part of the horizontal driving voltage line HVDDL that is connected to the first driving voltage line VDDL through an eighth contact hole CNT8. The first electrode CE11 and the second electrode CE12 may at least partially overlap with each other.

[0169] Figure 10 is a diagram Figure 8 of the plan view of the second sub-pixel.

[0170] Figure 10 The difference between the second sub-pixel SP2 of Figure 9 and the first sub-pixel SP1 of Figure 9 is that it further includes a sixth transistor ST6. Below, it will mainly be described around the difference from Figure 10 the first sub-pixel SP1 of

[0171] The sixth transistor ST6 may include an active layer ACT6, a gate electrode G6, a first electrode S6, and a second electrode D6. The gate electrode G6 of the sixth transistor ST6, which is part of the p-th scanning line Sp, may correspond to the overlapping region of the active layer ACT6 of the sixth transistor ST6 and the p-th scanning line Sp. The first anode connection electrode ANDE1 may be connected to the first electrode S6 of the sixth transistor ST6 through the sixth contact hole CNT6. The second anode connection electrode ANDE2 may be connected to the first anode connection electrode ANDE1 through the first anode contact hole AND_CNT1, as shown in Figure 12 as shown. The first electrode 171 of the light-emitting element EL may be connected to the second anode connection electrode ANDE2 through the second anode contact hole AND_CNT2, as shown in Figure 11 as shown. The second electrode D6 of the sixth transistor ST6 may be connected to the initialization connection electrode VIE through the fourth contact hole CNT4. The initialization voltage line VIL may be connected to the initialization connection electrode VIE through the fifth contact hole CNT5, and the initialization connection electrode VIE may be connected to the second electrode D1-2 of the (1-2)-th transistor ST1-2 and the second electrode D4 of the sixth transistor ST6 through the fourth contact hole CNT4. The initialization connection electrode VIE may be arranged to intersect the k-th scanning line Sk.

[0172] According to Figure 9 and Figure 10 the embodiment, since the sixth transistor ST6 is not provided in the first sub-pixel SP1, the first sub-pixel SP1 does not include the second protruding pixel portion PP2 of the second sub-pixel SP2. For example, since the sixth transistor ST6 does not exist, the second protruding pixel portion PP2 may not be provided in the first sub-pixel SP1. Therefore, when the first sub-pixel SP1 without the second protruding pixel portion PP2 is provided in the sensor region SDA, the wiring region LA may be arranged in the portion of the first sub-pixel SP1 where the second protruding pixel portion PP2 is omitted, and as a result, the size of the light-transmitting region TA may become wider compared to when the second sub-pixel SP2 having the second protruding pixel portion PP2 is applied to the sensor region SDA.

[0173] Figure 11 is a cross-sectional view taken along the line I-I' of Figure 9 and Figure 10 as shown. Figure 12 is a cross-sectional view taken along the line II-II' of Figure 9 as shown. Figure 13 is a cross-sectional view taken along the line III-III' of Figure 9 as shown.

[0174] Refer to Figures 11 to 13, the TFT layer TFTL, the light-emitting element layer EML, and the encapsulation layer TFE can be sequentially formed on the first substrate SUB1.

[0175] The TFT layer TFTL includes a light-shielding layer BML, a buffer film BF, an active layer ACT, a first gate layer GTL1, a second gate layer GTL2, a first source metal layer DTL1, a second source metal layer DTL2, a gate insulating film 130, a first interlayer insulating film 141, a second interlayer insulating film 142, a passivation film 150, a first planarization film 160, and a second planarization film 180.

[0176] The light-shielding layer BML can be formed on one surface of the first substrate SUB1. The light-shielding layer BML can be arranged to at least partially overlap with the active layer DT_ACT of the driving transistor DT to prevent the generation of leakage current in the case where light is incident on the active layer DT_ACT of the driving transistor DT. Figures 11 to 13 The figure shows that the light-shielding member BML only overlaps with the active layer DT_ACT of the driving transistor DT, but the present disclosure is not limited thereto. For example, the light-shielding layer BML can at least partially overlap with the active layer DT_ACT of the driving transistor DT, and can also at least partially overlap with the active layers ACT1-1, ACT1-2 to ACT6 of the first transistor ST1 to the sixth transistor ST6. The light-shielding layer BML can be a single-layer or multi-layer film including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), Ni, neodymium (Nd), Cu, or an alloy thereof.

[0177] The buffer film BF can be formed on the light-shielding layer BML. The buffer film BF can be formed on the first substrate SUB1 to protect the organic light-emitting layer 172 of the TFT and the light-emitting element layer EML from the influence of moisture that may penetrate through the first substrate SUB1 into the TFT and the organic light-emitting layer 172. The buffer film BF can include a plurality of inorganic films stacked alternately. For example, the buffer film BF can be a multi-layer film in which at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer is stacked alternately. The buffer film BF can be omitted.

[0178] The active layer ACT may be formed on the first substrate SUB1 or the buffer film BF. The active layer ACT may include polysilicon, single crystal silicon, low-temperature polysilicon, amorphous silicon, and / or oxide semiconductor. When the active layer ACT is formed of polysilicon, the active layer ACT may be conductive. Accordingly, the active layer ACT may include the active layer DT_ACT of the driving transistor DT and the active layers ACT1-1, ACT1-2, ACT2, ACT3, ACT4, ACT5, and ACT6 of the first transistor ST1 to the sixth transistor ST6, and may further include the source electrode DT_S and the drain electrode DT_D of the driving transistor DT and the source electrodes S1-1, S1-2, S2, S3-1, S3-2, S4, S5, and S6 and the drain electrodes D1-1, D1-2, D2, D3-1, D3-2, D4, D5, and D6 of the first transistor ST1 to the sixth transistor ST6.

[0179] The gate insulating film 130 may be formed on the active layer ACT. The gate insulating film 130 may be an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0180] The first gate layer GTL1 may be formed on the gate insulating film 130. The first gate layer GTL1 may include not only the gate electrode DT_G of the driving transistor DT and the gate electrodes G1-1, G1-2 to G6 of the first transistor ST1 to the sixth transistor ST6, but also the scanning line SL and the emission control line ECL. The first gate layer GTL1 may be a single-layer or multi-layer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof.

[0181] The first interlayer insulating film 141 may be formed on the first gate layer GTL1. The first interlayer insulating film 141 may be an inorganic film, such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film 141 may include a plurality of inorganic films.

[0182] The second gate layer GTL2 may be formed on the first interlayer insulating film 141. The second gate layer GTL2 may include the initialization voltage line VIL and the second electrode CE12 of the first capacitor C1. The second gate layer GTL2 may be a single-layer or multi-layer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof.

[0183] The second interlayer insulating film 142 may be formed on the second gate layer GTL2. The second interlayer insulating film 142 may be an inorganic film, such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film 142 may include a plurality of inorganic films.

[0184] The first source metal layer DTL1 may be formed on the second interlayer insulating film 142. The first source metal layer DTL1 may include a data line DL, a first driving voltage line VDDL, a first connection electrode BE1, a first anode connection electrode ANDE1, and an initialization connection electrode VIE. The first source metal layer DTL1 may be a single-layer or multi-layer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof.

[0185] The first planarization film 160 may be formed on the first source metal layer DTL1 to planarize the height difference formed by the active layer ACT, the first gate layer GTL1, the second gate layer GTL2, and the first source metal layer DTL1. The first planarization film 160 may be an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0186] A passivation film 150 may be additionally formed between the first source metal layer DTL1 and the first planarization film 160. The passivation film 150 may be an inorganic film, such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0187] The second source metal layer DTL2 may be formed on the first planarization film 160. The second source metal layer DTL2 may include a second anode connection electrode ANDE2. The second source metal layer DTL2 may be a single-layer or multi-layer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof.

[0188] The second planarization film 180 may be formed on the second source metal layer DTL2. The second planarization film 180 may be an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0189] The driving transistor DT and the first transistor ST1 to the sixth transistor ST6 may be top-gate transistors with gate electrodes disposed above the active layer, but the present disclosure is not limited thereto. Alternatively, the driving transistor DT and the first transistor ST1 to the sixth transistor ST6 may be bottom-gate transistors with gate electrodes disposed below the active layer or double-gate transistors with gate electrodes disposed above and below the active layer.

[0190] The first contact hole CNT1 may be a hole that penetrates the first interlayer insulating film 141 and the second interlayer insulating film 142 and exposes the gate electrode DT_G of the driving transistor DT. The first connection electrode BE1 may be connected to the gate electrode DT_G of the driving transistor DT through the first contact hole CNT1.

[0191] The second contact hole CNT2 may be a hole that passes through the gate insulating film 130 and the first interlayer insulating film 141 and the second interlayer insulating film 142 to expose the first electrode S1-1 of the (1-1)th transistor ST1-1 and the second electrode D3-1 of the (3-1)th transistor ST3-1. The second connection electrode BE2 may be connected to the first electrode S1-1 of the (1-1)th transistor ST1-1 and the second electrode D3_2 of the (3-2)th transistor ST3-2 through the second contact hole CNT2.

[0192] The third contact hole CNT3 may be a hole that passes through the gate insulating film 130 and the first interlayer insulating film 141 and the second interlayer insulating film 142 to expose the first electrode S2 of the second transistor ST2. The jth data line D j may be connected to the first electrode S2 of the second transistor ST2 through the third contact hole CNT3.

[0193] The fourth contact hole CNT4 may be a hole that passes through the gate insulating film 130 and the first interlayer insulating film 141 and the second interlayer insulating film 142 to expose the second electrode D1-2 of the (1-2)th transistor ST1-2 and the second electrode D6 of the sixth transistor ST6. The initialization connection electrode VIE may be connected to the second electrode D1-2 of the (1-2)th transistor ST1-2 and the second electrode D6 of the sixth transistor ST6 through the fourth contact hole CNT4.

[0194] The fifth contact hole CNT5 may be a hole that passes through the second interlayer insulating film 142 to expose the initialization voltage line VIL. The initialization connection electrode VIE may be connected to the initialization voltage line VIL through the fifth contact hole CNT5.

[0195] The sixth contact hole CNT6 may be a hole that passes through the gate insulating film 130 and the first interlayer insulating film 141 and the second interlayer insulating film 142 to expose the second electrode D5 of the fifth transistor ST5. The first anode connection electrode ANDE1 may be connected to the second electrode D5 of the fifth transistor ST5 through the sixth contact hole CNT6.

[0196] The seventh contact hole CNT7 may be a hole that passes through the gate insulating film 130 and the first interlayer insulating film 141 and the second interlayer insulating film 142 to expose the first electrode S4 of the fourth transistor ST4. The first drive voltage line VDDL may be connected to the first electrode S4 of the fourth transistor ST4 through the seventh contact hole CNT7.

[0197] The eighth contact hole CNT8 may be a hole that passes through the second interlayer insulating film 142 to expose the horizontal drive voltage line HVDDL. The first drive voltage line VDDL may be connected to the horizontal drive voltage line HVDDL through the eighth contact hole CNT8.

[0198] The first anode contact hole AND_CNT1 may be a hole that penetrates the passivation film 150 and the first planarization film 160 to expose the first anode connection electrode ANDE1.

[0199] The second anode contact hole AND_CNT2 may be a hole that penetrates the second planarization film 180 to expose the second anode connection electrode ANDE2.

[0200] The light-emitting element layer EML is formed on the TFT layer TFTL. The light-emitting element layer EML includes a light-emitting element 170 and a pixel defining film 190.

[0201] The light-emitting element 170 and the pixel defining film 190 may be formed on the second planarization film 180. Each of the light-emitting elements 170 may include a first electrode 171, an organic light-emitting layer 172, and a second electrode 173.

[0202] The first electrode 171 may be formed on the second planarization film 180. The first electrode 171 may be connected to the second anode connection electrode ANDE2 through the second anode contact hole AND_CNT2 that penetrates the second planarization film 180.

[0203] In a top-emission structure that emits light in the direction from the organic light-emitting layer 172 to the second electrode 173, the first electrode 171 may be formed of a metal material having a high reflectivity, such as a stack of Al and Ti (e.g., Ti / Al / Ti), a stack of Al and indium tin oxide (ITO) (e.g., ITO / Al / ITO), a silver-palladium-copper (APC) alloy, and / or a stack of the APC alloy and ITO (e.g., ITO / APC / ITO).

[0204] The pixel defining film 190 may define the first electrode 171 above the second planarization film 180, and thus define the emission region EA. The pixel defining film 190 may cover the edge of the first electrode 171. The pixel defining film 190 may be an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0205] The emission region EA refers to a region where the first electrode 171, the organic light-emitting layer 172, and the second electrode 173 are sequentially stacked such that holes from the first electrode 171 and electrons from the second electrode 173 are recombined in the organic light-emitting layer 172 to emit light.

[0206] The organic light-emitting layer 172 is formed on the first electrode 171 and the pixel defining film 190. The organic light-emitting layer 172 may include an organic material and may emit light of a predetermined color. For example, the organic light-emitting layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer.

[0207] The second electrode 173 may be formed on the organic light-emitting layer 172. The second electrode 173 may cover the organic light-emitting layer 172. The second electrode 173 may be a common layer formed for all sub-pixels. A capping layer may be formed on the second electrode 173.

[0208] In a top-emission structure, the second electrode 173 may be formed of a transparent conductive oxide (TCO) material such as ITO or IZO, or a semi-transparent metal material such as magnesium (Mg), Ag, or an alloy of Mg and Ag. When the second electrode 173 is formed of a semi-transparent metal material, the luminous efficiency of the light-emitting element layer EML may be increased due to the microcavity effect.

[0209] The encapsulation layer TFE may be formed on the light-emitting element layer EML. The encapsulation layer TFE may include at least one inorganic film for preventing oxygen or moisture from penetrating into the light-emitting element layer EML. In addition, the encapsulation layer TFE may include at least one organic film for protecting the light-emitting element layer EML from foreign substances such as dust.

[0210] The second substrate may be disposed on the light-emitting element layer EML instead of the encapsulation layer TFE. The space between the light-emitting element layer EML and the second substrate may be evacuated, or a filling film may be disposed in the space between the light-emitting element layer EML and the second substrate. The filling film may be an epoxy resin filling film or a silicone resin filling film.

[0211] Figure 14 is a plan view of Figure 5 region A shown. Figure 15 is a cross-sectional view taken along Figure 14 line IV-IV' shown.

[0212] Refer to Figure 14 and Figure 15 In the wiring region LA, the k-th scan line Sk may be connected to the first scan connection line SCE1 through the second connection contact hole BCNT2. In the wiring region LA, the first driving voltage line VDDL may be connected to the first power connection line PCE1 and the second power connection line PCE2 through the first connection contact hole BCNT1. For example, one of the first driving voltage lines VDDL may be connected to the first power connection line PCE1 through the first connection contact hole BCNT1, and the other of the first driving voltage lines VDDL may be connected to the second power connection line PCE2 through another first connection contact hole BCNT1.

[0213] Wiring may be completely omitted from the light-transmitting region TA in order to increase the light transmittance in the light-transmitting region TA. For example, as Figure 15As shown, transparent materials such as buffer film BF, gate insulating film 130, first interlayer insulating film 141 and second interlayer insulating film 142, passivation film 150, first planarization film 160 and second planarization film 180, pixel defining film 190, second electrode 173, and encapsulation layer TFE can be arranged in the light-transmitting region TA. In addition, the buffer film BF, gate insulating film 130, first interlayer insulating film 141 and second interlayer insulating film 142, passivation film 150, first planarization film 160 and second planarization film 180, pixel defining film 190, and encapsulation layer TFE can be completely or partially removed to increase the light transmittance in the light-transmitting region TA. In addition, the second electrode 173 can be removed to increase the light transmittance in the light-transmitting region TA.

[0214] In the wiring region LA, the j-th data line D j can at least partially overlap with the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the k-th scan line Sk, and the k-th emission line Ek. The overlapping region of the j-th data line D j and the initialization voltage line VIL can be larger than the overlapping region of the j-th data line D j and the (k - 1)-th scan line Sk-1, the overlapping region of the j-th data line D j and the k-th scan line Sk, and the overlapping region of the j-th data line D j and the k-th emission line Ek.

[0215] In the wiring region LA, the first power connection line PCE1 can at least partially overlap with the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the k-th scan line Sk, and the emission line Ek. The overlapping region of the first power connection line PCE1 and the (k - 1)-th scan line Sk-1 can be larger than the overlapping region of the first power connection line PCE1 and the initialization voltage line VIL, the overlapping region of the first power connection line PCE1 and the k-th scan line Sk, and the overlapping region of the first power connection line PCE1 and the k-th emission line Ek.

[0216] In the wiring region LA, the (j + 1)-th data line D j+1 can at least partially overlap with the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the k-th scan line Sk, and the k-th emission line Ek. The overlapping region of the (j + 1)-th data line D j+1 and the k-th scan line Sk can be larger than the overlapping region of the (j + 1)-th data line D j+1 and the initialization voltage line VIL, the overlapping region of the (j + 1)-th data line D j+1 and the (k - 1)-th scan line Sk-1, and the overlapping region of the (j + 1)-th data line D j+1 and the k-th emission line Ek.

[0217] In the wiring area LA, the second power supply connection line PCE2 may at least partially overlap with the initialization voltage line VIL, the (k-1)-th scan line Sk-1, the k-th scan line Sk, and the k-th emission line Ek. The overlapping area between the second power supply connection line PCE2 and the k-th emission line Ek may be larger than the overlapping areas between the second power supply connection line PCE2 and the initialization voltage line VIL, between the second power supply connection line PCE2 and the (k-1)-th scan line Sk-1, and between the second power supply connection line PCE2 and the k-th scan line Sk.

[0218] Figure 14 and Figure 15 It is illustrated that the first connection contact hole BCNT1 overlaps with the initialization voltage line VIL, but the present disclosure is not limited thereto. Alternatively, the first connection contact hole BCNT1 may at least partially overlap with one of the (k-1)-th scan line Sk-1, the first scan connection line SCE1, and the k-th emission line Ek. Another alternative is that one of the first connection contact holes BCNT1 may at least partially overlap with one of the initialization voltage line VIL, the (k-1)-th scan line Sk-1, the first scan connection line SCE1, and the k-th emission line Ek, and the other of the first connection contact holes BCNT1 may at least partially overlap with another one of the initialization voltage line VIL, the (k-1)-th scan line Sk-1, the first scan connection line SCE1, and the k-th emission line Ek.

[0219] In the wiring area LA, the j-th data line D j and the (j + 1)-th data line D j+1 may be formed by the first source metal layer DTL1. In the wiring area LA, the j-th data line D j and the (j + 1)-th data line D j+1 may be disposed on the second interlayer insulating film 142. In the wiring area LA, the first power supply connection line PCE1 and the second power supply connection line PCE2 may be formed by the second source metal layer DTL2. In the wiring area LA, the first power supply connection line PCE1 and the second power supply connection line PCE2 may be disposed on the first planarization film 160. For example, in the wiring area LA, the j-th data line D j and the (j + 1)-th data line D j+1 may be disposed in different layers from the first power supply connection line PCE1 and the second power supply connection line PCE2.

[0220] In the case where the j-th data line D j and the (j + 1)-th data line D j+1 and the first power supply connection line PCE1 and the second power supply connection line PCE2 are disposed in the same layer, if the j-th data line D j and the (j + 1)-th data line Dj+1 and if the distance between each pair of adjacent lines among the first power supply connection line PCE1 and the second power supply connection line PCE2 is less than a predetermined minimum distance, then the j-th data line D j and the (j + 1)-th data line D j+1 and the first power supply connection line PCE1 and the second power supply connection line PCE2 may be short-circuited due to process errors. Therefore, in the case where the j-th data line D j and the (j + 1)-th data line D j+1 and the first power supply connection line PCE1 and the second power supply connection line PCE2 are arranged in the same layer, considering process errors, the j-th data line D j and the (j + 1)-th data line D j+1 and the first power supply connection line PCE1 and the second power supply connection line PCE2 can be formed at a distance greater than the predetermined minimum distance between them.

[0221] In the wiring area LA, the j-th data line D j and the (j + 1)-th data line D j+1 and in the case where the first power supply connection line PCE1 and the second power supply connection line PCE2 are arranged in different layers, the j-th data line D j and the (j + 1)-th data line D j+1 and each pair of adjacent lines among the first power supply connection line PCE1 and the second power supply connection line PCE2 can be arranged in different layers. Therefore, if the j-th data line D j and the (j + 1)-th data line D j+1 are arranged in different layers from the first power supply connection line PCE1 and the second power supply connection line PCE2, then process errors do not need to be considered, and as a result, the distance between each pair of adjacent lines among the j-th data line D j and the (j + 1)-th data line D j+1 and the first power supply connection line PCE1 and the second power supply connection line PCE2 can be less than the predetermined minimum distance.

[0222] According to Figure 14 and Figure 15 In the structure depicted in, in the wiring area LA, the j-th data line D j and the (j + 1)-th data line D j+1 and in the case where the first power supply connection line PCE1 and the second power supply connection line PCE2 are arranged in different layers, the distance between the j-th data line D j and the (j + 1)-th data line D j+1 and the first power supply connection line PCE1 and the second power supply connection line PCE2 can become larger than when the j-th data line D j and the (j + 1)-th data line D j+1When both the first power connection line PCE1 and the second power connection line PCE2 are arranged in the same layer, it is narrow. As a result, the light-transmitting region TA can be widened.

[0223] In the wiring region LA, the (k - 1)-th scan line Sk-1 and the k-th emission line Ek can be formed by the first gate metal layer GTL1. In the wiring region LA, the (k - 1)-th scan line Sk-1 and the k-th emission line Ek can be arranged on the gate insulating film 130. In the wiring region LA, the initialization voltage line VIL and the first scan connection line SCE1 can be formed by the second gate metal layer GTL2. In the wiring region LA, the initialization voltage line VIL and the first scan connection line SCE1 can be arranged on the first interlayer insulating film 141. For example, in the wiring region LA, the initialization voltage line VIL and the first scan connection line SCE1 can be arranged in a different layer from the (k - 1)-th scan line Sk-1 and the k-th emission line Ek.

[0224] In the case where the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the first scan connection line SCE1, and the k-th emission line Ek are arranged in the same layer in the wiring region LA, if the distance between each pair of adjacent lines among the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the first scan connection line SCE1, and the k-th emission line Ek is less than a predetermined minimum distance, the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the first scan connection line SCE1, and the k-th emission line Ek may be short-circuited due to process errors. Therefore, in the case where the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the first scan connection line SCE1, and the k-th emission line Ek are arranged in the same layer, considering process errors, the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the first scan connection line SCE1, and the k-th emission line Ek can be formed at a distance greater than the predetermined minimum distance from each other.

[0225] In the case where the (k - 1)-th scan line Sk-1 and the k-th emission line Ek in the wiring region LA are arranged in a different layer from the initialization voltage line VIL and the first scan connection line SCE1, each pair of adjacent lines among the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the first scan connection line SCE1, and the k-th emission line Ek can be arranged in a different layer. Therefore, if the (k - 1)-th scan line Sk-1 and the k-th emission line Ek are arranged in a different layer from the initialization voltage line VIL and the first scan connection line SCE1, there is no need to consider process errors, and as a result, the distance between each pair of adjacent lines among the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the first scan connection line SCE1, and the k-th emission line Ek can be less than the predetermined minimum distance.

[0226] According toFigure 14 and Figure 15 In the structure depicted in Figure 15 , when the (k - 1)-th scan line Sk-1 and the k-th emission line Ek in the wiring region LA are arranged in different layers from the initialization voltage line VIL and the first scan connection line SCE1, the distance between the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the first scan connection line SCE1, and the k-th emission line Ek can become narrower than when the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the first scan connection line SCE1, and the k-th emission line Ek are all arranged in the same layer. As a result, the light-transmitting region TA can become wider.

[0227] Figure 16 is a plan view of the region A shown in Figure 5 . Figure 17 is a cross-sectional view taken along the line VIII-VIII' of Figure 16 .

[0228] Figure 16 and Figure 17 The embodiments of Figure 14 and Figure 15 differ from the embodiments of Figure 14 and Figure 15 in that the initialization voltage line VIL, the (k - 1)-th scan line Sk-1, the j-th data line D j and the first power connection line PCE1 are arranged to at least partially overlap each other in the thickness direction (e.g., the Z-axis direction), and the k-th scan line Sk, the k-th emission line Ek, the (j + 1)-th data line D j+1 and the second power connection line PCE2 are arranged to at least partially overlap each other in the thickness direction (e.g., the Z-axis direction).

[0229] According to the embodiments of Figure 16 and Figure 17 , since the (k - 1)-th scan line Sk-1 and the k-th emission line Ek in the wiring region LA are arranged in different layers from the initialization voltage line VIL and the first scan connection line SCE1, the adjacent initialization voltage line VIL and the (k - 1)-th scan line Sk-1 can be arranged to at least partially overlap each other in the thickness direction, and the adjacent first scan connection line SCE1 and the k-th emission line Ek can be arranged to at least partially overlap each other in the thickness direction. In addition, since the j-th data line D j and the (j + 1)-th data line D j+1 in the wiring region LA are arranged in different layers from the first power connection line PCE1 and the second power connection line PCE2, the adjacent j-th data line D j and the first power connection line PCE1 can be arranged to at least partially overlap each other in the thickness direction, and the adjacent (j + 1)-th data line D j+1The second power supply connection line PCE2 can be arranged to at least partially overlap with each other in the thickness direction. Thus, compared with the embodiments of Figure 14 and Figure 15 , the width of the wiring area LA can be further reduced, and as a result, the light-transmitting area TA can be further widened.

[0230] Figure 18 is a plan view of the area A shown in Figure 5 . Figure 19 is a cross-sectional view taken along the line V-V' of Figure 18 .

[0231] Figure 18 and Figure 19 The embodiments of Figure 14 and Figure 15 differ from the embodiments of Figure 14 and Figure 15 in that the initialization voltage line VIL is connected to the initialization connection line VE, and the initialization connection line VE and the first scan connection line SCE1 are formed by the light-shielding layer BML. Hereinafter, the embodiments of Figure 18 and Figure 19 will be mainly described with respect to the differences from the embodiments of

[0232] With reference to Figure 18 and Figure 19 , in the wiring area LA, the initialization voltage line VIL can be connected to the initialization connection line VE through the third connection contact hole BCNT3. In the wiring area LA, the k-th scan line Sk can be connected to the first scan connection line SCE1 through the fourth connection contact hole BCNT4.

[0233] In the wiring area LA, the j-th data line D j , the first power supply connection line PCE1, the (j + 1)-th data line D j+1 and the second power supply connection line PCE2 can at least partially overlap with the initialization connection line VE (instead of the initialization voltage line VIL).

[0234] In the wiring area LA, the initialization connection line VE and the first scan connection line SCE1 can be formed by the light-shielding layer BML. In the wiring area LA, the initialization connection line VE and the first scan connection line SCE1 can be arranged in the buffer film BF. In the wiring area LA, the (k - 1)-th scan line Sk - 1 and the k-th emission line Ek can be formed by the first gate metal layer GTL1. In the wiring area LA, the (k - 1)-th scan line Sk - 1 and the k-th emission line Ek can be arranged on the gate insulating film 130.

[0235] The distance between the light-shielding layer BML and the first gate metal layer GTL1 can be greater than the distance between the first gate metal layer GTL1 and the second gate metal layer GTL2. Therefore, the influence of the initialization connection line VE formed by the light-shielding layer BML and the first scan connection line SCE1 on the (k-1)th scan line Sk-1 and the kth emission line Ek formed by the first gate metal layer GTL1 can be reduced, and vice versa.

[0236] In the case where the (k-1)th scan line Sk-1 and the kth emission line Ek in the wiring area LA and the initialization connection line VE and the first scan connection line SCE1 are arranged in different layers, each pair of adjacent lines among the initialization connection line VE, the (k-1)th scan line Sk-1, the first scan connection line SCE1, and the kth emission line Ek can be arranged in different layers. Therefore, if the (k-1)th scan line Sk-1 and the kth emission line Ek and the initialization connection line VE and the first scan connection line SCE1 are arranged in different layers, process errors do not need to be considered, and as a result, the distance between each pair of adjacent lines among the initialization connection line VE, the (k-1)th scan line Sk-1, the first scan connection line SCE1, and the kth emission line Ek can be less than a predetermined minimum distance.

[0237] According to Figure 18 and Figure 19 In the structure depicted in, in the case where the (k-1)th scan line Sk-1 and the kth emission line Ek in the wiring area LA and the initialization connection line VE and the first scan connection line SCE1 are arranged in different layers, the distance between the initialization connection line VE, the (k-1)th scan line Sk-1, the first scan connection line SCE1, and the kth emission line Ek can become narrower than when the initialization connection line VE, the (k-1)th scan line Sk-1, the first scan connection line SCE1, and the kth emission line Ek are all arranged in the same layer. As a result, the light-transmitting area TA can become wider.

[0238] In Figure 18 and Figure 19 In the structure depicted in, the adjacent initialization connection line VE and the (k-1)th scan line Sk-1 can be arranged to at least partially overlap each other in the thickness direction, and the adjacent first scan connection line SCE1 and the kth emission line Ek can be arranged to at least partially overlap each other in the thickness direction. In addition, the adjacent jth data line D j and the first power connection line PCE1 can be arranged to at least partially overlap each other in the thickness direction, and the adjacent (j+1)th data line D j+1 and the second power connection line PCE2 can be arranged to at least partially overlap each other in the thickness direction. Therefore, the width of the wiring area LA can be further reduced, and as a result, the light-transmitting area TA can be further widened.

[0239] Figure 20 is a plan view of region A shown in the figure. Figure 5 of the region A. Figure 21 is a cross-sectional view taken along Figure 20 line VI-VI' of the figure.

[0240] Figure 20 and Figure 21 The embodiments of Figure 14 and Figure 15 differ from the embodiments of Figure 14 and Figure 15 in that the (k - 1)-th scan line Sk-1 is connected to the second scan connection line SCE2, and the k-th emission line Ek is connected to the emission connection line ECE. In the following, the description will mainly focus on the differences from the embodiments of Figure 14 and Figure 15 to describe the embodiments of Figure 20 and Figure 21 . In the sense that the details of various elements have been omitted herein, it can be assumed that these details are at least similar to the corresponding elements described previously.

[0241] Referring to Figure 20 and Figure 21 , in the wiring region LA, the (k - 1)-th scan line Sk-1 can be connected to the second scan connection line SCE2 through the fifth connection contact hole BCNT5. In the wiring region LA, the k-th emission line Ek can be connected to the emission connection line ECE through another fifth connection contact hole BCNT5.

[0242] In the wiring region LA, the j-th data line D j , the first power connection line PCE1, the (j + 1)-th data line D j+1 and the second power connection line PCE2 can at least partially overlap with the second scan connection line SCE2 (instead of the (k - 1)-th scan line Sk-1), and can at least partially overlap with the emission connection line ECE (instead of the k-th emission line Ek).

[0243] In the wiring region LA, the second scan connection line SCE2 and the emission connection line ECE can be formed by the light-shielding layer BML. In the wiring region LA, the second scan connection line SCE2 and the emission connection line ECE can be arranged in the buffer film BF. The initialization voltage line VIL and the first scan connection line SCE1 can be formed by the second gate metal layer GTL2. In the wiring region LA, the initialization voltage line VIL and the first scan connection line SCE1 can be arranged on the first interlayer insulating film 141.

[0244] The distance between the light-shielding layer BML and the second gate metal layer GTL2 can be greater than the distance between the first gate metal layer GTL1 and the second gate metal layer GTL2. Accordingly, the influence of the second scan connection line SCE2 and the emission connection line ECE formed by the light-shielding layer BML on the initialization voltage line VIL and the first scan connection line SCE1 formed by the second gate metal layer GTL2 due to coupling can be reduced, and vice versa.

[0245] In a case where the second scan connection line SCE2 and the emission connection line ECE and the initialization voltage line VIL and the first scan connection line SCE1 are arranged in different layers in the wiring region LA, each pair of adjacent lines among the initialization voltage line VIL, the first scan connection line SCE1, the second scan connection line SCE2, and the emission connection line ECE can be arranged in different layers. Accordingly, if the second scan connection line SCE2 and the emission connection line ECE and the initialization voltage line VIL and the first scan connection line SCE1 are arranged in different layers, process errors do not need to be considered, and as a result, the distance between each pair of adjacent lines among the initialization voltage line VIL, the first scan connection line SCE1, the second scan connection line SCE2, and the emission connection line ECE can be less than a predetermined minimum distance.

[0246] According to Figure 20 and Figure 21 In an embodiment, in a case where the second scan connection line SCE2 and the emission connection line ECE and the initialization voltage line VIL and the first scan connection line SCE1 are arranged in different layers in the wiring region LA, the distances between the initialization voltage line VIL, the first scan connection line SCE1, the second scan connection line SCE2, and the emission connection line ECE can become narrower than when the initialization voltage line VIL, the first scan connection line SCE1, the second scan connection line SCE2, and the emission connection line ECE are all arranged in the same layer. As a result, the light-transmitting region TA can become wider.

[0247] In Figure 20 and Figure 21 In an embodiment, the adjacent initialization voltage line VIL and the second scan connection line SCE2 can be arranged to at least partially overlap each other in the thickness direction, and the adjacent first scan connection line SCE1 and the emission connection line ECE can be arranged to at least partially overlap each other in the thickness direction. In addition, the adjacent j-th data line D j and the first power connection line PCE1 can be arranged to at least partially overlap each other in the thickness direction, and the adjacent (j + 1)-th data line D j+1 and the second power connection line PCE2 can be arranged to at least partially overlap each other in the thickness direction. Accordingly, the width of the wiring region LA can be further reduced, and as a result, the light-transmitting region TA can be further widened.

[0248] Figure 22 is a diagram Figure 1 of a plan view of pixels, scan lines, data lines, and a first driving voltage line in a sensor region of a display device.

[0249] Figure 22 An embodiment of Figure 5 differs from an embodiment of Figure 5 in that a voltage connection line VCE connected to the first driving voltage line VDDL is additionally provided. The following will mainly describe Figure 22 the embodiment in terms of the differences from the embodiment of

[0250] With reference to Figure 22 , the voltage connection line VCE can mainly extend in a first direction (e.g., the X-axis direction), and the first driving voltage line VDDL can mainly extend in a second direction (e.g., the Y-axis direction). The voltage connection line VCE can be arranged in the wiring region LA, and the first driving voltage line VDDL can be arranged in the pixel region PA and the wiring region LA. In the pixel region PA, the first driving voltage line VDDL can be connected to the voltage connection line VCE.

[0251] Since the voltage connection line VCE mainly extends in a first direction (e.g., the X-axis direction), one of the voltage connection lines VCE can be arranged on one side of the light-transmitting region TA, e.g., on the upper side of the light-transmitting region TA, and the other voltage connection line VCE can be arranged on the other side of the light-transmitting region TA, e.g., on the lower side of the light-transmitting region TA.

[0252] According to Figure 22 the embodiment of

[0253] Since there are the voltage connection line VCE and the first driving voltage line VDDL arranged in the pixel region PA on the upper side of the light-transmitting region TA, it is not necessary to connect to the first driving voltage line VDDL arranged in the pixel region PA on the lower side of the light-transmitting region TA. Therefore, the first driving voltage line VDDL can be omitted from the wiring region LA. Thus, the arrangement of the wiring in the wiring region LA can be simplified.

[0254] Figure 23 is a diagram Figure 22 of a plan view of region B of Figure 24is taken along the Figure 23 sectional view taken along line VII-VII'.

[0255] Figure 23 and Figure 24 The embodiments of Figure 14 and Figure 15 differ from the embodiments of

[0256] in that a voltage connection line VCE connected to the first driving voltage line VDDL is additionally provided, and the first power connection line PCE1 and the second power connection line PCE2 are not provided. In the sense that details of various elements have been omitted herein, it can be assumed that these details are at least similar to the corresponding elements described previously.

[0256] Referring to Figure 23 and Figure 24 , the voltage connection line VCE can be connected to a plurality of first driving voltage lines VDDL in the pixel region PA. For example, a plurality of first driving voltage lines VDDL that at least partially overlap with the first sub-pixels SP1 adjacent to each other in the first direction (e.g., the X-axis direction) can be connected to a single voltage connection line VCE.

[0257] The voltage connection line VCE can be arranged in a different layer from the first driving voltage line VDDL. In this case, the voltage connection line VCE can be connected to the first driving voltage line VDDL through a sixth connection contact hole BCNT6. For example, the voltage connection line VCE can be formed of a second source metal layer DTL2 and can be arranged on the first planarization film 160, as Figure 24 shown, but the present disclosure is not limited thereto. In another example, the voltage connection line VCE can be formed of a first gate metal layer GTl1 and can be arranged on the gate insulating film 130. In yet another example, the voltage connection line VCE can be formed of a second gate metal layer GTL2 and can be arranged on the first interlayer insulating film 141.

[0258] Alternatively, the voltage connection line VCE can be arranged in the same layer as the first driving voltage line VDDL. In this case, the voltage connection line VCE can be connected to the first driving voltage line VDDL without a contact hole. In order to arrange the voltage connection line VCE in the same layer as the first driving voltage line VDDL, the j-th data line D j and the (j + 1)-th data line D j+1 can be connected to a data connection electrode in the pixel region PA. The data connection electrode can be formed in the same layer as the first driving voltage line VDDL and can be arranged on the first planarization film 160.

[0259] In Figure 23 and Figure 24In an embodiment, the initialization voltage line VIL and the (k-1)th scan line Sk-1 adjacent to each other may be arranged to at least partially overlap each other in the thickness direction, and the first scan connection line SCE1 and the kth emission line Ek adjacent to each other may be arranged to at least partially overlap each other in the thickness direction. In this case, the width of the wiring region LA can be further reduced, and as a result, the light-transmitting region TA can be further widened.

[0260] According to the foregoing and other embodiments of the present disclosure, since the sensor region of the display panel of the display device includes a light-transmitting region through which light is transmitted, even if the sensor device is arranged to overlap the sensor region in the thickness direction of the display panel, light can enter the sensor device arranged on the bottom surface of the display panel through the light-transmitting region from the top surface of the display device. Therefore, deterioration of the sensing ability of the sensor device can be prevented or reduced.

[0261] In addition, since six transistors are not provided in the first sub-pixel, a wiring region can be provided in the region where the sixth transistor is not provided, and as a result, the light-transmitting region can be widened.

[0262] Furthermore, when adjacent wirings are arranged in different layers in the wiring region, the distance between the adjacent wirings can become narrower than when the adjacent wirings are arranged in the same layer in the wiring region, and thus, the light-transmitting region can be widened.

[0263] In addition, since the first driving voltage line is connected to the voltage connection line, the first driving voltage line on one side of the light-transmitting region does not need to be connected to the first driving voltage line on the other side of the light-transmitting region through the wiring region. Therefore, since the first driving voltage line is not provided in the wiring region, the arrangement of the wirings in the wiring region can be simplified.

[0264] Although the present invention has been specifically shown and described with respect to exemplary embodiments of the present invention, those of ordinary skill in the art will understand that various forms and details of the present invention can be changed without departing from the spirit and scope of the present invention defined by the appended claims.

Claims

1. A display device, comprising: A display panel including a main area and a sensor area; And A plurality of sensor devices at least partially overlapping with the sensor area of the display panel in the thickness direction of the display panel, Wherein the display panel includes a plurality of first sub-pixels arranged in the sensor area and a plurality of second sub-pixels arranged in the main area, Wherein the number of transistors of each of the plurality of first sub-pixels is different from the number of transistors of each of the plurality of second sub-pixels, Wherein the display panel further includes: A data line at least partially overlapping with the first sub-pixels and the second sub-pixels and to which a data voltage is applied; A first driving voltage line at least partially overlapping with the first sub-pixels and the second sub-pixels and to which a first driving voltage is applied; and A power connection line connected to the first driving voltage line, and Wherein the data line and the first driving voltage line are arranged on the same layer, and the power connection line is arranged above the data line and extends parallel to the data line in a plan view.

2. The display device according to claim 1, wherein, The number of transistors of each of the plurality of first sub-pixels is less than the number of transistors of each of the plurality of second sub-pixels.

3. The display device according to claim 2, wherein, The display panel further includes a scan line and an emission line, and Each of the plurality of first sub-pixels and the plurality of second sub-pixels includes: A driving transistor that controls a driving current flowing from a first electrode of the driving transistor to a second electrode according to a data voltage applied to a gate electrode of the driving transistor; A light-emitting element connected to the second electrode of the driving transistor; A first transistor turned on by a scan signal from one of the scan lines to connect the gate electrode of the driving transistor to an initialization voltage line to which an initialization voltage is applied; A second transistor turned on by a scan signal from another one of the scan lines to connect the first electrode of the driving transistor to one of the data lines; A third transistor turned on by a scan signal from yet another one of the scan lines to connect the gate electrode and the second electrode of the driving transistor; A fourth transistor turned on by an emission signal from one of the emission lines to connect the first electrode of the driving transistor to a first driving voltage line to which a first driving voltage is applied; and A fifth transistor turned on by the emission signal to connect the second electrode of the driving transistor to the light-emitting element.

4. The display device according to claim 3, wherein, Each of the second sub-pixels further includes: a sixth transistor turned on by a scan signal from yet another one of the scan lines to connect a first electrode of the light-emitting element to the initialization voltage line.

5. The display device according to claim 1, wherein, The display panel further includes a scan line at least partially overlapping with the first sub-pixels and the second sub-pixels and to which a scan signal is applied, and The number of scan lines that at least partially overlap with each of the first sub-pixels is different from the number of scan lines that at least partially overlap with each of the second sub-pixels.

6. The display device according to claim 5, wherein, The number of the scan lines that at least partially overlap with each of the first sub-pixels is less than the number of the scan lines that at least partially overlap with each of the second sub-pixels.

7. The display device according to claim 6, wherein, The display panel further includes a light-transmitting region disposed in the sensor region, and the light-transmitting region does not overlap with the first sub-pixels.

8. The display device according to claim 7, wherein, The light-transmitting region is at least partially surrounded by the first sub-pixels.

9. The display device according to claim 7, wherein, The display panel further includes a first scan connection line connected to one of the scan lines in a wiring region between the light-transmitting region and the first sub-pixels, and the first scan connection line and the scan line are disposed in different layers.

10. The display device according to claim 9, wherein, The display panel further includes an insulating film disposed between the first scan connection line and the scan line connected to the first scan connection line, and The first scan connection line is connected to the scan line to which the first scan connection line is connected through a contact hole penetrating the insulating film.

11. The display device according to claim 9, wherein, The display panel further includes: an initialization voltage line that at least partially overlaps with the first sub-pixels and the second sub-pixels and to which an initialization voltage is applied.

12. The display device according to claim 11, wherein, The power connection line is connected to one of the first driving voltage lines in the wiring region.

13. The display device according to claim 11, wherein, One of the data lines at least partially overlaps with one of the initialization voltage lines or the first scan connection line in the wiring region.

14. The display device according to claim 12, wherein, The power connection line at least partially overlaps with one of the scan lines.

15. The display device according to claim 12, wherein, The display panel further includes an insulating film disposed between the power connection line and one of the first driving voltage lines, and The power connection line is connected to the first driving voltage line to which the power connection line is connected through a contact hole penetrating the insulating film.

16. The display device according to claim 12, wherein, The data lines and the first driving voltage lines are disposed on the initialization voltage line and the first scan connection line, and The initialization voltage line and the first scan connection line are disposed on the scan lines.

17. The display device according to claim 12, wherein The display panel further includes an initialization connection line connected to one of the initialization voltage lines, and the initialization connection line and the initialization voltage line are disposed in different layers.

18. The display device according to claim 17, wherein, One of the data lines at least partially overlaps with the initialization connection line or the first scan connection line in the wiring region.

19. The display device according to claim 17, wherein, The display panel further includes an insulating film disposed between the initialization connection line and one of the initialization voltage lines, and The initialization connection line is connected to the initialization voltage line to which the initialization connection line is connected through a contact hole penetrating the insulating film.

20. The display device according to claim 17, wherein, The data line and the first driving voltage line are arranged on the scan line, and the scan line is arranged on the initialization connection line and the first scan connection line.

21. The display device according to claim 12, wherein, The display panel further includes: a second scan connection line connected to another one of the scan lines and arranged in a different layer from the scan line, an emission line that at least partially overlaps with the first sub-pixel and the second sub-pixel and to which an emission signal is applied, and an emission connection line connected to one of the emission lines and arranged in a different layer from the emission line.

22. The display device according to claim 21, wherein, In the wiring area, one of the data lines at least partially overlaps with the second scan connection line, and the other one of the data lines at least partially overlaps with the emission connection line.

23. The display device according to claim 21, wherein, The second scan connection line and the emission connection line are arranged in the same layer.

24. The display device according to claim 21, wherein the data line and the first driving voltage line are arranged on the initialization voltage line and the first scan connection line, the initialization voltage line and the first scan connection line are arranged on the scan line and the emission line, and the scan line and the emission line are arranged on the second scan connection line and the emission connection line.

25. The display device according to claim 11, wherein, The display panel further includes a voltage connection line connected to the first driving voltage line.

26. The display device according to claim 25, wherein the first driving voltage line mainly extends in a first direction, and the voltage connection line mainly extends in a second direction.

27. The display device according to claim 25, wherein, The voltage connection line is arranged on the first driving voltage line.

28. The display device according to claim 25, wherein, The first driving voltage line is arranged on the voltage connection line.

29. The display device according to claim 28, wherein, The voltage connection line is arranged in the same layer as the initialization voltage line and is arranged on the scan line.

30. The display device according to claim 28, wherein, The initialization voltage line is arranged on the voltage connection line and is arranged in the same layer as the scan line.

31. The display device according to claim 25, wherein, The first driving voltage line is arranged in the same layer as the voltage connection line.

32. A display device, comprising: a display panel including a main area and a sensor area; and a sensor device that at least partially overlaps with the sensor area of the display panel in the thickness direction of the display panel, wherein the display panel includes a plurality of first sub-pixels arranged in the sensor area, a plurality of second sub-pixels arranged in the main area, a data line that at least partially overlaps with the first sub-pixels and the second sub-pixels and to which a data voltage is applied, a first driving voltage line that at least partially overlaps with the plurality of first sub-pixels and the plurality of second sub-pixels and to which a first driving voltage is applied, and a power connection line connected to the first driving voltage line, wherein the power connection line is arranged in a different layer from the first driving voltage line, and wherein the data line and the first driving voltage line are arranged in the same layer, and the power connection line is arranged above the data line and extends parallel to the data line in a plan view.

Images