Semiconductor package

Abstract

A semiconductor package is disclosed, which includes a redistribution substrate and a semiconductor chip on the top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer covering the sidewalls of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first circuit portion. The width of the under-bump pattern at the top surface is greater than the width of the under-bump pattern at the bottom surface. The thickness of the under-bump pattern is greater than the thickness of the first circuit portion.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2019 - 0088551, filed with the Korean Intellectual Property Office on July 22, 2019, the entire content of which is incorporated herein by reference. Technical Field

[0003] The present inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including a redistribution substrate and a method of manufacturing the same. Background Art

[0004] Semiconductor packages are provided to implement integrated circuit chips used in electronic products. A semiconductor package is typically configured such that a semiconductor chip is mounted on a printed circuit board, and the semiconductor chip is electrically connected to the printed circuit board using bonding wires or bumps. With the development of the electronics industry, various studies have been conducted to improve the reliability and durability of semiconductor packages. Summary of the Invention

[0005] Some example embodiments of the present inventive concept provide a semiconductor package having enhanced reliability and durability and a method of manufacturing the same.

[0006] Some example embodiments of the present inventive concept provide a small - sized semiconductor package and a method of manufacturing the same.

[0007] According to some example embodiments of the present inventive concept, the present disclosure relates to a semiconductor package including: a redistribution substrate; and a semiconductor chip on a top surface of the redistribution substrate, wherein the redistribution substrate includes: an under - bump pattern; a lower dielectric layer covering sidewalls of the under - bump pattern; and a first redistribution pattern on the lower dielectric layer, the first redistribution pattern including a first line portion, wherein a width of the under - bump pattern at a top surface is greater than a width of the under - bump pattern at a bottom surface, and wherein a thickness of the under - bump pattern is greater than a thickness of the first line portion.

[0008] According to some example embodiments of the present inventive concept, the present disclosure relates to a semiconductor package including: a redistribution substrate; and a semiconductor chip on a top surface of the redistribution substrate, wherein the redistribution substrate includes: an under - bump pattern; a dielectric layer covering sidewalls of the under - bump pattern; and a redistribution pattern on the under - bump pattern, the redistribution pattern being coupled to the under - bump pattern, wherein an angle between a sidewall and a bottom surface of the under - bump pattern is in a range of 105° to 135°.

[0009] According to some example embodiments of the inventive concept, the present disclosure relates to a semiconductor package including: a redistribution substrate; and a semiconductor chip on a top surface of the redistribution substrate, wherein the redistribution substrate includes: conductive terminal pads; a lower dielectric layer covering sidewalls of the conductive terminal pads; a line pattern on the lower dielectric layer; and vias between the conductive terminal pads and the line pattern, the vias being in contact with top surfaces of the conductive terminal pads, wherein a thickness of the conductive terminal pads is greater than a thickness of the line pattern, and wherein a width of the vias is less than a width of the conductive terminal pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A , Figure 1C , Figure 1E , Figure 1G , Figure 1H , Figure 1I , Figure 1K , Figure 1L , Figure 1M , Figure 1O and Figure 1Q illustrate cross-sectional views showing a method of manufacturing a semiconductor package according to some example embodiments.

[0011] Figure 1B illustrate Figure 1A an enlarged view of part I of

[0012] Figure 1D illustrate Figure 1C an enlarged view of part I of

[0013] Figure 1F illustrate Figure 1E an enlarged view of part I of

[0014] Figure 1J illustrate Figure 1I an enlarged view of part I of

[0015] Figure 1L illustrate Figure 1K an enlarged view of part I of

[0016] Figure 1N illustrate Figure 1M an enlarged view of part I of

[0017] Figure 1P illustrate Figure 1O an enlarged view of part I of

[0018] Figure 1R illustrate Figure 1Q an enlarged view of part I of

[0019] Figure 2A , Figure 2C andFigure 2E The cross-sectional view shows a method of manufacturing a semiconductor package according to some exemplary embodiments.

[0020] Figure 2B The illustration shows Figure 2A an enlarged view of part I.

[0021] Figure 2D The illustration shows Figure 2C an enlarged view of part I.

[0022] Figure 2F The illustration shows Figure 2E an enlarged view of part I.

[0023] Figure 3A and Figure 3B The cross-sectional view shows a method of manufacturing a semiconductor package according to some example embodiments.

[0024] Figure 4 The cross-sectional view shows a semiconductor package according to some example embodiments.

[0025] Figure 5 The cross-sectional view shows a semiconductor package according to some example embodiments.

[0026] Figure 6A The plan view shows a semiconductor package according to some example embodiments.

[0027] Figure 6B The illustration shows a cross-sectional view taken along line II-III of Figure 6A The cross-sectional view shows a semiconductor package according to some example embodiments.

[0028] Figure 6C The illustration shows Figure 6B an enlarged view of part IV.

[0029] Figure 6D The cross-sectional view shows a semiconductor package according to some example embodiments.

[0030] Figure 6E The cross-sectional view shows a semiconductor package according to some example embodiments.

[0031] Figure 7A The cross-sectional view shows a semiconductor package according to some example embodiments.

[0032] Figure 7B The cross-sectional view shows a semiconductor package according to some example embodiments. DETAILED DESCRIPTION

[0033] In this specification, the same reference numerals may denote the same components. A semiconductor package and a method of manufacturing the same according to the inventive concept will be described below.

[0034] Figure 1A 、 Figure 1C 、 Figure 1E 、 Figure 1G 、 Figure 1H 、 Figure 1I 、 Figure 1K 、 Figure 1L 、 Figure 1M 、 Figure 1O and Figure 1Q illustrate cross - sectional views showing a method of manufacturing a semiconductor package according to some example embodiments. Figure 1B illustrate Figure 1A an enlarged view of part I of Figure 1D illustrate Figure 1C an enlarged view of part I of Figure 1F illustrate Figure 1E an enlarged view of part I of Figure 1J illustrate Figure 1I an enlarged view of part I of Figure 1L illustrate an enlarged view of part I of FIG. 1K. Figure 1N illustrate Figure 1M an enlarged view of part I of. FIG. 1P illustrates an enlarged view of part I of Figure 1O Figure 1R illustrate Figure 1Q an enlarged view of part I of

[0035] Referring to Figure 1A and Figure 1B , a lower seed layer 151 and a first dielectric layer 101 can be formed on a carrier substrate 900. A release layer 910 can also be interposed between the carrier substrate 900 and the lower seed layer 151. The lower seed layer 151 can be formed on the carrier substrate 900 and can cover the top surface of the release layer 910. The lower seed layer 151 can be formed by a deposition process. The lower seed layer 151 can include a conductive material. For example, the lower seed layer 151 can include one or more of copper, titanium, and their alloys. The release layer 910 can attach the lower seed layer 151 to the carrier substrate 900.

[0036] The first dielectric layer 101 can be formed on the top surface of the lower seed layer 151. For example, the first dielectric layer 101 can contact the top surface of the lower seed layer 151. The first dielectric layer 101 can be formed by a coating process such as spin coating or slot coating. The first dielectric layer 101 can include, for example, a photosensitive polymer. The photosensitive polymer can include, for example, one or more of photosensitive polyimide, polybenzoxazole, phenolic polymer, and benzocyclobutene polymer.

[0037] ​The first dielectric layer 101 can be patterned to form a first preliminary opening 119P in the first dielectric layer 101. The patterning of the first dielectric layer 101 can be performed by an exposure and development process. The first preliminary opening 119P can expose the lower seed layer 151 on the release layer 910 or the carrier substrate 900. The first preliminary opening 119P can have sidewalls 119c that are substantially perpendicular to the bottom surface 101b of the first dielectric layer 101.

[0038] Referring Figure 1C to Figure 1D and Figure 1D , the first dielectric layer 101 can undergo a curing process to form a first opening 119. The curing process of the first dielectric layer 101 can include a thermal curing process. During the curing process, as Figure 1D shown, a portion of the first dielectric layer 101 can flow into the first preliminary opening 119P, thereby forming the first opening 119. The first opening 119 can have a tapered shape. For example, the diameter of the first opening 119 can be greater at its top than at its bottom. The width of the first opening 119 can be greater at its top than at its bottom. The bottom of the first opening 119 can be closer to the carrier substrate 900 than the top of the first opening 119. The first opening 119 can expose the inner wall 101c of the first dielectric layer 101. The inner wall 101c of the first dielectric layer 101 can correspond to the sidewalls of the first opening 119. Because the first opening 119 has a tapered shape, an acute angle θ1 can be generated between the bottom surface 101b and the inner wall 101c of the first dielectric layer 101. For example, the first dielectric layer 101 can have an angle θ1 in the range of about 45° to about 75° between the bottom surface 101b and the inner wall 101c.

[0039] Referring Figure 1E to and Figure 1F Figure 1F , an under-bump pattern 150 can be formed in the first opening 119. The under-bump pattern 150 can be formed by performing an electroplating process using the lower seed layer 151 as an electrode. The first dielectric layer 101 can locally form the under-bump pattern 150 in the first opening 119. The electroplating process can continue until the height of the top surface of the under-bump pattern 150 is equal to or less than the height of the top surface of the first dielectric layer 101. The height difference between the top surface of the under-bump pattern 150 and the top surface of the first dielectric layer 101 can be less than the thickness T1 of the under-bump pattern 150. As Figure 1F shown, the first dielectric layer 101 can cover the sidewalls 150c of the under-bump pattern 150, but can not cover the top surface of the under-bump pattern 150 or the bottom surface 150b of the under-bump pattern 150. No separate seed layer can be provided between the under-bump pattern 150 and the first dielectric layer 101. The first dielectric layer 101 can physically contact the sidewalls 150c of the under-bump pattern 150.

[0040] The under-bump pattern 150 may have a shape corresponding to the shape of the first opening 119. The width W2 of the under-bump pattern 150 at the top surface may be greater than the width W1 of the under-bump pattern 150 at the bottom surface 150b. An obtuse angle θ10 may be formed between the bottom surface 150b and the sidewall 150c of the under-bump pattern 150. For example, the under-bump pattern 150 may have an angle θ10 in the range of about 105° to about 135° between the bottom surface 105b and the sidewall 150c. When the under-bump pattern 150 is formed in the opening defined by the resist pattern, the angle θ1 between the bottom surface 150b and the sidewall 150c of the under-bump pattern 150 may be about 90°. In this case, after the under-bump pattern 150 is formed, a removal process may be additionally performed to remove the resist pattern. According to some embodiments, since the under-bump pattern 150 is formed in the first opening 119 defined by the first dielectric layer 101, the formation and removal of the resist pattern may be skipped. As a result, the manufacturing of the semiconductor package may be simplified.

[0041] The under-bump pattern 150 may be a conductive terminal pad. The conductive terminal pad may include a solder pad or a pillar pad. The under-bump pattern 150 may include a metal. For example, the under-bump pattern 150 may include copper. The under-bump pattern 150 may not include, for example, titanium.

[0042] Referring to Figure 1G , the second dielectric layer 102 may be formed on the top surface of the first dielectric layer 101 and may cover the top surface of the first dielectric layer 101 and the top surface of the under-bump pattern 150. The second dielectric layer 102 may contact the top surface of the first dielectric layer 101 and the top surface of the under-bump pattern 150. The second dielectric layer 102 may include a photosensitive polymer. For example, the second dielectric layer 102 may include the same material as the first dielectric layer 101. The first dielectric layer 101 and the second dielectric layer 102 may be referred to as the lower dielectric layer.

[0043] The second dielectric layer 102 may be patterned to form a second preliminary opening (not shown) in the second dielectric layer 102. The second preliminary opening may have an inner wall substantially perpendicular to the bottom surface of the second dielectric layer 102. The second dielectric layer 102 may undergo a curing process to form the second opening 129. The curing process of the second dielectric layer 102 may include a thermal curing process. During the curing process, a part of the second dielectric layer 102 may flow. Therefore, the second opening 129 may have a tapered shape. For example, the second dielectric layer 102 may have an angle θ2 in the range of about 45° to about 75° between its inner wall and the bottom surface. The inner wall of the second dielectric layer 102 may correspond to the sidewall of the second opening 129. The second opening 129 may be formed above the under-bump pattern 150 to expose the top surface of the under-bump pattern 150.

[0044] Referring to Figure 1H , a first seed layer 111 may be formed in the second opening 129 and on the top surface of the second dielectric layer 102. The first seed layer 111 may conformally cover the top surface and the inner wall of the second dielectric layer 102, and may also conformally cover the top surface of the under-bump pattern 150 exposed in the second opening 129. The first seed layer 111 may include a conductive material. For example, the first seed layer 111 may include one or more of copper, titanium, and their alloys.

[0045] A first conductive layer 112 may be formed on the first seed layer 111. The first conductive layer 112 may fill the second opening 129 and may extend onto the top surface of the second dielectric layer 102. The first conductive layer 112 may be formed by performing an electroplating process using the first seed layer 111 as an electrode. The first conductive layer 112 may include a metal such as copper.

[0046] Referring to Figure 1I and Figure 1J , the first conductive layer 112 and the first seed layer 111 may be patterned to form a first redistribution pattern 110. The first conductive layer 112 and the first seed layer 111 may be patterned by an etching process using a mask layer (not shown). Each first redistribution pattern 110 may include a patterned first seed layer 111 and a patterned first conductive layer 112. The first redistribution patterns 110 may be spaced apart from each other and electrically isolated from each other.

[0047] Each first redistribution pattern 110 may include a first via portion 110V and a first line portion 110W. As Figure 1J shown, the first via portion 110V may be disposed in the second opening 129. The first via portion 110V may have a shape corresponding to the shape of the second opening 129. The first via portion 110V may have an angle θ20 in the range of about 105° to about 135° between its bottom surface 110b and sidewall 110c.

[0048] The first wiring portion 110W may be disposed on the first via portion 110V and on the top surface of the second dielectric layer 102, and may be connected to the first via portion 110V. The first wiring portion 110W may extend horizontally in a longitudinal direction. In the present specification, the term "horizontally" may mean "parallel to the bottom surface 101b of the first dielectric layer 101". The thickness T1 of the under-bump pattern 150 may be greater than the thickness T2 of the first wiring portion 110W. The thickness T1 of the under-bump pattern 150 may be about 2.5 to 10 times the thickness T2 of the first wiring portion 110W. The thicknesses T1 of the under-bump pattern 150 and T2 of the first wiring portion 110W may be measured in a direction perpendicular to the top surface of the substrate or the bottom surface 101b of the first dielectric layer 101.

[0049] The first via portion 110V may be interposed between the under-bump pattern 150 and the first wiring portion 110W. The first via portion 110V may contact the top surface of the under-bump pattern 150. The width of the first via portion 110V may be smaller than the width of the under-bump pattern 150. The minimum width W3 of the first via portion 110V may be smaller than the width W1 of the under-bump pattern 150 at the bottom surface 150b and smaller than the width W2 of the under-bump pattern 150 at the top surface. For example, the maximum width of the first via portion 110V may be smaller than the width W1 of the under-bump pattern 150 at the bottom surface 150b and smaller than the width W2 of the under-bump pattern 150 at the top surface. The width W1 of the under-bump pattern 150 at the bottom surface 150b may correspond to the minimum width of the under-bump pattern 150, and the width W2 of the under-bump pattern 150 at the top surface may correspond to the maximum width of the under-bump pattern 150, but the inventive concept is not limited thereto.

[0050] When the under-bump pattern 150 is formed in the opening defined by the resist pattern, after forming the under-bump pattern 150 and removing the resist pattern, the first dielectric layer 101 may be formed. The first dielectric layer 101 may be formed on the top surface of the lower seed layer 151 and on the top surface of the under-bump pattern 150. Accordingly, the first dielectric layer 101 may have undulations on its top surface. For example, the height difference between the uppermost and lowermost portions of the top surface of the first dielectric layer 101 may be the same as or similar to the thickness T1 of the under-bump pattern 150. Accordingly, the bottom surfaces 110a of the first wiring portions 110W may be at different heights from each other.

[0051] According to some embodiments, as Figures 1A to 1FAs described in [reference], the formation of the resist pattern can be skipped, and before forming the under-bump pattern 150, the first dielectric layer 101 can be formed on the release layer 910. The top surface of the first dielectric layer 101 can be substantially flat. The height difference between the top surface of the under-bump pattern 150 and the top surface of the first dielectric layer 101 can be much smaller than the thickness T1 of the under-bump pattern 150. The second dielectric layer 102 can be formed on the first dielectric layer 101 and the under-bump pattern 150, and the top surface of the second dielectric layer 102 can be substantially flat. As Figure 1I shown, since the first redistribution pattern 110 is formed on the top surface of the second dielectric layer 102, the bottom surface 110a of the first line portion 110W can be located at the same height or a similar height. For example, the maximum interval between the bottom surface 101b of the first dielectric layer 101 and the bottom surface 110a of the first line portion 110W can be 100% to 130% of the minimum interval between the bottom surface 101b of the first dielectric layer 101 and the bottom surface 110a of the first line portion 110W. In this case, the bottom surface 110a of the first line portion 110W can be defined to refer to the surface that physically contacts the second dielectric layer 102.

[0052] Referring to Figure 1K and Figure 1L , the third dielectric layer 103 can be formed on the second dielectric layer 102 and can cover the second dielectric layer 102 and the first redistribution pattern 110. The third dielectric layer 103 can contact the top surface of the second dielectric layer 102 and the top surface and sides of the first redistribution pattern 110. The third dielectric layer 103 can include a photosensitive polymer. A third opening 139 can be formed in the third dielectric layer 103. The third opening 139 can expose the top surface of the first redistribution pattern 110. The formation of the third opening 139 can include: patterning the third dielectric layer 103 to form a third preliminary opening, and performing a curing process on the third dielectric layer 103. The inner wall of the third dielectric layer 103 can correspond to the sidewall of the third opening 139. The patterning of the third dielectric layer 103 can be performed by the same method as the method for patterning the first dielectric layer 101 discussed in Figure 1A and Figure 1B . The curing process of the third dielectric layer 103 can be performed by the same method as the method for curing the first dielectric layer 101 discussed in Figure 1C and Figure 1D . The third opening 139 can have a tapered shape.

[0053] The second redistribution pattern 120 may be formed on the top surface of the third dielectric layer 103 and in the third opening 139, and may be electrically connected to the first redistribution pattern 110. According to some embodiments, a second seed layer 121 may be conformally formed on the sidewalls and bottom surface of the third opening 139 and on the top surface of the third dielectric layer 103. The second seed layer 121 may include a conductive material such as copper, titanium, or an alloy thereof. An electroplating process may be performed to form a second conductive layer 122 on the second seed layer 121. The second conductive layer 122 may fill the third opening 139 and may extend onto the top surface of the third dielectric layer 103. The second conductive layer 122 may include a metal such as copper. The second conductive layer 122 and the second seed layer 121 may be patterned by an etching process to form the second redistribution pattern 120. Each second redistribution pattern 120 may include a patterned second seed layer 121 and a patterned second conductive layer 122. The second redistribution patterns 120 may be spaced apart from each other. Each second redistribution pattern 120 may extend longitudinally in the horizontal direction.

[0054] Each second redistribution pattern 120 may include a second via portion 120V and a second line portion 120W. As Figure 1L shown, the second via portion 120V may be disposed in the third opening 139. The second redistribution pattern 120 may have an angle θ30 in the range of about 105° to about 135° between the bottom surface and the sidewalls of the second via portion 120V. The second line portion 120W may be disposed on the second via portion 120V and on the top surface of the third dielectric layer 103 and may be connected to the second via portion 120V.

[0055] Referring to Figure 1M and Figure 1N , a fourth dielectric layer 104 may be formed on the third dielectric layer 103 and may cover the third dielectric layer 103 and the second redistribution patterns 120. The fourth dielectric layer 104 may contact the top surface of the third dielectric layer 103 and the top surface and sides of the second redistribution patterns 120. The fourth dielectric layer 104 may include a photosensitive polymer. A fourth opening 149 may be formed in the fourth dielectric layer 104. The fourth opening 149 may expose the top surface of the second redistribution pattern 120. The formation of the fourth opening 149 may include: patterning the fourth dielectric layer 104 to form a fourth preliminary opening; and performing a curing process on the fourth dielectric layer 104. The fourth opening 149 may have a tapered shape.

[0056] A third redistribution pattern 130 may be formed on the top surface of the fourth dielectric layer 104 and in the fourth opening 149, and may be electrically connected to the second redistribution pattern 120. According to some embodiments, a third seed layer 131 may be conformally formed on the bottom surface and sidewalls of the fourth opening 149 and on the top surface of the fourth dielectric layer 104. The third seed layer 131 may include a conductive material such as copper or titanium. An electroplating process may be performed to form a third conductive layer 132 on the third seed layer 131. On the third seed layer 131, the third conductive layer 132 may fill the fourth opening 149. The third conductive layer 132 may extend onto the top surface of the fourth dielectric layer 104 and may cover the third seed layer 131. The third conductive layer 132 may include a metal such as copper. The third conductive layer 132 and the third seed layer 131 may be patterned to form the third redistribution pattern 130. Each third redistribution pattern 130 may include a patterned third seed layer 131 and a patterned third conductive layer 132.

[0057] Each third redistribution pattern 130 may include a third via portion 130V and a third line portion 130W. As Figure 1N shown, the third via portion 130V may be disposed in the fourth opening 149. The third redistribution pattern 130 may have an angle θ40 in the range of about 105° to about 135° between the bottom surface and the sidewall of the third via portion 130V. The third via portion 130V may contact the top surface of the second redistribution pattern 120. The third line portion 130W may be disposed on the top surface of the fourth dielectric layer 104 and may be connected to the third via portion 130V.

[0058] A fifth dielectric layer 105 may be formed on the fourth dielectric layer 104 and may cover the top surface of the fourth dielectric layer 104 and the third redistribution pattern 130. The fifth dielectric layer 105 may contact the top surface of the fourth dielectric layer 104 and the top surface and sides of the third redistribution pattern 130. The fifth dielectric layer 105 may include a photosensitive polymer.

[0059] A conductive pad 140 may be formed on the third redistribution pattern 130. Each conductive pad 140 may contact the top surface of a corresponding third redistribution pattern 130. The conductive pad 140 may include a metal such as copper or aluminum. The conductive pad 140 may be connected to a corresponding under-bump pattern 150 through the first redistribution pattern 110, the second redistribution pattern 120, and the third redistribution pattern 130. At least one of the conductive pads 140 may not be vertically aligned with the under-bump pattern 150 to which the at least one conductive pad 140 is connected. The term "vertically" may mean "perpendicular to the bottom surface 101b of the first dielectric layer 101". The fifth dielectric layer 105 may expose the top surface of the conductive pad 140. In some embodiments, the top surface of the fifth dielectric layer 105 may be coplanar with the top surface of the conductive pad 140. Different from the illustration, the bottom surface of the conductive pad 140 may be on the top surface of the fifth dielectric layer 105.

[0060] The redistribution substrate 100 may be manufactured by the above process. The redistribution substrate 100 may be a redistribution layer. The redistribution substrate 100 may include an under-bump pattern 150; a first dielectric layer 101, a second dielectric layer 102, a third dielectric layer 103, a fourth dielectric layer 104, and a fifth dielectric layer 105; a first redistribution pattern 110, a second redistribution pattern 120, and a third redistribution pattern 130; and conductive pads 140. The number of the dielectric layers 101, 102, 103, 104, and 105 and the number of the redistribution patterns 110, 120, and 130 are not limited to the shown numbers, but may be variously changed. One or more of the third dielectric layer 103, the fourth dielectric layer 104, and the fifth dielectric layer 105 may be referred to as upper dielectric layers.

[0061] Referring to Figure 1O and Figure 1P, a semiconductor chip 200 may be disposed on the redistribution substrate 100, and chip pads 205 of the semiconductor chip 200 face the redistribution substrate 100. A first connector 251 may be formed between a corresponding conductive pad 140 and a corresponding chip pad 205 and electrically connected to the corresponding conductive pad 140 and the corresponding chip pad 205. Each first connector 251 may include one or more of solder balls, pillars, and bumps. The first connector 251 may include a conductive material such as metal. For example, the first connector 251 may include solder. The semiconductor chip 200 may be electrically connected to the redistribution substrate 100 through the first connector 251. In this specification, the phrase "electrically connected to the redistribution substrate 100" may mean "electrically connected to one or more of the first redistribution pattern 110, the second redistribution pattern 120, and the third redistribution pattern 130". The phrase "coupled to the chip pad 205" may mean "coupled to the semiconductor chip 200" or "coupled to the integrated circuit in the semiconductor chip 200".

[0062] As Figure 1O shown, a molding layer 300 may be formed on the redistribution substrate 100 and may cover the semiconductor chip 200. The molding layer 300 may cover the uppermost layer among the dielectric layers 101, 102, 103, 104, and 105. The uppermost dielectric layer may be the fifth dielectric layer 105. The molding layer 300 may also extend toward the gap between the redistribution substrate 100 and the semiconductor chip 200 and may encapsulate the first connector 251. The molding layer 300 may include a dielectric polymer, such as an epoxy molding compound. For example, an under-fill layer (not shown) may be further formed in the gap between the redistribution substrate 100 and the semiconductor chip 200. Thereafter, the carrier substrate 900 and the release layer 910 may be removed to expose the lower seed layer 151.

[0063] As Figure 1P shown, the lower seed layer 151 may be removed to expose the bottom surface 101b of the first dielectric layer 101 and the bottom surface 150b of the under-bump pattern 150. The removal of the lower seed layer 151 may be performed by, for example, an etching process. The first dielectric layer 101 may expose the bottom surface 150b of the under-bump pattern 150. The bottom surface 150b of the under-bump pattern 150 may be coplanar with the bottom surface 101b of the first dielectric layer 101. For example, the bottom surface 150b of the under-bump pattern 150 may be located at a height substantially the same as the height of the bottom surface 101b of the first dielectric layer 101.

[0064] Referring to Figure 1Q and Figure 1R, external terminals 400 can be formed on the bottom surface of the redistribution substrate 100. The external terminals 400 can be disposed on the exposed bottom surface 150b of the under-bump pattern 150 and can be electrically connected to the under-bump pattern 150. The external terminals 400 can be coupled to at least one of the chip pads 205 through the under-bump pattern 150 and the redistribution patterns 110, 120, and 130. The external terminals 400 may not be vertically aligned with the at least one chip pad 205. As Figure 1Q shown, a plurality of external terminals 400 can be provided, and when observed in a plan view, at least one of the plurality of external terminals 400 can overlap with the molding layer 300. Each external terminal 400 can include one or more of solder balls, bumps, and pillars. The external terminals 400 can include solder. The solder can include, for example, tin, bismuth, lead, silver, or an alloy thereof.

[0065] When the thickness T1 of the under-bump pattern 150 is less than 2.5 times the thickness T2 of the first line portion 110W of the first redistribution pattern 110, the thickness T1 of the under-bump pattern 150 can be significantly reduced when the semiconductor package 10 operates continuously. When the thickness T1 of the under-bump pattern 150 is greater than 10 times the thickness T2 of the first line portion 110W of the first redistribution pattern 110, it may be difficult for the redistribution substrate 100 to have a compact size. According to some embodiments, the thickness T1 of the under-bump pattern 150 can be about 2.5 times to 10 times the thickness T2 of the first line portion 110W of the first redistribution pattern 110. Thus, even when the semiconductor package 10 operates continuously, the thickness T1 of the under-bump pattern 150 can satisfy the required range. As a result, the redistribution substrate 100 can increase durability and reliability. The redistribution substrate 100 can become compact in size. The thickness T1 of the under-bump pattern 150 can be greater than the thickness T3 of the second line portion 120W and the thickness T4 of the third line portion 130W. The thickness T1 of the under-bump pattern 150 can be about 2.5 to 10 times the thickness T3 of the second line portion 120W and about 2.5 to 10 times the thickness T4 of the third line portion 130W. The thickness T3 of the second line portion 120W and the thickness T4 of the third line portion 130W can be measured in a direction perpendicular to the top surface of the substrate or the bottom surface 101b of the first dielectric layer 101.

[0066] Through the above process, the semiconductor package 10 can be finally manufactured. The semiconductor package 10 can be a fan-out semiconductor package.

[0067] Figure 2A 、 Figure 2C and Figure 2E illustrates a cross-sectional view showing a method of manufacturing a semiconductor package according to some exemplary embodiments. Figure 2B illustrates showing Figure 2AAn enlarged view of Part I. Figure 2D illustrates an enlarged view of Figure 2C Part I. Figure 2F illustrates an enlarged view of Figure 2E Part I. Repeated descriptions will be omitted hereinafter.

[0068] Returning to reference Figure 1M and Figure 1N , a lower seed layer 151 and a redistribution substrate 100 may be formed on a carrier substrate 900.

[0069] Referring to Figure 2A and Figure 2B , a semiconductor chip 200 may be mounted on the redistribution substrate 100, and then a molding layer 300 may be formed on the redistribution substrate 100. Thereafter, the carrier substrate 900 and the release layer 910 may be removed to expose the bottom surface of the lower seed layer 151.

[0070] Referring to Figure 2C and Figure 2D , a lower mask pattern 920 may be formed on the bottom surface of the lower seed layer 151. The lower mask pattern 920 may have a lower opening 929 exposing the lower seed layer 151. The lower mask pattern 920 may be formed by coating, for example, a resist material.

[0071] A first lower under-bump pattern 152 may be formed in the lower opening 929 and may cover the bottom surface of the lower seed layer 151. The first lower under-bump pattern 152 may contact the bottom surface of the lower seed layer 151 and may completely cover the exposed bottom surface of the lower seed layer 151. The first lower under-bump pattern 152 may be formed by performing an electroplating process using the lower seed layer 151 as an electrode. The first lower under-bump pattern 152 may include a material different from that of the under-bump pattern 150. The first lower under-bump pattern 152 may include nickel. The first lower under-bump pattern 152 may be used as a barrier layer to prevent diffusion of the material (e.g., copper) included in the under-bump pattern 150.

[0072] The second lower bump under-pattern 153 may be formed in the lower opening 929 and may cover the bottom surface of the first lower bump under-pattern 152. The second lower bump under-pattern 153 may contact the bottom surface of the first lower bump under-pattern 152. The second lower bump under-pattern 153 may include a material different from the materials of the first lower bump under-pattern 152 and the bump under-pattern 150. Gold (Au) may have wettability with respect to solder. The second lower bump under-pattern 153 may include gold and may thus be used as a wetting layer. Each of the first lower bump under-pattern 152 and the second lower bump under-pattern 153 may be located in the lower opening 929 and may not extend onto the bottom surface of the lower mask pattern 920. Thereafter, the lower mask pattern 920 may be removed to expose the bottom surface of the lower seed layer 151.

[0073] Referring Figure 2E and Figure 2F , the lower seed layer 151 may be patterned to form seed patterns 151S. The patterning of the lower seed layer 151 may include performing an etching process on the exposed lower seed layer 151. The etching process may continue until the bottom surface 101b of the first dielectric layer 101 is exposed. The seed patterns 151S may be electrically separated from each other. The width of each seed pattern 151S may be the same as the width W1 of the bump under-pattern 150 at the bottom surface 150b. Each seed pattern 151S may have sidewalls aligned with the sidewalls of the first lower bump under-pattern 152 and the second lower bump under-pattern 153. The widths of the first lower bump under-pattern 152 and the second lower bump under-pattern 153 may be the same as the width W1 of the bump under-pattern 150 at the bottom surface 150b.

[0074] An external terminal 400 may be formed on the bottom surface of the second lower bump under-pattern 153. The second lower bump under-pattern 153 may be used as a wetting layer. For example, the second lower bump under-pattern 153 may reliably attach the external terminal 400 to the first lower bump under-pattern 152.

[0075] Through the above process, the semiconductor package 11 may be finally manufactured. The semiconductor package 11 may include stacked seed patterns 151S, a first lower bump under-pattern 152, and a second lower bump under-pattern 153. The seed patterns 151S, the first lower bump under-pattern 152, and the second lower bump under-pattern 153 may be interposed between the bump under-pattern 150 and the external terminal 400. Alternatively, one of the first lower bump under-pattern 152 and the second lower bump under-pattern 153 may not be formed.

[0076] The formation of the seed patterns 151S, the first lower bump under-pattern 152, and the second lower bump under-pattern 153 is not limited to Figures 2A to 2FRather, various changes can be made as described in

[0077] In some of the drawings, for the convenience of drawing, the first redistribution pattern 110, the second redistribution pattern 120, and the third redistribution pattern 130 are illustrated without distinguishing the seed layers 111, 121, and 131 from the conductive layers 112, 122, and 132. For example, the first redistribution pattern 110 is illustrated without distinguishing the first seed layer 111 from the first conductive layer 112. However, the inventive concept is not limited thereto.

[0078] Figure 3A and Figure 3B A cross-sectional view showing a method of manufacturing a semiconductor package according to some example embodiments is illustrated. Repeated descriptions will be omitted below.

[0079] Referring to Figure 3A , a redistribution substrate 100 can be formed on a carrier substrate 900. The redistribution substrate 100 may include an under-bump pattern 150; a first dielectric layer 101, a second dielectric layer 102, a third dielectric layer 103, a fourth dielectric layer 104, and a fifth dielectric layer 105; a first redistribution pattern 110, a second redistribution pattern 120, and a third redistribution pattern 130; and conductive pads 140. A lower seed layer 151 can be formed between the carrier substrate 900 and the first dielectric layer 101 and between the carrier substrate 900 and the under-bump pattern 150. For example, the lower seed layer 151 can be formed between the release layer 910 and the redistribution substrate 100. The formation of the lower seed layer 151 and the redistribution substrate 100 can be substantially the same as that discussed above in Figures 1A to 1N . The difference is that the redistribution substrate 100 can be formed at a panel or wafer level.

[0080] A semiconductor chip 200 can be disposed on the redistribution substrate 100. In this case, a plurality of semiconductor chips 200 can be provided, and the plurality of semiconductor chips 200 can be spaced laterally from each other. A first connector 251 can be formed between a corresponding conductive pad 140 and a corresponding chip pad 205. A molding layer 300 can be disposed on the top surface of the redistribution substrate 100, so that the semiconductor chip 200 can be covered with the molding layer 300. For example, the molding layer 300 can be formed between adjacent semiconductor chips 200. Thereafter, the carrier substrate 900 and the release layer 910 can be removed to expose the lower seed layer 151. The lower seed layer 151 can be etched to expose the bottom surface of the first dielectric layer 101 and the bottom surface of the under-bump pattern 150.

[0081] Referring to Figure 3B, the external terminal 400 may be formed on the exposed bottom surface of the under-bump pattern 150 and may be coupled to the under-bump pattern 150. The molding layer 300 and the redistribution substrate 100 may be cut along the dotted line to separate the plurality of semiconductor packages 10 from each other. In the present specification, the semiconductor package 10 may be manufactured at the chip, panel, or wafer level.

[0082] For simplicity, a single semiconductor package will be discussed below, but the method of manufacturing a semiconductor package is not limited to chip-level manufacturing.

[0083] Figure 4 A cross-sectional view showing a semiconductor package according to some example embodiments is illustrated. Repeated descriptions will be omitted below.

[0084] Referring to Figure 4 , the semiconductor package 12 may include a redistribution substrate 100 and a semiconductor chip 200. A first connector 251 may be interposed between the conductive pad 140 and the chip pad 205 of the semiconductor chip 200. An underfill pattern 260 may be disposed in the gap between the redistribution substrate 100 and the semiconductor chip 200 to encapsulate the first connector 251. The underfill pattern 260 may include a dielectric polymer, such as an epoxy-based polymer. The external terminal 400 may be disposed on the bottom surface of the under-bump pattern 150.

[0085] The formation of the redistribution substrate 100, the mounting of the semiconductor chip 200, and the formation of the external terminal 400 may be substantially the same as those discussed above in Figures 1A to 1R . Different from Figure 1O and Figure 1P discussed, in some embodiments, the formation of the molding layer 300 may be skipped. The width W20 of the semiconductor chip 200 may be substantially the same as the width W10 of the redistribution substrate 100. The semiconductor package 12 may be a fan-in semiconductor package.

[0086] Figure 5 A cross-sectional view showing a semiconductor package according to some example embodiments is illustrated. When explaining the following embodiments, reference will be made to Figure 1R , and repeated discussions will be omitted.

[0087] Referring to Figure 5 , the semiconductor package 13 may include a redistribution substrate 100, an external terminal 400, a first semiconductor chip 201, a second semiconductor chip 202, and a housing 800. The redistribution substrate 100 and the external terminal 400 may be substantially the same as those discussed above. The semiconductor package 13 may be a system-in-package (SIP).

[0088] The first semiconductor chip 201 can be mounted on the top surface of the redistribution substrate 100. For example, the first connector 251 can be formed between the chip pad 205' of the first semiconductor chip 201 and the corresponding conductive pad 140. The first semiconductor chip 201 and the first connector 251 can be respectively the same as the semiconductor chip 200 and the first connector 251 discussed in Figure 1Q and Figure 1R substantially the same.

[0089] On the top surface of the redistribution substrate 100, the second semiconductor chip 202 can be arranged to be spaced apart from the first semiconductor chip 201. The second semiconductor chip 202 can be a different type from the first semiconductor chip 201. For example, the first semiconductor chip 201 can be one of a logic chip, a memory chip, a system-on-chip (SOC), an application processor (AP) chip, and a microelectromechanical systems (MEMS) chip, while the second semiconductor chip 202 can be another one of a logic chip, a memory chip, a system-on-chip (SOC), an application processor (AP) chip, and a microelectromechanical systems (MEMS) chip. The second connector 252 can be interposed between the chip pad 206 of the second semiconductor chip 202 and the corresponding conductive pad 140, and can be coupled to the second semiconductor chip 202 and the redistribution substrate 100. The second connector 252 can include one or more of solder balls, bumps, and pillars. The second connector 252 can include a conductive material.

[0090] The first underfill pattern 261 can be disposed in the gap between the redistribution substrate 100 and the first semiconductor chip 201 to encapsulate the first connector 251. The second underfill pattern 262 can be disposed in the gap between the redistribution substrate 100 and the second semiconductor chip 202 to encapsulate the second connector 252. The first underfill pattern 261 and the second underfill pattern 262 can include a dielectric polymer, such as an epoxy-based polymer.

[0091] The housing 800 may be disposed on the redistribution substrate 100. The housing 800 may be arranged to be spaced apart from the first semiconductor chip 201 and the second semiconductor chip 202. The cavities 890 may be provided between the first semiconductor chip 201 and the housing 800 and between the second semiconductor chip 202 and the housing 800. A gas such as air may occupy the cavities 890. The housing 800 may protect the first semiconductor chip 201 and the second semiconductor chip 202 from the external environment. For example, the housing 800 may prevent the introduction of foreign objects or may absorb physical shocks. The housing 800 may include a material with high thermal conductivity and may be used as a heat sink or radiator. For example, when the semiconductor package 13 operates, the housing 800 may quickly discharge the heat generated from one or more of the redistribution substrate 100, the first semiconductor chip 201, and the second semiconductor chip 202 to the outside. The housing 800 may include a conductive material such as metal. In this case, the housing 800 may have conductivity and may be used as an electromagnetic shielding layer. For example, the housing 800 may shield the electromagnetic interference (EMI) of the first semiconductor chip 201 and the second semiconductor chip 202. The housing 800 may be electrically grounded through the redistribution substrate 100 and may prevent the first semiconductor chip 201 and / or the second semiconductor chip 202 from being electrically damaged, including the electrical damage caused by electrostatic discharge (ESD). Alternatively, the housing 800 may include a dielectric material. For example, the housing 800 may include a dielectric polymer.

[0092] The formation of the redistribution substrate 100, the mounting of the first semiconductor chip 201, and the formation of the external terminals 400 may be substantially the same as those discussed above in Figures 1A to 1R . Different from that discussed in Figure 1O and Figure 1P , the formation of the molding layer 300 may be skipped, and the second semiconductor chip 202 and the housing 800 may be further disposed on the redistribution substrate 100.

[0093] Although not shown, a third semiconductor chip may be further mounted on the redistribution substrate 100.

[0094] Figure 6A A plan view showing a semiconductor package according to some example embodiments is illustrated. Figure 6B A cross-sectional view taken along the line Figure 6A II-III is illustrated. Figure 6C An enlarged view of the IV portion of Figure 6B is illustrated.

[0095] Referring to Figure 6A , Figure 6B and Figure 6C, the semiconductor package 14 may include a redistribution substrate 100, a semiconductor chip 200, a connection substrate 500, and a molding layer 300. The manufacturing of the redistribution substrate 100, the mounting of the semiconductor chip 200, the formation of the molding layer 300, and the formation of the external terminals 400 may be substantially the same as those discussed above in Figures 1A to 1R . The difference is that when observed in a plan view, the semiconductor chip 200 may be disposed on the central region of the redistribution substrate 100, and the connection substrate 500 may also be disposed before the formation of the molding layer 300 discussed in Figure 1O and 1P .

[0096] The connection substrate 500 may be disposed on the redistribution substrate 100. The arrangement of the connection substrate 500 may be performed before or after the arrangement of the semiconductor chip 200. The connection substrate 500 may have holes 590 therethrough. For example, the holes 590 may be formed to penetrate the top and bottom surfaces of a printed circuit board (PCB), and the printed circuit board having the holes 590 may be used as the connection substrate 500. When observed in a plan view, the holes 590 may be formed on the central region of the redistribution substrate 100. The semiconductor chip 200 may be disposed in the holes 590 of the connection substrate 500. The connection substrate 500 may include a base layer 510 and a conductive structure 520. The base layer 510 may include a plurality of stacked base layers 510. The base layer 510 may include a dielectric material. For example, the base layer 510 may include a carbon-based material, a ceramic, or a polymer. The holes 590 may penetrate the base layer 510. The conductive structure 520 may be disposed in the base layer 510. As Figure 6C shown, the conductive structure 520 may include a first pad 521, conductive traces 523, vias 524, and a second pad 522. The first pad 521 may be exposed on the bottom surface 500b of the connection substrate 500 and may be coupled to one of the vias 524. The conductive traces 523 may be interposed between the base layers 510. The vias 524 may penetrate the base layer 510 to connect to the conductive traces 523. The second pad 522 may be exposed on the top surface 500a of the connection substrate 500 and may be coupled to one of the vias 524. The second pad 522 may be electrically connected to the first pad 521 through the vias 524 and the conductive traces 523. The second pad 522 may not be vertically aligned with the first pad 521. For example, the second pad 522 may be vertically offset from the first pad 521. The number of the second pads 522 may be different from the number of the first pads 521. The conductive structure 520 may include a metal. The conductive structure 520 may include, for example, one or more of copper, aluminum, gold, lead, stainless steel, silver, iron, and their alloys.

[0097] As Figure 6BAs shown, the third connector 253 can be interposed between the first pad 521 and the corresponding conductive pad 140 and coupled to the first pad 521 and the corresponding conductive pad 140. The conductive structure 520 can be electrically connected to the redistribution substrate 100 through the third connector 253. The third connector 253 can include a conductive material. The third connector 253 can include one or more of solder balls, bumps, and pillars. The third underfill pattern 263 can be disposed in the gap between the redistribution substrate 100 and the connection substrate 500 to encapsulate the third connector 253.

[0098] Each first connector 251 can be interposed between one of the chip pads 205 and the corresponding conductive pad 140. The first underfill pattern 261 can encapsulate the first connector 251. The semiconductor chip 200 can be electrically connected to the conductive structure 520 through one or more of the redistribution patterns 110, 120, and 130.

[0099] The molding layer 300 can be disposed on the semiconductor chip 200 and the connection substrate 500. For example, the molding layer 300 can cover the top surfaces of the semiconductor chip 200 and the connection substrate 500. The molding layer 300 can extend into the gap between the semiconductor chip 200 and the connection substrate 500 and fill the gap. The molding layer 300 can include a dielectric polymer, such as an epoxy-based polymer. In some embodiments, an adhesive dielectric film can be attached to the top surface of the connection substrate 500, the top surface of the semiconductor chip 200, and the sidewalls of the semiconductor chip 200 to form the molding layer 300. For example, an Ajinomoto build-up film (ABF) can be used as the adhesive dielectric film. In some embodiments, the first underfill pattern 261 can not be formed, and the molding layer 300 can also extend into the gap between the redistribution substrate 100 and the semiconductor chip 200. In some embodiments, the third underfill pattern 263 can not be formed, and the molding layer 300 can also extend into the gap between the redistribution substrate 100 and the connection substrate 500. Upper holes 390 can be provided in the molding layer 300 to expose the second pads 522 of the conductive structure 520. In some embodiments, the width of the upper holes 390 can gradually decrease as it approaches the second pads 522. For example, the width of the upper holes 390 can be wider near the upper surface of the molding layer 300 and narrower near the second pads 522.

[0100] A plurality of external terminals 400 can be correspondingly disposed on the plurality of under bump patterns 150. One or more external terminals 400 can be electrically connected to the semiconductor chip 200 through the redistribution patterns 110, 120, and 130, and another one or more external terminals 400 can be electrically connected to the conductive structure 520 through the redistribution patterns 110, 120, and 130.

[0101] Figure 6D illustrates a cross-section taken along line II-III Figure 6A showing a semiconductor package according to some example embodiments. Repeated descriptions will be omitted hereinafter.

[0102] Referring to Figure 6A and Figure 6D , the semiconductor package 15 may include a redistribution substrate 100, external terminals 400, semiconductor chips 200, a connection substrate 500, and a molding layer 300, and may further include an upper redistribution layer 600. According to some embodiments, each upper hole 390 may be provided with a conductor 350 filling the upper hole 390. The conductor 350 may include, for example, metal. In some embodiments, the width of the conductor 350 may gradually decrease as it approaches the second pad 522. For example, the width of the conductor 350 may be wider near the upper surface of the molding layer 300 and narrower near the second pad 522.

[0103] The upper redistribution layer 600 may be disposed on the top surface of the molding layer 300. The upper redistribution layer 600 may include a first upper dielectric layer 601, a second upper dielectric layer 602, a third upper dielectric layer 603, a first upper redistribution pattern 610, a second upper redistribution pattern 620, and an upper conductive pad 640. The first upper dielectric layer 601 may be disposed on the molding layer 300. The first upper dielectric layer 601 may include a photosensitive polymer. The first upper dielectric layer 601 may have a first upper opening 619 exposing the conductor 350. The first upper redistribution pattern 610 may be disposed on the first upper dielectric layer 601 and in the first upper opening 619. The first upper redistribution pattern 610 may include a metal such as copper. The first upper redistribution pattern 610 may be coupled to the conductor 350. The second upper dielectric layer 602 may be disposed on the first upper dielectric layer 601. The second upper dielectric layer 602 may include a photosensitive polymer. The second upper dielectric layer 602 may have a second upper opening 629 exposing the first upper redistribution pattern 610. The second upper redistribution pattern 620 may be disposed on the top surface of the second upper dielectric layer 602 and in the second upper opening 629. The second upper redistribution pattern 620 may be coupled to the first upper redistribution pattern 610. The second upper redistribution pattern 620 may include a metal such as copper. The upper conductive pad 640 may be formed on the top surface of the second upper redistribution pattern 620 and may be coupled to the second upper redistribution pattern 620. The upper conductive pad 640 may be coupled to the conductive structure 520 through the first upper redistribution pattern 610, the second upper redistribution pattern 620, and the conductor 350. The upper conductive pad 640 may not be vertically aligned with the conductor 350.

[0104] The third upper dielectric layer 603 may be formed on the second upper dielectric layer 602 and the second upper redistribution pattern 620. The third upper dielectric layer 603 may include a dielectric material. The third upper dielectric layer 603 may expose the top surface of the upper conductive pad 640.

[0105] The fabrication of the redistribution substrate 100, the installation of the semiconductor chip 200, the formation of the molding layer 300, and the formation of the external terminals 400 may be performed by methods substantially the same as those discussed above in Figures 1A to 1R FIG. 6A, Figure 6B and Figure 6C The difference is that, in some embodiments, after forming the connection substrate 500 and the molding layer 300 in the steps shown in Figure 6B and Figure 6C upper vias 390 and an upper redistribution layer 600 may also be formed.

[0106] Figure 6E FIG. shows a cross-section taken along line II-III of Figure 6A illustrating a semiconductor package according to some example embodiments.

[0107] Referring to Figure 6A and Figure 6E the semiconductor package 16 may include a first semiconductor package 14' and a second semiconductor package 20. The semiconductor package 14 discussed in Figures 6A to 6C may be used as the first semiconductor package 14'. For example, the first semiconductor package 14' may include a redistribution substrate 100, a semiconductor chip 200, a connection substrate 500, and a molding layer 300.

[0108] The second semiconductor package 20 may be disposed on the first semiconductor package 14'. The second semiconductor package 20 may include a package substrate 710, an upper semiconductor chip 720, and an upper molding layer 730. The package substrate 710 may be a printed circuit board. Metal pads 705 may be disposed on the bottom surface of the package substrate 710. Alternatively, the package substrate 710 may be a redistribution layer. For example, the second semiconductor package 20 may be a semiconductor package 10 fabricated as shown above in Figures 1A to 1R In this case, the metal pads 705 may have substantially the same shape and arrangement as the under-bump pattern 150 discussed above in Figures 1A to 1R FIG.

[0109] The upper semiconductor chip 720 may be disposed on the package substrate 710. The upper semiconductor chip 720 may include an integrated circuit, and the integrated circuit may include a memory circuit, a logic circuit, or a combination thereof. The upper semiconductor chip 720 may be a different type from the semiconductor chip 200. The upper semiconductor chip 720 may be electrically connected to the metal pad 705 through the connection line 715 in the package substrate 710. For example, the connection line 715 may be connected to the upper chip pad 725 of the upper semiconductor chip 720 to connect the upper semiconductor chip 720 to the metal pad 705. In Figure 6E FIG. Figure 6E , the connection line 715 is schematically shown, and the shape and arrangement of the connection line 715 may be changed differently. An upper molding layer 730 covering the upper semiconductor chip 720 may be disposed on the package substrate 710. The upper molding layer 730 may include a dielectric polymer, such as an epoxy-based polymer.

[0110] Connection terminals 750 may be disposed in each of the upper holes 390 of the molding layer 300. The second pad 522 and the metal pad 705 may be electrically connected to each other through the connection terminals 750 interposed between the second pad 522 and the metal pad 705. In this case, the second semiconductor package 20 may be electrically connected to the semiconductor chip 200 and the external terminals 400 through the connection terminals 750. The electrical connection of the second semiconductor package 20 may include an electrical connection to the integrated circuit in the upper semiconductor chip 720. According to some embodiments, since the connection substrate 500 is provided, the connection terminals 750 may be freely arranged. For example, the number and arrangement of the connection terminals 750 may not be limited by the number and arrangement of the first pads 521. As a result, the connection line 715 may be freely designed in the package substrate 710, and the integrated circuit may also be freely designed in the upper semiconductor chip 720.

[0111] In some embodiments, Figure 6D the semiconductor package 15 discussed in FIG. Figure 6D may be used as the first semiconductor package 14'. For example, the first semiconductor package 14' may include a redistribution substrate 100, a semiconductor chip 200, a connection substrate 500, and a molding layer 300, and may further include an upper redistribution layer 600. In this case, the connection terminals 750 may be interposed between the upper conductive pads 640 and the metal pad 705. Since the upper redistribution layer 600 is provided, the connection terminals 750 may be freely arranged.

[0112] Figure 7A FIG. Figure 7A illustrates a cross-sectional view of a semiconductor package according to some example embodiments. Repeated descriptions will be omitted below.

[0113] Referring to Figure 7A, the semiconductor package 17 may include a redistribution substrate 100, a semiconductor chip 200, external terminals 400, and a molding layer 300, and may further include a conductive structure 520' and an upper redistribution layer 600.

[0114] may not be provided in Figures 6A to 6E the connection substrate 500 discussed in. Instead of the connection substrate 500, a conductive structure 520' in which metal pillars are provided on the redistribution substrate 100 may be formed. For example, the conductive structure 520' may include metal pillars. The conductive structure 520' may be spaced apart from the semiconductor chip 200. The conductive structure 520' may be electrically connected to the redistribution substrate 100.

[0115] A molding layer 300 covering the semiconductor chip 200 may be provided on the redistribution substrate 100. The molding layer 300 may cover the sidewalls of the conductive structure 520', but may expose the top surface of the conductive structure 520'.

[0116] The upper redistribution layer 600 may be substantially the same as Figure 6D the upper redistribution layer 600 of. For example, the upper redistribution layer 600 may include a first upper dielectric layer 601, a second upper dielectric layer 602, and a third upper dielectric layer 603, a first upper redistribution pattern 610 and a second upper redistribution pattern 620, and upper conductive pads 640. The difference is that a first upper opening 619 in the first upper dielectric layer 611 may expose the top surface of the conductive structure 520'. The first upper redistribution pattern 610 may be provided in the first upper opening 619 and on the first upper dielectric layer 611. The first upper redistribution pattern 610 may contact the top surface of the conductive structure 520' and may have an electrical connection with the conductive structure 520'.

[0117] The manufacture of the redistribution substrate 100, the installation of the semiconductor chip 200, the formation of the molding layer 300, and the formation of the external terminals 400 may be performed by substantially the same methods as those discussed above in Figures 1A to 1R . The difference is that the conductive structure 520' and the upper redistribution layer 600 may be further formed in Figure 1O and the steps shown in FIG. 1P. After forming the conductive structure 520' and the upper redistribution layer 600, the external terminals 400 may be formed.

[0118] In some embodiments, the semiconductor package 17 may not include the upper redistribution layer 600.

[0119] Figure 7B The figure shows a cross-sectional view of a semiconductor package according to some example embodiments.

[0120] Repeated descriptions will be omitted below.

[0121] Reference Figure 7B ,the semiconductor package 18 may include a first semiconductor package 17' and a second semiconductor package 20. Figure 7A The semiconductor package 17 discussed in

[0122] may be used as the first semiconductor package 17'. For example, the first semiconductor package 17' may include a redistribution substrate 100, a semiconductor chip 200, a molding layer 300, a conductive structure 520', and an upper redistribution layer 600. Figure 6E The second semiconductor package 20 may be disposed on the first semiconductor package 17'. The second semiconductor package 20 may be substantially the same as the second semiconductor package 20 discussed in

[0123] For example, the second semiconductor package 20 may include a package substrate 710, an upper semiconductor chip 720, and an upper molding layer 730. The upper conductive pad 640 and the metal pad 705 may be electrically connected to each other through a connection terminal 750 interposed between the upper conductive pad 640 and the metal pad 705. The upper semiconductor chip 720 may be electrically connected to the redistribution substrate 100 through the connection terminal 750, the upper redistribution patterns 610 and 620, and the conductive structure 520'. Since the upper redistribution layer 600 is provided, the connection terminals 750 can be freely arranged. For example, a plurality of connection terminals 750 may be provided, and when viewed in a plan view, at least one of the plurality of connection terminals 750 may overlap with the semiconductor chip 200.

[0124] In some embodiments, the first semiconductor package 17' may not include the upper redistribution layer 600. In this case, the connection terminals 750 may be aligned with the conductive structure 520' and the metal pad 705 and coupled to the conductive structure 520' and the metal pad 705.

[0125] In the explanation of Figure 3A , Figure 3B , Figure 4 , Figure 5 , Figures 6A to 6E , Figure 7A and Figure 7B , although not shown, an under bump pattern 150 and an external terminal 400 may also have one or more of the first lower under bump patterns 152 and the second lower under bump patterns 153 discussed in Figures 2A to 2F disposed therebetween.

[0126] According to the inventive concept, the under-bump pattern may have a relatively large thickness, so that the semiconductor package can improve reliability and durability. Since the under-bump pattern is formed in the first opening defined by the first dielectric layer, the formation and removal of a resist pattern can be skipped. In addition, the manufacturing process of the semiconductor package can also be simplified. The first dielectric layer may have a flat top surface. Accordingly, the line portions of the redistribution pattern may be located at the same height or a similar height. The redistribution substrate can improve reliability.

[0127] The foregoing detailed description of the inventive concept should not be construed as being limited to the embodiments set forth herein. The inventive concept is intended to cover various combinations, modifications, and variations of the present invention without departing from the spirit and scope of the inventive concept.

Claims

1. A semiconductor package, comprising: a redistribution substrate; and a semiconductor chip on a top surface of the redistribution substrate, wherein the redistribution substrate includes: a under-bump pattern; a lower dielectric layer covering sidewalls of the under-bump pattern; and a first redistribution pattern on the lower dielectric layer, wherein the first redistribution pattern includes: a first conductive layer on a top surface of the lower dielectric layer and including a first tapered via portion and a first line portion, the first line portion extending in a horizontal direction and connected to the first tapered via portion; and a first seed layer between the top surface of the lower dielectric layer and the first conductive layer, the first seed layer covering a bottom surface and side surfaces of the first tapered via portion and a bottom surface of the first line portion, wherein a bottom surface of the first seed layer covering the first tapered via portion directly contacts a top surface of the under-bump pattern, wherein the top surface of the under-bump pattern is at the same vertical height as the top surface of the lower dielectric layer, or the top surface of the under-bump pattern is at a height lower than the vertical height of the top surface of the lower dielectric layer, wherein a width of the under-bump pattern at the top surface is greater than a width of the under-bump pattern at the bottom surface, wherein the under-bump pattern tapers from the top surface of the under-bump pattern to the bottom surface of the under-bump pattern to form a tapered shape, side surfaces of the tapered shape linearly extending from the top surface of the under-bump pattern to the bottom surface of the under-bump pattern, and wherein a thickness of the under-bump pattern is greater than a thickness of the first line portion.

2. The semiconductor package according to claim 1, wherein a width of the first tapered via portion is less than a width of the under-bump pattern at the top surface.

3. The semiconductor package according to claim 1, wherein the thickness of the under-bump pattern is 2.5 times to 10 times a thickness of the first line portion.

4. The semiconductor package according to claim 1, wherein the first line portion includes a plurality of first line portions spaced apart from each other, and wherein a maximum distance between a bottom surface of the lower dielectric layer and a bottom surface of the first line portion is 100% to 130% of a minimum distance between the bottom surface of the lower dielectric layer and the bottom surface of the first line portion.

5. The semiconductor package according to claim 1, further comprising: an upper dielectric layer on the lower dielectric layer; and a second redistribution pattern on a top surface of the upper dielectric layer, the second redistribution pattern including a second line portion, wherein a thickness of the under-bump pattern is greater than a thickness of the second line portion.

6. The semiconductor package according to claim 1, further comprising external terminals on a bottom surface of the under-bump pattern.

7. The semiconductor package according to claim 6, further comprising: a lower under-bump pattern between the under-bump pattern and the external terminals; and a seed pattern between the lower under-bump pattern and the under-bump pattern, wherein the lower under-bump pattern includes a material different from a material of the under-bump pattern.

8. The semiconductor package according to claim 1, further comprising: a connection substrate on the redistribution substrate, the connection substrate including a plurality of base layers and a conductive structure, wherein the connection substrate has holes, and wherein the semiconductor chip is disposed in the holes.

9. The semiconductor package according to claim 1, further comprising: a conductive structure on the top surface of the redistribution substrate, the conductive structure being spaced apart from the semiconductor chip; and a molding layer on the top surface of the redistribution substrate, the molding layer encapsulating the semiconductor chip and the sidewalls of the conductive structure.

10. The semiconductor package according to claim 1, further comprising: solder terminals, wherein the bottom surface of the under-bump pattern is coplanar with the bottom surface of the lower dielectric layer, and wherein the solder terminals contact the bottom surface of the under-bump pattern.

11. A semiconductor package, comprising: a redistribution substrate; a semiconductor chip on the top surface of the redistribution substrate; and solder terminals on the bottom surface of the redistribution substrate, wherein the redistribution substrate includes: an under-bump pattern; a dielectric layer covering the sidewalls of the under-bump pattern; and a redistribution pattern on the under-bump pattern and on the dielectric layer, the redistribution pattern being coupled to the under-bump pattern, wherein the solder terminals are on the bottom surface of the under-bump pattern, wherein the redistribution pattern includes: a conductive layer including a tapered via portion and a line portion, the line portion extending in a horizontal direction and connected to the tapered via portion; and a seed layer covering the bottom surface and the side surfaces of the tapered via portion and the bottom surface of the line portion, the seed layer being spaced apart from the top surface of the line portion, wherein the sidewalls of the under-bump pattern are in direct contact with the dielectric layer, wherein the top surface of the under-bump pattern is at the same vertical height as the top surface of the dielectric layer, or the top surface of the under-bump pattern is at a vertical height lower than the vertical height of the top surface of the dielectric layer, wherein the bottom surface of the seed layer covering the tapered via portion is in direct contact with the top surface of the under-bump pattern, wherein the seed layer includes a material different from that of the under-bump pattern, wherein the angle between the sidewalls and the top surface of the under-bump pattern is an acute angle, and wherein the angle between the sidewalls and the bottom surface of the under-bump pattern is in the range of 105° to 135°.

12. The semiconductor package according to claim 11, wherein, the sidewalls of the under-bump pattern linearly extend from the top surface of the under-bump pattern to the bottom surface of the under-bump pattern, wherein the under-bump pattern narrows from the top surface of the under-bump pattern to the bottom surface of the under-bump pattern to form a tapered shape, and wherein the dielectric layer exposes the bottom surface of the under-bump pattern.

13. The semiconductor package according to claim 12, wherein, the bottom surface of the under-bump pattern is coplanar with the bottom surface of the dielectric layer.

14. The semiconductor package according to claim 11, wherein, The width of the tapered via portion is smaller than the width of the under-bump pattern.

15. The semiconductor package according to claim 11, wherein, the bottom surface of the under-bump pattern is coplanar with the bottom surface of the dielectric layer, and wherein the solder terminal contacts the bottom surface of the under-bump pattern.

16. A semiconductor package, comprising: a redistribution substrate; a semiconductor chip on the top surface of the redistribution substrate; and solder terminals on the bottom surface of the redistribution substrate, wherein the redistribution substrate includes: conductive terminal pads; a lower under-bump pattern disposed on the bottom surface of the conductive terminal pads and including a material different from that of the conductive terminal pads; a lower dielectric layer covering the sidewalls of the conductive terminal pads; a line pattern on the lower dielectric layer; and a tapered via between the conductive terminal pads and the line pattern, the tapered via being in direct contact with the top surface of the conductive terminal pads wherein the top surface of the conductive terminal pads is at the same vertical height as the top surface of the lower dielectric layer, or the top surface of the conductive terminal pads is at a vertical height lower than the vertical height of the top surface of the lower dielectric layer, wherein the conductive terminal pads narrow from the top surface to the bottom surface of the conductive terminal pads to form a tapered shape, wherein the thickness of the conductive terminal pads is greater than the thickness of the line pattern, wherein the solder terminals are disposed on the bottom surface of the lower under-bump pattern, wherein the width of the tapered via is smaller than the width of the conductive terminal pads, and wherein the lower under-bump pattern does not extend on the bottom surface of the lower dielectric layer.

17. The semiconductor package according to claim 16, wherein, the angle between the sidewall and the bottom surface of the conductive terminal pads is in the range of 105° to 135°.

18. The semiconductor package according to claim 16, wherein, the thickness of the conductive terminal pads is 2.5 times to 10 times the thickness of the line pattern.

19. The semiconductor package according to claim 16, wherein, the lower dielectric layer includes a stacked first dielectric layer and a second dielectric layer, wherein the tapered via is disposed in the second dielectric layer, and wherein the line pattern is disposed on the top surface of the second dielectric layer and connected to the tapered via.

Images