Semiconductor device having multiple barrier patterns

Abstract

Semiconductor devices are provided. A semiconductor device includes a first active pattern on a first region of a substrate, a pair of first source / drain patterns on the first active pattern, a first channel pattern between the pair of first source / drain patterns, and a gate electrode extending across the first channel pattern. The gate electrode is on an uppermost surface and at least one sidewall of the first channel pattern. The gate electrode includes a first metal pattern including a p-type work function metal, a second metal pattern on the first metal pattern and including an n-type work function metal, a first barrier pattern on the second metal pattern and including an amorphous metal layer including tungsten (W), carbon (C), and nitrogen (N), and a second barrier pattern on the first barrier pattern. The second barrier pattern includes a p-type work function metal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2019-0088504 filed on July 22, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a field effect transistor and a method of manufacturing the same. Background Art

[0004] Semiconductor devices may include integrated circuits that include metal oxide semiconductor field effect transistors (MOSFETs). As the size of semiconductor devices decreases and the design rules of semiconductor devices decrease, MOSFETs have been scaled down. Scaling down MOSFETs may degrade the operating characteristics of semiconductor devices. Therefore, various studies have been conducted to develop methods for manufacturing semiconductor devices with superior performance while overcoming the limitations caused by the high integration of semiconductor devices. Summary of the Invention

[0005] Some example embodiments of the inventive concepts provide semiconductor devices having improved electrical characteristics.

[0006] According to some example embodiments of the present inventive concepts, a semiconductor device may include: a first active pattern located on a first region of a substrate; a pair of first source / drain patterns located on the first active pattern; a first channel pattern located between the pair of first source / drain patterns; and a gate electrode extending across the first channel pattern. The gate electrode may be located on an uppermost surface and at least one sidewall of the first channel pattern. The gate electrode may include: a first metal pattern including a p-type work function metal; a second metal pattern located on the first metal pattern, the second metal pattern including an n-type work function metal; a first barrier pattern located on the second metal pattern, the first barrier pattern including an amorphous metal layer including tungsten (W), carbon (C), and nitrogen (N); and a second barrier pattern located on the first barrier pattern. The second barrier pattern may include a p-type work function metal.

[0007] According to some example embodiments of the present inventive concepts, a semiconductor device may include: a substrate including an active pattern; a device isolation layer located on a lower sidewall of the active pattern, an upper portion of the active pattern protruding beyond an uppermost surface of the device isolation layer; a pair of source / drain patterns located on the active pattern; a channel pattern located between the pair of source / drain patterns; and a gate electrode extending across the channel pattern. The gate electrode may include: a first metal pattern including a p-type work function metal; a second metal pattern located on the first metal pattern, the second metal pattern including an n-type work function metal; a first barrier pattern located on the second metal pattern, the first barrier pattern including an amorphous metal layer including tungsten (W), carbon (C), and nitrogen (N); a second barrier pattern located on the first barrier pattern, the second barrier pattern including a p-type work function metal; and a third barrier pattern located between the second metal pattern and the first barrier pattern. The third barrier pattern may include a p-type work function metal.

[0008] According to some example embodiments of the present inventive concepts, a semiconductor device may include: a substrate including a plurality of active patterns spaced apart from each other in a first direction; a device isolation layer located on a lower sidewall of each of the plurality of active patterns, an upper portion of each of the plurality of active patterns protruding beyond an uppermost surface of the device isolation layer; a pair of source / drain patterns located on each of the plurality of active patterns; a channel pattern located between the pair of source / drain patterns; a gate electrode extending across the channel patterns in the first direction; and a gate dielectric pattern located between the gate electrode and the channel pattern. The gate dielectric pattern may be located on an upper portion of each of the plurality of active patterns. The gate electrode may include: a first metal pattern including a p-type work function metal; a second metal pattern located on the first metal pattern, the second metal pattern including an n-type work function metal; a first barrier pattern located on the second metal pattern, the first barrier pattern including an amorphous metal layer including tungsten (W), carbon (C), and nitrogen (N); and a second barrier pattern located on the first barrier pattern. The second barrier pattern may include a p-type work function metal. The thickness of the first barrier pattern may fall within a range of 1 nanometer (nm) to 5 nm. The thickness of the second barrier pattern may fall within a range of 5 nm to 70 nm. The first barrier pattern may be located between adjacent channel patterns among the channel patterns spaced apart from each other in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Plan views showing semiconductor devices according to some example embodiments of the inventive concepts are illustrated.

[0010] Figure 2A 、 Figure 2B 、 Figure 2C and Figure 2DShown are respectively along Figure 1 Cross-sectional views taken along line AA', line BB', line CC' and line DD'.

[0011] Figure 2E Shows the display Figure 2A An enlarged cross-sectional view of the gate electrode.

[0012] Figure 3 、 Figure 5 、 Figure 7 and Figure 9 Illustrated are plan views showing a method of fabricating a semiconductor device according to some example embodiments of the inventive concept.

[0013] Figure 4 、 Figure 6A 、 Figure 8A and Figure 10A Shown are respectively along Figure 3 、 Figure 5 、 Figure 7 and Figure 9 A cross-sectional view taken along line AA'.

[0014] Figure 6B 、 Figure 8B and Figure 10B Shown are respectively along Figure 5 、 Figure 7 and Figure 9 A cross-sectional view taken along line BB'.

[0015] Figure 6C 、 Figure 8C and Figure 10C Shown are respectively along Figure 5 、 Figure 7 and Figure 9 A cross-sectional view taken along line CC'.

[0016] Figure 6D 、 Figure 8D and Figure 10D Shown are respectively along Figure 5 、 Figure 7 and Figure 9 A cross-sectional view taken along line D-D'.

[0017] Figure 11 、 Figure 12 and Figure 13 Shown along Figure 9 The cross-sectional view taken along line AA' shows a method of forming a gate dielectric pattern and a gate electrode.

[0018] Figure 14A and Figure 14B Shown are respectively along Figure 1Cross-sectional views taken along lines AA′ and BB′ illustrate semiconductor devices according to some example embodiments of the inventive concepts.

[0019] Figure 14C Shows the display Figure 14A An enlarged cross-sectional view of the gate electrode.

[0020] Figure 15 Plan views showing semiconductor devices according to some example embodiments of the inventive concepts are illustrated.

[0021] Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D 、 Figure 16E and Figure 16F Shown are respectively along Figure 15 Cross-sectional views taken along line AA', line BB', line CC', line DD', line EE' and line FF'.

[0022] Figure 17 、 Figure 19 、 Figure 21 、 Figure 23 、 Figure 25 and Figure 27 Illustrated are plan views showing a method of fabricating a semiconductor device according to some example embodiments of the inventive concept.

[0023] Figure 18 、 Figure 20A 、 Figure 22A 、 Figure 24A 、 Figure 26A and Figure 28A Shown are respectively along Figure 17 、 Figure 19 、 Figure 21 、 Figure 23 、 Figure 25 and Figure 27 A cross-sectional view taken along line AA'.

[0024] Figure 20B 、 Figure 22B 、 Figure 24B 、 Figure 26B and Figure 28B Shown are respectively along Figure 19 、 Figure 21 、 Figure 23 、 Figure 25 and Figure 27 A cross-sectional view taken along line BB'.

[0025] Figure 24C 、 Figure 26C and Figure 28C Shown are respectively along Figure 23 、 Figure 25 and Figure 27 A cross-sectional view taken along line CC'.

[0026] Figure 29 Illustrated are plan views showing a chip region of a semiconductor device according to some example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0027] Figure 1 Plan views showing semiconductor devices according to some example embodiments of the inventive concepts are illustrated. Figure 2A 、 Figure 2B 、 Figure 2C and Figure 2D Shown are respectively along Figure 1 Cross-sectional views taken along line AA', line BB', line CC' and line DD'. Figure 2E Shows the display Figure 2A An enlarged cross-sectional view of the gate electrode.

[0028] Reference Figure 1 and Figures 2A to 2E The substrate 100 may include a first region PR and a second region NR. The substrate 100 may be a compound semiconductor substrate or a semiconductor substrate including silicon (Si), germanium (Ge), silicon germanium (SiGe), etc. For example, the substrate 100 may be a silicon substrate.

[0029] In some embodiments, the first region PR and the second region NR may be logic cell regions, each of which includes logic transistors constituting a logic circuit of the semiconductor device. For example, the logic transistors constituting the logic circuit may be provided on the logic cell region of the substrate 100. The first region PR and the second region NR may include at least one of the logic transistors. The first region PR may be a p-type metal oxide semiconductor field effect transistor (PMOSFET) region, and the second region NR may be an n-type metal oxide semiconductor field effect transistor (NMOSFET) region.

[0030] The first region PR and the second region NR may be defined by a second trench TR2 formed on an upper portion of the substrate 100. The second trench TR2 may be located between the first region PR and the second region NR. The first region PR and the second region NR may be spaced apart from each other in a first direction D1 across the second trench TR2. Each of the first region PR and the second region NR may extend in a second direction D2 that intersects the first direction D1.

[0031] The first active pattern AP1 and the second active pattern AP2 may be disposed on the first region PR and the second region NR, respectively. The first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be vertically protruding portions of the substrate 100. First trenches TR1 may be defined between adjacent first active patterns AP1 and between adjacent second active patterns AP2. The first trenches TR1 may be shallower (in the third direction D3) than the second trenches TR2.

[0032] The device isolation layer ST may fill the first trench TR1 and the second trench TR2. The device isolation layer ST may include a silicon oxide layer. The upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2 may vertically protrude beyond the device isolation layer ST (see FIG. Figure 2C ). Each of the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2 may have a fin shape. The device isolation layer ST may not cover the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2. The device isolation layer ST may cover the lower sidewall of the first active pattern AP1 and the lower sidewall of the second active pattern AP2.

[0033] A first source / drain pattern SD1 may be disposed on an upper portion of the first active pattern AP1. The first source / drain pattern SD1 may be an impurity region of a first conductivity type (e.g., p-type). A first channel pattern CH1 may be interposed between the pair of first source / drain patterns SD1. A second source / drain pattern SD2 may be disposed on an upper portion of the second active pattern AP2. The second source / drain pattern SD2 may be an impurity region of a second conductivity type (e.g., n-type). The second channel pattern CH2 may be interposed between the pair of second source / drain patterns SD2.

[0034] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed through a selective epitaxial growth process. The top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be at a higher level than the top surfaces of the first channel pattern CH1 and the second channel pattern CH2. For example, the first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. Therefore, the first source / drain pattern SD1 may provide compressive stress to the first channel pattern CH1. For example, the second source / drain pattern SD2 may include the same semiconductor element as the semiconductor element of the substrate 100 (e.g., Si).

[0035] The gate electrodes GE may be arranged to extend in the first direction D1 while running (i.e., extending) across the first active pattern AP1 and the second active pattern AP2. The gate electrodes GE may be spaced apart from each other in the second direction D2. The gate electrodes GE may vertically overlap the first channel pattern CH1 and the second channel pattern CH2. Each of the gate electrodes GE may surround the top surface and opposite sidewalls of each of the first channel pattern CH1 and the second channel pattern CH2 (see FIG. 2 ). Figure 2C ).

[0036] A pair of gate spacers GS may be disposed on opposing sidewalls of each gate electrode GE. The gate spacers GS may extend along the gate electrode GE in a first direction D1. The top surface of the gate spacers GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS may be coplanar with the top surface of the first interlayer dielectric layer 110, which will be discussed below. The gate spacers GS may include one or more of silicon carbonitride (SiCN), silicon carbon oxynitride (SiCON), and silicon nitride (SiN). In some embodiments, the gate spacers GS may include a multilayer structure including two or more of SiCN, SiCON, and SiN.

[0037] A gate capping pattern GP may be provided on each of the gate electrodes GE. The gate capping pattern GP may extend in a first direction D1 along the gate electrodes GE. The gate capping pattern GP may include a material having an etching selectivity with respect to the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120, which will be discussed below. For example, the gate capping pattern GP may include one or more of silicon oxynitride (SiON), SiCN, SiCON, and SiN.

[0038] The gate dielectric pattern GI may be interposed between the gate electrode GE and the first active pattern AP1, and between the gate electrode GE and the second active pattern AP2. The gate dielectric pattern GI may extend along the bottom surface of the gate electrode GE, overlapping with the gate dielectric pattern GI. For example, the gate dielectric pattern GI may cover the top surface and opposite sidewalls of the first channel pattern CH1. The gate dielectric pattern GI may cover the top surface and opposite sidewalls of the second channel pattern CH2. The gate dielectric pattern GI may cover the top surface of the device isolation layer ST located below the gate electrode GE.

[0039] In some embodiments, the gate dielectric pattern GI may include a high-k dielectric material having a dielectric constant greater than that of the silicon oxide layer. For example, the high-k dielectric material may include one or more of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0040] In some embodiments of the present invention, the gate dielectric pattern GI may include a ferroelectric material. The gate dielectric pattern GI including the ferroelectric material may function as a negative capacitor. For example, when an external voltage is applied to the ferroelectric material, a negative capacitance effect may occur due to a phase transition from an initial polarization state to a different polarization state due to the migration of dipoles in the ferroelectric material. In this case, a transistor including a ferroelectric material according to the present invention may have an increased total capacitance, thereby improving subthreshold swing characteristics and reducing operating voltage.

[0041] The ferroelectric material of the gate dielectric pattern GI may include hafnium oxide doped with (or containing) one or more of zirconium (Zr), silicon (Si), aluminum (Al), and lanthanum (La). Because the hafnium oxide is doped with one or more of zirconium (Zr), silicon (Si), aluminum (Al), and lanthanum (La) at a specific ratio, at least a portion of the ferroelectric material may have an orthorhombic crystal structure. When at least a portion of the ferroelectric material has an orthorhombic crystal structure, a negative capacitance effect may occur. The portion having the orthorhombic crystal structure may have a volume ratio of approximately 10% to approximately 50% in the ferroelectric material.

[0042] When the ferroelectric material includes zirconium-doped hafnium oxide (ZrHfO), the ratio of Zr atoms to Zr atoms and Hf atoms (or the ratio Zr / (Hf+Zr)) may fall within the range of about 45 at % to about 55 at %. When the ferroelectric material includes silicon-doped hafnium oxide (SiHfO), the ratio of Si atoms to Si atoms and Hf atoms (or the ratio Si / (Hf+Si)) may fall within the range of about 4 at % to about 6 at %. When the ferroelectric material includes aluminum-doped hafnium oxide (AlHfO), the ratio of Al atoms to Al atoms and Hf atoms (or the ratio Al / (Hf+Al)) may fall within the range of about 5 at % to about 10 at %. When the ferroelectric material includes lanthanum-doped hafnium oxide (LaHfO), the ratio of La atoms to La atoms and Hf atoms (or the ratio La / (Hf+La)) may fall within the range of about 5 at % to about 10 at %.

[0043] The gate electrode GE may include a first metal pattern WF1 , a second metal pattern WF2 , a first barrier pattern WF3 , a second barrier pattern WF4 , and an electrode pattern EL, which are sequentially stacked.

[0044] The first metal pattern WF1 may be disposed on the gate dielectric pattern GI. For example, the gate dielectric pattern GI may be interposed between the first metal pattern WF1 and the first channel pattern CH1 and between the first metal pattern WF1 and the second channel pattern CH2. The first metal pattern WF1 may have a thickness T1 of about 2 nm to about 5 nm (see FIG. Figure 2EThe first metal pattern WF1 may have an upper portion adjacent to the gate spacer GS, and a thickness T1 may correspond to a width of the upper portion of the first metal pattern WF1 in the second direction D2.

[0045] Return to reference Figure 2A and Figure 2B , the gate dielectric pattern GI and the first metal pattern WF1 may be chamfered at their upper portions so that the chamfered upper portions may be lower than the uppermost top surface GEt of the gate electrode GE. For example, the first metal pattern WF1 may have a recessed top surface RSt, and the recessed top surface RSt may be lower than the uppermost top surface GEt of the gate electrode GE. Therefore, the expression "recessed top surface" used herein means that the uppermost surface of the first metal pattern WF1 (for example, the top surface of the vertically protruding portion of the first metal pattern WF1) is lower than the uppermost top surface GEt. However, the uppermost surface of the first metal pattern WF1 does not necessarily have a recess. On the contrary, the uppermost surface of the first metal pattern WF1 may be a flat surface or a curved surface without a recess. The first metal pattern WF1 on the first region PR may be thicker than the first metal pattern WF1 on the second region NR.

[0046] The first metal pattern WF1 may include a metal nitride layer having a relatively high work function. For example, the first metal pattern WF1 may include a p-type work function metal. For example, the first metal pattern WF1 may include a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a titanium oxynitride (TiON) layer, a titanium silicon nitride (TiSiN) layer, a titanium aluminum nitride (TiAlN) layer, a tungsten carbonitride (WCN) layer, or a molybdenum nitride (MoN) layer.

[0047] The first metal pattern WF1 on the first region PR may be thicker than the first metal pattern WF1 on the second region NR. Because the first region PR is a PMOSFET region, the p-type work function metal may be relatively thick. Because the second region NR is an NMOSFET region, the p-type work function metal may be relatively thin.

[0048] The second metal pattern WF2 may be disposed on the first metal pattern WF1. The second metal pattern WF2 may cover the recessed top surface RSt (see FIG. 1 ) of the first metal pattern WF1. Figure 2A and Figure 2B The second metal pattern WF2 may have a thickness T2 of from about 3 nm to about 5 nm (see Figure 2E The second metal pattern WF2 may have an upper portion adjacent to the gate spacer GS, and a thickness T2 may correspond to a width of the upper portion of the second metal pattern WF2 in the second direction D2.

[0049] The second metal pattern WF2 may include a metal carbide having a relatively low work function. For example, the second metal pattern WF2 may include an n-type work function metal. The second metal pattern WF2 may include a metal carbide doped with (or containing) silicon and / or aluminum. For example, the second metal pattern WF2 may include aluminum-doped titanium carbide (TiAlC), aluminum-doped tantalum carbide (TaAlC), aluminum-doped vanadium carbide (VAlC), silicon-doped titanium carbide (TiSiC), or silicon-doped tantalum carbide (TaSiC). Alternatively, the second metal pattern WF2 may include aluminum-doped titanium carbide (TiAlSiC) or aluminum-doped tantalum carbide (TaAlSiC). As another example, the second metal pattern WF2 may include aluminum-doped titanium (TiAl).

[0050] The work function of the second metal pattern WF2 may be adjusted by controlling the concentration of dopants such as silicon or aluminum. For example, the impurities (eg, silicon or aluminum) included in the first metal pattern WF1 may have a concentration from about 0.1 at % to about 25 at %.

[0051] The first and second metal patterns WF1 and WF2 may be adjacent to the first and second channel patterns CH1 and CH2. The first and second metal patterns WF1 and WF2 may function as work function metals that control the threshold voltage of the transistor. For example, a desired threshold voltage may be achieved by controlling the thickness and composition of each of the first and second metal patterns WF1 and WF2.

[0052] The first barrier pattern WF3 may be disposed on the second metal pattern WF2. The first barrier pattern WF3 may be conformally formed on the second metal pattern WF2. The thickness T3 of the first barrier pattern WF3 may be less than the thickness T2 of the second metal pattern WF2. The thickness T3 of the first barrier pattern WF3 may be about 1 nm to about 5 nm (see FIG. Figure 2E The first barrier pattern WF3 may have an upper portion adjacent to the gate spacer GS, and a thickness T3 may correspond to a width of the upper portion of the first barrier pattern WF3 in the second direction D2.

[0053] Return to reference Figure 2C The first barrier pattern WF3 may be interposed between the first channel patterns CH1 adjacent to each other in the first direction D1. The first barrier pattern WF3 may also be interposed between the second channel patterns CH2 adjacent to each other in the first direction D1.

[0054] The first barrier pattern WF3 may include a p-type work function metal having a relatively high work function. The first barrier pattern WF3 may include an amorphous metal layer. For example, the first barrier pattern WF3 may include tungsten (W), carbon (C), and nitrogen (N). The first barrier pattern WF3 may include an amorphous tungsten carbonitride (WCN) layer. The WCN layer of the first barrier pattern WF3 may be a tungsten layer containing carbon and nitrogen as impurities. For example, the atomic percentage of tungsten contained in the first barrier pattern WF3 may be greater than the atomic percentage of each of carbon and nitrogen contained in the first barrier pattern WF3.

[0055] The first barrier pattern WF3 may further include additional metal elements diffused inward from adjacent metal layers. For example, the first barrier pattern WF3 may include titanium (Ti) in addition to tungsten (W), carbon (C), and nitrogen (N). The first barrier pattern WF3 may include a metal element such as titanium (Ti) at a very low content (e.g., approximately 5 at % or less).

[0056] For another example, the first barrier pattern WF3 may include an amorphous metal layer such as a titanium aluminum nitride (TiAlN) layer, a titanium silicon nitride (TiSiN) layer, a titanium oxynitride (TiON) layer, or a tantalum nitride (TaN) layer.

[0057] The second barrier pattern WF4 may be disposed on the first barrier pattern WF3. Among the patterns WF1 to WF4, the second barrier pattern WF4 may be thicker than any other pattern. The second barrier pattern WF4 may have a thickness T4 from about 5 nm to about 70 nm (see FIG. Figure 2E The second barrier pattern WF4 may have an upper portion adjacent to the gate spacer GS, and a thickness T4 may correspond to a width of the upper portion of the second barrier pattern WF4 in the second direction D2.

[0058] Refer again Figure 2C The second barrier pattern WF4 may be located in (eg, may completely fill) a space between the first channel patterns CH1 adjacent to each other in the first direction D1. The second barrier pattern WF4 may be located in (eg, may completely fill) a space between the second channel patterns CH2 adjacent to each other in the first direction D1.

[0059] The second barrier pattern WF4 may include a metal nitride layer having a relatively high work function. For example, the second barrier pattern WF4 may include a p-type work function metal. For example, the second barrier pattern WF4 may include a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, or a titanium oxynitride (TiON) layer. The second barrier pattern WF4 may include the same material as the first metal pattern WF1.

[0060] The second barrier pattern WF4 may include a crystalline metal nitride layer. For example, the second barrier pattern WF4 may include crystal grains. The second barrier pattern WF4 may include grain boundaries between the crystal grains.

[0061] Still refer to Figure 2C , the gate dielectric pattern GI and the patterns WF1 to WF4 may be located in (eg, may fill) the space SA between the first channel patterns CH1 adjacent to each other in the first direction D1. In some embodiments, when the distance between the first channel patterns CH1 in the first direction D1 is less than Figure 2C When the distance between the first channel patterns CH1 in the first direction D1 is shown in , the second barrier pattern WF4 may not be located in (eg, may not fill) the space SA.

[0062] The electrode pattern EL may be disposed on the second barrier pattern WF4. The electrode pattern EL may have a lower resistance than the resistance of the patterns WF1 to WF4. For example, the electrode pattern EL may include at least one low-resistance metal selected from aluminum (Al), tungsten (W), titanium (Ti), and tantalum (Ta).

[0063] The first barrier pattern WF3 and the second barrier pattern WF4 can suppress / prevent the metal of the electrode pattern EL from diffusing into the first metal pattern WF1 and the second metal pattern WF2. For example, because the second barrier pattern WF4 is formed relatively thick, the metal of the electrode pattern EL can be effectively suppressed / prevented from diffusing into the first metal pattern WF1 and the second metal pattern WF2.

[0064] According to some embodiments of the present invention, because the first barrier pattern WF3 includes an amorphous WCN layer, the first barrier pattern WF3 may lack grain boundaries. Therefore, the first barrier pattern WF3 can suppress / prevent material diffusion. For example, when depositing the electrode pattern EL, fluorine (F) may diffuse into the second metal pattern WF2 through the grain boundaries of the second barrier pattern WF4. This diffusion may lead to problems associated with a reduction in the effective work function (eWF) of the gate electrode GE. On the other hand, according to some embodiments of the present invention, the first barrier pattern WF3 may be interposed between the second metal pattern WF2 and the second barrier pattern WF4. Therefore, the diffusion of fluorine (F) into the second metal pattern WF2 may be suppressed / prevented. Consequently, the effective work function of the gate electrode can be increased, and the desired threshold voltage of the transistor can be achieved.

[0065] A first interlayer dielectric layer 110 may be disposed on the substrate 100. The first interlayer dielectric layer 110 may cover the gate spacer GS and the first and second source / drain patterns SD1 and SD2. The first interlayer dielectric layer 110 may have a top surface that is substantially coplanar with the top surface of the gate capping pattern GP and the top surface of the gate spacer GS. A second interlayer dielectric layer 120 may be disposed on the first interlayer dielectric layer 110, covering the gate capping pattern GP. For example, the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 may include silicon oxide layers.

[0066] One or more active contacts AC may be provided between the pair of gate electrodes GE, the one or more active contacts AC passing through the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 and electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. The active contacts AC may include, for example, at least one metal material selected from aluminum, copper, tungsten, molybdenum, and cobalt.

[0067] The active contact AC may be a self-aligned contact. For example, the gate capping pattern GP and the gate spacer GS may be used to form the active contact AC in a self-aligned manner. The active contact AC may cover the sidewalls of the gate spacer GS. A portion of the active contact AC may cover the top surface of the gate capping pattern GP.

[0068] A silicide layer may be interposed between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2. The active contact AC may be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 through the silicide layer. The silicide layer may include a metal silicide, for example, one or more of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0069] At least one gate contact GC may be provided on the device isolation layer ST, passing through the second interlayer dielectric layer 120 and the gate capping pattern GP and electrically connected to the gate electrode GE. The gate contact GC may include the same metal material as that of the active contact AC.

[0070] A barrier layer may be provided to cover each of the active contact AC and the gate contact GC. The barrier layer may cover the bottom surface and sidewalls of the active contact AC. The barrier layer may cover the bottom surface and sidewalls of the gate contact GC. The barrier layer may include one or more of a metal layer and a metal nitride layer. The metal layer may include one or more of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include one or more of a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CoN) layer, and a platinum nitride (PtN) layer.

[0071] Figure 3 、 Figure 5 、 Figure 7 and Figure 9 Illustrated are plan views showing a method of fabricating a semiconductor device according to some example embodiments of the inventive concept. Figure 4 、 Figure 6A 、 Figure 8A and Figure 10A Shown are respectively along Figure 3 、 Figure 5 、 Figure 7 and Figure 9 A cross-sectional view taken along line AA'. Figure 6B 、 Figure 8B and Figure 10B Shown are respectively along Figure 5 、 Figure 7 and Figure 9 A cross-sectional view taken along line BB'. Figure 6C 、 Figure 8C and Figure 10C Shown are respectively along Figure 5 、 Figure 7 and Figure 9 A cross-sectional view taken along line CC'. Figure 6D 、 Figure 8D and Figure 10D Shown are respectively along Figure 5 、 Figure 7 and Figure 9 A cross-sectional view taken along line D-D'. Figure 11 、 Figure 12 and Figure 13 Shown along Figure 9 The cross-sectional view taken along line AA' shows a method of forming a gate dielectric pattern and a gate electrode.

[0072] Reference Figure 3 and Figure 4 The substrate 100 may include a first region PR and a second region NR. The substrate 100 may be patterned to form a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 may be formed on the first region PR, and the second active pattern AP2 may be formed on the second region NR. A first trench TR1 may be formed between the first active pattern AP1 and the second active pattern AP2.

[0073] The substrate 100 may be patterned to form a second trench TR2 between the first region PR and the second region NR. The second trench TR2 may be formed deeper than the first trench TR1.

[0074] A device isolation layer ST may be formed on the substrate 100 to fill the first trench TR1 and the second trench TR2. The device isolation layer ST may include a dielectric material, such as a silicon oxide layer. The device isolation layer ST may be recessed until the upper portions of the first active pattern AP1 and the second active pattern AP2 are exposed. As a result, the upper portions of the first active pattern AP1 and the second active pattern AP2 may vertically protrude beyond the device isolation layer ST.

[0075] Reference Figure 5 and 6A to 6D , a sacrificial pattern PP may be formed that spans the first active pattern AP1 and the second active pattern AP2. Each of the sacrificial patterns PP may be formed to have a line shape or a stripe shape extending in the first direction D1. For example, forming the sacrificial pattern PP may include: forming a sacrificial layer over the entire surface of the substrate 100; forming a hard mask pattern MA on the sacrificial layer; and etching the sacrificial layer using the hard mask pattern MA as an etch mask. The sacrificial layer may include a polysilicon layer.

[0076] A pair of gate spacers GS may be formed on opposing sidewalls of each of the sacrificial patterns PP. Gate spacers GS may also be formed on opposing sidewalls of each of the first active pattern AP1 and the second active pattern AP2. Opposing sidewalls of each of the first active pattern AP1 and the second active pattern AP2 may be exposed portions not covered by the device isolation layer ST and the sacrificial pattern PP.

[0077] Forming the gate spacer GS may include: conformally forming a gate spacer layer on the entire exposed surface of the substrate 100; and anisotropically etching the gate spacer layer. The gate spacer layer may include one or more of SiCN, SiCON, and SiN. Alternatively, the gate spacer layer may have a multilayer structure including two or more of SiCN, SiCON, and SiN.

[0078] Reference Figure 7 and Figures 8A to 8D , a first source / drain pattern SD1 may be formed on an upper portion of each of the first active patterns AP1. A pair of first source / drain patterns SD1 may be formed on opposite sides of each of the sacrificial patterns PP.

[0079] For example, the hard mask pattern MA and the gate spacers GS may be used as an etching mask to etch the upper portions of the first active patterns AP1, which may result in the formation of first recesses. While the upper portions of the first active patterns AP1 are being etched, the gate spacers GS may also be removed from opposing sidewalls of each of the first active patterns AP1. While the upper portions of the first active patterns AP1 are being etched, the device isolation layer ST may be recessed between the first active patterns AP1.

[0080] The first recess of the first active pattern AP1 may have inner sidewalls that serve as a seed layer for a selective epitaxial growth process to form the first source / drain patterns SD1. The formation of the first source / drain patterns SD1 may define a first channel pattern CH1 between the pair of first source / drain patterns SD1. For example, the selective epitaxial growth process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The first source / drain patterns SD1 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. Each of the first source / drain patterns SD1 may be formed from a plurality of semiconductor layers.

[0081] For example, to form the first source / drain pattern SD1, impurities may be implanted in situ during a selective epitaxial growth process. For another example, after forming the first source / drain pattern SD1, impurities may be implanted into the first source / drain pattern SD1. The first source / drain pattern SD1 may be doped with impurities to have a first conductivity type (e.g., p-type).

[0082] A second source / drain pattern SD2 may be formed on an upper portion of each of the second active patterns AP2. A pair of second source / drain patterns SD2 may be formed on opposite sides of each of the sacrificial patterns PP.

[0083] For example, the hard mask pattern MA and the gate spacers GS may be used as an etching mask to etch the upper portion of the second active pattern AP2, thereby forming a second recess. The second recess of the second active pattern AP2 may have inner sidewalls that serve as a seed layer for the selective epitaxial growth process to form the second source / drain pattern SD2. The formation of the second source / drain pattern SD2 may define a second channel pattern CH2 between the pair of second source / drain patterns SD2. For example, the second source / drain pattern SD2 may include the same semiconductor element as that of the substrate 100 (e.g., Si). The second source / drain pattern SD2 may be doped with impurities to have a second conductivity type (e.g., n-type).

[0084] Different processes may be performed to sequentially form the first source / drain pattern SD1 and the second source / drain pattern SD2. For example, the first source / drain pattern SD1 and the second source / drain pattern SD2 may not be formed at the same time.

[0085] Reference Figure 9 and 10A to 10D A first interlayer dielectric layer 110 may be formed to cover the first and second source / drain patterns SD1 and SD2, the hard mask pattern MA, and the gate spacer GS. For example, the first interlayer dielectric layer 110 may include a silicon oxide layer.

[0086] The first interlayer dielectric layer 110 may be planarized until the top surface of the sacrificial pattern PP is exposed. An etch-back process or a chemical mechanical polishing (CMP) process may be used to planarize the first interlayer dielectric layer 110. The hard mask pattern MA may be completely removed during the planarization process. As a result, the first interlayer dielectric layer 110 may have a top surface that is substantially coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0087] The sacrificial pattern PP may be replaced by the gate electrode GE. For example, the exposed sacrificial pattern PP may be selectively removed. Removal of the sacrificial pattern PP may form an empty space. A gate dielectric pattern GI, a gate electrode GE, and a gate capping pattern GP may be formed in each of the empty spaces.

[0088] The following will refer to Figure 11 、 Figure 12 and Figure 13 The method of forming the gate dielectric pattern GI and the gate electrode GE is discussed in detail. Figure 9 and Figure 11 , the gate dielectric layer GIL may be formed to partially fill the empty space ET from which the sacrificial pattern PP is removed. The gate dielectric layer GIL may include a high-k dielectric material.

[0089] A first work function metal layer WFL1 may be formed on the gate dielectric layer GIL to partially fill the empty space ET. The first work function metal layer WFL1 may be formed thicker than the gate dielectric layer GIL. The first work function metal layer WFL1 may include a p-type work function metal with a relatively high work function. For example, the first work function metal layer WFL1 may include a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a titanium oxynitride (TiON) layer, a titanium silicon nitride (TiSiN) layer, a titanium aluminum nitride (TiAlN) layer, a tungsten carbonitride (WCN) layer, or a molybdenum nitride (MoN) layer. A filling material FM may be formed on the first work function metal layer WFL1 to fill the lower portion of the empty space ET.

[0090] Reference Figure 9 and Figure 12 The filler material FM may be used as a mask to etch the first work function metal layer WFL1 and the gate dielectric layer GIL to form a first metal pattern WF1 and a gate dielectric pattern GI, respectively. For example, the first work function metal layer WFL1 and the gate dielectric layer GIL may be chamfered to form the first metal pattern WF1 and the gate dielectric pattern GI, respectively. The first metal pattern WF1 may have a recessed top surface RSt that is lower than the top surface of the gate spacer GS.

[0091] Reference Figure 9 and Figure 13The filling material FM may be selectively removed. A second work function metal layer WFL2 , a third work function metal layer WFL3 , and a fourth work function metal layer WFL4 may be sequentially formed on the first metal pattern WF1 .

[0092] The second work function metal layer WFL2 may include an n-type work function metal with a relatively low work function. The second work function metal layer WFL2 may include a metal carbide doped with (or containing) one or more of silicon and aluminum.

[0093] The third work function metal layer WFL3 may be formed thinner than the second work function metal layer WFL2. The third work function metal layer WFL3 may include a p-type work function metal with a relatively high work function. The third work function metal layer WFL3 may include an amorphous metal layer capable of inhibiting / preventing material diffusion. The third work function metal layer WFL3 may include an amorphous tungsten carbonitride (WCN) layer. As another example, the third work function metal layer WFL3 may include an amorphous metal layer, such as a titanium aluminum nitride (TiAlN) layer, a titanium silicon nitride (TiSiN) layer, a titanium oxynitride (TiON) layer, or a tantalum nitride (TaN) layer.

[0094] The fourth work function metal layer WFL4 may be formed thicker than any other work function metal layer. The fourth work function metal layer WFL4 may include a p-type work function metal having a relatively high work function. For example, the fourth work function metal layer WFL4 may include a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a titanium oxynitride (TiON) layer, a titanium silicon nitride (TiSiN) layer, a titanium aluminum nitride (TiAlN) layer, a tungsten carbonitride (WCN) layer, or a molybdenum nitride (MoN) layer.

[0095] An electrode layer ELL may be formed on the fourth work function metal layer WFL4 to completely fill the empty space ET. The electrode layer ELL may include a low resistance metal such as tungsten (W).

[0096] In some embodiments of the present inventive concept, forming the electrode layer ELL may include performing atomic layer deposition or chemical vapor deposition using tungsten fluorine (WF6) gas. Tungsten contained in the WF6 gas may be deposited on the fourth work function metal layer WFL4 to form the electrode layer ELL.

[0097] The fourth work function metal layer WFL4 may include crystal grains. The fourth work function metal layer WFL4 may include grain boundaries between the crystal grains. When forming the electrode layer ELL, fluorine (F) contained in the WF6 gas may diffuse through the grain boundaries of the fourth work function metal layer WFL4 into the third work function metal layer WFL3.

[0098] Because the third work function metal layer WFL3 is formed of an amorphous metal layer, the third work function metal layer WFL3 can inhibit / prevent fluorine (F) from diffusing into the second work function metal layer WFL2. For example, the third work function metal layer WFL3 can serve as a barrier layer that stops the diffusion of fluorine (F).

[0099] In summary, according to some embodiments of the present inventive concept, because the third work function metal layer WFL3 stops the diffusion of fluorine (F), degradation of the second work function metal layer WFL2 can be reduced / prevented, and the effective work function (eWF) of the gate electrode GE can be increased. In addition, the transistor can achieve a desired threshold voltage.

[0100] Return to reference Figure 9 and Figure 10A The second work function metal layer WFL2, the third work function metal layer WFL3, the fourth work function metal layer WFL4, and the electrode layer ELL may be planarized to form a second metal pattern WF2, a first barrier pattern WF3, a second barrier pattern WF4, and an electrode pattern EL, respectively. Patterns WF1 to WF4 and the electrode pattern EL may constitute a gate electrode GE. The upper portion of the gate electrode GE may be recessed, and a gate capping pattern GP may be formed on the gate electrode GE.

[0101] Return to reference Figure 1 and Figures 2A to 2D , a second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110. The second interlayer dielectric layer 120 may include a silicon oxide layer or a low-k oxide layer. For example, the low-k oxide layer may include a carbon-doped silicon oxide layer, such as SiCOH. The second interlayer dielectric layer 120 may be formed by chemical vapor deposition (CVD).

[0102] Active contacts AC may be formed through the second interlayer dielectric layer 120 and the first interlayer dielectric layer 110 and electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. The gate capping pattern GP and the gate spacers GS may be used as a mask to form the active contacts AC in a self-aligned manner. On the device isolation layer ST, gate contacts GC may be formed through the second interlayer dielectric layer 120 and the gate capping pattern GP and electrically connected to the gate electrode GE.

[0103] Figure 14A and Figure 14B Shown are respectively along Figure 1 Cross-sectional views taken along lines AA′ and BB′ illustrate semiconductor devices according to some example embodiments of the inventive concepts. Figure 14C Shows the display Figure 14A In the following examples, the above reference can be omitted. Figure 1 and Figures 2A to 2EThe detailed description of the technical features discussed is repeated and will be discussed in detail with reference to the above Figure 1 and Figures 2A to 2E Discuss the differences in technical features.

[0104] Reference Figure 1 and 14A to 14C A third barrier pattern WF5 may be interposed between the second metal pattern WF2 and the first barrier pattern WF3. The third barrier pattern WF5 may have a thickness T5 that is less than the thickness T2 of the second metal pattern WF2. The third barrier pattern WF5 may include a p-type work function metal with a relatively high work function. The third barrier pattern WF5 may include a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a titanium oxynitride (TiON) layer, a titanium silicon nitride (TiSiN) layer, a titanium aluminum nitride (TiAlN) layer, a tungsten carbonitride (WCN) layer, or a molybdenum nitride (MoN) layer. The third barrier pattern WF5 may include the same material as the first metal pattern WF1.

[0105] When forming the second metal pattern WF2, oxidation of the n-type work function metal may cause problems associated with increased resistance of the second metal pattern WF2. The third barrier pattern WF5 may be directly disposed on the second metal pattern WF2, thereby protecting / preventing oxidation of the second metal pattern WF2. As a result, the resistance of the gate electrode GE may be reduced.

[0106] The thickness T5 of the third barrier pattern WF5 may fall within the range from 1 nm to about 5 nm (see Figure 14C The third barrier pattern WF5 may have an upper portion adjacent to the gate spacer GS, and a thickness T5 may correspond to a width of the upper portion of the third barrier pattern WF5 in the second direction D2.

[0107] The gate electrode GE may omit the electrode pattern EL. Because the third barrier pattern WF5 is added to the gate electrode GE, there may not be enough space to form the electrode pattern EL. Alternatively, the gate electrode GE may include both the electrode pattern EL and the third barrier pattern WF5. The second barrier pattern WF4 may completely fill the space between the pair of gate spacers GS. Therefore, the thickness T4 of the second barrier pattern WF4 may be relatively large. The thickness T4 of the second barrier pattern WF4 may be approximately equal to the channel length. The thickness T4 may correspond to the width of the upper portion of the second barrier pattern WF4 in the second direction D2.

[0108] Figure 15 Plan views showing semiconductor devices according to some example embodiments of the inventive concepts are illustrated. Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D 、 Figure 16E and Figure 16FShown are respectively along Figure 15 The cross-sectional views taken along the lines A-A', B-B', C-C', D-D', E-E' and F-F' of FIG. Figure 1 and Figures 2A to 2E The detailed description of the technical features discussed is repeated and will be discussed in detail with reference to the above Figure 1 and Figures 2A to 2E Discuss the differences in technical features.

[0109] Reference Figure 15 and 16A to 16F The substrate 100 may include a first region PR and a second region NR. The first region PR and the second region NR may be logic cell regions, each of which includes logic transistors constituting a logic circuit of the semiconductor device. The first region PR may be a PMOSFET region, and the second region NR may be an NMOSFET region.

[0110] The trench TR formed on the upper portion of the substrate 100 may define a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 may be disposed on the first region PR. The second active pattern AP2 may be disposed on the second region NR. Each of the first active pattern AP1 and the second active pattern AP2 may have a line shape or a stripe shape extending in the second direction D2.

[0111] A device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may fill the trench TR. The device isolation layer ST may have a top surface lower than top surfaces of the first and second active patterns AP1 and AP2.

[0112] A first channel pattern CH1 and a first source / drain pattern SD1 may be disposed on each of the first active patterns AP1. The first channel pattern CH1 may be interposed between a pair of first source / drain patterns SD1. A second channel pattern CH2 and a second source / drain pattern SD2 may be disposed on each of the second active patterns AP2. The second channel pattern CH2 may be interposed between a pair of second source / drain patterns SD2.

[0113] The first channel pattern CH1 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked in sequence. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in a third direction D3 perpendicular to the top surface of the substrate 100. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may vertically overlap each other. Each of the first source / drain patterns SD1 may directly contact a sidewall of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may electrically connect a pair of adjacent first source / drain patterns SD1.

[0114] The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the first channel pattern CH1 may have the same thickness or different thicknesses. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the first channel pattern CH1 may have different maximum lengths in the second direction D2. For example, the first length may refer to the maximum length of the first semiconductor pattern SP1 in the second direction D2. The second length may refer to the maximum length of the second semiconductor pattern SP2 in the second direction D2. The third length may refer to the maximum length of the third semiconductor pattern SP3 in the second direction D2. The first length may be greater than the second length. The third length may be greater than the second length.

[0115] The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the first channel pattern CH1 may include one or more of silicon (Si), germanium (Ge), and silicon germanium (SiGe). The first channel pattern CH1 is shown as including the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3, but the number of semiconductor patterns is not particularly limited. For example, the first channel pattern CH1 may include at least two semiconductor patterns.

[0116] The second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked in sequence. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the second channel pattern CH2 may have substantially the same length in the second direction D2. The detailed description of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 included in the second channel pattern CH2 may be substantially the same as or similar to the detailed description of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 included in the first channel pattern CH1 discussed above.

[0117] The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the first channel pattern CH1, and the first recess RS1 of the first active pattern AP1 may serve as a seed layer, from which each of the first source / drain patterns SD1 is grown as an epitaxial pattern. Each of the first source / drain patterns SD1 may fill the first recess RS1 of the first active pattern AP1. The first recess RS1 may be defined between adjacent first channel patterns CH1. The first recess RS1 may have a bottom portion having a level lower than that of the top surface of the first active pattern AP1.

[0118] The first source / drain pattern SD1 may have a maximum width in the second direction D2 at a middle portion thereof (see FIG. Figure 16A The width of the first source / drain pattern SD1 in the second direction D2 may increase as it approaches the middle portion from the upper portion of the first source / drain pattern SD1. The width of the first source / drain pattern SD1 in the second direction D2 may decrease as it approaches the lower portion of the first source / drain pattern SD1 from the middle portion.

[0119] The first source / drain pattern SD1 may be an impurity region having a first conductivity type (e.g., p-type). The first source / drain pattern SD1 may provide compressive stress to the first channel pattern CH1. For example, the first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 100.

[0120] The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the second channel pattern CH2, and the second recess RS2 of the second active pattern AP2 may serve as a seed layer, from which each of the second source / drain patterns SD2 is grown as an epitaxial pattern. Each of the second source / drain patterns SD2 may fill the second recess RS2 of the second active pattern AP2. The second recess RS2 may be defined between adjacent second channel patterns CH2. The second recess RS2 may have a bottom portion having a level lower than that of the top surface of the second active pattern AP2.

[0121] The second source / drain pattern SD2 may be an impurity region having a second conductivity type (eg, n-type). For example, the second source / drain pattern SD2 may include the same semiconductor element as that of the substrate 100 (eg, Si).

[0122] The gate electrode GE may be arranged to extend in a first direction D1 while running across (i.e., extending) the first channel pattern CH1 and the second channel pattern CH2. The gate electrodes GE may be spaced apart from each other in a second direction D2. The gate electrode GE may vertically overlap the first channel pattern CH1 and the second channel pattern CH2. A pair of gate spacers GS may be provided on opposing sidewalls of each of the gate electrodes GE. A gate capping pattern GP may be provided on the gate electrode GE.

[0123] The gate electrode GE may include a first metal pattern WF1, a second metal pattern WF2, a first barrier pattern WF3, a second barrier pattern WF4, and an electrode pattern EL stacked in sequence. The detailed description of the patterns WF1 to WF4 and the electrode pattern EL may be the same as that described above with reference to FIG. Figure 1 and Figures 2A to 2E The detailed descriptions of the discussed patterns WF1 to WF4 and the electrode pattern EL are substantially the same.

[0124] The gate electrode GE according to some embodiments may surround each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 (see FIG. Figure 16C and Figure 16D For example, the gate electrode GE may surround the top and bottom surfaces and opposite sidewalls of each of the first, second, and third semiconductor patterns SP1, SP2, and SP3. In these configurations, the transistor according to some embodiments may be a gate-all-around type field effect transistor.

[0125] A gate dielectric pattern GI may be interposed between the gate electrode GE and each of the first, second, and third semiconductor patterns SP1, SP2, and SP3. The gate dielectric pattern GI may surround each of the first, second, and third semiconductor patterns SP1, SP2, and SP3. The gate dielectric pattern GI may cover an upper portion of the first active pattern AP1, and an upper portion of the first active pattern AP1 may protrude vertically from the device isolation layer ST. The gate dielectric pattern GI may include a high-k dielectric material having a dielectric constant greater than that of the silicon oxide layer.

[0126] A first space SA1 may be defined between the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the first channel pattern CH1. For example, the first space SA1 may be defined between a pair of vertically adjacent patterns among the first, second, and third semiconductor patterns SP1, SP2, and SP3.

[0127] The first space SA1 may be filled with the gate dielectric pattern GI, the first metal pattern WF1, and the second metal pattern WF2. The gate dielectric pattern GI and the first metal pattern WF1 may conformally fill the first space SA1. The second metal pattern WF2 may completely fill the remaining portion of the first space SA1 not occupied by the gate dielectric pattern GI and the first metal pattern WF1.

[0128] The first space SA1 may not be filled with the first barrier pattern WF3 , the second barrier pattern WF4 , and the electrode pattern EL. For example, any of the first barrier pattern WF3 , the second barrier pattern WF4 , and the electrode pattern EL may not be in the first space SA1 .

[0129] Return to reference Figure 16C and Figure 16D , the second metal pattern WF2 may not completely fill the first space SA1. The second metal pattern WF2 may cover the first metal pattern WF1 that surrounds the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3, respectively. Therefore, the first barrier pattern WF3 may not be in the first space SA1, but may only cover the surface of the second metal pattern WF2.

[0130] Return to reference Figure 15 and 16A to 16F A second space SA2 may be defined on the third semiconductor pattern SP3 or the uppermost semiconductor pattern of the first channel pattern CH1. The second space SA2 may be a cavity surrounded by a pair of gate spacers GS, the gate capping pattern GP, ​​and the third semiconductor pattern SP3.

[0131] The second space SA2 may be filled with the gate dielectric pattern GI, the patterns WF1 to WF4, and the electrode pattern EL. The detailed description of the gate electrode GE in the second space SA2 may be the same as that in the above reference. Figure 1 and Figures 2A to 2E The detailed description of the gate electrode GE discussed is substantially the same.

[0132] On the first region PR, the gate dielectric pattern GI may contact the first source / drain pattern SD1 (see FIG. Figure 16A For example, the gate dielectric pattern GI may be interposed between the first metal pattern WF1 and the first source / drain pattern SD1.

[0133] On the second region NR, an inner spacer IS may be interposed between the second source / drain pattern SD2 and the gate dielectric pattern GI (see FIG. Figure 16B). The internal spacer IS may be interposed between vertically spaced patterns among the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate dielectric pattern GI on the second region NR may contact the internal spacer IS. For example, the gate dielectric pattern GI on the second region NR may be interposed between the first metal pattern WF1 and the internal spacer IS. For example, the internal spacer IS may include a silicon nitride layer.

[0134] A first interlayer dielectric layer 110 may be disposed over the entire surface of the substrate 100. The first interlayer dielectric layer 110 may cover the device isolation layer ST, the gate spacer GS, and the first and second source / drain patterns SD1 and SD2. The first interlayer dielectric layer 110 may have a top surface that is substantially coplanar with a top surface of the gate capping pattern GP. A second interlayer dielectric layer 120 may be disposed on the first interlayer dielectric layer 110. For example, the first and second interlayer dielectric layers 110 and 120 may include a silicon oxide layer or a silicon oxynitride layer. One or more active contacts AC may be provided through the first and second interlayer dielectric layers 110 and 120 and electrically connected to the first and second source / drain patterns SD1 and SD2.

[0135] Figure 17 、 Figure 19 、 Figure 21 、 Figure 23 、 Figure 25 and Figure 27 Illustrated are plan views showing a method of fabricating a semiconductor device according to some example embodiments of the inventive concept. Figure 18 、 Figure 20A 、 Figure 22A 、 Figure 24A 、 Figure 26A and Figure 28A Shown are respectively along Figure 17 、 Figure 19 、 Figure 21 、 Figure 23 、 Figure 25 and Figure 27 A cross-sectional view taken along line AA'. Figure 20B 、 Figure 22B 、 Figure 24B 、 Figure 26B and Figure 28B Shown are respectively along Figure 19 、 Figure 21 、 Figure 23 、 Figure 25 and Figure 27 A cross-sectional view taken along line BB'. Figure 24C 、 Figure 26C and Figure 28C Shown are respectively along Figure 23 、 Figure 25 and Figure 27In the following examples, the cross-sectional view taken along the line C-C' can be omitted. Figures 3 to 13 The detailed description of the technical features discussed are repeated and will be explained in detail with the above reference Figures 3 to 13 Discuss the differences in technical features.

[0136] Reference Figure 17 and Figure 18 The sacrificial layer SAC and the semiconductor layer SEL may be alternately and repeatedly stacked on the entire surface (e.g., the entire top surface) of the substrate 100. The semiconductor layer SEL is shown as being repeatedly stacked three times, but the present inventive concept is not limited thereto. The sacrificial layer SAC may include a material having an etching selectivity relative to the semiconductor layer SEL. In this sense, the semiconductor layer SEL may include a material that is not substantially etched during the process of etching the sacrificial layer SAC. For example, the sacrificial layer SAC may include silicon germanium (SiGe) or germanium (Ge), and the semiconductor layer SEL may include silicon (Si).

[0137] The first region PR of the substrate 100 will be mainly described below. Figure 19 、 Figure 20A and Figure 20B A patterning process may be performed so that the sacrificial layer SAC and the semiconductor layer SEL are patterned to form a first preliminary pattern PAP1 on the first region PR of the substrate 100. In the patterning process, an upper portion of the substrate 100 may be etched to form trenches TR defining the first active pattern AP1.

[0138] The trench TR may define the first active pattern AP1 while extending in the second direction D2. The trench TR may be formed between a pair of first active patterns AP1 adjacent to each other in the first direction D1.

[0139] The first preliminary pattern PAP1 may be disposed on the first active pattern AP1. The first preliminary pattern PAP1 may vertically overlap the first active pattern AP1. For example, the first preliminary pattern PAP1 may have a planar shape substantially the same as that of the first active pattern AP1. The first preliminary pattern PAP1 and the first active pattern AP1 may be formed to have a line shape or a stripe shape extending in the second direction D2.

[0140] A device isolation layer ST may be formed to fill the trench TR. Forming the device isolation layer ST may include: forming a dielectric layer on the entire surface of the substrate 100; and recessing the dielectric layer to completely expose the first preliminary pattern PAP1. The device isolation layer ST may have a top surface lower than that of the first active pattern AP1.

[0141] Reference Figure 21 、 Figure 22A and Figure 22B, may be formed as a sacrificial pattern PP across the first preliminary pattern PAP1. The sacrificial pattern PP may be formed to have a line shape or a stripe shape extending in the first direction D1. The sacrificial pattern PP may be formed by a mask pattern MP overlapping the sacrificial pattern PP. A pair of gate spacers GS may be formed on opposing sidewalls of each of the sacrificial patterns PP.

[0142] Reference Figure 23 and Figures 24A to 24C The mask pattern MP and the gate spacer GS may be used as an etching mask to etch the first preliminary pattern PAP1, thereby forming a first channel pattern CH1. The semiconductor layer SEL of the first preliminary pattern PAP1 may be patterned to form a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3. The first channel pattern CH1 may include the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0143] While forming the first channel pattern CH1, the first preliminary pattern PAP1 may be etched to form a first recess RS1. The first recess RS1 may be formed between a pair of adjacent first channel patterns CH1.

[0144] The first source / drain pattern SD1 may be formed to fill the first recess RS1. Forming the first source / drain pattern SD1 may include performing a selective epitaxial growth process in which the first active pattern AP1 and the first, second, and third semiconductor patterns SP1, SP2, and SP3 on the first active pattern AP1 serve as seed layers.

[0145] Reference Figure 25 and Figures 26A to 26C , a first interlayer dielectric layer 110 may be formed on the substrate 100. Then, a planarization process may be performed on the first interlayer dielectric layer 110 until the top surface of the sacrificial pattern PP is exposed.

[0146] A removal process may be performed to selectively remove the sacrificial pattern PP exposed during the planarization process. Removal of the sacrificial pattern PP may form an empty space between a pair of adjacent gate spacers GS. The empty space may expose the sacrificial layer SAC and the first, second, and third semiconductor patterns SP1, SP2, and SP3.

[0147] A removal process may be performed to selectively remove the sacrificial layer SAC exposed in the empty space. While etching the sacrificial layer SAC, the first, second, and third semiconductor patterns SP1, SP2, and SP3 may not be etched but remain. The selective removal of the sacrificial layer SAC may result in an empty space exposing the top and bottom surfaces and sidewalls of each of the first, second, and third semiconductor patterns SP1, SP2, and SP3.

[0148] The empty space may include a first space SA1 and a second space SA2. Specifically, the selective removal of the sacrificial layer SAC may define a first space SA1 between a pair of vertically adjacent patterns among the first, second, and third semiconductor patterns SP1, SP2, and SP3. For example, the first space SA1 may be defined between the first and second semiconductor patterns SP1 and SP2. The second space SA2 may be defined on the uppermost semiconductor pattern or the third semiconductor pattern SP3.

[0149] Reference Figure 27 and Figures 28A to 28C A gate dielectric layer GIL may be conformally formed on the exposed first, second, and third semiconductor patterns SP1, SP2, and SP3, and on the exposed upper portion of the first active pattern AP1. The gate dielectric layer GIL may partially fill each of the first and second spaces SA1 and SA2. A first work function metal layer WFL1 may be conformally formed on the gate dielectric layer GIL. The first work function metal layer WFL1 may partially fill each of the first and second spaces SA1 and SA2.

[0150] A filling material FM may be formed on the first work function metal layer WFL1 , and the filling material FM may completely fill the first space SA1 , and may fill a lower portion of the second space SA2 .

[0151] Return to reference Figure 15 and 16A to 16F The filler material FM can be used as a mask to etch the first work function metal layer WFL1 and the gate dielectric layer GIL, thereby forming a first metal pattern WF1 and a gate dielectric pattern GI, respectively. For example, the first work function metal layer WFL1 and the gate dielectric layer GIL can be chamfered to form the first metal pattern WF1 and the gate dielectric pattern GI, respectively. Then, the filler material FM can be selectively removed.

[0152] A second metal pattern WF2, a first barrier pattern WF3, and a second barrier pattern WF4 may be sequentially formed on the first metal pattern WF1. The second metal pattern WF2 may completely fill the first space SA1. Therefore, the first barrier pattern WF3 and the second barrier pattern WF4 may not be present in the first space SA1. An electrode pattern EL may be formed on the second barrier pattern WF4. The patterns WF1 to WF4 and the electrode pattern EL may constitute the gate electrode GE.

[0153] A gate capping pattern GP may be formed on the gate electrode GE. A second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110. An active contact AC may be formed through the first and second interlayer dielectric layers 110 and 120 and connected to the first source / drain pattern SD1.

[0154] Figure 29 Illustrated are plan views showing a chip region of a semiconductor device according to some example embodiments of the inventive concepts.

[0155] Reference Figure 29 The chip region CHR of the semiconductor device may include a plurality of logic regions. For example, the chip region CHR may include a first logic region LG1 and a second logic region LG2. The chip region CHR may be a semiconductor wafer (eg, a logic wafer or a logic chip).

[0156] The first logic region LG1 may include the above-referenced Figure 1 and Figures 2A to 2E For example, a FinFET may be provided on the first logic region LG1. The second logic region LG2 may include the transistors discussed above. Figure 15 and 16A to 16F For example, a multi-bridge channel FET (MBCFET) may be provided on the second logic region LG2.

[0157] A semiconductor device according to the present invention may include an amorphous first barrier pattern interposed between a second metal pattern including an n-type work function metal and a second barrier pattern having grains. The first barrier pattern can prevent the second metal pattern from accepting materials such as fluorine, thereby reducing or preventing problems associated with a reduction in the effective work function of the gate electrode. As a result, a desired threshold voltage of the transistor can be achieved.

[0158] Although some exemplary embodiments of the present invention have been discussed with reference to the accompanying drawings, it should be understood that various changes in form and details may be made without departing from the scope of the present invention. Therefore, it should be understood that the above embodiments are illustrative in all aspects and not restrictive.

Claims

1. A semiconductor device comprising: a first active pattern located on a first region of the substrate; a pair of first source / drain patterns, located on the first active pattern; a first channel pattern located between the pair of first source / drain patterns; and a gate electrode extending across the first channel pattern, wherein the gate electrode is located on the uppermost surface and at least one sidewall of the first channel pattern, and Wherein, the gate electrode comprises: a first metal pattern comprising a p-type work function metal; a second metal pattern located on the first metal pattern, wherein the second metal pattern comprises an n-type work function metal; a first barrier pattern on the second metal pattern, the first barrier pattern including an amorphous metal layer including tungsten (W), carbon (C), and nitrogen (N); and a second barrier pattern, which is located on the first barrier pattern, Wherein, the second barrier pattern includes the p-type work function metal.

2. The semiconductor device according to claim 1, wherein The second barrier pattern has a plurality of grains and grain boundaries between the grains.

3. The semiconductor device according to claim 1, in, The gate electrode further includes an electrode pattern on the second barrier pattern, and The electrode pattern includes at least one low-resistance metal, and the low-resistance metal includes aluminum (Al), tungsten (W), titanium (Ti) or tantalum (Ta).

4. The semiconductor device according to claim 1, in, The p-type work function metal includes a metal nitride layer, and the metal nitride layer includes a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a titanium oxynitride (TiON) layer, a titanium silicon nitride (TiSiN) layer, a titanium aluminum nitride (TiAlN) layer, a tungsten carbonitride (WCN) layer, or a molybdenum nitride (MoN) layer, and The n-type work function metal includes aluminum-doped titanium carbide (TiAlC), aluminum-doped tantalum carbide (TaAlC), aluminum-doped vanadium carbide (VAlC), silicon-doped titanium carbide (TiSiC), silicon-doped tantalum carbide (TaSiC), aluminum-silicon-doped titanium carbide (TiAlSiC), aluminum-silicon-doped tantalum carbide (TaAlSiC) or aluminum-doped titanium (TiAl).

5. The semiconductor device according to claim 1, in, The atomic percentage of tungsten in the first barrier pattern is greater than the atomic percentage of carbon in the first barrier pattern, and The atomic percentage of tungsten in the first barrier pattern is greater than the atomic percentage of nitrogen in the first barrier pattern.

6. The semiconductor device according to claim 1, in, The thickness of the second barrier pattern is greater than that of the second metal pattern, and Wherein, the thickness of the second metal pattern is greater than the thickness of the first barrier pattern.

7. The semiconductor device according to claim 1, in, The uppermost surface of the first metal pattern is lower than the uppermost surface of the gate electrode, and Wherein, the second metal pattern is located on the uppermost surface of the first metal pattern.

8. The semiconductor device according to claim 1, in, The first channel pattern includes a plurality of stacked semiconductor patterns, wherein the first metal pattern and the second metal pattern are located in a first space between adjacent semiconductor patterns among the plurality of semiconductor patterns vertically spaced apart from each other, and The first barrier pattern and the second barrier pattern are not in the first space.

9. The semiconductor device according to claim 8, wherein The first and second metal patterns and the first and second barrier patterns are located in a second space located on an uppermost semiconductor pattern among the plurality of semiconductor patterns.

10. The semiconductor device according to claim 1, further comprising: a second active pattern located on a second region of the substrate; a pair of second source / drain patterns, which are located on the second active pattern; as well as a second channel pattern located between the pair of second source / drain patterns, wherein the gate electrode further extends across the second channel pattern, wherein the first region is a p-type metal oxide semiconductor field effect transistor region, and the second region is an n-type metal oxide semiconductor field effect transistor region, and A first thickness of a first portion of the first metal pattern on the first channel pattern is greater than a second thickness of a second portion of the first metal pattern on the second channel pattern.

11. A semiconductor device comprising: a substrate comprising an active pattern; a device isolation layer, located on a lower sidewall of the active pattern, wherein an upper portion of the active pattern protrudes beyond an uppermost surface of the device isolation layer; a pair of source / drain patterns located on the active pattern; a channel pattern located between the pair of source / drain patterns; as well as a gate electrode extending across the channel pattern, Wherein, the gate electrode comprises: a first metal pattern comprising a p-type work function metal; a second metal pattern located on the first metal pattern, wherein the second metal pattern comprises an n-type work function metal; a first barrier pattern on the second metal pattern, the first barrier pattern comprising an amorphous metal layer including tungsten (W), carbon (C), and nitrogen (N); a second barrier pattern located on the first barrier pattern, the second barrier pattern comprising the p-type work function metal; and a third barrier pattern located between the second metal pattern and the first barrier pattern, Wherein, the third barrier pattern includes the p-type work function metal.

12. The semiconductor device according to claim 11, in, The gate electrode further includes an electrode pattern on the second barrier pattern, and The electrode pattern includes at least one low-resistance metal, and the low-resistance metal includes aluminum (Al), tungsten (W), titanium (Ti) or tantalum (Ta).

13. The semiconductor device according to claim 11, in, The p-type work function metal includes a metal nitride layer, and the metal nitride layer includes a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a titanium oxynitride (TiON) layer, a titanium silicon nitride (TiSiN) layer, a titanium aluminum nitride (TiAlN) layer, a tungsten carbonitride (WCN) layer, or a molybdenum nitride (MoN) layer, and The n-type work function metal includes aluminum-doped titanium carbide (TiAlC), aluminum-doped tantalum carbide (TaAlC), aluminum-doped vanadium carbide (VAlC), silicon-doped titanium carbide (TiSiC), silicon-doped tantalum carbide (TaSiC), aluminum-silicon-doped titanium carbide (TiAlSiC), aluminum-silicon-doped tantalum carbide (TaAlSiC) or aluminum-doped titanium (TiAl).

14. The semiconductor device according to claim 11, in, The thickness of the second barrier pattern is greater than that of the second metal pattern, and Wherein, the thickness of the second metal pattern is greater than the thickness of the first barrier pattern.

15. The semiconductor device according to claim 11, in, The uppermost surface of the first metal pattern is lower than the uppermost surface of the gate electrode, and Wherein, the second metal pattern is located on the uppermost surface of the first metal pattern.

16. A semiconductor device comprising: a substrate comprising a plurality of active patterns spaced apart from each other in a first direction; a device isolation layer located on a lower sidewall of each of the plurality of active patterns, an upper portion of each of the plurality of active patterns protruding beyond an uppermost surface of the device isolation layer; a pair of source / drain patterns located on each of the plurality of active patterns; a channel pattern located between the pair of source / drain patterns; a gate electrode extending across the channel pattern in the first direction; as well as a gate dielectric pattern located between the gate electrode and the channel pattern, wherein the gate dielectric pattern is located on an upper portion of each of the plurality of active patterns, and Wherein, the gate electrode comprises: a first metal pattern comprising a p-type work function metal; a second metal pattern located on the first metal pattern, wherein the second metal pattern comprises an n-type work function metal; a first barrier pattern on the second metal pattern, the first barrier pattern including an amorphous metal layer including tungsten (W), carbon (C), and nitrogen (N); and a second barrier pattern, which is located on the first barrier pattern, Wherein, the second barrier pattern comprises the p-type work function metal, The thickness of the first barrier pattern is within a range of 1 nm to 5 nm. wherein the thickness of the second barrier pattern falls within a range of 5 nm to 70 nm, and The first barrier pattern is located between adjacent channel patterns among the channel patterns spaced apart from each other in the first direction.

17. The semiconductor device according to claim 16, in, The second barrier pattern has a plurality of grains and grain boundaries between the grains, and The first barrier pattern has no grain boundaries.

18. The semiconductor device according to claim 16, in, The gate electrode further includes an electrode pattern on the second barrier pattern, and The electrode pattern includes at least one low-resistance metal, and the low-resistance metal includes aluminum (Al), tungsten (W), titanium (Ti) or tantalum (Ta).

19. The semiconductor device according to claim 16, in, The p-type work function metal includes a metal nitride layer, and the metal nitride layer includes a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a titanium oxynitride (TiON) layer, a titanium silicon nitride (TiSiN) layer, a titanium aluminum nitride (TiAlN) layer, a tungsten carbonitride (WCN) layer, or a molybdenum nitride (MoN) layer, and The n-type work function metal includes aluminum-doped titanium carbide (TiAlC), aluminum-doped tantalum carbide (TaAlC), aluminum-doped vanadium carbide (VAlC), silicon-doped titanium carbide (TiSiC), silicon-doped tantalum carbide (TaSiC), aluminum-silicon-doped titanium carbide (TiAlSiC), aluminum-silicon-doped tantalum carbide (TaAlSiC) or aluminum-doped titanium (TiAl).

20. The semiconductor device according to claim 16, in, The uppermost surface of the first metal pattern is lower than the uppermost surface of the gate electrode, and Wherein, the second metal pattern is located on the uppermost surface of the first metal pattern.

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