Storage device, operation method thereof and electronic device including the same

Abstract

A storage device, an operation method thereof, and an electronic device including the same are provided. The storage device includes a nonvolatile memory and a controller, the nonvolatile memory including a main metadata area and a log area. The controller updates an address mapping table by executing a flash translation layer (FTL) stored in a working memory, the address mapping table including a plurality of page mapping entries divided into a plurality of segments; stores updated page mapping entries among the plurality of page mapping entries as log data in the log area; and stores the plurality of segments in the main metadata area, the plurality of segments each having a size smaller than a physical page of the nonvolatile memory.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0088963 filed in the Korean Intellectual Property Office on July 23, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the inventive concept described herein relate to a storage device for improving log replay, an operating method thereof, and an electronic device including the storage device. Background Art

[0004] A storage device as a non-volatile storage medium can retain data permanently or semi-permanently regardless of whether power is supplied thereto. The storage device may include both non-volatile memory and volatile memory, the capacity of the volatile memory being smaller than that of the non-volatile memory but having a fast input / output speed. For example, the storage device may use the volatile memory as a cache memory with respect to the non-volatile memory.

[0005] However, when power events such as sudden power outage (SPO) and system crash occur, data stored in the volatile memory of the storage device may be lost. Therefore, in order to prevent data loss, the storage device may store the data stored in the volatile memory in the non-volatile memory. Summary of the invention

[0006] According to an exemplary embodiment of the present invention, a storage device includes a nonvolatile memory and a controller, wherein the nonvolatile memory includes a main metadata area and a log area. The controller updates an address mapping table by executing a flash translation layer (FTL) stored in a working memory, wherein the address mapping table includes a plurality of page mapping entries divided into a plurality of segments; an updated page mapping entry among the plurality of page mapping entries is stored as log data in the log area; and the plurality of segments are stored in the main metadata area, wherein the plurality of segments each have a size smaller than a physical page of the nonvolatile memory.

[0007] According to an exemplary embodiment of the present invention, a method for operating a storage device includes a controller and a non-volatile memory, the controller is configured to execute a flash translation layer (FTL), and the non-volatile memory includes a main metadata area and a log area. The method includes: updating an address mapping table including a plurality of page mapping entries by the controller; storing updated page mapping entries among the plurality of page mapping entries as log data in the log area; and based on the order in which the updated page mapping entries are stored in the log area and the number of the updated page mapping entries of each of the plurality of fragments into which the plurality of page mapping entries are divided, storing the plurality of fragments in the main metadata area.

[0008] According to an exemplary embodiment of the present invention, an electronic device includes a host and a storage device, the host is configured to send a request including a logical address, and the storage device includes a non-volatile memory and a controller. The non-volatile memory includes a main metadata area and a log area. The controller is configured to: update an address mapping table by processing the request of the host, the address mapping table including a plurality of page mapping entries divided into a plurality of fragments; store updated page mapping entries in the plurality of page mapping entries as log data in the log area; and store the plurality of fragments in the main metadata area, the plurality of fragments each having a size smaller than a physical page of the non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the present inventive concept will become apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the attached drawings.

[0010] Figure 1 A block diagram of an electronic device according to an exemplary embodiment of the inventive concept is shown.

[0011] Figure 2 A block diagram of an electronic device according to an exemplary embodiment of the inventive concept is shown.

[0012] Figures 3 to 6 A diagram for describing how a controller according to an exemplary embodiment of the inventive concept stores metadata in a nonvolatile memory is shown.

[0013] Figure 7 and Figure 8 An example in which a controller according to an exemplary embodiment of the inventive concept stores metadata together with a time stamp is illustrated.

[0014] Fig. 9 A flowchart including a process in which a controller stores an address mapping table in a nonvolatile memory according to an exemplary embodiment of the inventive concept is shown.

[0015] Fig.10 An exemplary embodiment according to the present invention is shown. Fig. 9 FIG. 1 is a flowchart of detailed operations of operation S160 .

[0016] Fig.11 A flowchart including a process in which a controller restores an address mapping table according to an exemplary embodiment of the inventive concept is shown.

[0017] Fig.12 An exemplary embodiment according to the present inventive concept is shown. Figure 1 Detailed block diagram of the controller.

[0018] Fig.13 An exemplary embodiment according to the present inventive concept is shown. Figure 2 Detailed block diagram of the controller.

[0019] Fig.14 A block diagram of an electronic device according to an exemplary embodiment of the inventive concept is shown.

[0020] Fig.15 is a block diagram illustrating a computing system including a storage device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0021] Exemplary embodiments of the inventive concept provide a storage device for improving journal replay, an operating method thereof, and an electronic device including the storage device.

[0022] Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings.Throughout the application, like reference numerals may refer to like elements.

[0023] Figure 1 A block diagram of an electronic device according to an exemplary embodiment of the inventive concept is shown. The electronic device 10a may be a personal computer, a workstation, a notebook, a tablet computer, a mobile device, or a smart phone, and may be referred to as a "computing system", "electronic system", or "mobile system". The electronic device 10a may include a host 11 and a storage device 100a.

[0024] The host 11 may send a command CMD to the storage device 100a. The host 11 may exchange data "DATA" with the storage device 100a. The host 11 may receive a response RSP to the command CMD from the storage device 100a. The host 11 may be implemented to include one or more processor cores. For example, the host 11 may include a general-purpose processor, a dedicated processor, or an application processor. The host 11 may be the processor itself, or the host 11 may be a system or electronic device including a processor.

[0025] The storage device 100a may communicate with the host 11 according to various interface protocols. For example, the storage device 100a may be a solid state drive (SSD), an embedded memory card integrated in the electronic device 10a, a removable memory card of the electronic device 10a, a secure digital (SD) card, an embedded multimedia card (eMMC), a universal flash memory (UFS) card, etc. The storage device 100a may include a controller 110a and a non-volatile memory 130. The controller 110a may write data "DATA" into the non-volatile memory 130 based on a command CMD of the host 11; or, based on a command CMD of the host 11, the controller 110a may read data "DATA" from the non-volatile memory 130, and may send the read data "DATA" to the host 11. The controller 110a may process the command CMD, and may send a response RSP indicating a processing result to the host 11. The controller 110a may include a working memory 112a having a faster data input / output speed than the non-volatile memory 130. The controller 110 a may use the working memory 112 a as a cache memory.

[0026] The controller 110a may execute a flash translation layer (FTL) stored in the working memory 112a. The FTL may be loaded into the working memory 112a as firmware or a program stored in a ROM or non-volatile memory 130 of the storage device 100a. The FTL may exist in the file system of the host 11 (refer to Fig.14 ) and the non-volatile memory 130. The FTL may perform an address mapping operation to manage the mapping between the logical address provided from the host 11 and the physical address of the non-volatile memory 130. In addition to performing the address mapping operation, the FTL may also perform a garbage collection operation, a wear leveling operation, and the like. The FTL may be executed by the controller 110a to address the following limitations of the non-volatile memory 130: non-rewritable or non-in-place write, the life of the memory cell, a limited number of program / erase cycles, and an erase speed that is slower than a write speed. When the logical address is sent from the host 11 to the controller 110a together with a command CMD or a request and the controller 110a processes the command CMD or the request, the FTL may update an address mapping table AMT including information about the mapping between the logical address and the physical address. The address mapping table AMT may be stored in the working memory 112a.

[0027] The FTL may manage a fragment mapping table SMT indicating a location of the nonvolatile memory 130 where mapping information of the address mapping table AMT is stored. The fragment mapping table SMT may be stored in the working memory 112a, and the size of the fragment mapping table SMT may be smaller than the size of the address mapping table AMT. When the controller 110a processes a request from the host 11, the FTL may update a portion of the mapping information in the address mapping table AMT (partial mapping information), and may store the updated information of the address mapping table AMT in the log buffer JB. The log buffer JB may be located at the working memory 112a.

[0028] The working memory 112a may include or store FTL, an address mapping table AMT, a segment mapping table SMT, and a log buffer JB. The working memory 112a may include an area for storing FTL, an area for storing the address mapping table AMT, an area for storing the segment mapping table SMT, and an area allocated to the log buffer JB, and the controller 110a may pre-set the above areas in the working memory 112a, or may adjust the above areas according to the request of the host 11 or the user. For example, the working memory 112a may be a storage medium or on-chip memory including latches, registers, static random access memory (SRAM), dynamic random access memory (DRAM), thyristor random access memory (TRAM), tightly coupled memory (TCM), etc.

[0029] Under the control of the controller 110a, the nonvolatile memory 130 may store (or write or program) data, or may provide the data stored therein to the controller 110a. The nonvolatile memory 130 may include a user data area USER DATA and a reserved area OP. The user data area USER DATA may be an area allocated to the host 11, and may store data based on a request of the host 11. The reserved area OP may not be an area allocated to the host 11, and may not be open to the host 11. The controller 110a may use the reserved area OP to manage the nonvolatile memory 130. For example, the reserved area OP may also be referred to as a "metadata area".

[0030] For example, when a power event such as a sudden power outage (SPO) or a system crash (volatile) occurs, the metadata stored in the working memory 112a may be lost. The metadata may include the address mapping table AMT, the segment mapping table SMT, and the update information of the address mapping table AMT stored in the log buffer JB (hereinafter referred to as "log data"). In addition, the metadata may also include information about the read / write unit (e.g., page) of the non-volatile memory 130, about the erase unit (e.g., block BLK (refer to Fig.14 )) information, etc. In order to prevent the above loss, the controller 110a may store the metadata stored in the working memory 112a in a reserved area OP of the non-volatile memory 130. The FTL may store the address mapping table AMT in the main metadata areas MMA1 and MMA2, the segment mapping table SMT in the segment mapping table area SMTA, and the log data stored in the log buffer JB in the log areas JA1 and JA2. The controller 110a may set the above areas in the working memory 112a in advance, or may adjust the above areas according to the request of the host 11 or the user. The non-volatile memory 130 may include non-volatile memory cells such as NAND flash memory cells, NOR flash memory cells, resistive random access memory (RRAM) cells, ferroelectric random access memory (FRAM) cells, phase change random access memory (PRAM) cells, or magnetic random access memory (MRAM) cells.

[0031] Figure 2 A block diagram of an electronic device according to an exemplary embodiment of the inventive concept is shown. The electronic device 10b may include a host 11 and a storage device 100b. The electronic device 10b may be substantially the same as the electronic device 10a except for the storage device 100b. The storage device 100b may include a controller 110b and a non-volatile memory 130. Compared with the storage device 100a, the storage device 100b may further include a buffer memory 120. The controller 110b may include a working memory 112b substantially the same as the working memory 112a, and unlike the controller 110a, the controller 110b may further use the buffer memory 120 as a high-speed cache memory. For example, the buffer memory 120 may be located outside the controller 110b.

[0032] The controller 110b may store and load the address mapping table AMT into the buffer memory 120. Figure 1Different from the example shown, the controller 110b can store and load the address mapping table AMT to both the working memory 112b and the buffer memory 120. As the capacity of the non-volatile memory 130 increases, the size of the address mapping table AMT can increase. In this case, the address mapping table AMT can be stored in the buffer memory 120 located outside the controller 110b. For example, the buffer memory 120 can be a storage medium including latches, registers, SRAM, DRAM, TRAM, TCM, etc. The controller 110b can store and load the FTL, the segment mapping table SMT and the log buffer JB to the working memory 112b. In addition to the storage device 100b also including the buffer memory 120, the operation of the storage device 100b can be similar to the operation of the storage device 100a. In the following, the storage device 100 may refer to one of the storage devices 100a and 100b, the controller 110 may refer to one of the controllers 110a and 110b, and the working memory 112 may refer to one of the working memories 112a and 112b.

[0033] The FTL executed by the controller 110 of the storage device 100 according to an exemplary embodiment of the present invention can reduce the time or cost of performing log replay, which is used to restore the address mapping table AMT loaded into the working memory 112 or the buffer memory 120 based on the information read from the log areas JA1 and JA2 of the non-volatile memory 130.

[0034] Figures 3 to 6 FIG. 1 is a diagram for describing how a controller according to an exemplary embodiment of the inventive concept stores metadata in a nonvolatile memory. Figure 1 and Figure 2 To describe Figures 3 to 6 .

[0035] The address mapping table AMT may include a page mapping entry PME. The page mapping entry PME may store a physical address PA corresponding to the logical address LA. The location of the page mapping entry PME on the address mapping table AMT may correspond to the logical page number LPN, and the page mapping entry PME may store a physical page number PPN corresponding to the logical page number LPN. Figure 3 , some page mapping entries PME of the address mapping table AMT may store physical page numbers PPNa to PPNd corresponding to the logical page numbers LPN1 to LPN3 and LPN20, respectively. Here, the logical page numbers LPN1 to LPN3 and LPN20 and the physical page numbers PPNa to PPNd are only examples. The physical page numbers PPNa to PPNd may indicate the physical page numbers allocated to the Figure 1 and Figure 2For example, the page mapping entries PME of the address mapping table AMT may be implemented in the form of an array and may be divided in units of pages. The page of the address mapping table AMT may correspond to the data input / output size of the file system executable on the host 11 and may be 4KB, but the inventive concept is not limited to the above values. The number of page mapping entries PME of the address mapping table AMT is not limited to Figures 3 to 6 Example shown.

[0036] The segment mapping table SMT may indicate the location (or physical address PA) of the storage segment SG of the main metadata area MMA1 of the nonvolatile memory 130. The segments SG1 to SG8 may include page mapping entries PME of the address mapping table AMT. The page mapping entries PME of the address mapping table AMT may be divided into segments SG1 to SG8. The size of a physical page (NVM page) of the nonvolatile memory 130 may correspond to a write unit or a read unit of the nonvolatile memory 130, and the size of the segment SG may be smaller than the size of the physical page of the nonvolatile memory 130. Generally, when data having the size of the physical page of the nonvolatile memory 130 is collected, this data may be written into the nonvolatile memory 130. Without using the segment mapping table SMT, the controller 110 may write the page mapping entry PME into the main metadata area MMA1 in units of the size of the physical page of the nonvolatile memory 130. For example, the controller 110 may change or adjust the size of the segment SG.

[0037] In contrast, the controller 110 according to an exemplary embodiment of the inventive concept may logically divide one physical page of the nonvolatile memory 130 that is not physically divided into smaller pieces into a plurality of fragments, may collect page mapping entries PME in units of the size of the fragments, and may write the fragments in units of the size of one physical page of the nonvolatile memory 130 into the main metadata area MMA1. Figure 3 , the segment mapping table SMT may include segments SG1 to SG8 and physical page numbers PPN1 to PPN4 indicating storage locations of the segments SG1 to SG8 and offsets OFF1 and OFF2. Offset OFF1 may indicate the location of a specific area of ​​the physical page, and offset OFF2 may indicate the location of another area of ​​the physical page. In the case of dividing one physical page into two or more segments, the number of offsets may increase according to the number of segments.

[0038] For the convenience of description and explanation, an example is shown in which the page size of the address mapping table AMT is the same as the size of the segment SG, but the page size of the address mapping table AMT and the size of the segment SG may be different from each other. The number of page mapping entries PME allocated to the segment SG, the number of segments per physical page, and the number of physical pages included in the main metadata area MMA1 are not limited to Figure 3 In the example shown, the main metadata area MMA1 may include one or more blocks.

[0039] exist Figure 3 In FIG. 1 , it is assumed that the page mapping entries of the address mapping table AMT stored in the working memory 112 or the buffer memory 120 are stored or written in the main metadata area MMA1 of the nonvolatile memory 130. Figure 3 In the embodiment, the address mapping table AMT stored in the working memory 112 or the buffer memory 120 may be consistent with (identical, the same as, or matched with) the address mapping table AMT stored in the main metadata area MMA1 of the nonvolatile memory 130 .

[0040] The controller 110 may execute the FTL, and the FTL may update the address mapping table AMT. For example, the FTL may update the physical page numbers corresponding to the logical page numbers LPN1 to LPN3 and LPN20 from Figure 3 PPNa to PPNd is updated or changed to Figure 4 The physical page numbers PPNe to PPNh may indicate some remaining physical pages among the physical pages of the block allocated to the user data area USER DATA. The page mapping entry updated by the FTL is in Figure 4 The number and location of updated page mapping entries are not limited to Figure 4 In this case, the address mapping table AMT stored in the working memory 112 or the buffer memory 120 may be different from the address mapping table AMT stored in the main metadata area MMA1 of the nonvolatile memory 130 .

[0041] Instead of writing the entire address mapping table AMT (e.g., all page mapping entries of the address mapping table AMT) into the nonvolatile memory 130 to achieve data consistency, the FTL may store or collect updated page mapping entries U1 from among all page mapping entries of the address mapping table AMT in a log buffer JB of the working memory 112, and then may store or write the updated page mapping entries U1 stored in the log buffer JB into the log area JA1 of the nonvolatile memory 130. For example, when the log buffer JB becomes full as the updated page mapping entries U1 are stored in the log buffer JB, the FTL may store the updated page mapping entries stored in the log buffer JB in the log area JA1 of the nonvolatile memory 130.

[0042] Reference Figure 4 , the FTL may update the page mapping entry U1, and may store the logical page numbers LPN1 to LPN3 and LPN20 of the page mapping entry U1 and the updated physical page numbers PPNe to PPNh in the log buffer JB. For example, each page mapping entry PME may store only the physical page number PPN corresponding to the logical page number LPN, while each log entry JE of the log buffer JB may store both the physical page number PPN and the logical page number LPN. The size of each log entry JE may be larger than the size of each page mapping entry PME. The size of the log buffer JB may be the same as the size of the physical page of the non-volatile memory 130, or may be smaller than the size of the physical page of the non-volatile memory 130. The number of log entries JE of the log buffer JB is not limited to Figure 4 The example shown, and the log entry JE can correspond to the log data.

[0043] When updating the address mapping table AMT, the FTL may also update the segment mapping table SMT. The number and location of the updated segments SG are not limited to Figure 4 The segment mapping table SMT may also include information about the time UT at which the segment SG is updated and information about the number (or count CNT) of updated page mapping entries U1 that each segment SG has.

[0044] Figure 4An example is shown in which three page mapping entries U1 of fragment SG3 are updated. In the fragment mapping table SMT, the FTL may mark the time when fragment SG3 is updated (hereinafter referred to as "update time") as "UT1", and may mark the number CNT of updated page mapping entries U1 of fragment SG3 as "3". For example, the update time of the updated page mapping entries U1 belonging to fragment SG3 may be the same or different, and the FTL may determine the update time of fragment SG3 based on the most recently updated page mapping entry. For example, the FTL may count the updated page mapping entries U1 of the page mapping entries belonging to fragment SG3. As described above, the FTL may mark the update time of fragment SG7 as "UT1", and may mark the number CNT of updated page mapping entries U1 of fragment SG7 as "1".

[0045] As described above, the FTL may determine the update time UT of the segment SG based on the most recently updated page mapping entry. As another example, the FTL may determine the update time UT of the segment SG based on the time at which the updated page mapping entry stored in the log buffer JB is stored in the log area JA1 or is sent to the log area JA1. The update times UT1 of the segments SG3 and SG7 in the segment mapping table SMT may be the same or different. In any case, the update time UT1 of the segments SG3 and SG7 may indicate the order in which the segments SG3 and SG7 are updated, or the order in which the updated page mapping entries U1 of the segments SG3 and SG7 are stored in the log area JA1.

[0046] The FTL may update the page mapping entry U1 and then may also update other page mapping entries U2 in the address mapping table AMT. Figure 5 , shows an example of a page mapping entry U2 updated by the FTL. The FTL may store or rewrite the updated page mapping entry PME in the log buffer JB. Thereafter, the FTL may store or write the updated page mapping entry U2 stored in the log buffer JB in the log area JA1 of the nonvolatile memory 130. Figure 4 and Figure 5 , the FTL may store the updated page mapping entry U1 at the physical page PPN5 of the log area JA1, and may store the updated page mapping entry U2 at the physical page PPN6 of the log area JA1. The FTL may update the page mapping entries U1 and U2 of the address mapping table AMT, may store the updated page mapping entries U1 and U2 in the log buffer JB, and may store the updated page mapping entries U1 and U2 in the log buffer JB in the log area JA1. The page mapping entries U1 and U2 updated by the controller 110 may be accumulated in the log area JA1 through the log buffer JB.

[0047] Reference Figure 5 , the FTL may update the page mapping entry U2, and may also update the fragment mapping table SMT. In the fragment mapping table SMT, the FTL may mark the time when the fragment SG1 is updated as "UT2", and may mark the number CNT of updated page mapping entries U2 of the fragment SG1 as "2". As described above, in the fragment mapping table SMT, the FTL may mark the time when the fragment SG5 is updated as "UT2", and may mark the number CNT of updated page mapping entries U2 of the fragment SG5 as "2". The FTL may identify (check) the update times UT1 and UT2 of the fragment mapping table SMT, and may identify that the fragments SG3 and SG7 are updated before the fragments SG1 and SG5, and the updated fragment mapping entries of the fragments SG3 and SG7 are stored in the log area JA1 before the updated fragment mapping entries of the fragments SG1 and SG5. The FTL may identify the count CNT of the fragment mapping table SMT, and may identify that the fragment SG3 has the largest number of updated page mapping entries U1, and the fragment SG7 has the smallest number of updated page mapping entries U1.

[0048] The number of physical pages allocated to the log area JA1 is not limited to Figure 5 In the example shown, the log area JA1 may include one or more blocks. However, the size or capacity of the log area JA1 allocated by the controller 110 may be limited, and the controller 110 may not be able to store updated page mapping entries in the log area JA1 indefinitely. For ease of description and explanation, it is assumed that when the updated page mapping entry U2 is stored in the physical page PPN6 of the log area JA1, the log area JA1 is full.

[0049] When the log area JA1 is full, the FTL may store the address mapping table AMT in the main metadata area MMA2 of the nonvolatile memory 130. The physical pages PPN1 to PPN4 of the main metadata area MMA2 are different from the physical pages PPN1 to PPN4 of the main metadata area MMA1, and the main metadata areas MMA1 and MMA2 are different areas. The page mapping entries PME of the address mapping table AMT may be divided into segments SG1 to SG8. Figures 3 to 6 , in order to describe data consistency, update of the address mapping table AMT, and log technology, segments SG1 and SG2, segments SG3 and SG4, segments SG5 and SG6, and segments SG7 and SG8 are shown as being sequentially stored in physical pages PPN1, PPN2, PPN3, and PPN4 of the main metadata area MMA1, respectively. However, according to an exemplary embodiment of the inventive concept, the FTL may store the segments SG1 to SG8 in the nonvolatile memory 130 based on priority.

[0050] The FTL may store the segments SG1 to SG8 in the main metadata area MMA2 with reference to the segment mapping table SMT. The FTL may identify the time (e.g., UT1 and UT2) when the segments SG1 to SG8 are updated, and may store the segments SG1 to SG8 in the main metadata area MMA2 based on the order in which the segments SG1 to SG8 are updated. For example, because the segments SG3 and SG7 are updated before the segments SG1 and SG5, the FTL may first store the segments SG3 and SG7 in the main metadata area MMA2, and then may store the segments SG1 and SG5 in the main metadata area MMA2.

[0051] In addition, the FTL may check the number CNT of updated page mapping entries (e.g., U1 and U2) of each of the segments SG1 to SG8, ​​and may store the segments SG1 to SG8 in the main metadata area MMA2 based on the number CNT of updated page mapping entries (e.g., U1 and U2) of each of the segments SG1 to SG8. For example, because the number of updated page mapping entries of the segment SG3 is greater than the number of updated page mapping entries of the segment SG7, the FTL may store the segment SG3 in the main metadata area MMA2, and then may store the segment SG7 in the main metadata area MMA2. However, even if the number of updated page mapping entries of each of the segments SG1 and SG5 is greater than the number of updated page mapping entries of the segment SG7, because the segment SG7 is updated before the segments SG1 and SG5, the FTL may still store the segment SG7 in the main metadata area MMA2 first. FTL may determine the priority of storing fragments SG1 to SG8 in the main metadata area MMA2 by first considering the update time (e.g., UT1 and UT2) of fragments SG1 to SG8 and then considering the number CNT of updated page mapping entries (e.g., U1 and U2) of each of fragments SG1 to SG8.

[0052] In an exemplary embodiment of the inventive concept, the FTL may determine the priority of storing metadata in the nonvolatile memory 130 based on the type of metadata. As described above, the metadata type may include an address mapping table AMT (the address mapping table AMT includes information about page mapping between logical addresses and physical addresses), a segment mapping table SMT, and log data, and may also include information about the nonvolatile memory 130 (e.g., information about a physical page as a read / write unit and information about a block as an erase unit). For example, the FTL may store the information about the page mapping between the logical address and the physical address in the nonvolatile memory 130 before storing the information about the nonvolatile memory 130. The FTL may determine the priority of storing metadata in the nonvolatile memory 130 in consideration of the update time (e.g., UT1 and UT2) of the segments SG1 to SG8, ​​the number CNT of updated page mapping entries (e.g., U1 and U2) of each of the segments SG1 to SG8, ​​and the type of metadata.

[0053] Figure 5 and Figure 6 An example is shown in which the number of segments updated at the same or similar time UT1 (i.e., SG3 and SG7) is 2 and the number of segments updated at the same or similar time UT2 (i.e., SG1 and SG5) is 2. However, the number of segments updated at the same or similar time may be more than 2. The FTL may determine the priority of storing the segments updated at the same or similar time in the main metadata area MMA2 with reference to the number CNT of updated page mapping entries (e.g., U1 / U2) of each segment updated at the same or similar time. The FTL may store a segment having a relatively large number of updated page mapping entries in the main metadata area MMA2 before a segment having a relatively small number of updated page mapping entries.

[0054] Based on the above priorities, the FTL may store the segments SG3 and SG7 updated at time UT1 in the physical page PPN1 of the main metadata area MMA2, may store the segments SG1 and SG5 updated at time UT2 in the physical page PPN2 of the main metadata area MMA2, and may store the remaining segments SG2, SG4, SG6, and SG8 that are not updated in the physical pages PPN3 and PPN4 of the main metadata area MMA2. The controller 110 may send data of one physical page unit to the nonvolatile memory 130, and the nonvolatile memory 130 may store or write the data sent from the controller 110 at a location (e.g., a physical page) requested by the controller 110. Figure 6, it is assumed that the controller 110 transmits data to be stored at one physical page to the nonvolatile memory 130 , but the controller 110 may transmit data to be stored at one or more physical pages to the nonvolatile memory 130 .

[0055] At write time W1, fragments SG3 and SG7 may be stored in physical page PPN1 of main metadata area MMA2; at write time W2 after write time W1, fragments SG1 and SG5 may be stored in physical page PPN2 of main metadata area MMA2; at write time W3 after write time W2, fragments SG2 and SG4 may be stored in physical page PPN3 of main metadata area MMA2; at write time W4 after write time W3, fragments SG6 and SG8 may be stored in physical page PPN4 of main metadata area MMA2. At write time W4, in the case where all fragments SG of address mapping table AMT are stored in main metadata area MMA2, the address mapping table AMT stored in main metadata area MMA2 may be the most recent (latest) compared to the address mapping table AMT stored in main metadata area MMA1. After write time W4, FTL may invalidate the address mapping table AMT stored in main metadata area MMA1, and may erase the address mapping table AMT stored in main metadata area MMA1. The FTL may erase at least one block allocated to the main metadata area MMA1 in the non-volatile memory 130 .

[0056] As described above, the FTL may store fragments SG1 to SG8 in the main metadata area MMA2 based on priority. The address mapping table AMT stored in the main metadata area MMA1 may be invalidated at write time W4; in contrast, because fragments SG1 to SG8 are stored in the main metadata area MMA2 based on priority, log data associated with updated page mapping entries U1 and U2 stored in the log area JA1 may be invalidated before write time W4. When fragments SG3 and SG7 are stored in the main metadata area MMA2 at write time W1, log data associated with page mapping entry U1 of physical page PPN5 stored in the log area JA1 may be invalidated at write time W1. Similarly, when fragments SG1 and SG5 are stored in the main metadata area MMA2 at write time W2, log data associated with page mapping entry U2 of physical page PPN6 stored in the log area JA1 may be invalidated at write time W2. Based on the priority, the FTL may store the segment having the log data stored in the log area JA1 in the main metadata area MMA2, and may invalidate the log data stored in the log area JA1 relatively early. For example, the FTL may erase the log data stored in the log area JA1 after the write time W2. The FTL may erase at least one block allocated to the log area JA1 in the non-volatile memory 130.

[0057] According to an exemplary embodiment of the present invention, the FTL may store segments SG1 to SG8 in the main metadata area MMA2 based on priority. The FTL may store the segments SG in the main metadata area MMA2 in the order in which the log data is stored in the log area JA1, and may store the segments SG in the main metadata area MMA2 in descending order starting from the segment with the largest number of updated page mapping entries. According to an exemplary embodiment of the present invention, since the log data stored in the log area JA1 is invalidated relatively early, the time or cost of performing log replay may be reduced, and the log replay is an operation in which the FTL reads the log data stored in the log area JA1 and updates the address mapping table AMT on the working memory 112 or the buffer memory 120 based on the log data. For example, as the amount of log data to be invalidated increases, the amount of log data read by the FTL may be reduced. In addition, the write amplification factor (WAF) of the storage device 100 may be improved. In addition, after the storage device 100 is powered on or a power supply voltage is provided to the storage device 100, the time spent on initializing the storage device 100 may be reduced.

[0058] In an exemplary embodiment of the present inventive concept, the FTL may store the segments SG1 to SG8 in the main metadata area MMA2 based on the priority, and may update the segment mapping table SMT so that the segment mapping table SMT has the locations of the storage segments SG1 to SG8 of the main metadata area MMA2. The segment mapping table SMT may include the locations (e.g., PPN1 and OFF1) of the storage segment SG3 of the non-volatile memory 130. Like the location of the segment SG3, the locations of the remaining segments SG1, SG2, and SG4 to SG8 may be updated in the segment mapping table SMT. For example, the FTL may store the updated segment mapping table SMT in the segment mapping table area SMTA of the non-volatile memory 130 after the write time W4.

[0059] The FTL may also update the address mapping table AMT on the working memory 112 or the buffer memory 120 after the write time W4 or while storing the address mapping table AMT in the main metadata area MMA2. Figure 6 , the FTL may update the page mapping entry marked with "U3" in the address mapping table AMT. The FTL may store or rewrite the updated page mapping entry U3 in the log buffer JB. The FTL may store or write the updated page mapping entry U3 stored in the log buffer JB in the log area JA2 of the non-volatile memory 130. Figures 3 to 5 , the above process is similar to the operation of storing and accumulating log data in the log area JA1. The physical pages PPN5 and PPN6 of the log area JA1 are different from the physical page PPN5 of the log area JA2, and the log areas JA1 and JA2 are different. When the log area JA2 is full, the FTL may store the address mapping table AMT in a main metadata area different from the main metadata area MMA2. The different main metadata area may be the (erased) main metadata area MMA1, or may be a main metadata area additionally allocated for storing the address mapping table AMT of the reserved area OP of the nonvolatile memory 130. One main metadata area and one log area may configure (constitute) a group, and refer to Figures 3 to 6 An example in which the number of groups is 2 is described. However, the number of groups in the reserved area OP may be more than 2. Figures 3 to 6 As described, the FTL may store the address mapping table AMT and the log data of the log buffer JB in two or more groups repeatedly and indefinitely.

[0060] Figure 7 and Figure 8An example in which a controller according to an exemplary embodiment of the inventive concept stores metadata together with a timestamp is shown. For example, the controller 110 may generate a timestamp and may send the metadata together with the timestamp to the nonvolatile memory 130. The nonvolatile memory 130 may store the metadata and the timestamp at a location requested by the controller 110.

[0061] Figures 3 to 6 An example is shown in which each physical page of the nonvolatile memory 130 stores two segments, but the inventive concept is not limited thereto. Figure 7 and Figure 8 An example is shown in which each physical page of the nonvolatile memory 130 stores two or more fragments. The number of physical pages and the number of blocks allocated to the main metadata areas MMA1 and MMA2 and the log areas JA1 and JA2 are not limited to Figure 7 and Figure 8 Example shown.

[0062] Reference Figure 7 , the controller 110 may send a plurality of segments (e.g., SG111 to SG11y: y is a natural number) and a timestamp (e.g., TS11) to the nonvolatile memory 130. In this case, the total size of the plurality of segments SG111 to SG11y and the timestamp TS11 may correspond to the size of one physical page of the nonvolatile memory 130. The timestamp TS11 sent together with the plurality of segments SG111 to SG11y may indicate the time at which the segments SG111 to SG11y are sent to the nonvolatile memory 130 or stored in the nonvolatile memory 130. For example, the values ​​of the timestamps TS11 to TS1x (x is a natural number) of the physical pages stored in the main metadata area MMA1 may be different from the values ​​of the timestamps TS21 to TS2x stored in the physical pages of the main metadata area MMA2. Similar to the above manner in which the segments SG111 to SG11y and the time stamp TS11 are stored, the remaining segments SG121 to SG1xy and SG211 to SG2xy and the remaining time stamps TS12 to TS1x and TS21 to TS2x may be stored in the main metadata areas MMA1 and MMA2.

[0063] The controller 110 may send log entries (e.g., JE111 to JE11n: n is a natural number) stored in the log buffer JB and a timestamp TS31 to the nonvolatile memory 130. In this case, the total size of the log entries JE111 to JE11n and the timestamp TS31 may correspond to the size of one physical page of the nonvolatile memory 130. The log entries JE111 to JE11n may be log data. The timestamp TS31 sent together with the plurality of log entries JE111 to JE11n may indicate the time at which the log entries JE111 to JE11n are sent to the nonvolatile memory 130 or stored in the nonvolatile memory 130. For example, the values ​​of the log entries TS31 to TS3m of the physical page stored in the log area JA1 may be different from the values ​​of the log entries TS41 to TS4m of the physical page stored in the log area JA2. In addition, the values ​​of the timestamps TS31 to TS3m and TS41 to TS4m stored in the log areas JA1 and JA2 may be different from the values ​​of the timestamps TS11 to TS1x and TS21 to TS2x stored in the main metadata areas MMA1 and MMA2. Similar to the way the log entries JE111 to JE11n and the timestamp TS31 are stored above, the remaining log entries JE1m1 to JE1mn and JE211 to JE2mn and the remaining timestamps TS3m and TS41 to TS4m may be stored in the log areas JA1 and JA2.

[0064] Reference Figure 8 , the controller 110 may send one time stamp (e.g., TS111) for each segment (e.g., SG111) to the nonvolatile memory 130. In this case, the total size of the plurality of segments (e.g., SG111 to SG11y) and the plurality of time stamps (e.g., TS111 to TS11y) may correspond to the size of one physical page of the nonvolatile memory 130. Figure 8 The time stamps TS111 to TS1xy and TS211 to TS2xy may respectively indicate the times at which the segments SG111 to SG1xy and SG211 to SG2xy are transmitted to the nonvolatile memory 130 or stored in the nonvolatile memory 130. For example, the values ​​of the time stamps TS111 to TS1xy stored in the main metadata area MMA1 may be different from the values ​​of the time stamps TS211 to TS2xy stored in the main metadata area MMA2.

[0065] In an exemplary embodiment of the inventive concept, in case of restoring the address mapping table AMT, the FTL may identify time stamps TS11 to TS1x, TS21 to TS2x, TS31 to TS3m, and TS41 to TS4m (in Figure 7 ) or TS111 to TS1xy, TS211 to TS2xy, TS31 to TS3m and TS41 to TS4m (in Figure 8 Based on the timestamp TS, the FTL can identify the main metadata area storing the most recent address mapping table AMT from the main metadata areas MMA1 and MMA2, and can identify the log area storing the log data of the most recent address mapping table AMT from the log areas JA1 and JA2. In addition, the FTL can Figure 6 The timestamp TS of the log area JA1 and the main metadata area MMA2 makes the storage Figure 6 The log data in the log area JA1 is invalid. The FTL may restore the address mapping table AMT on the working memory 112 or the buffer memory 120 based on the most recent address mapping table AMT and the most recent log data.

[0066] Fig. 9 A flowchart showing a process in which a controller stores an address mapping table in a nonvolatile memory according to an exemplary embodiment of the inventive concept is shown. Figures 1 to 8 To describe Fig. 9 .

[0067] In operation S110, the controller 110 may receive a request from the host 11. The request from the host 11 may include a logical address. In operation S120, the controller 110 may update the address mapping table AMT, the log buffer JB, and the segment mapping table SMT according to the request from the host 11. In operation S120, the controller 110 may Figures 3 to 6 The controller 110 may update the page mapping entries U1, U2 and U3 of the address mapping table AMT as shown. Figures 3 to 6 The updated page mapping entries U1, U2 and U3 are stored or rewritten in the log buffer JB as shown. The controller 110 may Figures 3 to 6 The update times UT of the page mapping entries U1 , U2 , and U3 of the segments SG in the segment mapping table SMT and the numbers of the page mapping entries U1 , U2 , and U3 of the corresponding segments SG in the segment mapping table SMT are updated as shown.

[0068] In operation S130, the controller 110 may identify whether the log buffer JB is full. When the log buffer JB is full (yes), the controller 110 may perform operation S140; when the log buffer JB is not full (no), the controller 110 may repeatedly perform operations S110 to S130.

[0069] In operation S140, the controller 110 may store or rewrite the log data stored in the log buffer JB in the log area (one of JA1 and JA2) of the nonvolatile memory 130. Figure 7 and Figure 8 As described, the controller 110 may transmit the log data stored in the log buffer JB together with the time stamp to the nonvolatile memory 130. The log data stored in the log buffer JB and the time stamp may be stored together in the log area (one of JA1 and JA2).

[0070] In operation S150, the controller 110 may identify whether the log area (one of JA1 and JA2) is full. When the log area (one of JA1 and JA2) is full (yes), the controller 110 may perform operation S160; when the log area (one of JA1 and JA2) is not full (no), the controller 110 may repeatedly perform operations S110 to S150.

[0071] In operation S160, the controller 110 may write or store the segments SG of the address mapping table AMT in the new main metadata area (in Figure 6 The controller 110 may store the segment SG in the new main metadata area based on the priority while keeping the segment SG stored in another main metadata area (in Figure 6 In the case of MMA1) and the previous address mapping table AMT stored in the log area (in Figure 6 In the case of JA1), the log data in is invalid.

[0072] Fig.10 An exemplary embodiment according to the present invention is shown. Fig. 9 In operation S161, the controller 110 may store log data in a log area (in Figure 6 In the case of JA1), the fragment SG is selected in the order in which the fragment is selected. Figure 6 In this case, the controller 110 may select segments SG3 and SG7 corresponding to the log data previously stored in the log area JA1.

[0073] In operation S162, the controller 110 may select a segment SG according to the count CNT of the segment mapping table SMT. As described above, the count CNT of the segment mapping table SMT may indicate the number of updated page mapping entries for each segment SG. Figure 6 In the case of , the controller 110 may select segments SG3 and SG7. As another example, Figure 6Compared with the case where the number of segments selected in operation S161 is greater, the segment SG may be selected according to the count CNT of the segment mapping table SMT.

[0074] In operation S163, the controller 110 may transmit the segments selected in operations S161 and S162 to the main metadata area (in the Figure 6 In operation S164, the controller 110 may update the segment mapping table SMT so that the segment mapping table SMT has the location of the segment sent in operation S163 stored in the nonvolatile memory 130. In operation S165, the controller 110 may identify whether all segments SG of the address mapping table AMT are sent to the nonvolatile memory 130. When some segments SG are not sent to the nonvolatile memory 130 (No), the controller 110 may repeatedly perform operations S161 to S165; when all segments SG are sent to the nonvolatile memory 130 (Yes), the controller 110 may perform operation S166.

[0075] In operation S166, the controller 110 may erase the nonvolatile memory 130 allocated to the previous main metadata area (in Figure 6 In the case of MMA1), or an address mapping table AMT and log data stored in the block. In an exemplary embodiment of the present inventive concept, the controller 110 can identify the timestamps stored in each main metadata area and the timestamps stored in each log area, can identify main metadata areas and log areas that are not the most recent (for example, corresponding to previous main metadata areas and log areas), and can delete the data stored in the identified areas.

[0076] In an exemplary embodiment of the present inventive concept, the controller 110 may process the request of the host 11 received in operation S110 while performing operations S120 to S160 and operations S161 to S166. The operations respectively performed in operation S110 may be performed simultaneously or may be performed at different times. Fig. 9 and Fig.10 Operations S110 to S160 and operations S161 to S166 shown in the flowchart of FIG.

[0077] Fig.11A flowchart including a process of a controller restoring an address mapping table according to an exemplary embodiment of the present invention is shown. In operation S210, the storage device 100 may be powered on, or a power supply voltage may be provided to the storage device 100, and the controller 110 may start a recovery operation. The recovery operation may refer to the following process after a power event: metadata is read from the non-volatile memory 130, and the metadata is loaded again onto the working memory 112 or the buffer memory 120. The recovery operation requires a log replay as follows: the log data stored in the log area is read and the metadata loaded again is updated based on the log data (e.g., the address mapping table AMT).

[0078] In operation S220, the controller 110 may identify the timestamp stored in the main metadata area. The controller 110 may compare the timestamps to identify the main metadata area of ​​the latest date. In operation S230, the controller 110 may read the address mapping table AMT stored in the main metadata area with the latest timestamp. While the segments of the address mapping table AMT are stored in the main metadata area MMA2 (in Figure 6 In the event that a power event occurs during the time between the write time W1 and the write time W4 of the memory, all the fragments may not be normally stored in the main metadata area MMA2. In this case, the controller 110 may read the fragments stored in the main metadata area MMA2 with the most recent timestamp and the main metadata area MMA1 with the timestamp immediately before the most recent timestamp, and may load the address mapping table AMT obtained by combining the read fragments onto the working memory 112 or the buffer memory 120.

[0079] In operation S240, the controller 110 may identify the timestamps stored in the log area. The controller 110 may compare the timestamps to identify the most recent log area. In addition, the controller 110 may identify whether the log data stored in each log area is invalid by comparing the timestamp of operation S220 with the timestamp of operation S240. For example, the controller 110 may compare the timestamps of operation S220 with the timestamp of operation S240. Figure 6 The log data of the physical page PPN5 of the log area JA1 is stored together with the timestamp and Figure 6 The fragments of the physical page PPN1 of the main metadata area MMA2 are compared with the timestamps stored together to identify Figure 6 The log data of the physical page PPN5 of the log area JA1 is invalidated after the write time W1. Figure 6 The log data of the physical page PPN6 of the log area JA1 is invalidated after the write time W2.

[0080] In operation S250 , the controller 110 may read log data in the log area having the latest time stamp, and may update the address mapping table AMT loaded on the working memory 112 or the buffer memory 120 based on the read log data, and the controller 110 may perform log replay.

[0081] Several example scenarios according to exemplary embodiments of the inventive concept will be described below.

[0082] Assume the following conditions: 1) Figure 6 1) a power event occurs after the log data is stored in the physical page PPN5 of the log area JA2 after the write time W4; 2) the address mapping table AMT loaded on the working memory 112 or the buffer memory 120 is lost due to the power event; 3) the storage device 100 is powered on again, or the power supply voltage is provided to the storage device 100. The controller 110 can compare the timestamps stored in the respective main metadata areas MMA1 and MMA2, can read the segments SG1 to SG8 of the address mapping table AMT from the nearest main metadata area MMA2, and can load the address mapping table AMT to the working memory 112 or the buffer memory 120. The controller 110 can compare the timestamps stored in the respective log areas JA1 and JA2, can read the log data from the nearest log area JA2, and can update the address mapping table AMT loaded to the working memory 112 or the buffer memory 120 based on the log data.

[0083] Assume the following conditions: 1) Figure 61) A power event occurs after the write time W2 and before the write time W3; 2) The address mapping table AMT loaded on the working memory 112 or the buffer memory 120 is lost due to the power event; 3) The storage device 100 is powered on again, or a power voltage is provided to the storage device 100. Because the main metadata area MMA2 does not store a complete and recent address mapping table AMT, the controller 110 can restore the address mapping table AMT on the working memory 112 or the buffer memory 120 based on the address mapping table AMT stored in the main metadata areas MMA1 and MMA2. The controller 110 may compare the timestamps stored in the respective main metadata areas MMA1 and MMA2, may read the segments SG3, SG7, SG1, and SG5 of the address mapping table AMT from the most recent main metadata area MMA2, may read the segments SG2, SG4, SG6, and SG8 of the address mapping table AMT from the previous main metadata area MMA1, and may load the address mapping table AMT including the segments SG3, SG7, SG1, and SG5 in the main metadata area MMA2 and the segments SG2, SG4, SG6, and SG8 in the main metadata area MMA1 onto the working memory 112 or the buffer memory 120. The controller 110 may compare the timestamps stored in the log area JA1 with the timestamps stored in the main metadata area MMA2, and may recognize that all log data stored in the log area JA1 is invalid. The controller 110 may not perform log replay, and may restore the address mapping table AMT on the working memory 112 or the buffer memory 120.

[0084] Assume the following conditions: 1) Figure 61) a power event occurs after the write time W1 and before the write time W2; 2) the address mapping table AMT loaded on the working memory 112 or the buffer memory 120 is lost due to the power event; 3) the storage device 100 is powered on again, or a power voltage is provided to the storage device 100. The controller 110 may compare the timestamps stored in the respective main metadata areas MMA1 and MMA2, may read the segments SG3 and SG7 of the address mapping table AMT from the most recent main metadata area MMA2, may read the segments SG1, SG5, SG2, SG4, SG6, and SG8 of the address mapping table AMT from the previous main metadata area MMA1, and may load the address mapping table AMT including the segments SG3 and SG7 in the main metadata area MMA2 and the segments SG1, SG5, SG2, SG4, SG6, and SG8 in the main metadata area MMA1 onto the working memory 112 or the buffer memory 120. By comparing the timestamp stored in the log area JA1 and the timestamp stored in the main metadata area MMA2, the controller 110 can identify that the log data of the physical page PPN5 stored in the log area JA1 is invalid, and can identify that the log data of the physical page PPN6 stored in the log area JA1 is valid. In this case, the controller 110 does not need to perform a log replay that reads the log data of the physical page PPN5 stored in the log area JA1 and applies the log data to the address mapping table AMT. In contrast, the controller 110 can perform a log replay that reads the log data of the physical page PPN6 stored in the log area JA1 and applies the log data to the address mapping table AMT.

[0085] Fig.12 An exemplary embodiment according to the present inventive concept is shown. Figure 1 The controller 110a may include a processor 111, a working memory 112a, a host interface circuit (host I / F) 113, and a non-volatile memory interface circuit (NVM I / F) 114. Figure 1 The working memory 112a is described. For example, the controller 110a may be implemented by using a system on chip (SoC), an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA).

[0086] The processor 111 may control the working memory 112a, the host interface circuit 113, and the non-volatile memory interface circuit 114. The processor 111 may include one or more cores (e.g., homogeneous multi-cores or heterogeneous multi-cores). For example, the processor 111 may include at least one of a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a visual processing unit (VPU), or a neural processing unit (NPU). The processor 111 may execute the FTL loaded on the working memory 112a, and may execute Figures 9 to 11 1 to 160 , S161 to S166 , and S210 to S250 in the flowchart of .

[0087] The host interface circuit 113 may communicate with the host 11 according to an interface protocol. For example, the interface protocol may be a universal serial bus (USB), a small computer system interface (SCSI), a peripheral component interconnect express (PCIe), a mobile PCIe (M-PCIe), a non-volatile memory express (NVMe), an advanced technology attachment (ATA), a parallel ATA (PATA), a serial ATA (SATA), a serially attached SCSI (SAS), an integrated drive electronics (IDE), a universal flash storage (UFS), FireWire, etc.

[0088] The nonvolatile memory interface circuit 114 may communicate with the nonvolatile memory 130 according to an interface protocol such as dual-state double data rate (DDR). The nonvolatile memory interface circuit 114 may send segments of the address mapping table AMT to the nonvolatile memory 130 based on priority and under the control of the processor 111 executing the FTL. The nonvolatile memory interface circuit 114 may send a segment mapping table SMT to the nonvolatile memory 130 under the control of the processor 111. The nonvolatile memory interface circuit 114 may send log data stored in the log buffer JB to the nonvolatile memory 130 under the control of the processor 111.

[0089] Fig.13 An exemplary embodiment according to the present inventive concept is shown. Figure 2 The controller 110b may include a processor 111, a working memory 112b, a host interface circuit (host I / F) 113, a non-volatile memory interface circuit (NVM I / F) 114, and a buffer memory interface circuit (Buffer I / F) 115. Fig.12 A processor 111, a host interface circuit 113, and a non-volatile memory interface circuit 114 are described. Figure 2The working memory 112 b is described. The buffer memory interface circuit 115 can communicate with the buffer memory 120 according to an interface protocol such as the DDR standard. The buffer memory interface circuit 115 can load and update the address mapping table AMT to the buffer memory 120 under the control of the processor 111. In addition, the buffer memory interface circuit 115 can provide a fragment of the address mapping table AMT loaded on the buffer memory 120 to the non-volatile memory interface circuit 114 under the control of the processor 111.

[0090] Fig.14 A block diagram of an electronic device according to an exemplary embodiment of the inventive concept is shown. The electronic device 1000 may include a host 1100 and a storage device 1200. The host 1100 may include a processor 1110, a host memory 1120, and an interface circuit 1130. The processor 1110 may execute software loaded on the host memory 1120. The processor 1110 may include a homogeneous multi-core or a heterogeneous multi-core. For example, the processor 1110 may include at least one of a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a visual processing unit (VPU), or a neural processing unit (NPU).

[0091] An operating system OS that manages all hardware and software in the electronic device 1000 may be loaded onto the host memory 1120. Application programs included in the user space, a file system included in the kernel space, and a device driver may be loaded onto the host memory 1120. The programs and software layers loaded onto the host memory 1120 are not limited to Fig.14 The software layer loaded onto the host memory 1120 may be included in a software stack for accessing the storage device 1200 .

[0092] The host memory 1120 may include storage media such as registers, on-chip memory, SRAM devices, TCM devices, or DRAM devices. The application may be executed as a basic (or default) service, or may be executed according to a user's request. The user space storing the application and the kernel space storing the file system, device drivers, etc. may be separated from each other. The application does not directly access resources such as the storage device 1200. Instead, the application may call functions defined in a library including a system call function, and may request necessary tasks from the kernel. In the case of calling a system call function, a switch from user mode to kernel mode may occur.

[0093] The file system may manage files or data stored in the storage device 1200. For example, the file system may include a file allocation table (FAT), a new technology file system (NTFS), a hierarchical file system (HFS), a high performance file system (HPFS), a Unix file system (UFS), an auxiliary extended file system (EXT2), EXT3, EXT4, a journaling file system (JFS), JSF2, ISO 9660, Files-11, a veritas file system (VxFS), ZFS, ReiserFS, Reiser4, a universal disk format (UDF), Gnome VFS, BFS, WinFS, etc.

[0094] The device driver is a program used as part of the kernel to control a hardware device such as the storage device 1200. The device driver may generate a command or request for controlling the storage device 1200 under the control of the file system. The device driver may play a role in converting information managed by the file system into information recognizable by the storage device 1200.

[0095] The interface circuit 1130 may provide a physical connection between the host 1100 and the storage device 1200. For example, the interface circuit 1130 may convert commands, addresses, and data corresponding to various IO requests generated by the host 1100 according to a communication method with the storage device 1200.

[0096] The storage device 1200 may process a request of the host 1100. The storage device 1200 may include a controller 1210, a buffer memory 1220, and a non-volatile memory device 1230. The controller 1210 may be a reference Figures 1 to 13 The buffer memory 1220 may be one of the controllers 110, 110a, and 110b described above. Figures 2 to 13 The non-volatile memory device 1230 may include a reference Figures 1 to 13 The nonvolatile memory device 1230 may include at least one of the nonvolatile memories 130 described above. The nonvolatile memory device 1230 may include one or more nonvolatile memories 130 communicating with the controller 1210 through the channel CH1, and one or more nonvolatile memories 130 communicating with the controller 1210 through the channel CH2. The number of channels between the nonvolatile memory device 1230 and the controller 1210 is not limited to Fig.14 Example shown.

[0097] In an exemplary embodiment of the inventive concept, the nonvolatile memory 130 may include a three-dimensional memory array having a three-dimensional array structure. The three-dimensional memory array may be monolithically formed in one or more physical layers of a memory cell array having an active area arranged on a circuit related to the operation of the memory cell. The circuit related to the operation of the memory cell may be located in or on a silicon substrate. The term "monolithic" refers to the layers of each level of the array being deposited directly on the layers of the level of the array below that level.

[0098] The three-dimensional memory array includes a vertical NAND string oriented vertically so that at least one memory cell is located above another memory cell. At least one memory cell includes a charge trapping layer. Each vertical NAND string may include at least one selection transistor located above the memory cell. At least one selection transistor may have a structure substantially the same as that of the memory cell and may be formed monolithically with the memory cell. The three-dimensional memory array may include a plurality of blocks BLK, and the memory cell having the three-dimensional memory array may be divided into a plurality of blocks BLK. A plurality of blocks BLK may be allocated to the above-mentioned user data area USER DATA, a reserved area OP, main metadata areas MMA1 and MMA2, log areas JA1 and JA2, and a segment mapping table area SMTA. The following patent documents describing suitable configurations of the three-dimensional memory structure are incorporated herein by way of introduction: U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235 and U.S. Patent Publication No. 2011 / 0233648.

[0099] Fig.15 2 is a block diagram illustrating a computing system including a storage device according to an exemplary embodiment of the inventive concept. The computing system 2000 may include an application processor 2100, a memory module 2200, a network module 2300, a storage device 2400, and a user interface 2500. The application processor 2100 may drive an operating system (OS) and components included in the computing system 2000 as a SoC. For example, the application processor 2100 may include a reference Figures 1 to 14 The memory module 2200 may be used as a main memory, a working memory, a buffer memory, or a cache memory of the computing system 2000. The memory module 2200 may include a volatile random access memory or a non-volatile random access memory. The network module 2300 may communicate with an external device in a wired / wireless communication manner. The storage device 2400 may be a reference Figures 1 to 14One of the storage devices 100a, 100b, and 1200 described. The user interface 2500 may include an interface for inputting data or commands to the application processor 2100 or outputting data to an external device.

[0100] As described above, a controller according to an exemplary embodiment of the inventive concept may reduce the cost of log replay by storing segments of an address mapping table according to priorities.

[0101] While the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications in form and details may be made without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A storage device, comprising: A non-volatile memory including a primary metadata area and a log area; as well as Controller, Wherein, the controller is configured as: updating an address mapping table by executing a flash translation layer stored in a working memory, the address mapping table comprising a plurality of page mapping entries divided into a plurality of segments; storing updated page mapping entries among the plurality of page mapping entries as log data in the log area; and Based on the order in which the multiple fragments are updated and the number of the updated page mapping entries of each of the multiple fragments, the multiple fragments are stored in the main metadata area, and the multiple fragments each have a size smaller than a physical page of the non-volatile memory.

2. The storage device according to claim 1, wherein: The controller is also configured to: A priority for storing the plurality of segments in the primary metadata area is determined based on the order and the number of the updated page mapping entries for each of the plurality of segments.

3. The storage device according to claim 1, wherein: The controller is also configured to: A fragment mapping table indicating locations where the primary metadata area stores the plurality of fragments, the order, and the number of updated page mapping entries for each of the plurality of fragments is updated.

4. The storage device according to claim 3, wherein: The controller is also configured to: The segment mapping table is stored in a segment mapping table area of ​​the non-volatile memory.

5. The storage device according to claim 3, further comprising: Buffer memory, Wherein, the controller is further configured as: loading the flash translation layer and the segment mapping table into the working memory; and The address mapping table is loaded into the working memory or the buffer memory.

6. The storage device according to claim 1, wherein: The controller is also configured to: storing a first timestamp together with the log data in the log area; storing at least one second timestamp with the plurality of segments in the primary metadata area; and The log data stored in the log area is invalidated based on the first time stamp and the at least one second time stamp.

7. The storage device according to claim 1, wherein: The updated page mapping entry is a first updated page mapping entry, the log data is first log data, the log area is a first log area, and the master metadata area is a first master metadata area. Wherein, the controller is further configured as: Further updating the address mapping table; storing a second updated page mapping entry of the plurality of page mapping entries in a log area of ​​the nonvolatile memory different from the first log area; and The plurality of segments are stored in a main metadata area of ​​the nonvolatile memory that is different from the first main metadata area.

8. The storage device according to claim 1, wherein: The controller is further configured to adjust the size of each of the plurality of segments.

9. A method for operating a storage device, the storage device comprising a controller and a non-volatile memory, the controller being configured to execute a flash translation layer, the non-volatile memory comprising a primary metadata area and a log area, the method comprising: updating, by the controller, an address mapping table including a plurality of page mapping entries; storing updated page mapping entries among the plurality of page mapping entries as log data in the log area; and Based on the order in which the updated page mapping entries are stored in the log area and the number of the updated page mapping entries for each of the plurality of segments dividing the plurality of page mapping entries, the plurality of segments are stored in the main metadata area.

10. The operating method according to claim 9, wherein: When the log area is full, the controller starts storing the plurality of segments in the main metadata area.

11. The operating method according to claim 10, further comprising: After completing storing the plurality of fragments in the main metadata area, at least one block allocated to the log area in the nonvolatile memory is erased.

12. The operating method according to claim 9, wherein: The storing the updated page mapping entry as the log data in the log area comprises: storing a first timestamp together with the log data in the log area, The storing of the plurality of segments in the main metadata area includes: storing at least one second timestamp together with the plurality of segments in the main metadata area.

13. The operating method according to claim 12, further comprising: identifying the at least one second timestamp after the power event occurs; as well as The plurality of segments are read from the main metadata area to load the address mapping table.

14. The operating method according to claim 13, further comprising: When the power event occurs after the storage of the plurality of segments in the main metadata area is completed, log data is read from a log area different from the log area in the nonvolatile memory to update the address mapping table.

15. The operating method according to claim 13, further comprising: When the power event occurs before completing storing the plurality of segments in the main metadata area, the log data is read from the log area to update the address mapping table.

16. An electronic device comprising: A host configured to send a request including a logical address; as well as A storage device, the storage device comprising a non-volatile memory and a controller, wherein the non-volatile memory comprises a primary metadata area and a log area, Wherein, the controller is configured as: updating an address mapping table by processing the request of the host, the address mapping table comprising a plurality of page mapping entries divided into a plurality of segments; storing updated page mapping entries among the plurality of page mapping entries as log data in the log area; and Based on the order in which the multiple fragments are updated and the number of the updated page mapping entries of each of the multiple fragments, the multiple fragments are stored in the main metadata area, and the multiple fragments each have a size smaller than a physical page of the non-volatile memory.

17. The electronic device according to claim 16, wherein: The non-volatile memory further includes a user data area storing data associated with the request, Each of the plurality of page mapping entries includes a physical address of the user data area corresponding to the logical address.

18. The electronic device according to claim 17, wherein: The controller comprises: a memory storing a flash translation layer, the flash translation layer being configured to manage the address mapping table associated with the logical address and the physical address; and A processor is configured to execute the flash translation layer stored in the memory.

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