Current generator circuit

Abstract

Embodiments of the present disclosure relate to a current generator circuit. A current generator circuit includes: an output current generator circuit having a control branch coupled to a control current generator and adapted to provide control current pulses; and a driver electrically coupled between the control branch and an output leg. The compensation circuit includes: a first compensation branch configured to generate compensation current pulses that are a function of the control current pulses; and a second compensation branch coupled to the first compensation branch in a current mirror configuration to receive the compensation current pulses. The second compensation branch includes a resistive block having a resistance that is a function of the resistance of the output load. The second compensation branch is electrically coupled to the control branch, and the driver is electrically coupled to the control branch and the output leg.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Italian Patent Application No. 102019000013695, filed on August 1, 2019, which is incorporated herein by reference. Field of the Invention

[0003] The present invention generally relates to current generator circuits, devices including such current generator circuits, and electronic systems. Background of the Invention

[0004] Phase change non-volatile memories (also known as PCM - "phase change memories") are known in the art. To store information, the properties of materials having the property of switching between phases with different electrical characteristics are utilized. For example, such materials can switch between an amorphous, disordered phase and an ordered crystalline or polycrystalline phase; the two phases are associated with significantly different values of resistivity and thus with different stored data values.

[0005] For example, elements of Group VI of the periodic table (such as tellurium (Te), selenium (Se) or antimony (Sb), known as chalcogenides or chalcogen materials) can be advantageously used for the implementation of phase change memory cells. The phase change is obtained by locally increasing the temperature of the chalcogen material by a resistive electrode (commonly referred to as a heater) arranged in contact with the corresponding region of the chalcogen material.

[0006] A selection device (e.g., a MOSFET transistor) is connected to the heater and enables an electrical programming current to flow through the corresponding heater (electrical pulses known as "SET" and "RESET", suitable for setting the corresponding phase of the material); the current generates the temperature increase required for the phase change by the Joule effect. During a read operation, by applying a voltage across the selected cell that is low enough so as not to cause significant heating, and then by reading the value of the current flowing in the cell, the state of the chalcogen material is detected. Since the current is proportional to the conductivity of the chalcogen material, the state of the material can be determined and thus the data stored in the memory cell.

[0007] In a known manner, non-volatile memories include a matrix of memory cells organized in rows (word lines) and columns (bit lines); in the case of PCM memories, each memory cell is formed by a phase change storage element and a selector transistor connected in series. Column decoders and row decoders allow the selection of the addressed memory cell based on the received input logic signals and decoding scheme, and specifically the selection of the corresponding word line and bit line.

[0008] The column decoder includes a plurality of analog selection switches (implemented by transistors) that receive address signals at respective control terminals; the selection switches are organized hierarchically according to a tree structure, and their number at each hierarchical level is linked to the organization and size of the memory matrix. When enabled, the selection switches allow the selected bit lines to be biased at defined voltage and / or current values according to the operation to be performed; in particular, a current path is created between the programming or read level and the selected bit lines. This current path is defined by a certain number of selection switches in series.

[0009] In a known manner, a sense amplifier reads the data stored in a memory cell (so-called "dual-ended" read) by comparing the current flowing into the selected memory cell (also called the "direct cell") (or a quantity associated with the current) with a reference current flowing in a complementary cell. Clearly, the programming step must also provide for the writing of logical data in both the direct memory cell and the complementary cell. For example, writing a bit in the complementary cell (e.g., logic "1") is associated with the RESET state (by a RESET pulse), while the same bit ("1") is written in the direct cell by a SET pulse.

[0010] Figure 1 A circuit commonly used to implement the column decoder 1 is shown. Any local bit line BL is selected only when the corresponding path to V HIGH is enabled. The first addressing level is formed by PMOS transistors YM (here, 4 transistors YM[0] to YM[3]), and the PMOS transistors YM are connected to the drain terminals of transistors M (here, a number J of transistors M[0]…M[J], e.g., J = 32). In addition, PMOS transistors YO (i.e., one transistor per bit line BL) implement the second addressing level. To ensure that the programming current generated by the transistors M is correctly fed into the selected PCM cell, at a given time, only one of the four YM transistors connected to its drain terminal is turned on, and only one of the transistors YO connected to the active transistor YM is turned on. In addition, each transistor M can program one cell belonging to any associated bit line BL. The row decoder selects the addressed cell by raising the corresponding word line WL to the bias voltage generated by the row voltage regulator.

[0011] Figure 2 A circuit 11 for generating a programming current for programming a PCM memory cell according to known techniques is shown.

[0012] The circuit 11 comprises a control branch 2, which comprises: a current generator 4, configured to cooperate with the generation of a RESET or SET pulse depending on operating conditions, connected between a reference terminal 4a (ground, GND) and a bias terminal 4b; and a control transistor 6 (here, a diode-connected P-type MOSFET), forming a first element of a current mirror 5.

[0013] The current generator 4 is, for example, a digital-to-analog converter DAC and is configured to generate a current pulse I in the control branch 2. DAC .

[0014] The current generator 4 and the control transistor 6 are connected in series between the ground reference terminal 4a and a V voltage equal to, for example, 5V. HIGH Between the line 34 of the voltage. Between the current generator 4 and the transistor 6, the control branch 2 also includes a switch 3 connected in series with the current generator 4 and the control transistor 6, the switch 3 being suitable for being turned on and off in order to respectively connect and disconnect the current generator 4 from the rest of the control branch 2 (in particular, to connect / disconnect the current generator 4 from the current mirror 5); the switch 3 is for example an n-type MOSFET device controlled by a Vdd signal generated by a control logic which is not part of the present invention. The Vdd signal has a value suitable for turning on the switch 3 when the memory is programmed and turning off the switch 3 otherwise so that no undesired current flows to the memory cell through the mirror 5. The switch 3 is optional and can be omitted or designed in a different way.

[0015] The control branch 2 further comprises a cascode switch 7, for example an n-type MOSFET device, which is arranged in series with the switch 3 and electrically arranged between the switch 3 and the mirror device 5. The cascode switch 7 has a control terminal (gate) controlled by a signal Vcasc, which is provided by a regulator of a known type. The cascode switch 7 has the function of improving the connection between the portion of the control branch 2 comprising the current generator 4 (the low voltage portion of the branch 2, where the voltage is in the range of 0.5V-0.9V) and the portion of the control branch 2 comprising the current mirror 5 (the high voltage portion of the control branch 2, at a voltage V HIGH ) between the two parts, so that reverse transmission is reduced because there is no direct coupling between the two parts at different voltages.

[0016] During use, when the current generator 4 is controlled to generate a current I DAC (SET or RESET pulse), the current I DAC Flow through V HIGH The control branch 2 between the line and the ground reference terminal GND is mirrored on multiple main bit lines MBL1...MBL through the current mirror 5. J The corresponding programming current I PROGin.

[0017] Upon activation of transistor M (here, a P-type MOSFET), current I PROG (SET / RESET pulse) flows through the corresponding main bit lines MBL1…MBL J . Transistor M is connected to transistor 6 in a current mirror configuration. In particular, the activation of transistor M is controlled by two corresponding switches, which are turned on and off by enable signals EN_PULSE, / EN_PULSE (where / EN_PULSE has a logic value complementary to the logic value of EN_PULSE).

[0018] Referring to main bit line MBL1, switch 10 (e.g., a P-channel transistor) is coupled between the gate of transistor M[0] and the gate of control transistor 6, and switch 12 (e.g., a P-channel transistor) is coupled between the gate of transistor M[0] and the V HIGH line. In this way, it is obvious to those skilled in the art that current I on control branch 2 is mirrored in main bit line MBL1 only when switch 10 is on and at the same time switch 12 is off, i.e., only when signals EN_PULSE and / EN_PULSE have corresponding (complementary) values that keep switch 10 in the on state and switch 12 in the off state. DAC is mirrored in main bit line MBL1.

[0019] Then, the same configuration is repeated for all “J” main bit lines forming the memory device.

[0020] In summary, programming current I PROG (SET / RESET pulse) is provided to each phase change memory element that must be programmed by means of this current. Obviously, the current pulse should be shaped and have a certain amplitude in order to cause a phase change in the phase change memory element to which it is applied. In addition, the applicant knows that current pulses are applied in parallel to several memory elements in order to accelerate the write operation.

[0021] Due to an undesired change in the drain-source voltage V of transistor M DS (due to an uncontrolled change in the resistance on main bit lines MBL1…MBL J ), transistor M is affected by channel modulation. This effect is due to the fact that, because of variations that occur during the manufacturing process and during use, the resistance of each PCM cell is not exactly equal to the resistance of other PCM cells, and at the same time, due to non-ideality, the intensity of the programming pulses may vary unexpectedly from one cycle to another.

[0022] In other words, main bit lines MBL1…MBL JThe voltages at nodes 8a, 9a (terminals of drive transistors M[0]…M[J]) unpredictably depend on the resistance values of the programmed phase change memory elements and on the amplitude of the current pulses applied to them.

[0023] The channel modulation effect has an impact on the current pulse amplitude accuracy. This means that not all programming pulses are equally effective and not all programming pulses are suitable for setting the desired resistance state (SET or RESET) into the memory element to which the programming pulse is applied.

[0024] The same problem can be found in other types of circuits or applications, especially in cases where a current generation circuit using a current mirror configuration is employed to provide an output current to a resistive load. SUMMARY OF THE INVENTION

[0025] Embodiments of the present invention relate to a current generator circuit (e.g., a programming circuit for writing data in a phase change memory cell), to a phase change memory device (e.g., a phase change memory) including the current generator circuit, and to a system including the device.

[0026] Embodiments of the present invention relate to a current generator circuit that is operable to generate an output current pulse to be fed to a resistive load. The current generator circuit includes: a control branch coupled to a control current generator adapted to generate a control current pulse; and a driver electrically coupled to the control branch and the resistive load. The compensation circuit includes: a first compensation branch configured to generate a first compensation current pulse that is part of the control current pulse; a second compensation branch coupled to the first compensation branch in a current mirror configuration for receiving the first compensation current pulse. The second branch includes a resistive block having a resistance that mimics the resistance of the resistive load. The second compensation branch is electrically coupled to the control branch to provide a compensation current pulse to the control branch such that the compensation current pulse is added to the control current pulse / the compensation current pulse is subtracted from the control current pulse to generate a compensated current pulse. The driver is electrically coupled to the control branch and the resistive load to receive the compensated current pulse from the control branch and generate an output current pulse based on the compensated current pulse. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To better understand the present invention, its preferred embodiments are now described by way of non-limiting example and with reference to the accompanying drawings, in which:

[0028] Figure 1 is a circuit representation of a part of a known phase change memory device including a column decoder;

[0029] Figure 2is a circuit representation of a programming circuit for writing logic data in a phase change memory cell according to known techniques;

[0030] Figure 3 is a circuit representation of a programming circuit for writing logic data in a phase change memory cell according to the present invention;

[0031] Figure 4 is a simplified block diagram of a PCM device including a programming circuit that includes Figure 3 ;

[0032] Figure 5 is a simplified block diagram of an electronic system of a PCM device including Figure 4 ; and

[0033] Figure 6 is a circuit representation of a general current generator circuit for supplying an output current to a resistive load according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] Without loss of generality, the present invention will now be described specifically with reference to a programming circuit adapted to generate programming current pulses suitable for programming one or more memory cells of the phase change type. In particular, as will be apparent from Figure 6 and the related description, the present invention can be used as a programming circuit for any type of resistive memory (e.g., conductive bridge RAM - CBRAM, oxide - based RAM - OxRAM, etc.), as well as a current generator for a resistive heater employed in a high - temperature gas sensor, a reconfigurable integrated antenna, a dispenser cathode, beam control in a semiconductor laser, and also as a current generator for other applications, devices, and systems that require a current generator insensitive to the effects of a resistive load.

[0035] Figure 3 FIG. shows a programming circuit 21 for generating programming current pulses suitable for programming one or more memory cells of the phase change type. The programming circuit 21 includes a compensation circuit 20 operatively coupled to Figure 2 circuit 11 for the purpose of compensating or reducing the above - mentioned channel modulation effect.

[0036] The compensation circuit 20 includes a bias branch 22 and a compensation branch 24; the bias branch 22 extends between a high - voltage line 34 at a voltage V HIGH (e.g., between 4V and 6V) and a reference terminal GND at a reference voltage (e.g., at 0V). The bias branch 22 is configured to generate a bias current I bias and mirror the bias current I bias to the compensation branch 24 through a current mirror 23 (specifically, having a unity gain).

[0037] The compensation branch 24 similarly extends between the high voltage line 34 and the reference terminal GND.

[0038] More specifically, the bias branch 22 includes a current generator 26 (e.g., a digital-to-analog converter or DAC to allow digital current control), which is configured to generate a current pulse in the bias branch 22, and the current pulse has an amplitude that is part of the amplitude of the current pulse I Figure 2 generated by the control branch 2 of the circuit 11. DAC Assume that the current pulse I DAC generated by the control branch 2 has an amplitude of "A", then the current pulse I bias generated by the DAC 26 has an amplitude of "α·A", where α ≤ 1 (preferably α < 1, more preferably 0.5 < α < 0.8).

[0039] The bias branch 22 further includes a first control switch 28, and the first control switch 28 is adapted to be turned on and off for the purpose of connecting and disconnecting the DAC 26 from the rest of the bias branch 22 respectively (specifically, connecting / disconnecting the DAC 26 to / from the current mirror 23); the first control switch 28 is, for example, an n-type MOFET device controlled by the Vdd signal, as discussed in reference Figure 2 . The Vdd signal has a value that is adapted to turn on the first control switch 28 when the memory is programmed, and is adapted to turn off the first control switch 28 when a programming operation is not required. The first control switch 28 is optional and can be omitted.

[0040] The bias branch 22 further includes a cascode switch 30, such as an n-type MOSFET device, which is arranged in series with the first control switch 28 and is electrically connected between the DAC 26 and the high voltage line 34 (specifically, between the first control switch 28 (when present) and the high voltage line 34). The cascode switch 30 has a control terminal (gate) controlled by a signal V casc , and the signal V casc is provided by a regulator as already discussed in reference Figure 2 . The cascode switch 30 has the function of improving the electrical isolation between the part of the bias branch 22 including the DAC 26 (the low voltage part of the bias branch 22, where the voltage is in the range of 0.5V - 0.9V) and the part of the bias branch 22 including the current mirror 23 (the high voltage part of the bias branch 22, at a voltage V HIGH in the range of 4V - 6V), so that reverse transmission is reduced because there is no direct coupling between the two parts at different voltages.

[0041] The current mirror 23 is formed in part by a mirror device 32 (here, a p-type MOSFET), which is arranged in series with the cascode switch 30 in the bias branch 22, more specifically, between the cascode switch 30 and the high-voltage line 34. The mirror device 32 is diode-connected, i.e., its control terminal (gate) is electrically connected to its drain terminal. During use, when the DAC 26 is controlled to generate a current I bias , the current I bias flows through the bias branch 22 and is mirrored to the compensation branch 24.

[0042] As a circuit, the compensation branch 24 substantially replicates the bias branch 22, as it includes a current generator 36, a second control switch 38, and a cascode switch 40. The current generator 36 (e.g., a digital-to-analog converter or DAC to allow digital current control) is configured to generate current pulses in the compensation branch 24, the amplitude of which is equal to the amplitude of the current pulses generated by the current generator 26 in the bias branch 22 (I bias = α·A, where α < 1).

[0043] The second control switch 38 (e.g., an n-type MOFET) is adapted to be turned on and off for the purpose of connecting and disconnecting the DAC 36 to and from the remainder of the compensation branch 24, respectively. The second control switch 38 is controlled by a Vdd signal generated by control logic. The second control switch 38 is optional and can be omitted.

[0044] The cascode switch 40 (e.g., an n-type MOSFET device) is electrically coupled in series to the DAC 36, between the DAC 36 and the high-voltage line 34 (e.g., arranged in series with the second control switch 38, electrically coupled between the second control switch 38 and the high-voltage line 34). The cascode switch 40 has a control terminal (gate) controlled by a signal Vcasc.

[0045] In addition, the current mirror 23 is formed in part by a second mirror device 42 (here, a p-type MOSFET), which is arranged in series with the cascode switch 40 in the compensation branch 24, more specifically, between the cascode switch 40 and the high-voltage bias line 34 at a voltage V HIGH . The second mirror device 42 has a control terminal (gate) connected to the control terminal (gate) of the mirror device 32, thereby forming the current mirror 23.

[0046] According to one aspect of the present invention, the compensation branch 24 further includes a resistive block 50, which simulates (in one embodiment, is equal to) each main bit line MBL1…MBL during a programming step (i.e., during logical data writing in the phase change element) JThe equivalent resistance at nodes 8a and 9a. The main source of the resistance is given by the series of the resistance of the selector device of column decoder 1 and the resistance of the phase change element of the memory cell to be addressed (to be programmed).

[0047] For example, when transistor M[0] is activated to propagate a current pulse I prog (SET or RESET pulse) on main bit line MBL1, the main source of the resistance in the electrical path between the terminal 8a of transistor M[0] and the cell to be programmed is given by the series of the resistance of the PCM memory cell itself and any resistance introduced by the selector device on this path. In the disclosed embodiment, the selector device particularly includes transistors YM and YO, which are activated (turned on) to address the PCM memory cell to be programmed, that is, activated to connect the local bit line BL (the PCM to be programmed is coupled to this local bit line BL) to the main bit line MBL1. According to the specific design of the memory under consideration, additional selector devices (not shown in this embodiment) may be coupled to the main bit line MBL1 and / or the local bit line BL.

[0048] During the programming step of the PCM memory cell coupled to transistor M[J] through the selector devices YM and YO of column decoder 1, a similar resistance is seen at the terminal 9a of transistor M[J].

[0049] To reproduce / simulate the series resistance identified above, the resistive block 50 is designed to have a resistance that is given by the sum of the resistance of the phase change memory cell during the programming step plus any resistance introduced by one or more selector YM, YO devices, where one or more selector YM, YO devices are present on the path (programming path) between the driving transistor and the phase change memory cell to be programmed. In the disclosed embodiment, the resistance R COMP of block 50 is COMP R PCM = R YO + R YM .

[0050] The resistance R PCM is the resistance of the phase change material of the memory cell at its melting point. The resistances R YO and R YM are the resistances of transistors YO and YM when activated (i.e., during conduction), respectively.

[0051] Since the resistance R PCM of the phase change memory cell is higher than the resistances R YO and R YM of transistors YO and YM, in one embodiment of the present invention, the resistances R YO and R YMsuch that during the programming step, the resistance of the resistive block 50 is approximated by the resistance R of the memory cell PCM R COMP = R PCM (in the case of PCM, R PCM is the resistance of the phase change material of the memory cell at its melting point).

[0052] Node 24a is identified in the compensation branch 24, between the cascode switch 40 and the DAC 36, more precisely between the cascode switch 40 and the second control switch 38. Similarly, node 2a is identified in the control branch 2 of the circuit 11, between the cascode switch 7 and the current generator 4, more precisely between the cascode switch 7 and the switch 3.

[0053] Note that the current generator 36 absorbs current I from the branch 22 through the mirror 23 bias , however, due to the channel modulation effect of the transistor 42 caused by the difference between the drain-source voltages of the transistors 42 and 32, the current I NC ≠ I bias flows through the transistor 42.

[0054] Node 24a is electrically connected (specifically, short-circuited) to node 2a in order to supply the current I COMP = I NC - I bias from the compensation branch 24 to the control branch 2. The current I COMP can be a positive current that is added to the current I DAC generated by the current generator 4, or can be a negative current that is subtracted from the current I DAC . Thus, the current I CTR flowing in the control branch 2 is given by I DAC - I COMP ; the current I CTR is mirrored in the programming current I prog through the current mirror 5. If the resistive block 50 is designed as described above, the voltage drop V DS_COMP across the second mirror device 43 is (substantially) equal to the voltage drop V DS_PROG across the transistor M[0] (similarly, across the transistor M[J]), and I prog ≈ I DAC . Typically, the current mirror 5 is designed to have a gain G (e.g., G = 10), such that I prog ≈ G · I DAC .

[0055] According to the above, the programming current I progNo longer rely on (or minimally rely on) the resistance of the phase change material of the programmed memory cell, because the modulation effect on the drain-source voltage of transistor M is compensated by current I COMP balanced.

[0056] Figure 4 The schematic block diagram of shows the memory system 50, including the previously disclosed circuits 11 and 20, and including the PCM memory array 52, the finite state machine (FSM) 54, two decoders (i.e., the row decoder 56 and the column decoder 1), the voltage regulator 58, the internal oscillator 60, the digital-to-analog converter (DAC) 62, and several internal registers 64.

[0057] Most of the memory system 50 is occupied by the PCM memory array 52, which contains, for example, 557568 memory cells, divided into 528 rows (WL) and 1056 columns (BL). Data is stored in the memory using a differential method, and thus, the cells are divided into two categories: direct cells (DC) and complementary cells (CC). When a programming operation is issued to store a given data, the information is written into the DC as it is received, but is also complemented and then written into the corresponding CC. In this way, each data present in the memory has a complementary counterpart. The FSM 54 controls the internal operations of the memory system 50 (e.g., boot, write, read, etc.), and manages the reception and transmission of data through, for example, a 32-bit advanced high-performance bus (AHB), which adopts the AMBA (Advanced Microcontroller Bus Architecture) protocol. This protocol is open source and is generally used to implement communication inside the SoC and is not part of the present invention. The clock is provided to the FSM 54 by the internal oscillator 60, which is designed to operate at 10 MHz and is trimmed during the EWS phase to adjust its frequency in order to attenuate the impact of process spread. In addition, during the boot operation, the FSM 54 loads the trim configuration and pulse settings from the memory reserved sector into the registers.

[0058] Figure 5 Illustrated is a part of the electronic system 70, which can be used in electronic devices such as: PDA (Personal Digital Assistant); portable or fixed computers, possibly with wireless data transmission capabilities; mobile phones; digital audio players; cameras or camcorders; wearable electronic devices; or other devices capable of processing, storing, transmitting, and receiving information.

[0059] Specifically, by way of non - limiting example, the electronic system 70 includes a controller 71 (e.g., provided with a microprocessor, DSP or microcontroller), an input / output device 72 for inputting and displaying data (e.g., provided with a keyboard and a display), a memory system 50, a wireless interface 74 for transmitting and receiving data via a radio frequency wireless communication network (e.g., an antenna), and a RAM 75, all of which are coupled via a bus 76. A battery 77 can be used as a power source in the electronic system 70, and the electronic system can further be provided with a camera or a video camera 78.

[0060] Figure 6 A current generator circuit 100 is shown, and the current generator circuit 100 is operable to generate output current pulses I to be fed to one or more resistive loads 102 ( Figure 6 a plurality of resistive loads are shown). load In Figure 3 common elements with the Figure 6 circuit are evident, and thus reference can be made to them for a better understanding of the

[0061] Figure 6 invention can be used as a current generation circuit for any type of resistive memory (e.g., conductive - bridge RAM - CBRAM, oxide - based RAM - OxRAM, etc.), as well as a resistive heater employed in a high - temperature gas sensor, a reconfigurable integrated antenna, a dispenser cathode, a current generator for beam control in a semiconductor laser, and also as a current generator for other applications, devices and systems that require a current generator insensitive to the effects of resistive loads.

[0062] In Figure 6 each resistive load 102 has a resistance R that is approximately the same as the resistance R of the other resistive loads 102 load R load .

[0063] The current generator circuit 100 includes a current generator circuit 104 and a compensation circuit 112. The current generator circuit 104 includes: a control branch 106, coupled to a control current generator 108, the control current generator 108 being adapted to generate control current pulses I DAC ; and one or more drivers 110, each driver 110 being electrically coupled to the control branch 106 and a corresponding resistive load 102. The compensation circuit 112 includes: a first compensation branch 114, configured to generate a first compensation current pulse I bias , the first compensation current pulse I bias being the control current pulse I DACfunctions (e.g., multiples or divisors or fractions); and a second compensation branch 116 coupled to the first compensation branch 114 in a current mirror configuration 118 for receiving a first compensation current pulse I bias and includes a resistive block 120 having a resistance R of each of the analog resistive loads 102 load with a resistance R load’ .

[0064] The second compensation branch 116 is electrically coupled to the control branch 106 to provide a compensation current pulse I to the control branch 106 COMP such that from the control current pulse I DAC subtracting the compensation current pulse I COMP to generate a compensated current pulse I CTR . Each driver 110 is electrically coupled to the control branch 106 and a corresponding resistive load 102 to receive the compensated current pulse I from the control branch 106 CTR and generates an output current pulse I according to the compensated current pulse I CTR . load .

[0065] More specifically, according to an exemplary embodiment of the present invention, the first compensation branch and the second compensation branches 114, 116 are connected in a current mirror configuration 118 as described, for which the first compensation branch 114 includes a p-channel transistor 132 having a source node, a gate node, and a drain node. The source node is coupled to a supply voltage node V HIGH and the gate node (also referred to herein as the mirror node) is coupled to the drain node at an intermediate node 131. The p-channel transistor 132 is thus a diode-connected device.

[0066] A current generator (or current source) 136 (e.g., a digital-to-analog converter or DAC to allow digital current control) is configured to generate a current pulse I in the first bias branch 114 bias and is thus serially coupled to the transistor 132 between the drain node of the transistor 132 and a ground reference node GND.

[0067] The second compensation branch 116 includes a p-channel transistor 142 having a source node, a gate node, and a drain node. The source node is coupled to a supply voltage node V HIGH and the gate node is connected to the gate (mirror) node of the transistor 132, thereby forming a current mirror 118.

[0068] The current generator (current source) 138 is coupled to the drain node of the transistor 142 in series connection and is coupled to the ground reference node GND. The current source 138 draws a current I from the gate (mirror) node of the transistor 132 DAC .

[0069] According to the present invention, the resistive block 120 has a resistance R that is a function (i.e., “analog”) of each of the resistive loads 102 load resistance R load’ . In one embodiment, R load’ = R load .

[0070] The circuit 100 further includes a control branch 106, which in turn includes a current generator 108 and a control transistor 156 (here, a diode-connected P-type MOSFET). The current generator 108 is, for example, a digital-to-analog converter DAC and is configured to generate a current pulse I DAC in the control branch 106. The current generator 108 and the control transistor 156 are connected in series with each other between the supply voltage node V HIGH and the ground reference node GND such that the source node of the control transistor 156 is coupled to the supply voltage node V HIGH , and the drain node of the control transistor 156 is coupled to the current generator 108

[0071] Note that the current generator 138 draws a current I from the branch 114 through the mirror 118 bias ; however, due to the channel modulation effect of the transistor 142 caused by the difference between the drain-source voltages of the transistors 142 and 132, the current I NC ≠ I bias flows through the transistor 142

[0072] The node 124a (defined in the compensation branch 116, between the resistive block 120 and the current generator 138) is electrically connected (specifically, short-circuited) to the node 124b (defined in the control branch 106, between the control transistor 156 and the current generator 108) so as to supply the current I COMP = I NC - I bias from the compensation branch 116 to the control branch 106. The current I COMP can be a positive current that is added to the current I DAC generated by the current generator 108, or can be a negative current that is subtracted from the current I DAC . Thus, the current I CTR flowing in the control branch 106 is given by I DAC - I COMP .

[0073] Circuit 100 also includes a plurality of output legs 126. Each output leg 126 is formed by a respective p-channel transistor 128 having a source node, a gate node, and a drain node. The source node is coupled to a supply voltage node V HIGH , and the gate node is connected to the gate node of transistor 156 (current mirror configuration 155) through switch circuit 150. In response to an enable signal EN, switch circuit 150 is actuated to a closed state to enable current mirror operation in each output leg 126 to output an output current I CTR that mirrors the control current I load . A mirror ratio of 1:G (e.g., 1:10) may exist between transistor 156 and each transistor 128, and the mirror ratio is defined by a difference in transistor size (width / length). Each electrical (resistive) load 102 is serially connected to a respective transistor 128 in a respective output leg 126.

[0074] According to the above, the output current I load no longer depends on (or minimally depends on) the resistance R of the load 102 load .

[0075] Note that, according to requirements and specific applications, each of branches 114, 116, and 106 of circuit 100 may include one or more switches (transistors), such as transistors 28, 30, 38, 40, 3, 7 as previously referenced Figure 2 and Figure 3 discussed.

[0076] From what has been previously described and illustrated, the advantages provided by the column decoder according to the present invention are apparent.

[0077] In particular, the mirror ratio is increased, and a more precise pulse shape is achieved.

[0078] In addition, the impact on area can be negligible compared to PCM programming circuitry.

[0079] In addition, the dependence of the current on the power supply is significantly reduced, and no additional voltage regulator is required to power the circuit.

[0080] In addition, the increased power consumption is negligible compared to the power consumption of the write pulse.

[0081] Finally, note that when generating the ramp for switching the DAC configuration (as required in the programming pulse for SET of the PCM cell), the obtained slope has higher precision compared to the standard solution.

[0082] Finally, it is obvious that modifications and variations can be made to what has been described and illustrated herein without departing from the scope of the invention as defined by the appended claims.

Claims

1. A current generator circuit operable to generate an output current pulse to be fed through an output leg to an output load coupled to the output leg, the circuit comprising: An output current generator circuit, comprising: A control branch coupled to a control current generator and adapted to provide a control current pulse; and A driver electrically coupled between the control branch and the output leg; and A compensation circuit, comprising: A first compensation branch configured to generate a compensation current pulse that is a function of the control current pulse; and A second compensation branch coupled to the first compensation branch in a current mirror configuration to receive the compensation current pulse, the second compensation branch including a resistive block having a resistance that is a function of the resistance of the output load; Wherein the second compensation branch is electrically coupled to the control branch to provide the compensation current pulse to the control branch such that the compensation current pulse is added to the control current pulse / the compensation current pulse is subtracted from the control current pulse to generate a compensated current pulse; and Wherein the driver is electrically coupled to the control branch and the output leg to receive the compensated current pulse from the control branch and generate the output current pulse in accordance with the compensated current pulse.

2. The circuit according to claim 1, wherein the driver includes a current mirror circuit arrangement having a mirror gain, the current mirror circuit arrangement including a first mirror transistor connected in a current mirror configuration to a second mirror transistor.

3. The circuit according to claim 2, wherein the first mirror transistor is coupled to the control current generator and the second mirror transistor is coupled to the output leg such that the output current pulse is a copy of the compensated current pulse amplified by the mirror gain.

4. The circuit according to claim 1, wherein the first compensation branch is coupled between a bias line at a first voltage and a reference line at a second voltage lower than the first voltage, the first compensation branch including: A first compensation current generator electrically coupled to the reference line and configured to generate the compensation current pulse; A first cascode transistor electrically coupled between the first compensation current generator and the bias line; And A third mirror transistor electrically coupled between the first cascode transistor and the bias line.

5. The circuit according to claim 4, wherein the second compensation branch is coupled between the bias line and the reference line, the second compensation branch including: A second compensation current generator electrically coupled to the reference line and configured to generate the compensation current pulse; A second cascode transistor electrically coupled between the second compensation current generator and the bias line; And A fourth mirror transistor electrically coupled between the second cascode transistor and the bias line.

6. The circuit according to claim 5, wherein the third mirror transistor and the fourth mirror transistor are connected to each other according to the current mirror configuration to absorb the compensation current pulse from the first compensation branch.

7. The circuit according to claim 6, wherein the driver includes a current mirror circuit device having a mirror gain, the current mirror circuit device including a first mirror transistor, the first mirror transistor being connected to a second mirror transistor in a current mirror configuration; and wherein the first mirror transistor is coupled to the control current generator, and the second mirror transistor is coupled to the output leg such that the output current pulse is a copy of the compensated current pulse amplified by the mirror gain.

8. The circuit according to claim 7, wherein the control branch includes a third cascode transistor, the third cascode transistor being serially electrically coupled to the first mirror transistor and the control current generator and being between the first mirror transistor and the control current generator; wherein a first node is defined between the second cascode transistor and the second compensation current generator, and a second node is defined between the third cascode transistor and the control current generator; and wherein the first node and the second node are shorted to each other to supply the compensation current pulse from the second compensation branch to the control branch.

9. The circuit according to claim 6, wherein the resistive block is serially electrically coupled to the fourth mirror transistor and the second cascode transistor and is between the fourth mirror transistor and the second cascode transistor.

10. The circuit according to claim 1, wherein the output leg is coupled to a column decoder of a memory array, the memory array including at least one bit line, and a phase change memory cell to be programmed by the output current pulse is coupled to the at least one bit line; wherein the column decoder includes one or more selector devices operable to address the bit line; and wherein during a programming operation of the phase change memory cell, the resistance of the resistive block is a function of the resistance of the phase change memory cell.

11. The circuit according to claim 10, wherein the resistance of the resistive block is also a function of the resistance of the one or more selector devices such that during the programming operation, the resistance of the resistive block is given by the sum of the resistance of the one or more selector devices and the resistance of the phase change memory cell.

12. The circuit according to claim 10, wherein during the programming operation, the resistance of the phase change memory cell is the resistance of the phase change material of the phase change memory cell at its melting point.

13. A circuit, comprising: a bias line at a first voltage; a reference line at a second voltage lower than the first voltage; a control current generator; an output leg; An output current generator circuit, including a control branch and a driver, the control branch being coupled to the control current generator, and the driver being electrically coupled between the control branch and the output leg; and a compensation circuit, including: a first compensation branch, coupled between the bias line and the reference line; and a second compensation branch, coupled between the bias line and the reference line and electrically coupled to the control branch, the first compensation branch and the second compensation branch being coupled in a current mirror configuration; wherein the first compensation branch includes: a first compensation current generator, electrically coupled to the reference line; a first cascode transistor, electrically coupled between the first compensation current generator and the bias line; and a third mirror transistor, electrically coupled between the first cascode transistor and the bias line; and wherein the second compensation branch includes: a resistive block having a resistance that is a function of the resistance of an output load to be coupled to the output leg; a second compensation current generator, electrically coupled to the reference line; a second cascode transistor, electrically coupled between the second compensation current generator and the bias line; and a fourth mirror transistor, electrically coupled between the second cascode transistor and the bias line, the third mirror transistor and the fourth mirror transistor being connected to each other according to the current mirror configuration.

14. The circuit according to claim 13, wherein the driver includes a current mirror circuit device having a mirror gain, the current mirror circuit device including a first mirror transistor, the first mirror transistor being connected to a second mirror transistor in a current mirror configuration, the first mirror transistor being coupled to the control current generator, and the second mirror transistor being coupled to the output leg.

15. The circuit according to claim 14, wherein the control branch includes a third cascode transistor, the third cascode transistor being serially electrically coupled to the first mirror transistor and the control current generator and between the first mirror transistor and the control current generator.

16. The circuit according to claim 13, wherein the resistive block is serially electrically coupled to the fourth mirror transistor and the second cascode transistor and between the fourth mirror transistor and the second cascode transistor.

17. The circuit according to claim 13, further including: a memory array having a plurality of local bit lines, the plurality of local bit lines being connected to corresponding phase change memory cells; and a column decoder, coupled to the output leg and the memory array for addressing one of the local bit lines connected to a memory cell to be programmed.

18. The circuit according to claim 17, wherein the column decoder includes a plurality of selector devices coupled to the local bit lines, and wherein the resistive block has a resistance that is a function of the resistance of a phase change memory cell addressed by the column decoder and programmed by the output current generator circuit.

19. The circuit according to claim 18, wherein the resistance of the resistive block is also a function of the resistance of an addressing selector device, the addressing selector device being coupled to the addressed phase change memory cell.

20. A phase change memory device, comprising: A memory array provided with a plurality of local bit lines, the plurality of local bit lines being connected to respective memory cells storing respective logic data; A column decoder coupled to the memory array for addressing one of the local bit lines connected to a memory cell to be programmed; A current generator circuit coupled to the memory array through the column decoder for generating a programming current pulse to write logic data into the memory cell connected to the addressed local bit line, the current generator circuit comprising: An output current generator circuit, comprising: A control branch coupled to the current generator circuit, the control branch being adapted to provide a control current pulse; and A driver electrically coupled between the control branch and the column decoder; and A compensation circuit, comprising: A first compensation branch configured to generate a compensation current pulse, the compensation current pulse being a function of the control current pulse; and A second compensation branch coupled to the first compensation branch in a current mirror configuration to receive the compensation current pulse, the second compensation branch including a resistive block having a resistance that is a function of the resistance of the addressed local bit line; Wherein the second compensation branch is electrically coupled to the control branch to provide the compensation current pulse to the control branch such that the compensation current pulse is added to the control current pulse / the compensation current pulse is subtracted from the control current pulse to generate a compensated current pulse; and Wherein the driver is electrically coupled to the control branch to receive the compensated current pulse from the control branch and generate the programming current pulse based on the compensated current pulse.

21. The phase change memory device according to claim 20, further comprising: A programming circuit; A main bit line connecting the programming circuit to the addressed local bit line; And A selector device coupled to the addressed local bit line and operative to electrically connect the addressed local bit line to the main bit line to establish a circuit path between the main bit line and the memory cell to be written.

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