Non-volatile memory device and operating method thereof

Abstract

A nonvolatile memory device and an operating method thereof are provided. The nonvolatile memory device includes an array of memory cells having a vertical stack structure, a bit line for applying a program voltage to the array of memory cells, and a control logic. The array of memory cells includes memory cells each including a corresponding portion of a semiconductor layer and a corresponding portion of a resistive layer. The memory cells include unselected memory cells, a compensation memory cell, and a selected memory cell. The control logic is configured to apply an adjusted program voltage to the selected memory cell based on applying a first voltage to the compensation memory cell, applying a second voltage to the selected memory cell, and applying a third voltage to the unselected memory cells. The adjusted program voltage can be lowered compared to the program voltage due to the compensation memory cell.

Description

Technical Field

[0001] This disclosure relates to non-volatile storage devices and methods of operating thereof. Background Technology

[0002] Non-volatile memory is a semiconductor memory device that includes multiple memory cells, each of which retains information even when its power supply is interrupted, and the stored information becomes available whenever power is restored. Examples of applications of non-volatile memory include mobile phones, digital cameras, personal digital assistants (PDAs), mobile computing devices, fixed computing devices, and other devices.

[0003] Recently, research has been conducted on the use of three-dimensional (or vertical) NAND (VNAND) in chips that form next-generation neuromorphic computing platforms or neural networks.

[0004] In particular, there is a need for technologies that allow random access to memory cells with highly integrated and low-power characteristics. Summary of the Invention

[0005] A non-volatile storage device capable of sensing various levels of resistance states and its operation method are provided.

[0006] A non-volatile storage device for outputting the resistor state with a linear scaling type and its operation method are provided.

[0007] Additional aspects will be set forth in part in the description which follows and will be apparent in part from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0008] According to one embodiment, a non-volatile memory device includes a memory cell array having a vertically stacked structure, bit lines configured to apply a programming voltage to the memory cell array, and control logic. The memory cell array may include a semiconductor layer and a variable resistor layer. The memory cell array may include a plurality of memory cells, each memory cell including a corresponding portion of the semiconductor layer and a corresponding portion of the variable resistor layer. The plurality of memory cells may include unselected memory cells, compensation memory cells, and selected memory cells. The control logic may be configured to apply an regulated programming voltage to the selected memory cells based on applying a first voltage to the compensation memory cells, a second voltage to the selected memory cells, and a third voltage to the unselected memory cells, wherein the regulated programming voltage is reduced compared to the programming voltage due to the compensation memory cells. The first voltage may allow a certain magnitude of current to flow to the compensation memory cells. The second voltage may allow current to flow only to the corresponding portion of the variable resistor layer of the selected memory cells. The third voltage may allow current to flow only to the semiconductor layer of the unselected memory cells.

[0009] In some implementations, the absolute value of the first voltage may be greater than the absolute value of the second voltage.

[0010] In some implementations, the absolute value of the first voltage may be less than the absolute value of the third voltage.

[0011] In some implementations, the magnitude of the first voltage may allow the resistance of the corresponding portion of the semiconductor layer in the compensation memory cell to be less than the resistance of the corresponding portion of the variable resistance layer in the compensation memory cell.

[0012] In some embodiments, the resistance of the corresponding portion of the semiconductor layer in the compensation memory cell is less than or equal to 1 / 10 of the resistance of the corresponding portion of the variable resistance layer in the compensation memory cell.

[0013] In some implementations, a first voltage is applied to the compensation memory cell based on control logic. The magnitude of the first voltage allows the resistance of the corresponding portion of the semiconductor layer in the compensation memory cell to be within 10 ohms. 5 Ωm -1 Up to 10 7 Ωm -1 Within the range.

[0014] In some implementations, a first voltage is applied to the compensation memory cell based on control logic. The magnitude of the first voltage allows the resistance of the corresponding portion of the variable resistance layer in the compensation memory cell to be within 10 ohms. 8 Ωm -1 Up to 10 11 Ωm - Within the range of 1.

[0015] In some implementations, the compensation storage unit and the selected storage unit can be connected in series with each other.

[0016] In some implementations, the control logic can be configured to allow a current of a certain magnitude to flow to the corresponding portion of the variable resistance layer in the selected memory cell during programming operations.

[0017] In some implementations, the corresponding portions of the semiconductor layer in the compensation memory cell and the corresponding portions of the variable resistance layer in the compensation memory cell can be connected in parallel with each other.

[0018] In some embodiments, the memory cell array may include: a semiconductor layer extending in a first direction; a plurality of gates and a plurality of insulators extending in a second direction perpendicular to the first direction, the plurality of gates and the plurality of insulators being arranged alternately; a gate insulating layer extending in the first direction between the plurality of gates, the plurality of insulators and the semiconductor layer; and a variable resistor layer extending in the first direction on the semiconductor layer.

[0019] In some implementations, the variable resistance layer may be in contact with the semiconductor layer.

[0020] In some implementations, the variable resistance layer may be spaced apart from the gate insulating layer and the semiconductor layer may be located between them.

[0021] In some implementations, the variable resistance layer may have hysteresis characteristics.

[0022] In some embodiments, the variable resistance layer may include transition metal oxides, transition metal nitrides, or both transition metal oxides and transition metal nitrides.

[0023] In some implementations, the compensation storage unit may be a first compensation storage unit, and the plurality of storage units may further include a second compensation storage unit, and the first compensation storage unit and the second compensation storage unit may be connected in series to the selected storage unit.

[0024] According to one embodiment, a method of operating a non-volatile memory device is provided. The non-volatile memory device includes a memory cell array having a vertically stacked structure and comprising a semiconductor layer and a variable resistance layer. The memory cell array includes a plurality of memory cells, each memory cell including a corresponding portion of the semiconductor layer and a corresponding portion of the variable resistance layer. The method includes: applying a first voltage to a compensation memory cell among the plurality of memory cells, the first voltage allowing a current of a certain magnitude to flow to the compensation memory cell in the memory cell array; applying a second voltage to selected memory cells among the plurality of memory cells, the second voltage allowing current to flow only to the corresponding portion of the variable resistance layer in the selected memory cell of the memory cell array; applying a third voltage to unselected memory cells among the plurality of memory cells, the third voltage allowing current to flow only to the semiconductor layer of the unselected memory cells of the memory cell array; and applying a programming voltage, which decreases due to the compensation memory cells, to the selected memory cells of the memory cell array.

[0025] In some implementations, the absolute value of the first voltage may be greater than the absolute value of the second voltage.

[0026] In some implementations, the absolute value of the first voltage may be less than the absolute value of the third voltage.

[0027] In some implementations, the magnitude of the first voltage may allow the resistance of the corresponding portion of the semiconductor layer in the compensation memory cell to be less than the resistance of the corresponding portion of the variable resistance layer in the compensation memory cell.

[0028] In some embodiments, the resistance of the corresponding portion of the semiconductor layer in the compensation memory cell may be less than or equal to 1 / 10 of the resistance of the corresponding portion of the variable resistance layer in the compensation memory cell.

[0029] In some implementations, the magnitude of the first voltage can allow compensation of the resistance of the corresponding portion of the semiconductor layer in the memory cell within 10 ohms. 5 Ωm -1 Up to 10 7 Ωm -1 Within the range.

[0030] In some implementations, the compensation storage unit and the selected storage unit can be connected in series with each other.

[0031] In some implementations, the corresponding portions of the semiconductor layer and the corresponding portions of the variable resistor layer in the compensation memory cell can be connected in parallel with each other.

[0032] According to one embodiment, a non-volatile memory device includes a substrate, a cell string on the substrate, bit lines connected to the cell string, a plurality of word lines on the substrate, and control logic. The cell string may include a plurality of memory cells stacked one on top of another, a semiconductor layer, and a variable resistor layer. Each of the plurality of memory cells in the cell string may include a corresponding portion of the semiconductor layer connected to a corresponding portion of the variable resistor layer. The plurality of memory cells may include unselected memory cells, compensated memory cells, and selected memory cells. The bit lines may be configured to apply a programming voltage to the cell string during a programming operation. The plurality of word lines may include unselected word lines connected to the corresponding portions of the semiconductor layer of the unselected memory cells, compensated word lines connected to the corresponding portions of the semiconductor layer of the compensated memory cells, and selected word lines connected to the corresponding portions of the semiconductor layer of the selected memory cells. During a programming operation, the control logic may be configured to apply an adjusted programming voltage to the selected memory cell based on applying an on-state voltage to the unselected word line, applying an off-state voltage to the selected word line, and applying a compensated voltage to the compensated word line. The adjusted programming voltage can be smaller than the programming voltage. The compensation voltage can be between the turn-on voltage and the turn-off voltage.

[0033] In some implementations, the absolute value of the compensation voltage can be greater than the absolute value of the turn-off voltage, and the absolute value of the compensation voltage can be less than the absolute value of the turn-on voltage.

[0034] In some implementations, the compensation memory cell and the selected memory cell can be connected in series with each other, and the variable resistance layer can directly contact the semiconductor layer.

[0035] In some implementations, the selected storage cell can be between an unselected storage cell and a compensation storage cell.

[0036] In some embodiments, the variable resistance layer may include transition metal oxides, transition metal nitrides, or both transition metal oxides and transition metal nitrides. Attached Figure Description

[0037] The above and other aspects, features and advantages of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0038] Figure 1 This is a block diagram of a storage system according to one embodiment;

[0039] Figure 2 yes Figure 1 A block diagram illustrating an implementation example of a storage device;

[0040] Figure 3 yes Figure 1 A block diagram of a storage cell array;

[0041] Figure 4 This is a diagram of the equivalent circuit corresponding to the memory block according to one embodiment;

[0042] Figure 5 This is a diagram illustrating the physical structure corresponding to a storage block according to one embodiment;

[0043] Figure 6A yes Figure 5 XZ cross-sectional view of the storage block;

[0044] Figure 6B yes Figure 5 YZ cross-sectional view of the storage block;

[0045] Figure 7 It operates in the programming mode of a non-volatile storage device according to one embodiment. Figure 4 A diagram of the equivalent circuit of the memory block;

[0046] Figure 8 This is a graph showing the relationship between the resistance of the compensated memory cell and the resistance of the selected memory cell in programming mode according to one embodiment.

[0047] Figure 9A and Figure 9BIt is a diagram of the current movement in a variable resistor layer in programming mode according to one embodiment;

[0048] Figure 10 This is a reference diagram illustrating a concept of a variable resistance layer capable of ensuring multiple resistance states according to one embodiment;

[0049] Figure 11 This is a diagram of the equivalent circuit in the programming mode of the memory block according to another embodiment;

[0050] Figure 12 This is a diagram of a memory block including a compensated memory cell without a variable resistance layer, according to another embodiment;

[0051] Figure 13 This is a diagram of the equivalent circuit of a memory block in read mode according to one embodiment;

[0052] Figure 14 It's about in Figure 13 A graph of current movement in the selected memory cell during read mode;

[0053] Figure 15 This is a diagram illustrating the circuitry during the read mode of a memory block according to another embodiment; and

[0054] Figure 16 It's about in Figure 15 A graph showing the movement of current in the selected memory cell during the read mode. Detailed Implementation

[0055] The embodiments will now be described in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, by referring to the accompanying drawings, only embodiments are described below to explain aspects. When used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire column of elements without modifying individual elements within that column when following a list of elements.

[0056] Phrases such as "in some embodiments of this disclosure" or "in one embodiment of this disclosure" throughout the specification do not necessarily represent the same embodiment of this disclosure.

[0057] Some embodiments of this disclosure can be represented as functional block structures, various processing stages, and / or various processing operations. Some or all of the functional blocks can be implemented by any number of hardware and / or software components configured to perform specified functions. For example, the functional blocks of this disclosure can be implemented by one or more microprocessors or circuit structures for performing desired and / or alternatively predetermined functions. Additionally, for example, the functional blocks of this disclosure can be implemented using any programming language or scripting language. The functional blocks can be implemented as algorithms that execute on one or more processors. Furthermore, this disclosure can employ any number of conventional techniques for electronic configurations, signal processing, and / or data processing, etc. The terms "mechanism," "element," "tool," and "configuration" are used extensively and are not limited to mechanical or physical components.

[0058] Additionally, the connecting lines or connectors shown in the various accompanying figures are intended to illustrate example functional relationships and / or physical or electrical connections between the various components. It should be noted that actual equipment may contain electrical connections, physical connections, or connections between components through many alternative or additional functional relationships.

[0059] The terms “consisting of” or “including (or comprising)” should not be construed or understood to include, without exception, all of the multiple elements or steps disclosed in this specification. In other words, it should be understood that some elements or steps may be excluded, or further additional elements or steps may be included.

[0060] When a layer, film, region, or panel is referred to as being "on" another element, it can be directly on / below / to the left / right of the other layer or substrate, or an intervening layer may also be present. In the following, one or more embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0061] It will be understood that although the terms "first" and "second" are used here to describe various elements, these elements should not be limited by these terms. The terms are only used to distinguish one element from others.

[0062] This disclosure will now be described in detail with reference to the accompanying drawings.

[0063] Figure 1 This is a block diagram of a storage system 10 according to one embodiment.

[0064] Reference Figure 1The storage system 10 may include a storage controller 100 and a storage device 200. The storage controller 100 performs control operations on the storage device 200. For example, the storage controller 100 provides the storage device 200 with an address (ADD) and a command (CMD) to perform programming (or writing), reading, and erasing operations on the storage device 200. Moreover, read data and data used for programming operations can be transferred between the storage controller 100 and the storage device 200.

[0065] The storage device 200 may include a cell array 210 and a voltage generator 220. The cell array 210 may include a plurality of memory cells arranged on regions where a plurality of word lines and a plurality of bit lines intersect each other. The cell array 210 includes non-volatile memory cells that store data in a non-volatile manner, and as non-volatile memory cells, the cell array 210 may include flash memory cells such as NAND flash memory cells or NOR flash memory cells. Hereinafter, one or more embodiments of the present disclosure will be described under the assumption that the cell array 210 includes a flash memory cell array 210 and the storage device 200 is a non-volatile storage device.

[0066] The storage controller 100 may include a record / read controller (also referred to as a "write / read controller") 110, a voltage controller 120, and a data determiner 130. In an example embodiment, the storage controller 100 may include processing circuitry, such as hardware including logic circuitry; a hardware / software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The storage controller 100 may operate in response to a request from a host (not shown) and may be configured to access the storage device 200 and control the operations discussed below, thereby turning the storage controller 100 into a dedicated controller. As discussed below, the storage controller 100 may improve the functionality of the storage device 200 by reducing and / or suppressing dielectric breakdown and current overshoot of selected storage cells and / or by allowing the recording of multi-resistance states in the storage cells of the storage device 200.

[0067] The record / read controller 110 can generate address ADD and command CMD to perform programming / read / erase operations on the memory cell array 210. Furthermore, the voltage controller 120 can generate control signals for controlling at least one voltage level used in the non-volatile memory device 200. As an example, the voltage controller 120 can generate voltage control signals for controlling the voltage level of word lines to read data from or program data onto the memory cell array 210.

[0068] Additionally, the data determiner 130 can perform a determination operation on data read from the non-volatile storage device 200. For example, by determining the data read from the memory cells, the number of on and / or off cells in the memory cells can be determined. As an operational example, when programming multiple memory cells, the state of the data from the memory cells is determined using a desired and / or alternatively predetermined read voltage to determine whether programming has been successfully completed on each cell. Alternatively or additionally, the storage device 200 can provide a pass / fail signal P / F to the storage controller 100 based on the read result of the read data. The storage controller 100 can refer to the pass / fail signal P / F and thus control the write and read operations of the memory cell array 210.

[0069] As described above, the storage cell array 210 may include non-volatile storage cells, for example, the storage cell array 210 may include flash storage cells. Moreover, flash storage cells may be implemented in various types, for example, the storage cell array 210 may include three-dimensional (or vertical) NAND (VNAND) storage cells.

[0070] Figure 2 yes Figure 1 A block diagram of an implementation example of the storage device 200.

[0071] like Figure 2 As shown, the storage device 200 may also include a line decoder 230, an input / output (I / O) circuit 240, and control logic 250.

[0072] The memory cell array 210 can be connected to one or more string select lines SSL, multiple word lines WL (WL1 to WLm-1, WLm, including normal word lines WL and dummy word lines WL), and one or more common source lines CSL, and can also be connected to multiple bit lines BL1, BL2 to BLn. Voltage generator 220 can generate one or more word line voltages V1, V2 to Vi that can be provided to the row decoder 230. Signals for programming / read / erase operations can be applied to the memory cell array 210 via bit lines BL1 to BLn.

[0073] Furthermore, the data to be programmed can be provided to the memory cell array 210 via the input / output circuitry 240, and the data to be read can be provided to an external source (e.g., a memory controller) via the input / output circuitry 240. In an example embodiment, the control logic 250 may include processing circuitry, such as hardware including logic circuitry; hardware / software combinations such as a processor executing software; or combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The control logic 250 may respond to input from the memory controller 100 (see... Figure 1 The control logic 250 operates in response to requests from the storage controller 100 and can provide various control signals related to storage operations to the line decoder 230 and voltage generator 220. As discussed below, the control logic 250 can improve the functionality of the storage device 200 by reducing and / or suppressing dielectric breakdown and current overshoot in the selected storage cells and / or by allowing the recording of multi-resistance states in the storage cells of the storage device 200.

[0074] According to the decoding operation of the line decoder 230, word line voltages V1 to Vi can be provided to the respective lines SSL, WL1 to WLm, and CSL. For example, word line voltages V1 to Vi can include serial select voltage, word line voltage, and ground select voltage. The serial select voltage can be provided to one or more serial select lines SSL, the word line voltage can be provided to one or more word lines WL1 to WLm, and the ground select voltage can be provided to one or more common source lines CSL.

[0075] Figure 3 yes Figure 1 A block diagram of the storage cell array 210.

[0076] Reference Figure 3 The storage cell array 210 includes multiple storage blocks BLK (BLK1, BLK2 to BLKz). Each storage block BLK (BLK1 to BLKz) has a three-dimensional (or vertical) structure. For example, each storage block BLK includes a structure extending upwards from a first to a third dimension. For example, as shown in reference... Figure 4 In the context of this discussion, each storage block BLK comprises multiple cell strings CS extending in a second direction. For example, multiple cell strings CS are provided along the first to third directions.

[0077] Each cell string CS is connected to the bit line BL, the string select line SSL, the word line WL, and the common source line CSL. That is, each memory block BLK (BLK1 to BLKz) is connected to multiple bit lines BL, multiple string select lines SSL, multiple word lines WL, and multiple common source lines CSL. The following will refer to... Figure 4 A more detailed description of the storage blocks BLK (BLK1 to BLKz).

[0078] Figure 4 This is a diagram of the equivalent circuit corresponding to the memory block BLKi according to one embodiment. As an example, Figure 3 One of the storage blocks BLK (BLK1 to BLKz) in the storage cell array 210 is shown in the figure.

[0079] Reference Figure 3 and Figure 4 The storage block BLKi consists of multiple cell strings CS (e.g., CS11 to CSkn). The multiple cell strings CS are arranged in rows and columns.

[0080] Each of the cell strings CS11 to CSkn includes a memory cell MC and a string selection transistor SST. The memory cells MC and string selection transistor SST in each of the cell strings CS11 to CSkn can be stacked in the height direction.

[0081] The multiple cell strings CS11 to CSkn are connected to different string select lines SSL1 to SSLk. For example, the string select transistors SST in cell strings CS11 to CS1n are all connected to the string select line SSL1. The string select transistors SST in cell strings CSk1 to CSkn are all connected to the string select line SSLk.

[0082] Multiple cell strings CS are connected to different bit lines BL1 to BLn. For example, the memory cell MC and the string select transistor SST in cell strings CS11 to CSk1 can be connected to bit line BL1, and the memory cell MC and the string select transistor SST in cell strings CS1n to CSkn can be connected to bit line BLn.

[0083] Multiple cell strings CS can be connected to different common source lines CSL1 to CSLk. For example, the string select transistors SST in cell strings CS11 to CS1n can be connected to the common source line CSL1, and the string select transistors SST in cell strings CSk1 to CSkn can be connected to the common source line CSLk.

[0084] Memory cells at the same height from the substrate (or string select transistor SST) are connected to the same word line WL, while memory cells at different heights from the substrate (or string select transistor SST) can be connected to different word lines WL1 to WLm respectively.

[0085] Figure 4 The storage block BLKi shown is an example. One or more implementations are not limited to this. Figure 4 The storage block BLKi is shown. For example, the number of rows of cell strings CS can be increased or decreased. As the number of rows of cell strings CS changes, the number of string select lines connected to the rows of cell strings CS and the number of cell strings CS connected to a bit line can also change. As the number of rows of cell strings CS changes, the number of common source lines connected to the rows of cell strings CS can also change.

[0086] The number of columns in a unit string CS can also be increased or decreased. As the number of columns in a unit string CS changes, the number of bit lines connected to the columns of the unit string CS and the number of unit strings CS connected to a string select line can also change.

[0087] The height of a cell string (CS) can be increased or decreased. For example, the number of memory cells stacked in each cell string (CS) can be increased or decreased. As the number of memory cells stacked in each cell string (CS) changes, the number of word lines (WL) can also change. For example, the number of string select transistors supplied to each cell string (CS) can be increased. As the number of string select transistors supplied to each cell string (CS) changes, the number of string select lines or common source lines can also change. With the increase in the number of string select transistors, the string select transistors can be stacked like memory cells (MC).

[0088] For example, write and read operations can be performed row by row of cell string CS. Cell string CS is selected row by row by common source line CSL, and can also be selected row by row by string select line SSL. Moreover, voltage can be applied on a unit of at least two common source lines CSL. Voltage can also be applied on a unit of all common source lines CSL.

[0089] Within the selected rows of the cell string CS, programming and reading operations can be performed on a page-by-page basis. A page can represent a row of memory cells MC connected to a word line WL. Within the selected rows of the cell string CS, memory cells MC can be selected by word lines WL on a page-by-page basis.

[0090] Additionally, each memory cell MC can correspond to a circuit in which transistors and resistors are connected in parallel.

[0091] Figure 5 This is a diagram illustrating the physical structure corresponding to a storage block according to one embodiment. Figure 6A yes Figure 5 A cross-sectional view of the storage block in the XZ plane. Figure 6B yes Figure 5 A cross-sectional view of the storage block in the YZ plane.

[0092] Referring to the accompanying drawings, a substrate 501 is prepared. Substrate 501 may comprise a silicon material doped with a first type of impurity. For example, substrate 501 may comprise a silicon material doped with a p-type impurity. For example, substrate 501 may comprise a p-type well (e.g., a pouch-type p-well). Hereinafter, it will be assumed that substrate 501 comprises p-type silicon. However, substrate 501 is not limited to p-type silicon.

[0093] A doped region 510 is provided in the substrate 501. For example, the doped region 510 may have a second type different from that of the substrate 501. For example, the doped region 510 may be n-type. In the following, it will be assumed that the doped region 510 is n-type. However, the doped region 510 is not limited to n-type. The doped region 510 may be a common source line.

[0094] On substrate 501, a plurality of gates 531 and a plurality of insulators 532 extending in a horizontal direction may be arranged alternately. That is, the plurality of gates 531 and the plurality of insulators 532 may be stacked alternately on top of each other in a vertical direction perpendicular to the horizontal direction. For example, the gates 531 may include a metallic material (e.g., copper, silver, etc.), and the insulators 532 may include silicon oxide, but are not limited thereto. Each gate 531 is connected to one of the word line WL and the serial select line SSL.

[0095] The post 520 is provided to penetrate a plurality of gates 531 and a plurality of insulators 532 in a vertical direction, wherein the plurality of gates 531 and the plurality of insulators 532 are arranged alternately.

[0096] The pillar 520 may include multiple layers. In one embodiment, the outermost layer of the pillar 520 may be a gate insulating layer 521. For example, the gate insulating layer 521 may include silicon oxide. The gate insulating layer 521 may be conformally stacked on the pillar 520.

[0097] Furthermore, the semiconductor layer 522 can be conformally deposited on the inner surface of the gate insulating layer 521. In one embodiment, the semiconductor layer 522 may include silicon material doped with a first type of impurity. The semiconductor layer 522 may include silicon material doped with the same type as the substrate 501. For example, when the substrate 501 includes silicon material doped with p-type impurities, the semiconductor layer 522 may also include silicon material doped with p-type impurities. Alternatively, the semiconductor layer 522 may include materials such as Ge, IGZO, GaAs, etc.

[0098] A variable resistance layer 523 may be disposed along the inner surface of the semiconductor layer 522. The variable resistance layer 523 may be disposed in contact with the semiconductor layer 522 and may be conformally stacked on the semiconductor layer 522. In one embodiment, the variable resistance layer 523 may comprise a material having a resistance that varies depending on the applied voltage. The variable resistance layer 523 may switch from a high resistance state to a low resistance state, or from a low resistance state to a high resistance state, depending on the voltage applied to the gate 531. The aforementioned variable resistance may be caused by oxygen vacancies in the variable resistance layer 523, or by changes in the current conduction mechanism in the variable resistance layer 523 attributable to electron capture / decapture.

[0099] The variable resistance layer 523 may comprise a material having hysteresis properties. For example, the variable resistance layer 523 may comprise transition metal oxides and / or transition metal nitrides. Specifically, the variable resistance layer 523 may comprise an oxide of at least one element selected from the group consisting of: zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), praseodymium (Pr), and silicon (Si). Moreover, the variable resistance layer 523 may comprise silicon nitrides and aluminum nitrides.

[0100] The insulating layer 524 may be filled within the variable resistance layer 523. For example, the insulating layer 524 may comprise silicon oxide.

[0101] Semiconductor layer 522 and variable resistance layer 523 may be in contact with doped region 510 (e.g., common source region).

[0102] Drain 540 can be provided on pillar 520. Drain 540 may include silicon material doped with a second type of impurity. For example, drain 540 may include silicon material doped with an n-type impurity.

[0103] Bit line 550 can be provided on drain 540. Drain 540 and bit line 550 can be connected to each other via contact plugs. Bit line 550 can include metallic and / or semiconductor materials, such as polysilicon. Bit line can be formed of conductive material.

[0104] and Figure 4 In contrast, multiple gates 531, multiple insulators 532, gate insulating layer 521, semiconductor layer 522, and variable resistor layer 523 are elements of the cell string CS. Specifically, gates 531, gate insulating layer 521, and semiconductor layer 522 are elements of a transistor, and variable resistor layer 523 can be a resistor.

[0105] As shown in the figure, because the variable resistor layer 523 and the semiconductor layer 522 of the transistor are directly bonded to each other, the variable resistor layer 523 can have a high resistance state or a low resistance state to record data on the memory cell MC. The variable resistor layer 523 and the semiconductor layer 522 of the transistor are connected in parallel in each memory cell MC, and the parallel connection structure is arranged continuously in the vertical direction to form a cell string CS. In addition, the common source line 510 and the bit line 550 can be connected to opposite ends of the cell string CS. When a voltage is applied to the common source line 510 and the bit line 550, programming, reading, and erasing operations can be performed on multiple memory cells MC.

[0106] According to the present invention, the memory block includes a variable resistance layer 523 instead of using a phase change material, thus solving problems such as heat generation and stress (pressure) caused when using a phase change material. Furthermore, because the memory block is configured and operated as described above, ion transfer between adjacent memory cells, as well as leakage current and operational failures due to ion transfer, can be prevented even when the memory cells included in the memory block are repeatedly operated. Because the scaling problem between memory cells in next-generation VNAND can be solved, the density in the memory block can be increased.

[0107] The memory block according to embodiments of this disclosure can be implemented as a chip for use as a neuromorphic computing platform. Additionally, the memory block according to embodiments of this disclosure can be implemented as a chip for configuring neural networks.

[0108] The storage controller 100 can control the storage device 200 to operate in programming mode.

[0109] Figure 7 According to the programming mode of a non-volatile storage device according to one embodiment Figure 4 The diagram shows the equivalent circuit of memory block 700.

[0110] exist Figure 7 In this context, each of the plurality of storage units 710, 720, and 730 may include Figure 5 It has a gate 531, a gate insulating layer 521, a variable resistance layer 523, and a semiconductor layer 522.

[0111] The plurality of storage cells 710, 720, and 730 in storage block 700 may include a compensation storage cell 710, a selected storage cell 720, and an unselected storage cell 730. The programming mode of the non-volatile storage device represents the mode in which programming operations are performed on storage cells MC, and the storage cell MC that is the target of the programming operation can be referred to as the selected storage cell 720. Conversely, the storage cell MC that is not the target of the programming operation can be referred to as the unselected storage cell 730.

[0112] The compensation storage unit 710 can represent a storage unit MC that adjusts the magnitude of the current flowing in the selected storage unit 720. Because the compensation storage unit 710 and the selected storage unit 720 are connected in series, the magnitude of the current flowing in the selected storage unit 720 can be controlled when the magnitude of the current flowing in the compensation storage unit 710 is controlled.

[0113] Control logic 250 can control the application of a turn-on voltage Von to the serial select line SSL connected to the selected memory cell 720 among the multiple serial select lines SSL. Additionally, among the multiple word lines WL, control logic 250 applies a compensation voltage Vcc to the word line WL connected to the compensation memory cell 710, applies a turn-off voltage Voff to the word line WL connected to the selected memory cell 720, and applies a turn-on voltage Von to the word line WL connected to the unselected memory cell 730.

[0114] The compensation voltage Vcc can be a voltage that allows a certain amount of current to flow in the compensation memory cell 710; for example, a certain amount of current can flow in the semiconductor layer 522 of the compensation memory cell 710. The turn-off voltage Voff is a voltage of a magnitude used to turn off the transistor and prevents current from flowing in the semiconductor layer 522 of the transistor included in the selected memory cell 720. The turn-on voltage Von is a voltage of a magnitude used to turn on the transistor and allows current to flow only in the semiconductor layer 522 of the transistor included in the unselected memory cell 730.

[0115] The magnitudes of the compensation voltage Vcc, turn-off voltage Voff, and turn-on voltage Von can vary depending on the type and thickness of the materials included in the gate 531, gate insulating layer 521, semiconductor layer 522, and variable resistor layer 523 in the memory cell MC. The absolute value of the turn-on voltage Von is generally greater than the absolute value of the turn-off voltage Voff.

[0116] The absolute value of the compensation voltage Vcc can be less than the absolute value of the turn-on voltage Von and greater than the absolute value of the turn-off voltage Voff. Furthermore, the compensation voltage Vcc can be such that the resistance of the semiconductor layer 522 in the compensation memory cell 710 is less than the resistance of the variable resistor layer 523. For example, the compensation voltage Vcc can be such that the resistance of the semiconductor layer 522 in the compensation memory cell 710 is equal to or less than 1 / 10 of the resistance of the variable resistor layer 523 in the compensation memory cell 710.

[0117] Alternatively, the compensation voltage Vcc can be adjusted to compensate for a resistance of 10 ohms in the semiconductor layer 522 of the memory cell 710. 5 Ωm -1 Up to 10 7 Ωm -1Or the resistance of the variable resistor layer 523 of the compensation storage cell 710 is 10. 8 Ωm -1 Up to 10 11 Ωm -1 Within the range.

[0118] Because the semiconductor layer 522 and the variable resistor layer 523 in the compensation memory cell 710 are connected in parallel, and the resistance of the semiconductor layer 522 is relatively smaller than the resistance of the variable resistor layer 523, the magnitude of the current flowing in the compensation memory cell 710 can be determined based on the magnitude of the current flowing in the semiconductor layer 522 of the compensation memory cell 710. Therefore, the magnitude of the current flowing in the compensation memory cell 710 can be determined based on the magnitude of the compensation voltage Vcc applied to the transistor of the compensation memory cell 710.

[0119] Additionally, the programming voltage Vprogram can be applied to one of the multiple bit lines BL connected to the selected memory cell 720. The programming voltage Vprogram can be provided from an external source, such as the memory controller 100, via the input / output circuit 240. The programming voltage Vprogram is the voltage used to record data on the memory cell MC, and the magnitude of the programming voltage Vprogram can vary depending on the data.

[0120] Of the multiple bit lines BL, the bit line BL that is not connected to the selected memory cell 720 can be grounded or floated. Because the bit line that is not connected to the selected memory cell 720 is grounded or floated, power loss due to leakage current can be prevented. Therefore, the control logic 250 can perform programming operations on the selected memory cell 720.

[0121] In programming mode, because a turn-off voltage Voff is applied to the selected memory cell 720, the semiconductor layer 522 of the selected memory cell 720 can have insulating properties. Conversely, because a turn-on voltage Von is applied to the unselected memory cell 730, the semiconductor layer 522 of the unselected memory cell 730 can have conductive properties. Therefore, due to the programming voltage Vprogram, a voltage difference exists between the compensation memory cell 710 and the selected memory cell 720.

[0122] Because a certain current flows through the compensated memory cell 710, a programming voltage Vprogram' of the voltage drop across the compensated memory cell 710 is applied to the selected memory cell 720. The programming voltage Vprogram' (also called the regulated programming voltage) is less than the programming voltage Vprogram. Therefore, dielectric breakdown and current overshoot attributable to the programming voltage Vprogram in the selected memory cell 720 can be limited and / or suppressed.

[0123] Figure 8 This illustrates the resistance R of the compensation storage unit 710 in programming mode according to one embodiment. CC and the resistor R of the selected memory cell 720 RS A diagram showing the relationships between them.

[0124] like Figure 8 As shown, the memory block may include a gate 531, an insulator 532, a gate insulating layer 521, a semiconductor layer 522, a variable resistor layer 523, and an insulating layer 524 on a substrate (not shown). The gate insulating layer 521, the semiconductor layer 522, the variable resistor layer 523, and the insulating layer 524 may extend in the z-direction. The gate 531 and the insulator 532 may be alternately stacked in the z-direction and extend in a direction perpendicular to the z-direction.

[0125] In addition, the gate 531, insulator 532, gate insulating layer 521 and semiconductor layer 522 are transistor elements, and the variable resistor layer 523 can correspond to a resistor.

[0126] In programming mode, control logic 250 can control the application of a compensation voltage Vcc to the gate 531a of the compensation memory cell 710, the application of a turn-off voltage Voff to the gate 531b of the selected memory cell 720, and the application of a turn-on voltage Von to the gate 531c of the unselected memory cell 730. Therefore, the semiconductor layer 522b of the selected memory cell 720 has insulating properties, while the semiconductor layer 522c of the unselected memory cell 730 can have conductive properties. When the programming voltage Vprogram is applied to the bit line electrically connected to the selected memory cell 720, a voltage difference exists between the compensation memory cell 710 and the selected memory cell 720.

[0127] Furthermore, since a certain magnitude of current flows through the compensation storage cell 710 due to the compensation voltage Vcc, and the compensation storage cell 710 and the selected storage cell 720 are connected in series, the aforementioned voltage difference can be distributed between the compensation storage cell 710 and the selected storage cell 720. That is, the magnitude of the current flowing through the selected storage cell 720 is controlled by the compensation voltage Vcc applied to the compensation storage cell 710, and the programming voltage Vprogram', which decreases due to the compensation storage cell 710, can be applied to the selected storage cell 720.

[0128] Because the magnitude of the current flowing through the selected memory cell 720 is controlled by the compensation memory cell 710, dielectric breakdown and current overshoot in the selected memory cell 720 during programming mode can be limited and / or suppressed. Furthermore, because the magnitude of the current flowing through the selected memory cell 720 can be adjusted by regulating the compensation voltage Vcc applied to the compensation memory cell 710, the selected memory cell 720 can have various levels of resistance. Therefore, more information can be recorded on the memory cell MC.

[0129] Because oxygen vacancies in the variable resistance layer 523b of the selected memory cell 720 move toward the semiconductor layer 522b due to the voltage difference, the variable resistance layer 523b can be in a low-resistance state. The low-resistance state of the variable resistance layer 523b of the selected memory cell 720 indicates that the value of the resistors included in the selected memory cell 720 has decreased. The variable resistance layer 523 includes a variable resistance layer 523a for compensating the memory cell 710, a variable resistance layer 523b for the selected memory cell 720, and a variable resistance layer 523c for the unselected memory cell 730.

[0130] Figure 9A and Figure 9B It is a diagram of the current movement in the variable resistor layer 523 in programming mode according to one embodiment.

[0131] The decreasing programming voltage Vprogram' allows oxygen vacancies in the variable resistor layer 523b corresponding to the selected memory cell 720 to move toward the semiconductor layer 522b. For example... Figure 9A As shown, when the density of oxygen vacancies is high in the region of the variable resistance layer 523b adjacent to the semiconductor layer 522b, conductive filaments are generated. Therefore, the variable resistance layer 523b is in a low-resistance state, and the selected memory cell 720 can have ohmic conductivity.

[0132] Or, such as Figure 9B As shown, when the oxygen vacancy density is low in the region of the variable resistance layer 523b adjacent to the semiconductor layer 522b, the decreasing programming voltage Vprogram' allows electrons to be filled in traps spaced apart from each other at constant intervals within the variable resistance layer 523b. Therefore, the variable resistance layer 523b is in a low-resistance state due to the change in current conduction type, and the selected memory cell 720 can have bulk conductivity characteristics such as Hopping, SCLC, and Poole-Frenkel.

[0133] Figure 10 This is a reference diagram illustrating the concept of a variable resistance layer 523 capable of ensuring multiple resistance states according to one embodiment.

[0134] exist Figure 10 In the diagram, (i) represents the current-voltage characteristics of the transistor in the compensation memory cell 710. The current flowing on the semiconductor layer 522 of the transistor can vary depending on the voltage applied to the gate 531 of the transistor, which means that the current applied to the selected memory cell 720 can be controlled by controlling the voltage applied to the gate 531 of the transistor.

[0135] exist Figure 10 In the diagram, (ii) represents the current-voltage characteristics of the variable resistance layer 523 included in the selected memory cell 720. The variable resistance layer 523 of the selected memory cell 720 may have hysteresis characteristics. The variable resistance layer 523 of the memory cell MC may have different resistance characteristics before and after current flow.

[0136] exist Figure 10 In diagram (iii), the current-voltage characteristics of the variable resistance layer 523 according to the applied current are shown. The current applied to the selected memory cell 720 can be determined by the compensation memory cell 710 (that is, the voltage at the gate 531 of the compensation memory cell 710). Furthermore, the variable resistance layer 523 of the selected memory cell 720 can have various levels of resistance depending on the magnitude of the applied current. That is, the variable resistance layer 523 can have resistance characteristics that vary depending on the magnitude of the applied current. Therefore, more information can be recorded on a memory cell MC.

[0137] Figure 11 This is a diagram of the equivalent circuit in the memory block programming mode according to another embodiment. When Figure 7 and Figure 11 When compared to each other, Figure 7 In the middle, a unit string includes a compensation storage unit 710, while Figure 11 In the process, a unit string includes multiple compensation storage units 710, such as a first compensation storage unit 710a and a second compensation storage unit 710b. Figure 11 Two compensation storage units 710a and 710b are shown, but one or more embodiments are not limited thereto. That is, three or more compensation storage units may be provided.

[0138] Multiple first and second compensation memory cells, such as first compensation memory cell 710a and second compensation memory cell 710b, are connected in series to the selected memory cell 720. The magnitude of the current flowing through each of the first compensation memory cells 710a and second compensation memory cells 710b can be determined based on the compensation voltage Vcc applied to each of the first compensation memory cells 710a and second compensation memory cells 710b. The magnitude of the current applied to the selected memory cell 720 can be determined based on the minimum magnitude of the current flowing through the multiple compensation memory cells, such as first compensation memory cells 710a and second compensation memory cells 710b. The falling programming voltage Vprogram' applied to the selected memory cell 720 connected to the multiple compensation memory cells 710a and 710b is much lower than the falling programming voltage applied to the selected memory cell 720 connected to one compensation memory cell.

[0139] As in the selected memory cell 720 and the unselected memory cell 730, the compensation memory cell 710 may include a transistor and a variable resistance layer. However, one or more embodiments are not limited thereto. In some embodiments, the variable resistance layer may be omitted and / or not included in the compensation memory cell 710.

[0140] Figure 12 This is a diagram of a memory block according to another embodiment, including a compensation memory cell 710 that does not contain a variable resistance layer 523. (See diagram for reference.) Figure 12 As shown, the compensation memory cell 710c is located at the top of the memory block. The compensation memory cell 710c may include a gate 531, a gate insulating layer 521, and a semiconductor layer 522. The semiconductor layer 522 of the compensation memory cell 710c is directly connected to the drain 540 and can be connected to a common source line 510 via the semiconductor layers 522 of multiple memory cells MC. Figure 12 In this embodiment, the compensation storage unit 710c is located at the top of the storage block, but one or more embodiments are not limited to this. The compensation storage unit 710c may be arranged at the bottom of the storage block or in the middle of the storage block.

[0141] Figure 13 This is a diagram of the equivalent circuit of a memory block 800 in read mode according to one embodiment. (Refer to...) Figure 13 Each of the multiple storage cells MC in storage block 800 may include Figure 5 The diagram shows a gate 531, a gate insulating layer 521, a semiconductor layer 522, and a variable resistor layer 523.

[0142] The storage cell MC in storage block 800 may include a compensation storage cell 710, a selected storage cell 720, and an unselected storage cell 730. The read mode of the non-volatile storage device represents the mode in which a read operation is performed on the storage block, and the selected storage cell 720 may represent the storage cell MC to which a read operation is performed.

[0143] During read mode, among the multiple string select lines SSL, control logic 250 can apply an on-state voltage Von to the string select line SSL connected to the selected memory cell 720, and can apply an off-state voltage Voff to the string select line not connected to the selected memory cell 720. Additionally, control logic 250 can apply an on-state voltage Von to the word line WL among the multiple word lines WL connected to the compensation memory cell 710 and the unselected memory cell 730, and can apply an off-state voltage Voff to the word line WL connected to the selected memory cell 720.

[0144] Here, the on-state voltage Von has a magnitude that enables the transistor to conduct (e.g., allows current to flow only on the semiconductor layer 522 of the transistor). The off-state voltage Voff has a magnitude that enables the transistor to turn off (e.g., prevents current from flowing on the semiconductor layer 522 of the transistor). The values ​​of the on-state voltage Von and the off-state voltage Voff can vary depending on the type, thickness, etc. of the materials included in the gate 531, gate insulating layer 521, semiconductor layer 522, and variable resistor layer 523 in the multiple memory cells MC. The absolute value of the on-state voltage Von is generally greater than the absolute value of the off-state voltage Voff.

[0145] Additionally, among the multiple bit lines BL, a read voltage Vread is applied to the bit line BL connected to the selected memory cell 720 to perform a read operation on the selected memory cell 720. The read voltage Vread can be provided externally (e.g., from the memory controller 100) via the input / output circuit 240. The read voltage Vread can be a voltage used to read data recorded on the selected memory cell 720. Among the multiple bit lines BL, the bit line BL not connected to the selected memory cell 720 can be grounded or floating. In this way, a read operation can be performed on the selected memory cell 720.

[0146] Figure 14 It's about in Figure 13 A graph showing the current movement in the selected memory cell 720 during the read mode.

[0147] In read mode, a read voltage Vread is applied to the bit line BL connected to the selected memory cell 720, and a turn-on voltage Von is applied to the compensation memory cell 710 and the unselected memory cell 730. Therefore, the semiconductor layer 522a in the compensation memory cell 710 and the semiconductor layer 522c in the unselected memory cell 730 are conductive. Consequently, the read current Iread flows through the semiconductor layer 522a of the compensation memory cell 710 and the semiconductor layer 522c of the unselected memory cell 730. However, because a turn-off voltage Voff is applied to the selected memory cell 720, the read current Iread flows only through the variable resistance layer 523b of the selected memory cell 720, and a read operation can be performed on the selected memory cell 720.

[0148] The resistance states of the variable resistor layer 523 generally have a logarithmic scale (dynamic range) distribution. Therefore, the ratio of the maximum to the minimum resistance of the variable resistor layer 523 may be large, and the deviation may also be significant. The resistance variation of the variable resistor layer 523 can exceed the limits of the dynamic range of the sensing amplifier that senses the resistor. Therefore, it may be difficult to integrate the sensing amplifier into the memory cell MC or other memory devices.

[0149] Figure 15 This is a diagram illustrating the circuitry during read mode of a memory block according to another embodiment. (See also...) Figure 2 , Figure 6A and Figure 15 During read mode, among the multiple string select lines SSL, control logic 250 can apply an on-state voltage Von to the string select line SSL connected to the selected memory cell 720, and can apply an off-state voltage Voff to the string select line not connected to the selected memory cell 720. Additionally, control logic 250 can apply an on-state voltage Von to the word lines WL connected to the compensated memory cell 710 and the unselected memory cell 730.

[0150] Control logic 250 can apply a current-on voltage Vion to the word line WL connected to the selected memory cell 720. The current-on voltage Vion can be a magnitude that allows current to flow across both the semiconductor layer 522 and the variable resistor layer 523 of the transistors included in the selected memory cell 720. The absolute value of the current-on voltage Vion can be greater than the absolute value of the turn-off voltage Voff and less than the absolute value of the turn-on voltage Von. The value of the current-on voltage Vion can vary depending on the type and thickness of the materials included in the gate 531, gate insulating layer 521, semiconductor layer 522, and variable resistor layer 523 of the multiple memory cells MC. In particular, the current-on voltage Vion can allow the resistance distribution of the selected memory cell 720 to have a linear scaling.

[0151] Additionally, the read voltage Vread can be applied to one of the multiple bit lines BL connected to the selected memory cell 720. The read voltage Vread can be obtained from an external source (e.g., the memory controller 100) via the input / output circuit 240. Figure 1 Provided. Among the multiple bit lines BL, the bit line BL that is not connected to the selected memory cell 720 can be grounded or floating. In this way, a read operation can be performed on the selected memory cell 720.

[0152] Figure 16 It's about in Figure 15 A graph showing the current flow in the selected memory cell 720 during the read mode.

[0153] In read mode, a read voltage Vread is applied to the bit line BL connected to the selected memory cell 720, and a turn-on voltage Von is applied to the unselected memory cell 730, thus making the semiconductor layer 522c in the unselected memory cell 730 conductive. Therefore, the read current Iread flows through the semiconductor layer 522c of the unselected memory cell 730. However, because the turn-on voltage Vion is applied to the selected memory cell 720, the read current Iread flows through both the semiconductor layer 522b and the variable resistor layer 523b of the selected memory cell 720.

[0154] The current-on voltage Vion can have a resistance R in the semiconductor layer 522b of the memory cell 720 that allows selection. si The resistance R of the variable resistance layer 523b of the selected memory cell 720 RS Within a similar range. Depending on the magnitude of the current-on voltage Vion, the resistance of the semiconductor layer 522b of the selected memory cell 720 is equal to or greater than the minimum resistance of the variable resistance layer 523b of the selected memory cell 720, or equal to or less than the maximum resistance of the variable resistance layer 523b of the selected memory cell 720. Alternatively, when the resistance range of the variable resistance layer 523b is from 10... 4 Ωm -1 Up to 10 12 Ωm -1 At that time, the magnitude of the on-state voltage Vion can vary from 10 to the resistance of the semiconductor layer 522b. 4 Ωm -1 Up to 10 12 Ωm -1Within a certain range. Alternatively, the magnitude of the current-on voltage Vion can allow the ratio of the maximum to the minimum combined resistance of the semiconductor layer 522b and the variable resistor layer 523b in the selected memory cell 720 to be 10 or less. Therefore, the total resistance of the selected memory cell 720 can be determined as the parallel resistance of the semiconductor layer 522b and the variable resistor layer 523b.

[0155] Because the total resistance of the selected memory cell 720 is determined to be the resistance of the parallel-connected semiconductor layer 522b and variable resistance layer 523b, the total resistance of the selected memory cell 720 can have a linear scaling distribution even when the resistance state of the variable resistance layer 523b is logarithmically scaled. Therefore, the uniformity of the resistance state relative to the memory cell MC can be improved, and a current within a certain range can be output from the selected memory cell 720, thereby improving the combination characteristics of the sensing amplifier relative to sensing the selected memory cell 720.

[0156] According to this disclosure, various levels of resistance states can be generated on the selected memory cell by controlling the magnitude of the current flowing through it. Because the memory cell can have various levels of resistance states, more information can be stored on it. In read mode, by applying a voltage within the range where the semiconductor layer and the variable resistor layer can act as resistors to the memory cell of the non-volatile memory device, the resistance value of the memory cell can be distributed within a linear scaling range. This improves the uniformity of the current output from the non-volatile memory device. Furthermore, a sensing amplifier for detecting the current of the non-volatile memory device can be easily incorporated.

[0157] The above description of this disclosure is provided for illustrative purposes, and those skilled in the art will understand that various changes and modifications can be made without altering the technical concept and essential features of this disclosure. Therefore, the embodiments of this disclosure set forth herein or shown above are to be interpreted in an illustrative and non-limiting sense. For example, each component described as having a single type may be implanted in a distributed manner. Similarly, components described as distributed may be implanted in a combined manner.

[0158] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

[0159] This application claims the benefit of Korean Patent Application No. 10-2019-0092660, filed on July 30, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A non-volatile storage device, comprising: A memory cell array having a vertically stacked structure, the memory cell array including a semiconductor layer and a variable resistor layer, the memory cell array including a plurality of memory cells, each memory cell including a corresponding portion of the semiconductor layer and a corresponding portion of the variable resistor layer, the plurality of memory cells including unselected memory cells, compensated memory cells and selected memory cells; Bit lines are configured to apply programming voltages to the memory cell array; as well as The control logic is configured to apply an adjusted programming voltage to the selected memory cell based on applying a first voltage to the compensation memory cell, applying a second voltage to the selected memory cell, and applying a third voltage to the unselected memory cell. The adjusted programming voltage decreases due to the compensation memory cell compared to the programming voltage. The first voltage allows a certain magnitude of current to flow to the compensation memory cell, the second voltage allows the current to flow only to the corresponding portion of the variable resistance layer of the selected memory cell, and the third voltage allows the current to flow only to the semiconductor layer of the unselected memory cell.

2. The non-volatile storage device according to claim 1, wherein the absolute value of the first voltage is greater than the absolute value of the second voltage.

3. The non-volatile storage device according to claim 1, wherein the absolute value of the first voltage is less than the absolute value of the third voltage.

4. The non-volatile memory device of claim 1, wherein the magnitude of the first voltage allows the resistance of the corresponding portion of the semiconductor layer in the compensated memory cell to be less than the resistance of the corresponding portion of the variable resistance layer in the compensated memory cell.

5. The non-volatile memory device according to claim 1, wherein the resistance of the corresponding portion of the semiconductor layer in the compensation memory cell is less than or equal to 1 / 10 of the resistance of the corresponding portion of the variable resistance layer in the compensation memory cell.

6. The non-volatile storage device according to claim 1, wherein, Based on the control logic, the first voltage is applied to the compensation memory cell, the magnitude of which allows the resistance of the corresponding portion of the semiconductor layer in the compensation memory cell to be within 10 ohms. 5 Ωm -1 Up to 10 7 Ωm -1 Within the range.

7. The non-volatile storage device according to claim 1, wherein, Based on the control logic, the first voltage is applied to the compensation memory cell, the magnitude of which allows the resistance of the corresponding portion of the variable resistance layer in the compensation memory cell to be within 10. 8 Ωm -1 Up to 10 11 Ωm -1 Within the range.

8. The non-volatile storage device of claim 1, wherein the compensation storage cell and the selected storage cell are connected in series with each other.

9. The non-volatile memory device of claim 1, wherein the control logic is configured to cause a current of the specified magnitude to flow to the corresponding portion of the variable resistance layer in the selected memory cell during a programming operation.

10. The non-volatile memory device of claim 1, wherein the corresponding portion of the semiconductor layer in the compensation memory cell and the corresponding portion of the variable resistance layer in the compensation memory cell are connected in parallel with each other.

11. The non-volatile storage device of claim 1, wherein the storage cell array comprises: The semiconductor layer extending in the first direction; A plurality of gates and a plurality of insulators extend in a second direction perpendicular to the first direction, the plurality of gates and the plurality of insulators being arranged alternately; A gate insulating layer extends in the first direction between the plurality of gates, the plurality of insulators and the semiconductor layer; as well as The variable resistance layer extends on the semiconductor layer in the first direction.

12. The non-volatile memory device of claim 11, wherein the variable resistance layer is in contact with the semiconductor layer.

13. The non-volatile memory device of claim 11, wherein the variable resistance layer is spaced apart from the gate insulating layer and the semiconductor layer is located between them.

14. The non-volatile memory device of claim 1, wherein the variable resistance layer has hysteresis characteristics.

15. The non-volatile memory device of claim 1, wherein the variable resistance layer comprises a transition metal oxide, a transition metal nitride, or both the transition metal oxide and the transition metal nitride.

16. The non-volatile storage device according to claim 1, wherein The compensation storage unit is the first compensation storage unit. The plurality of storage units also include a second compensation storage unit, and The first compensation storage unit and the second compensation storage unit are each connected in series to the selected storage unit.

17. A method of operating a non-volatile memory device, the non-volatile memory device comprising a memory cell array having a vertically stacked structure, the memory cell array comprising a semiconductor layer and a variable resistor layer, the memory cell array comprising a plurality of memory cells, each memory cell comprising a corresponding portion of the semiconductor layer and a corresponding portion of the variable resistor layer, the method comprising: A first voltage is applied to the compensation memory cell among the plurality of memory cells, the first voltage allowing a certain amount of current to flow into the compensation memory cell in the memory cell array; A second voltage is applied to a selected memory cell among the plurality of memory cells, the second voltage allowing current to flow only to the corresponding portion of the variable resistance layer in the selected memory cell of the memory cell array; A third voltage is applied to the unselected memory cells among the plurality of memory cells, the third voltage allowing current to flow only to the semiconductor layer of the unselected memory cells in the memory cell array; as well as The programming voltage that decreases due to the compensation memory cell is applied to the selected memory cell in the memory cell array.

18. The operating method according to claim 17, wherein the absolute value of the first voltage is greater than the absolute value of the second voltage.

19. The operating method according to claim 17, wherein the absolute value of the first voltage is less than the absolute value of the third voltage.

20. The method of operation according to claim 17, wherein the magnitude of the first voltage allows the resistance of the corresponding portion of the semiconductor layer in the compensated memory cell to be less than the resistance of the corresponding portion of the variable resistance layer in the compensated memory cell.

21. The method of operation according to claim 17, wherein the resistance of the corresponding portion of the semiconductor layer in the compensation memory cell is less than or equal to 1 / 10 of the resistance of the corresponding portion of the variable resistance layer in the compensation memory cell.

22. The method of operation according to claim 17, wherein the magnitude of the first voltage allows the resistance of the corresponding portion of the semiconductor layer in the compensated memory cell to be within 10 ohms. 5 Ωm -1 Up to 10 7 Ωm -1 Within the range.

23. The method of operation according to claim 17, wherein the compensation storage unit and the selected storage unit are connected in series with each other.

24. The method of operation according to claim 17, wherein the corresponding portions of the semiconductor layer and the corresponding portions of the variable resistance layer in the compensation memory cell are connected in parallel with each other.

25. A non-volatile storage device, comprising: Substrate; A cell string on the substrate, the cell string comprising a plurality of memory cells stacked on top of one another, a semiconductor layer and a variable resistor layer, each of the plurality of memory cells in the cell string comprising a corresponding portion of the semiconductor layer, the corresponding portion of the semiconductor layer being connected to a corresponding portion of the variable resistor layer, the plurality of memory cells comprising an unselected memory cell, a compensated memory cell and a selected memory cell; Bit lines connected to the cell string are configured to apply a programming voltage to the cell string during programming operations; The substrate has a plurality of word lines, the plurality of word lines including unselected word lines connected to the corresponding portion of the semiconductor layer of the unselected memory cell, compensation word lines connected to the corresponding portion of the semiconductor layer of the compensation memory cell, and selected word lines connected to the corresponding portion of the semiconductor layer of the selected memory cell; as well as The control logic, during the programming operation, is configured to apply an adjusted programming voltage to the selected memory cell based on applying an on-state voltage to the unselected word line, applying an off-state voltage to the selected word line, and applying a compensation voltage to the compensation word line. The adjusted programming voltage is less than the magnitude of the original programming voltage. The magnitude of the compensation voltage is between the magnitude of the on-state voltage and the magnitude of the off-state voltage.

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