Multi-chip package

Abstract

A multi-chip package includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a primary integrated circuit that is coupled to one or more secondary integrated circuits, particularly using the back surface of the primary integrated circuit. BACKGROUND

[0002] Coupling a primary integrated circuit to one or more smaller secondary integrated circuits (ICs) is typically performed on the surface of the primary IC where active devices are disposed, sometimes referred to as the "active surface" or "top surface." The opposite surface of the primary IC is the "passive surface" or "bottom surface." This active surface of the IC or die is typically extended to accommodate the total area for bond pads for the primary IC and bond pads for the secondary ICs. The total area includes any guard band or die boundary as specified by the design of the IC.

[0003] Providing more than one die in a package provides a variety of functionality that is beneficial for different applications. Different dies and ICs have different technology capabilities and are optimized by selecting particular materials and processes to form the IC or die, and therefore not all ICs can be easily manufactured in the same die and coupled together after manufacture.

[0004] Examples of multi-chip packages include a complementary metal-oxide-semiconductor (CMOS) digital processor (primary IC) coupled to a gallium arsenide (GaAs) transceiver (secondary IC), a low-frequency synthesizer (primary IC) coupled to a high-frequency voltage-controlled oscillator (VCO) and prescaler (secondary IC), and a low-voltage CMOS memory (primary IC) coupled to a high-voltage power regulator (secondary IC). The primary IC is sometimes referred to as the "parent" or "host," and the secondary IC is referred to as the "child." SUMMARY

[0005] The present disclosure relates to coupling one or more secondary integrated circuits or dies to a larger primary IC or die with minimal increase in the overall die area of the primary IC while maintaining compatibility with current front-end semiconductor processes.

[0006] In one embodiment, a first die includes a recess or trench in a passive surface of the first die, where a second die is positioned in the recess. The first die includes a contact pad exposed from the passive surface, and is coupled to the second die by a trace or electrical connection that extends from the recess to the contact pad.

[0007] The present disclosure describes a multi-chip package including a first integrated circuit including a plurality of solder balls and a shaped passive surface. At an edge of the first integrated circuit, a first conductive layer positioned medially within the first integrated circuit is coupled to a second conductive layer formed on the shaped passive surface. A second integrated circuit is coupled to the second conductive layer of the first integrated circuit. The second integrated circuit is positioned in a first thinned region on a second side of the first integrated circuit. A second thinned region is adjacent to the edge of the first integrated circuit. At the second thinned region, a portion of the second conductive layer is exposed and coupled to the first integrated circuit. The first thinned region can be a recess on the second side such that the second integrated circuit is coupled to a conductive trace within the recess.

[0008] In another embodiment of the present disclosure, a package includes a first die and a second die. The first die is larger than the second die. The first die includes a semiconductor substrate having an active surface and a passive surface. The second die includes a semiconductor substrate having an active surface and a passive surface.

[0009] A redistribution layer is on the active surface of the substrate of the first die, including solder balls or external contacts on a first surface of the package. A plurality of contact pads are coplanar with the active surface of the substrate of the first die. The plurality of contact pads are exposed by removing portions of the substrate from the passive surface of the first die, the removing portions of the substrate forming a first thinned region at an edge of the first die and a second thinned region at a central region of the first die.

[0010] The second die is positioned in the second thinned region. Solder balls or electrical contacts of the second die are coupled to electrical traces that extend from the second thinned region across the thinned passive surface of the first die and are coupled to the plurality of contact pads. The package can include a mold compound surrounding the first die and the second die. BRIEF DESCRIPTION OF DRAWINGS

[0011] Reference will now be made to the drawings. In the drawings, like reference numerals identify like elements or acts. However, different reference numerals can be used to identify the same or similar elements. The size and relative positions of elements in the drawings are not necessarily drawn to scale. Some of these elements can be exaggerated and positioned to improve drawing legibility.

[0012] Figure 1 is a cross-sectional view of a multi-chip package according to a preferred embodiment.

[0013] Figure 2 is a plan view of a multi-chip package according to an embodiment of Figure 1 , with a mold compound omitted for clarity.

[0014] Figure 3 is a plan view of a multi-chip package according toFigure 1 A cross-sectional view of the first integrated circuit before the process of coupling the second integrated circuit begins, according to an embodiment.

[0015] Figure 4 It is based on Figure 1 A cross-sectional view of the first integrated circuit after the grooves have been etched into the first integrated circuit and the area near the edge of the first integrated circuit has been thinned, according to an embodiment.

[0016] Figure 5 It is based on Figure 1 A cross-sectional view of the first integrated circuit after the deposition and patterning of the dielectric, according to an embodiment.

[0017] Figure 6 It is based on Figure 1 A cross-sectional view of the first integrated circuit after the conductive layer has been deposited and patterned, according to an embodiment.

[0018] Figure 7 It is based on Figure 1 A cross-sectional view of the first integrated circuit and the second integrated circuit coupled to the first integrated circuit in an embodiment.

[0019] Figure 8 It is based on Figure 1 A cross-sectional view of a package including a first integrated circuit and a second integrated circuit, according to an embodiment of the invention.

[0020] Figure 9 This is a cross-sectional view of an alternative embodiment of a multi-chip package. Detailed Implementation

[0021] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the art will recognize that the embodiments can be practiced without one or more of these specific details or using other methods, components, materials, etc. In other instances, well-known structures or methods associated with chip processing are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0022] Unless the context otherwise indicates, throughout the following specification and claims, the word “comprising” and its variations (such as “having” and “including”) shall be interpreted in an open, inclusive sense, meaning “including but not limited to”. Furthermore, unless the context clearly specifies otherwise, the terms “first,” “second,” and similar indicators of sequence shall be interpreted as interchangeable.

[0023] Throughout this specification, reference can be made to "one embodiment" or "an embodiment." This does not necessarily refer to the same embodiment, although it may. Different

[0024] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its broadest sense, including either or both of the constituent terms, unless the content clearly dictates otherwise.

[0025] Reference is made to Figure 1 In one preferred embodiment, a multi-chip device or package 100 includes a "parent" or first integrated circuit 102 coupled to a "child" or second integrated circuit 104. The first integrated circuit 102 can be referred to as a first die and the second integrated circuit 104 can be referred to as a second die. The first integrated circuit includes a first side 106, a second side 108, and an edge or sidewall 110. The first integrated circuit 102 also includes a semiconductor substrate 112 having an active first side 114 or first surface and having an inactive second side 116 or second surface. The semiconductor substrate can be silicon or any other suitable semiconductor material.

[0026] The active first side 114 of the substrate 112 includes active and passive components 111 formed in and on the substrate. The active and passive components can include transistors, resistors, capacitors, and other circuitry useful in integrated circuits. Aspects of the active and passive components, including electrical connections, are formed in a plurality of dielectric and metal layers formed on the active first side 114 of the substrate 112. For example, a gate 113 is part of an exemplary transistor that includes dielectric sidewalls and source / drain regions in the substrate. The gate 113 and the source / drain regions are coupled to a plurality of interconnect or conductive layers 149 that provide power and signals through the integrated circuit. For simplicity, not all connections are shown. The connections illustrated are described below.

[0027] A first dielectric layer 115 is formed on the active first side 114 of the substrate and surrounds the gate 113. A plurality of conductive layers 149 includes a first plurality of vias 144 that couple devices formed on and in the substrate to a plurality of contact pads, such as the pad array 136, through the respective layers. The vias 144 are formed in a second dielectric layer 117. A first interconnect layer 146, which can be metal 1, is formed in a third dielectric layer 119. A second plurality of vias 148 couples the first interconnect layer to a second interconnect layer 150, which can be metal 2. The second plurality of vias 148 is formed in a fourth dielectric layer 99, and the second interconnect layer 150 is formed in a fifth dielectric layer 123.

[0028] The second interconnect layer 150 provides contact pads for coupling to a redistribution layer, or other suitable chip handling technology, to form connections to other devices or printed circuit boards. There can be more dielectric layers and interconnect layers as can be dictated by the end use of the chip. The first and second interconnect layers are shown for illustrative purposes.

[0029] A sixth dielectric layer 125 is formed on the second interconnect layer 150 and includes openings 127 to expose a conductive surface. A first redistribution layer 152, which is conductive, is formed in the openings 127 and extends over a portion of the sixth dielectric layer. A seventh dielectric layer 174 is formed on the first redistribution layer 152 and includes openings 131 that expose a conductive surface of the first redistribution layer in a pattern that matches the pad array 136. Solder balls 138 are coupled to the pad array 136.

[0030] At an early stage in the process of building the active and passive components 111 of the first integrated circuit, a plurality of first contact pads 118 is formed. In particular, the first contact pads 118 are formed in the first dielectric layer 115. The plurality of first contact pads 118 can be formed at the same time as the gate 113, if the materials are suitable. Alternatively, the gate and the first contact pads can be formed at different times. In another alternative, the plurality of first contact pads 118 can be in the second dielectric layer. The plurality of first contact pads 118 is closer to the active first side 114 (the active surface of the substrate) than the pad array 136. The plurality of first contact pads 118 is closer to the active first side 114 (the active surface of the substrate) than the first redistribution layer 152.

[0031] Examples of materials used for the plurality of first contact pads 118 include: conductive materials, such as doped polysilicon; and metals, such as aluminum (Al) with a titanium-tungsten (TiW) contact reinforcement layer, and copper (Cu) with a titanium nitride (TiN) barrier layer. The plurality of first contact pads 118 may be electrically coupled to a plurality of conductive layers 149 on a first side 106 of the first integrated circuit 102. Examples of electrical coupling include current coupling and capacitive coupling.

[0032] The non-active second side 116 of the first integrated circuit has a unique surface because it has been contoured or otherwise shaped to accommodate the second integrated circuit. The substrate 112 includes angled sidewalls 133 that extend from the active first side 114 of the substrate to the non-active second side 116 of the substrate and slope inward toward the recess 126.

[0033] The widest dimension (first dimension 135) of the first integrated circuit 102 extends from sidewall 110 to the opposite sidewall 110. The substrate 112 has a widest dimension (second dimension 137), which is smaller than the first dimension 135. A recess 126 has a third dimension 145 at its recess surface 128. The third dimension is smaller than both the first and second dimensions. The outermost surface 147 of the substrate 112 has a fourth dimension 141, which is smaller than both the first and second dimensions. A fifth dimension 139 extends between a first corner 143 and a second corner 149 on the second side 108 of the substrate. This fifth dimension 139 is smaller than both the first and second dimensions.

[0034] Contact pad 118 is located in region 151, which is between sidewall 110 and the widest edge 153 of substrate 112. At least a portion of contact pad 118 is not covered by substrate 112. This at least portion of contact pad 118 is exposed when substrate 112 is etched and shaped to form recess 126 and other surfaces of the second side of the first integrated circuit 102.

[0035] A conductive trace or redistribution layer 120 is included on the second side 108, extending from the recess 126 to the contact pad 118. A dielectric layer 122 is formed on the substrate, which may be a polyimide layer or any other suitable dielectric. The dielectric layer 122 is located between the redistribution layer 120 and the substrate 112. Examples of materials that can be used for the redistribution layer 120 include conductive metals, such as copper (Cu) with a TiN barrier layer and aluminum (Al). Near the sidewall 110 of the first integrated circuit 102, a plurality of first contact pads 118 are exposed from the substrate 112. The redistribution layer 120 forms a plurality of second contact pads 121 on the second side 108 of the integrated circuit 102, at which the redistribution layer 120 is coupled to the first contact pads 118. The dielectric layer 122 includes openings at which the conductive trace 120 is coupled to the contact pads 118.

[0036] A recess 126 in the second side 108 of the first integrated circuit 102 includes a recess surface 128 and an adjacent recess wall 129. In this embodiment, the recess is centrally located. The recess 126 at least partially surrounds the second integrated circuit 104. A redistribution layer 120 extends from the second contact pad 121 to the recess surface 128 inside the recess 126. The second integrated circuit 104 includes a ball grid array 130 coupled to the redistribution layer 120. An underfill or dielectric material 132 between the first integrated circuit 102 and the second integrated circuit 104 increases mechanical strength and protects the coupling between the second conductive layer 120 and the second integrated circuit 104.

[0037] Molding compound 134 encapsulates the non-active second side 116 of the first integrated circuit 102 and the second integrated circuit 104 in resin. The pad array 136 of the first integrated circuit 102 is exposed, and solder balls 138 are coupled to the pad array 136.

[0038] Figure 2 This is a top view of a multi-chip package 100 without molding compound 134, showing a second side 108 of a first integrated circuit 102 and a second integrated circuit 104. The second integrated circuit 104 is centrally positioned within a recess 126 of the first integrated circuit. Solder balls of a ball grid array 130 are formed in the recess and coupled to corresponding layers in a plurality of redistribution layers 120. Each redistribution layer 120 has been patterned to couple a plurality of first contact pads 118 to corresponding terminals of the ball grid array 130 via second contact pads 121.

[0039] First contact pads 118 are formed in region 151 between the widest edge 153 of substrate 112 and sidewall 110. As substrate 112 is etched to form recesses 126, openings 157 are etched through the substrate to expose each first contact pad 118. The peripheral region surrounding the first contact pads 118 may contain a semiconductor substrate to provide support and protection for those portions of the integrated circuit. Openings 157 are illustrated as U-shaped extending all the way to sidewall 110, but other shapes are also contemplated. For example, openings 157 may not extend all the way to sidewall 110.

[0040] Below Figures 3-8 Description Figure 1 The processing and assembly of multi-chip packages 100. Figures 3-8 Is it through Figure 2 A cross-sectional view of the cutting line 1-1. Processing of a multi-chip package 100 is performed at the wafer scale. Figure 8 After molding is applied, the wafer with a plurality of first integrated circuits 102 (single die) attached to the second integrated circuit 104 is cut. Figures 3-8 The diagram illustrates the processing of a first integrated circuit 102 and a second integrated circuit 104.

[0041] Now for reference Figure 3 The first integrated circuit 102 is formed after the active and passive components 111, the dielectric layer 172, and the interconnect layer have been formed, but before the second side 108 of the substrate 112 is processed and the assembled package is assembled. The substrate 112 includes a die boundary 140, which is a line representing the boundary formed after the individual dies are separated from the wafer (diced). A plurality of first contact pads 118 contact the substrate 112 near the sidewall 110, which is coplanar with the die boundary 140.

[0042] Now for reference Figure 4 The second substrate side or non-active second side 116 of the substrate 112 is shaped to form a groove and expose the first contact pad 118. Some portions of the substrate are removed in one or more steps to create different substrate surfaces. For example, the substrate can be patterned by using an etch mask and then etching the die boundary 140 and the groove 126. One or more of many silicon etching methods known to those skilled in the art can be used, examples of which include wet etching, dry etching, and chemical mechanical removal. The etching of the die boundary 140 and the etching of the groove 126 can be performed concurrently, separately, or partially concurrently in a series of etching process steps.

[0043] Etching the die boundary 140 creates an opening 157 adjacent to the sidewall 110, exposing the first contact pads 118. In other areas not shown in this cross-section, portions of the substrate may be retained. The etching process forms an etched substrate boundary 156 with a slope 158. Etching of the die boundary 140 continues at least until the plurality of first contact pads 118 are exposed to the second side 108, and the slope 158 allows for the subsequent patterning and deposition of the dielectric layer 122 and the redistribution layer 120.

[0044] Preferably, the recess surface 128 is flat (substantially planar) to allow coupling of the first integrated circuit 102 to the second integrated circuit 104. The recess sidewall 129 has a slope 164 that is low enough to allow for the patterning and deposition of subsequent dielectric layers 122 and redistribution layers 120.

[0045] Now for reference Figure 5 A dielectric layer 122 is deposited on the boundary 156, on the outermost surface, or on the non-active second side 116 and in the groove 126. An opening 157 is then formed through the dielectric layer 122. This can be achieved by patterning and etching or by other suitable techniques. The opening exposes a plurality of first contact pads 118 to the second side 108. In some embodiments, a small portion of the dielectric layer 122 is retained along the sidewall 110.

[0046] Now for reference Figure 6 A redistribution layer 120 is deposited and patterned, forming second contact pads 121 on the second side 108 and extending beyond the boundaries of the plurality of first contact pads 118 to the sidewall 110. The plurality of first contact pads 118 and the redistribution layer 120 are electrically coupled. An opening 159 is retained in a recess 126 between some layers of the redistribution layer 120. An example of the redistribution layer 120 is Cu with a TiN barrier layer. The use of Cu interconnects over a polyimide dielectric is well known in the art, wherein Cu is grown using electrolysis over a TiN barrier with a thin seed Cu pattern. Other conductive materials, including aluminum (Al), can be used for the redistribution layer 120.

[0047] Now for reference Figure 7The second integrated circuit 104 includes an active surface 168 (such as a ball grid side) and a passive surface 161. The active surface is coupled to active and passive circuitry formed in the substrate of the second integrated circuit, similar to the active and passive circuitry already described with respect to the first integrated circuit. The first and second integrated circuits are designed to work together and share signals via at least a first contact pad 118. The second integrated circuit may be a sensor, while the first integrated circuit is a processor or other application-specific integrated circuit. A ball grid array 130 is coupled to contact pads (not shown) on the active surface 168 of the second integrated circuit. One or more redistribution layers (not shown) may also be present, providing coupling structures for the solder balls of the ball grid array 130. The solder balls are directly or indirectly coupled to redistribution or traces 120 formed on the substrate.

[0048] Underfill 132 is applied to at least a portion of the ball gate side 168, and the second integrated circuit 104 is oriented and positioned with the ball gate side 168 facing the recess surface 128. The second integrated circuit 104 is at least partially located within the recess 126. Heat is applied to mechanically and electrically couple the ball gate array 130 to the redistribution layer 120. The underfill 132, pre-applied to at least a portion of the ball gate side 168, is compressed and pressed between the first integrated circuit 102 and the second integrated circuit 104.

[0049] Now for reference Figure 8 Resin is injected onto the second side 108 of the first integrated circuit 102 to encapsulate the second side 108 and the second integrated circuit 104 within a molding compound 134. The pad array 136 is exposed externally. Referring now... Figure 1 The solder balls are coupled to the pad array 136. At this point, the wafer is diced.

[0050] Now for reference Figure 9 Another embodiment of the multi-chip package 200 includes a first die 202 and a second die 204. The first die 202 is larger than the second die 204. The first die 202 includes a first surface 206, which is an active surface on which active and passive components can be formed. Active components may include transistors 245, and passive components may be resistors 218 or capacitors. These components are formed in a substrate that is part of the wafer. Additional layers, such as a plurality of interconnect layers 214, are formed on the wafer.

[0051] The first die 202 has a second side 208 or a second surface, which is the remaining surface after the substrate has been formed. The first side 206 may be referred to as the "upper side" or the "active device side" because at least most of the active devices 245 are on the first side 206. The second die has a first active side 210 and a second passive side 212.

[0052] The multi-chip package 200 also includes a plurality of interconnect layers 214 coupled to a first surface 206 of a first die 202. The plurality of interconnect layers 214 include a first dielectric layer 201 formed on the first surface of the die. The gate of a transistor may be formed at the same level as the first dielectric layer 201. A second dielectric layer 219 is formed on the first dielectric layer 201. A plurality of vias 205 are formed in the second dielectric layer and couple active and passive components to other layers of the first die.

[0053] A first conductive layer 216 is formed on a second dielectric layer 219. A third dielectric layer 207 surrounds the first conductive layer 216. Examples of the first conductive layer 216 include a contact layer, a polysilicon layer, a metal layer, and a redistribution layer. A plurality of vias 203 are formed in a fourth dielectric layer 209. A second conductive layer 211 is formed on the fourth dielectric layer 209. A fifth dielectric layer 213 is at the same level as the second conductive layer 211. A redistribution layer 215, including dielectric and conductive layers, is formed on the second conductive layer 211. Solder balls 227 are coupled to the redistribution layer 215.

[0054] A portion of the substrate of the first die 202 has been removed near multiple edges 217, creating a region 199 around the first die 202 that exposes the first interconnect layer 216. Removal of portions 247 of the multiple interconnect layers 214 is performed until the first conductive layer 216 is exposed. In this embodiment, the first dielectric layer 201 and the second dielectric layer 219 are removed to form an opening at the edge 217. Examples of techniques for selectively removing portions of the die 202 and portions of the multiple interconnect layers 214, to name just a few, include wet chemical etching, dry etching, chemical mechanical removal, and mechanical removal.

[0055] During the removal of the first and second dielectric layers, the first contact surface 221 is exposed. The first contact surface 221 can be exposed during the same processing steps as removing excess portions of the substrate, while sloped sidewalls 223 and surfaces 225 are formed on the passive side of the first die 202. The first contact surface 221 is part of the first conductive layer 216, such that some portions of the first conductive layer are aligned with the substrate, and some portions of the first conductive layer are not covered by the substrate. In other embodiments, the first conductive layer may be entirely in the space not covered by the substrate.

[0056] The substrate begins with a first dimension 237 in a first direction, corresponding to the distance between edges 217. After removing some portions of the substrate, the largest dimension in the first direction is a second dimension 233. A third dimension 231 extends between the remaining edges of the plurality of interconnect layers 214. The first dimension is larger than the second dimension 233. The first dimension is larger than the third dimension 231. The third dimension is larger than the second dimension 233.

[0057] Surface 225 has a fourth dimension 235 in a first direction. The fourth dimension is smaller than the second dimension 233. In this embodiment, no groove is formed. Thus, the mask pattern and steps will be related to... Figure 1 The described embodiments differ.

[0058] The multi-chip package 200 also includes a plurality of conductive traces 220 formed on inclined surfaces 223 and 225. An insulator 222 is located between the first die 202 and the plurality of conductive traces 220. Through openings in the insulator above the first conductive surface 221, the plurality of conductive traces 220 are electrically coupled to the first conductive layer 216 near a plurality of edges 217 exposing the first conductive layer 216.

[0059] As mentioned above Figure 1 Similar to the second integrated circuit or die discussed, the second die 204 includes active and passive components and includes contact pads on the active surface to which solder balls 224 are coupled.

[0060] The second die 204 is oriented with its first side 210 facing the second side 208 of the first die 202. Specifically, the first active side 210 faces surface 225. The second die is electrically and mechanically coupled to a plurality of conductive traces 220 on the second side 208 using solder balls 224. An opening 241 exists between adjacent conductive traces 220. An underfill 226 is placed between the first die 202 and the second die 204 and within the opening 241. The underfill may extend on the side surface of the die 204. In other embodiments, the underfill may be omitted.

[0061] Molding compound 243 can be formed around the first and second dies to form the final package.

[0062] In another embodiment, a multi-chip device is similar to Figure 1 The device comprises a first integrated circuit (IC) which is the master IC, and a second integrated circuit which is a secondary IC with a smaller area than the master IC. The multi-chip device includes one or more secondary integrated circuits mounted in one or more recesses on the second side or "back side" of the parent IC.

[0063] In another embodiment, the multi-chip device is similar to one in which the molding compound 134 is omitted. Figure 1 The device. Examples of the utility of this embodiment include the ability to mount multi-chip packages onto a printed circuit board and to encapsulate multi-chip modules in resin bonded to the printed circuit board.

[0064] In another embodiment, the multi-chip package is similar to one where the underfill 132 is omitted.Figure 1 Multi-chip packaging.

[0065] Alternative embodiments, and Figure 1 or Figure 9 A similar multi-chip package includes a second substrate that is located on a second side away from the first substrate and is electrically coupled to a second conductive layer using bonding wires.

[0066] exist Figures 1-8 In one embodiment, the substrate 112 has a first thickness from the first surface 114 or the active first side to the second surface 116 or the non-active second side. A second thickness exists from the active first surface 114 to the recessed surface 128. The second thickness is less than the first thickness.

[0067] The various embodiments described above may be combined to provide other embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in and / or listed in the application data sheets are incorporated herein by reference in their entirety. If it is necessary to employ the concepts of various patents, applications, and publications to provide other embodiments, aspects of the embodiments may be modified.

[0068] These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents to such claims. Therefore, the claims are not limited by the disclosure. In the various drawings, the same reference numerals are used for similar or identical features.

Claims

1. An apparatus comprising: The first integrated circuit includes: The first substrate has an active surface and a passive surface; A first conductive layer is formed on the active surface of the first substrate; A second conductive layer is formed on the passive surface of the first substrate; A groove, in the passive surface of the first substrate; and At the edge portion of the first substrate, the first conductive layer is coupled to the second conductive layer at the edge portion; and A second integrated circuit is coupled in the groove to the second conductive layer of the first integrated circuit on the passive surface of the first substrate.

2. The device according to claim 1, wherein the first integrated circuit comprises: A first dimension in a first direction, the first dimension extending from a first sidewall of the first integrated circuit to a second sidewall of the first integrated circuit; as well as A second dimension in the first direction, the second dimension extending from a first edge of the first substrate to a second edge of the first substrate, the second dimension being smaller than the first dimension, the edge portion being between the first sidewall and the first edge of the first substrate.

3. The device according to claim 1, further comprising: Bottom filler is located between the first integrated circuit and the second integrated circuit.

4. The device of claim 1, wherein the edge portion includes an opening aligned with a portion of the first conductive layer.

5. The device of claim 1, wherein the first integrated circuit includes a plurality of interconnect layers on the active surface of the first substrate, the plurality of interconnect layers including a plurality of conductive and dielectric layers.

6. The device of claim 5, wherein the first integrated circuit further includes a plurality of contact pads coupled to the plurality of interconnect layers.

7. The device according to claim 6, further comprising: The plurality of contact pads are exposed from the molding compound surrounding the first integrated circuit and the second integrated circuit.

8. An apparatus comprising: A first substrate has a first surface and a second surface; A recessed surface, located between the second surface and the first surface; The first contact pad is on the first surface of the first substrate; The second contact pad is located between the first surface and the second surface of the first substrate; An opening in the first substrate, the opening exposing a portion of the second contact pad; A first conductive layer is formed on the second surface of the first substrate and is coupled to the second contact pad through the opening; as well as The second substrate is coupled to the first conductive layer at the recessed surface.

9. The device according to claim 8, further comprising: The dielectric between the first conductive layer and the first substrate.

10. The device according to claim 8, further comprising: A second substrate is disposed on the second surface of the first substrate; as well as The third contact pad is located on the first conductive layer of the first substrate, through which the second substrate is coupled to the first conductive layer.

11. The device of claim 10, wherein the first substrate includes a sidewall, and the second contact pad is closer to the sidewall than the third contact pad.

12. The device of claim 10, wherein the second substrate includes a fourth contact pad coupled to the third contact pad of the first conductive layer.

13. An apparatus comprising: A first substrate having a first surface opposite to a second surface, the first substrate including a recessed surface opposite to the second surface, the first substrate comprising: A first region having a first thickness, the first region being located between the first surface and the second surface; and A second region having a second thickness, the second region being between the recessed surface and the second surface, wherein the first thickness is greater than the second thickness; A plurality of first contact pads are located on the second surface of the first substrate; and A plurality of second contact pads are located between the first surface and the second surface of the first substrate, and some of the plurality of first contact pads are coupled to some of the plurality of second contact pads. Multiple third contact pads on the recessed surface of the first substrate; The second substrate is coupled to the first substrate at the recessed surface via the plurality of third contact pads.

14. The device of claim 13, wherein the plurality of first contact pads are in the first region, and the second substrate includes a plurality of fourth contact pads coupled to the plurality of second contact pads.

15. The device of claim 14, further comprising a plurality of conductive traces on the first region and the second region, and coupled between the plurality of fourth contact pads and the plurality of second contact pads.

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