Display device

Abstract

A display device is provided. The display device includes a display unit having a display area and a non-display area, a first driver located in the non-display area, a second driver located in the non-display area and spaced apart from the first driver, a bending portion connected to the display unit, and a connection member connected to the bending portion, wherein a first wire portion connected to the first driver and a second wire portion connected to the second driver are arranged in the non-display area, and the first wire portion and the second wire portion are connected to each other via a connection wire portion.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0091155, filed with the Korean Intellectual Property Office on July 26, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display device whose configuration and size are optimized while providing efficient and accurate transmission of signals that enable the display of images. Background Technology

[0004] A display device typically includes a display element and driving circuitry for controlling electrical signals applied to the display element. The driving circuitry may include thin-film transistors, storage capacitors, and suitable wiring.

[0005] To precisely control the emission of display elements and the degree of emission, the number of thin-film transistors to be electrically connected to a single display element may increase. In this regard, the integration of these connections and the resulting power consumption of the display device have become a focus of ongoing development for display devices with the aforementioned emission control. Summary of the Invention

[0006] One or more embodiments may include a display device that can minimize the width of the terminal portion and improve responsiveness.

[0007] Additional aspects will be set forth in part in the detailed description below, and in part will be apparent from this description, or may be learned herein by practice of the embodiments.

[0008] According to an embodiment, the display device may include a display having a display area and a non-display area, a first driver located in the non-display area, a second driver located in the non-display area and spaced apart from the first driver, a bent portion connected to the display, a connector connected to the bent portion, a first wire portion connected to the first driver, a second wire portion connected to the second driver, and a connecting wire portion connecting the first wire portion and the second wire portion to each other, wherein the first wire portion and the second wire portion are arranged in the non-display area.

[0009] The connecting wire section can be arranged in the connector.

[0010] The display device may include terminals connected to the connecting wires.

[0011] The display device may include data driving circuitry arranged in the connector.

[0012] The display area can have a circular shape.

[0013] The first and second conductor portions can be arranged on the same layer, and the connecting conductor portion can be arranged on a different layer than the same layer on which the first and second conductor portions are arranged.

[0014] At least one of the first and second conductor sections and the connecting conductor section may be arranged in different directions relative to each other.

[0015] At least one of the first guide section and the second guide section may extend perpendicularly to the bending axis of the bend, and the connecting guide section may extend parallel to the bending axis of the bend.

[0016] Multiple first guide sections and multiple second guide sections can be configured. The multiple first guide sections and multiple second guide sections can be arranged symmetrically relative to each other based on any center line of the display device.

[0017] Signals of the same polarity can be transmitted to the first and second conductor sections, which can be symmetrical about each other based on any center line of the display device.

[0018] According to an embodiment, the display device may include a substrate having a first region, a second region, and a bend located between the first region and the second region; an inorganic insulating layer disposed on the substrate and having an opening corresponding to the bend; a conductive portion extending from the first region through the bend into the second region and disposed on the inorganic insulating layer to overlap at least a portion of the opening; and an organic material layer located between the inorganic insulating layer and the conductive portion and filling the opening. A portion of the conductive portion may be connected to a first driver in the first region, another portion of the conductive portion may be connected to a second driver in the first region, and the conductive portions in one portion and the other portion of the conductive portion may be connected via a connecting conductive portion.

[0019] The connecting wire section can be located in the second area.

[0020] The display device may include terminals connected to the connecting wires.

[0021] The connecting wire portion may be arranged on the inorganic insulation layer differently from the wire portion.

[0022] Another part of the conductor section and yet another part of the conductor section can be based on the arbitrary center line of the display device extending between the conductor sections being symmetrical with respect to each other, so that the conductor sections are equally divided on opposite sides of the arbitrary center line of the display device.

[0023] The conductors that can transmit signals with the same polarity can be symmetrical about each other based on any center line of the display device.

[0024] The connection wire portions can be provided in a plurality, and the plurality of connection wire portions can be spaced apart from each other in a plane to respectively connect a portion of the wire portion connected to a first driver in the first area and another portion of the wire portion connected to a second driver in the first area.

[0025] The first area can have a circular shape.

[0026] The display device can include a data driving circuit disposed in the second area.

[0027] Each of the wire portions and the connection wire portions can be arranged in different directions with respect to each other.

[0028] Each of the wire portions can extend perpendicularly with respect to a bending axis of the bending portion, and the connection wire portions can extend in parallel with the bending axis of the bending portion.

[0029] According to an embodiment, a display device can include a substrate having a first area, a second area, and a bending portion between the first area and the second area, an inorganic insulation layer disposed on the substrate and having an opening corresponding to the bending portion, a wire portion extending from the first area to the second area via the bending portion and disposed on the inorganic insulation layer to overlap at least a portion of the opening, and an organic material layer between the inorganic insulation layer and the wire portion and filling the opening, wherein a portion of the wire portion can be connected to a first driver in the first area, another portion of the wire portion can be connected to a second driver in the first area, and the portion and the another portion of the wire portion can be connected to each other.

[0030] The portion and the another portion of the wire portion can be connected to each other via a plurality of connection wire portions, respectively, and extend perpendicularly with respect to a bending axis of the bending portion, and the connection wire portions can extend in parallel with the bending axis of the bending portion. BRIEF DESCRIPTION OF DRAWINGS

[0031] The above and other aspects, features, and advantages of embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 A display device according to an embodiment is illustrated in a perspective view;

[0033] Figure 2 A display device according to an embodiment is illustrated in a perspective view; Figure 1 A display device according to an embodiment is illustrated in a perspective view;

[0034] Figure 3A A display device according to an embodiment is illustrated in a perspective view; Figure 1 A display device according to an embodiment is illustrated in a perspective view;

[0035] Figure 3B A display device according to an embodiment is illustrated in a perspective view; Figure 1A plan view showing the layout configuration of the display device;

[0036] Figure 4 A schematic diagram showing the equivalent circuit of a pixel according to an implementation method;

[0037] Figure 5 Exhibition along Figure 2 A schematic cross-sectional view of the display device taken by line A-A';

[0038] Figure 6 exhibit Figure 2 An enlarged plan view of the wiring;

[0039] Figure 7 A plan view showing the layout configuration of a display device according to another embodiment is presented;

[0040] Figure 8 A schematic cross-sectional view of the bent portion of a display device according to another embodiment is shown;

[0041] Figure 9 A plan view of a display device according to another embodiment is shown;

[0042] Figure 10 A perspective view of a display device according to another embodiment is shown; and

[0043] Figure 11 A perspective view of a display device according to another embodiment is shown. Detailed Implementation

[0044] Referring now to the embodiments shown in the accompanying drawings, where similar reference numerals consistently indicate similar elements. In this respect, embodiments may take different forms and should not be construed as limited to the description set forth herein. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all or variations thereof of a, b, and c.

[0045] It will be understood that while terms such as "first," "second," etc., may be used in this document to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another.

[0046] Unless otherwise explicitly indicated by the context, the singular forms “a,” “one,” and “the” used in this document are intended to include the plural forms as well.

[0047] It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, or components, but do not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. It will be understood that when a layer, region or component is referred to as being "on" another layer, region or component, it can be directly on the other layer, region or component, or intervening layers, regions or components can also be present. For example, an intervening layer, region or component can be present.

[0048] For the sake of convenience, the dimensions of the elements in the drawings can be exaggerated relative to other elements. Conversely, the thicknesses of the components and the sizes of the elements can be arbitrarily shown for the sake of explanation.

[0049] The x-axis, y-axis and z-axis are not limited to three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that can not be perpendicular to each other.

[0050] "About" or "approximately" as used herein can include within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account measurements and error associated with the particular quantity being measured (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or, for example, within 30%, 20%, or 5% of the stated value.

[0051] In the following embodiments, it will be understood that when an element, region or layer is referred to as being "connected to" another element, region or layer, it can be directly or indirectly connected to the other element, region or layer. It will also be understood that when an element, region or layer is referred to as being "on" another element, region or layer, it can be directly or indirectly on the other element, region or layer. For example, in this specification, it will be understood that when an element, region or layer is referred to as being in contact with or electrically connected to another element, region or layer, it can be directly or indirectly in contact with or electrically connected to the other element, region or layer.

[0052] Further, the phrase "in plan view" means when viewing the object portion from above, the phrase "in cross-sectional view" means when viewing a cross-section taken by cutting the element portion vertically. Additionally, the term "overlapped" or "overlapping" means that a first object can be above or below a second object, or at a side of the second object, and vice versa. Additionally, the term "overlapped" can include stacked, piled, faced or faced with, extended above, covered or partially covered, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art. The terms "faced" and "faced with" mean that a first element can be directly or indirectly opposite a second element. A first element and a second element can be understood to be indirectly opposite each other, although still facing each other, in the case that a third element is interposed between the first element and the second element. When elements are described as "non-overlapping" or "not overlapping" with another element, this can include the elements being spaced apart from each other, offset from each other, or separated from each other, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art. When a layer, region, substrate, or area is referred to as being "on" another layer, region, substrate, or area, it can be directly on the other layer, region, substrate, or area, or intervening layers, regions, substrates, or areas can be present therebetween. Conversely, when a layer, region, substrate, or area is referred to as being "directly on" another layer, region, substrate, or area, there can be no intervening layers, regions, substrates, or areas therebetween. Further, when a layer, region, substrate, or area is referred to as being "under" another layer, region, substrate, or area, it can be directly under the other layer, region, substrate, or area, or intervening layers, regions, substrates, or areas can be present therebetween. Conversely, when a layer, region, substrate, or area is referred to as being "directly under" another layer, region, substrate, or area, there can be no intervening layers, regions, substrates, or areas therebetween. Further, "above" or "up" can include being above or below an object, and does not necessarily imply a direction based on gravity.

[0053] For the sake of description, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for describing the relationship between one element or component and another element or component as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, in the event that the device shown in the figures is turned over, elements described as "below" or "beneath" other elements or components would then be oriented "above" the other elements or components. The illustrative term "below" can include both a lower position and an upper position. The device can also be oriented in other directions; and as such, the spatially relative terms can be interpreted differently depending upon the particular orientation of the device.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0055] In situations in which the present implementation can be implemented in different manners, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed at substantially the same time or in the reverse order of the described sequence.

[0056] Figure 1 The display device 10 according to an embodiment is illustrated. Figure 2 The display device 10 according to an embodiment is illustrated. Figure 1 The display device 10 according to an embodiment is illustrated. Figure 3A The display device 10 according to an embodiment is illustrated. Figure 1 The display device 10 according to an embodiment is illustrated. Figure 3B The display device 10 according to an embodiment is illustrated. Figure 1 The display device 10 according to an embodiment is illustrated.

[0057] Referring to Figures 1-3B The display device 10 can include a substrate 100. The substrate 100 can have a display area DA and a peripheral area PA including a non-display area located outside the display area DA. The substrate 100 can include a first area 1A, a second area 2A, and a bending area or a bending portion BA. The first area 1A can include a display, and the second area 2A can define a connector to be connected to an external device. The display can implement an image via the display area DA in a case in which the display area DA can be exposed to the outside so that a user can perceive. The above-described display area DA can be included in the first area 1A. The peripheral area PA can include a portion of the first area 1A located outside the display area DA and portions of the second area 2A and the bending area BA.

[0058] The first area 1A can have a non-rectangular shape. The non-rectangular shape can be a circular shape, an elliptical shape, a polygonal shape of which a portion can be a circular shape, or a polygonal shape other than a quadrilateral.

[0059] The substrate 100 can include the bending area BA extending in the first direction DI1. The bending area BA can be located between the first area 1A and the second area 2A in the first direction DI1. For example, as Figure 1 and Figure 2As illustrated in FIG. 1, the substrate 100 can be bent based on a bending axis BAX that can extend in a second direction DI2 intersecting the first direction DI1. The substrate 100 can be bent according to a radius of curvature about the bending axis BAX. However, embodiments can not be limited thereto. For example, the substrate 100 can be bent in a manner that can be inconsistent with respect to the radius of curvature of the bending axis BAX.

[0060] The substrate 100 can include various flexible or bendable materials. For example, the substrate 100 can include a polymeric resin such as polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, or a combination thereof, but is not limited thereto. The substrate 100 can have a single layer or multiple layers including the above-described materials. In a case where the substrate 100 can have multiple layers, the substrate 100 can include an inorganic layer.

[0061] The first area 1A can include a display area DA. For example, as illustrated in FIG. 1, the first area 1A can include the display area DA and a portion of a peripheral area PA outside the display area DA. The second area 2A can include another portion of the peripheral area PA. Figure 2 As illustrated in FIG. 1, the first area 1A can include the display area DA and a portion of a peripheral area PA outside the display area DA. The second area 2A can include another portion of the peripheral area PA.

[0062] The pixels PX can be arranged in the display area DA of the substrate 100, and thus can display an image. Devices such as a thin film transistor TFT, an organic light emitting device OLED, and a first capacitor Cst can be located in the display area DA.

[0063] The display area DA can have a shape corresponding to a shape of a portion of the substrate 100. In a case where the display area DA has a circular shape, the substrate 100 can have a corresponding circular shape. Figure 2 In a case where a portion of the substrate 100 has a circular shape, the display area DA can have a corresponding circular shape.

[0064] The pixels PX and signal lines for applying an electrical signal to the pixels PX can be located in the display area DA. The pixels PX can include a first pixel PX1 that can emit light having a first color, a second pixel PX2 that can emit light having a second color, and a third pixel PX3 that can emit light having a third color. A pixel unit PU can include the first pixel PX1, the second pixel PX2, and the third pixel PX3. As illustrated in FIG. 1, for example, the pixel unit PU can be repeatedly arranged in the first direction DI1 and the second direction DI2. The pixel unit PU can be appropriately arranged according to a shape of the display area DA. Figure 2

[0065] The signal lines for applying an electrical signal to the pixels PX can include a data line DL, a scan line SL, and an emission control line EL. Each of a plurality of data lines DL can extend in the first direction DI1. Each of a plurality of scan lines SL and a plurality of emission control lines EL can extend in the second direction DI2.​

[0066] Each of the plurality of pixels PX can be connected to a corresponding scan line among the plurality of scan lines SL, a corresponding emission control line among the plurality of emission control lines EL, and a corresponding data line DL among the plurality of data lines DL.

[0067] Signal lines, such as a drive voltage line PL for transmitting power and a common power line, can also be included in the display area DA. The drive voltage line PL can be connected to the drive power line 30 in the peripheral area PA. Further, although not shown, a common power line, a gate driver, and a data driver can be arranged in the peripheral area PA.

[0068] A driver for supplying a signal for driving the pixels PX can be arranged in the peripheral area PA in which the pixels PX can not be arranged. For example, a first driver 11A and a second driver 11B, which can be spaced apart from each other, can be located in the peripheral area PA. The first driver 11A and the second driver 11B can transmit the same signal or different signals to each of the plurality of pixels PX. For example, one of the first driver 11A and the second driver 11B can include one of the first scan driving circuit 120, the second scan driving circuit 130, and the emission control circuit 140. The other of the first driver 11A and the second driver 11B can include the other of the first scan driving circuit 120, the second scan driving circuit 130, and the emission control circuit 140. In another embodiment, one of the first driver 11A and the second driver 11B can include two of the first scan driving circuit 120, the second scan driving circuit 130, and the emission control circuit 140, and the other of the first driver 11A and the second driver 11B can include the other of the first scan driving circuit 120, the second scan driving circuit 130, and the emission control circuit 140. In another embodiment, each of the first driver 11A and the second driver 11B can include the scan driving circuit and the emission control circuit 140. In the case where one driver can include at least two circuits (such as at least two of the scan driving circuit, the emission control circuit, and the test circuit), the at least two circuits can be arranged in a line so as to be adjacent to each other along the boundary of the display area DA. For example, one of the at least two circuits and the other thereof can be spaced apart from each other along the boundary of the display area DA. Accordingly, each of the above-described three circuits can be arranged outside the display area DA. Accordingly, the scan driving circuit, the emission control circuit, and the test circuit can be provided. The scan driving circuit, the emission control circuit, and the test circuit can be spaced apart from each other. The scan driving circuit, the emission control circuit, and the test circuit can be alternately arranged with respect to each other. Although not shown in FIG. 1B, at least one scan driving circuit, at least one emission control circuit, and at least one test circuit can be arranged in the peripheral area PA in which the pixels PX can not be arranged. Figure 3B Figure 3B ​The region in which the first scan driving circuit 120 can be arranged, the region in which the second scan driving circuit 130 can be arranged, and / or the region in which the emission control circuit 140 can be arranged. In another embodiment, a portion of the plurality of circuits can be arranged along a portion of the boundary of the display area DA, and another portion of those circuits can be arranged along another portion of the boundary of the display area DA. With this configuration, the portion of the circuits and the other portion of the circuits can be arranged in a line outside the boundary of the display area DA so as to be adjacent to each other. The layout discussed above can not be limited thereto, such that the plurality of circuits can be arranged by combining the above-described layout methods.

[0069] The first driver 11A can include the first scan driving circuit 120 and the emission control circuit 140, and the second driver 11B can include the second scan driving circuit 130, as discussed below hereinafter. As shown in FIG. 1A, the first driver 11A and the second driver 11B can face each other. The first driver 11A and the second driver 11B described above are not limited to the above description, but can include the gate driver and the data driver described above. Figure 2

[0070] The first scan driving circuit 120 and the second scan driving circuit 130 can output each scan signal to each scan line SL. The emission control circuit 140 can output an emission control signal (see EM) to an emission control line EL. The data driving circuit 150 can output a data signal (see DATA) to a data line DL. Figure 4 Figure 4

[0071] The first scan driving circuit 120, the second scan driving circuit 130, and the emission control circuit 140 can be located in the peripheral area PA of the first area 1A along the end of the display area DA (i.e., along the circumference of the display area DA).

[0072] The data driving circuit 150 can be arranged in various ways. For example, the data driving circuit 150 can be arranged directly on the upper portion of the substrate 100 by using a chip on glass (COG) or a chip on plastic (COP) method, while the upper portion of the substrate 100 can extend from and can protrude from the remaining portion of the substrate 100. In another embodiment, the data driving circuit 150 can be located on a further flexible printed circuit board (FPCB). The FPCB can be connected to the terminal portion 20. As discussed below herein, the data driving circuit 150 can be arranged on the FPCB.

[0073] ​​​The terminal portion 20 can be located at one end of the peripheral area PA, and can include a plurality of terminals 21 and 22. The terminal portion 20 can not be covered by the insulating layer, and can be exposed to be electrically connected to an FPCB or a controller (not shown) such as a driver integrated circuit (IC). The controller can provide a data signal, a gate signal, a driving voltage ELVDD, and a common voltage ELVSS.

[0074] The driving power line 30 can be connected to the controller via the terminal 22, and can provide the driving voltage ELVDD supplied from the controller to the pixels PX via a driving voltage line PL. The driving power line 30 can be arranged along one side or area of the display area DA in the peripheral area PA.

[0075] The wire 40 can include a first wire portion 40A, a second wire portion 40B, a third wire portion 40C, and a connection wire portion 40D. The first wire portion 40A, the second wire portion 40B, and the third wire portion 40C can overlap or face the bending area BA. The first wire portion 40A, the second wire portion 40B, and the third wire portion 40C can extend from the first area 1A into the second area 2A via the bending area BA. The first wire portion 40A, the second wire portion 40B, and the third wire portion 40C can intersect the bending axis BAX and extend to the terminal portion 20. For example, the first wire portion 40A, the second wire portion 40B, and the third wire portion 40C can extend vertically with respect to the bending axis BAX. However, embodiments can not be limited thereto. For example, various variations can be provided, including, for example, a case where the first wire portion 40A, the second wire portion 40B, and the third wire portion 40C can extend obliquely at a predetermined angle with respect to the bending axis BAX. The first wire portion 40A, the second wire portion 40B, and the third wire portion 40C can have various shapes, such as a curved shape and a zigzag shape.

[0076] At least one of the above-described first wire portion 40A, the second wire portion 40B, and the third wire portion 40C can be provided as a plurality. For example, the first wire portion 40A can be provided as at least one. The second wire portion 40B can be provided as at least one. The third wire portion 40C can be provided as a plurality. Each of the first wire portions 40A can be connected to the first driver 11A, and each of the second wire portions 40B can be connected to the second driver 11B. A portion of the plurality of first wire portions 40A can be connected to the first scan driving circuit 120, and another portion of the plurality of first wire portions 40A can be connected to the emission control circuit 140. A portion of the plurality of third wire portions 40C can be connected to the driving power line 30, and another portion of the plurality of third wire portions 40C can be connected to the data line DL. The third wire portion 40C connectable to the data line DL can intersect the driving power line 30 so as to supply a data or gate signal to the display area DA. The third wire portion 40C connectable to the data line DL can be connected to a wire of another layer via a contact hole.

[0077] The first wire portions 40A, the second wire portions 40B, and the third wire portions 40C described above can be arranged at respective positions. However, the following discusses, for example, a case in which the first wire portions 40A, the second wire portions 40B, and the third wire portions 40C can be arranged as shown in FIG. 10. Figure 2

[0078] The connection wire portion 40D can connect, for example, two of the wirings 40. The connection wire portion 40D can connect, for example, two wire portions of the wirings 40 for applying the same signal to each other. For example, the connection wire portion 40D can connect one of the plurality of first wire portions 40A to one of the plurality of second wire portions 40B. In other words, the connection wire portion 40D can provide a connector between the first wire portion 40A and the second wire portion 40B. One of the terminals 21 or 22 can be connected to the connection wire portion 40D.

[0079] The connection wire portion 40D can be connected to one of the plurality of first wire portions 40A and one of the plurality of second wire portions 40B. The connection wire portion 40D can connect two different wire portions of the plurality of third wire portions 40C.

[0080] The connection wire portion 40D can be arranged in a second direction DI2 different from the first direction DI1. For example, the connection wire portion 40D can be formed to have a longitudinal dimension in a direction parallel to the bending axis BAX, and be perpendicular to one of the first wire portion 40A, the second wire portion 40B, and the third wire portion 40C.

[0081] A plurality of connection wire portions 40D can be provided. The plurality of connection wire portions 40D can be spaced apart from each other along the longitudinal direction of each of the first wire portion 40A, the second wire portion 40B, and the third wire portion 40C. Each of the plurality of connection wire portions 40D can be offset from each other without overlapping each other in the plane. The connection wire portion 40D can be disposed on a layer different from the layer on which the first wire portion 40A, the second wire portion 40B, and the third wire portion 40C can be disposed.

[0082] One of the connection wire portions 40D described above can be connected to one of the terminals 21 or 22. Signals input to one of the terminals 21 or 22 can be transmitted to the first wire portion 40A and the second wire portion 40B via the connection wire portion 40D, and thus to the first driver 11A and the second driver 11B via the first wire portion 40A and the second wire portion 40B, respectively. For example, these signals can be signals commonly used by the first driver 11A and the second driver 11B. For example, these signals can include at least one of various signals such as a start signal, an initialization voltage, a gate control signal, a clock signal, and a voltage.

[0083] ​In a case where the same signal transmitted to the first driver 11A and the second driver 11B can be input to one of the terminals 21 or 22 via the connection wire portion 40D, the display device 10 can reduce the size of the terminal portion 20 and the size of the peripheral area PA. For example, since the connection wire portion 40D is capable of transmitting the same signal to other different wire portions (e.g., the first wire portion 40A and the second wire portion 40B), the size of the peripheral area PA in the bending area BA and the second area 2A can be reduced.

[0084] In view of the above, the display device 10 can minimize the delay that can be generated in a case where the same signal can be transmitted to the first driver 11A and the second driver 11B.

[0085] The display device 10 can prevent each of the plurality of wire portions from being connected to each other in other cases due to the narrow space of the plurality of wire portions and their layout, which is caused by the bending area BA being narrower than other parts of the display device 10.

[0086] Figure 4 A schematic diagram of an equivalent circuit of a pixel PX according to an embodiment is shown.

[0087] Referring to Figure 4 Each pixel PX can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a first capacitor Cst, a second capacitor Cbt, an organic light emitting device OLED as a display element, and a plurality of signal lines SL1, SL2, SL3, SL4, EL, and DL, an initialization voltage line VIL, and a driving voltage line PL connected thereto. In another embodiment (not shown), at least one of the plurality of signal lines SL1, SL2, SL3, SL4, EL, and DL, the initialization voltage line VIL, and / or the driving voltage line PL can be shared by adjacent pixels. The first transistor T1 to the seventh transistor T7 can include thin film transistors. In Figure 4 In the above, the third transistor T3 and the fourth transistor T4 can include n-channel metal oxide semiconductor field effect transistors (i.e., NMOSFETs), and the other transistors can include p-channel MOSFETs (i.e., PMOSFETs).

[0088] The plurality of signal lines SL1, SL2, SL3, SL4, EL, and DL can include a data line DL, a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, and an emission control line EL. The second scan line SL2 can be connected to the first scan line SL1, and a first scan signal GP1 can be a second scan signal GP2.

[0089] The driving voltage line PL can transmit a driving voltage ELVDD to the first transistor T1, and the initialization voltage line VIL can transmit an initialization voltage Vint for initializing the first transistor T1 and the organic light emitting device OLED to the pixel PX.

[0090] The first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the emission control line EL, and the initialization voltage line VIL can extend in the second direction DI2 and can be spaced apart from each other according to rows. The data line DL and the driving voltage line PL can extend in the first direction DI1 and can be separated from each other according to columns.

[0091] The first transistor T1 can be connected to the driving voltage line PL via the fifth transistor T5, and can be electrically connected to the organic light emitting device OLED via the sixth transistor T6. The first transistor T1 can function as a driving transistor, can receive a data signal DATA according to a switching operation of the second transistor T2, and can transmit a driving current I OLED to the organic light emitting device OLED.

[0092] The second transistor T2 can be connected to the first scan line SL1 and the data line DL, and can be connected to the driving voltage line PL via the fifth transistor T5. The second transistor T2 can be turned on according to a first scan signal GP1 transmitted via the first scan line SL1, and can perform a switching operation of transmitting a data signal DATA to a node N, while the data signal DATA can be transmitted to the data line DL.

[0093] The third transistor T3 can be connected to the fourth scan line SL4, and can be connected to the organic light emitting device OLED via the sixth transistor T6. The third transistor T3 can be turned on according to a fourth scan signal GN2 transmitted via the fourth scan line SL4, and can diode-connect the first transistor T1.

[0094] The fourth transistor T4 can be connected to the third scan line SL3 and the initialization voltage line VIL, can be turned on according to a third scan signal GN1 transmitted via the third scan line SL3, and can transmit an initialization voltage Vint from the initialization voltage line VIL to a gate electrode of the first transistor T1, thereby initializing a voltage of the gate electrode of the first transistor T1.

[0095] The fifth transistor T5 and the sixth transistor T6 can be connected to the emission control line EL, can be simultaneously turned on according to an emission control signal EM transmitted via the emission control line EL, and can form a current path in which a driving current I OLED flows in a direction from the driving voltage line PL to the organic light emitting device OLED.

[0096] The seventh transistor T7 can be connected to the second scan line SL2 and the initialization voltage line VIL, can be turned on according to the second scan signal GP2 transmitted via the second scan line SL2, and can transmit the initialization voltage Vint from the initialization voltage line VIL to the organic light emitting device OLED, thereby initializing the organic light emitting device OLED. In other embodiments, the seventh transistor T7 can be omitted.

[0097] The first capacitor Cst can include a first electrode CE1 and a second electrode CE2. The first electrode CE1 can be connected to the gate electrode of the first transistor T1, and the second electrode CE2 can be connected to the driving voltage line PL. The first capacitor Cst can store and hold a voltage corresponding to a difference between voltages across the driving voltage line PL and the gate electrode of the first transistor T1, thereby maintaining a voltage applied to the gate electrode of the first transistor T1.

[0098] The second capacitor Cbt can include a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 can be connected to the first scan line SL1 and the gate electrode of the second transistor T2. The fourth electrode CE4 can be connected to the gate electrode of the first transistor T1 and the first electrode CE1 of the first capacitor Cst. The second capacitor Cbt can be a boost capacitor that can boost a voltage of the node N to reduce a voltage (e.g., a black voltage) for displaying black in a case where the first scan signal GP1 of the first scan line SL1 can be a voltage for turning off the second transistor T2.

[0099] The organic light emitting device OLED can include a pixel electrode and an opposite electrode, and the opposite electrode can receive a common voltage ELVSS. The organic light emitting device OLED can receive a driving current I OLED and can emit light, thereby displaying an image.

[0100] During an initialization period, in a case where a third scan signal GN1 can be supplied via the third scan line SL3, the fourth transistor T4 can be turned on according to the third scan signal GN1, and the first transistor T1 can be initialized by an initialization voltage Vint supplied from the initialization voltage line VIL.

[0101] During a data programming period, the second transistor T2, the seventh transistor T7, and the third transistor T3 can be turned on according to the first scan signal GP1, the second scan signal GP2, and the fourth scan signal GN2, in a case where the first scan signal GP1, the second scan signal GP2, and the fourth scan signal GN2 can be supplied via the first scan line SL1, the second scan line SL2, and the fourth scan line SL4. The first transistor T1 can be diode-connected by the turned-on third transistor T3, and can be biased in a forward direction. A voltage, which can compensate for a threshold voltage of the first transistor T1 by a data signal DATA supplied from the data line DL, can be applied to a gate electrode of the first transistor T1. The organic light emitting device OLED can be initialized by an initialization voltage Vint, while the initialization voltage Vint is supplied from an initialization voltage line VIL by the turned-on seventh transistor T7. A driving voltage ELVDD and a compensation voltage can be applied to both ends of the first capacitor Cst, and a charge corresponding to a voltage difference between both ends can be stored in the first capacitor Cst.

[0102] During an emission period, the fifth transistor T5 and the sixth transistor T6 can be turned on by an emission control signal EM supplied from an emission control line EL. A driving current I OLED can be generated by a voltage difference between a voltage of the gate electrode of the first transistor T1 and the driving voltage ELVDD, and the driving current I OLED can be supplied to the organic light emitting device OLED via the sixth transistor T6.

[0103] At least one of the first transistor T1 to the seventh transistor T7 can include a semiconductor layer including an oxide, and the other transistors can include a semiconductor layer including silicon. The first transistor T1, which directly affects brightness of the display device 10, can include a semiconductor layer including polysilicon, and thus a display device having high resolution can be implemented.

[0104] Because the oxide semiconductor can have high carrier mobility and low leakage current, a voltage drop can not be excessive even though a driving time can be long. For example, a color change of an image according to a voltage drop can not be excessive even during low frequency driving, and thus low frequency driving can be performed. Because the oxide semiconductor can have low leakage current, at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 can employ the oxide semiconductor, and thus leakage current that can flow through the gate electrode of the first transistor T1 can be prevented, and at the same time, power consumption can be reduced.

[0105] Figure 5 A schematic cross-sectional view of the display device 10 taken along a line A-A' of FIG. Figure 2 A schematic cross-sectional view of the display device 10 taken along a line A-A' of FIG.

[0106] Referring to Figure 5The display device 10 can include a substrate 100, a first thin film transistor TFT1 including silicon oxide, a second thin film transistor TFT2 including an oxide semiconductor, a first capacitor Cst, and a second capacitor Cbt. The first thin film transistor TFT1 can include a first transistor T1, a second transistor T2, a fifth transistor T5, a sixth transistor T6, or a seventh transistor T7. The second thin film transistor TFT2 can include a third transistor T3 or a fourth transistor T4 of Figure 4

[0107] The substrate 100 can include, for example, a glass material, a ceramic material, a metal material, or a flexible or bendable material. In the case where the substrate 100 is flexible or bendable, the substrate 100 can include a polymer resin such as polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, or a combination thereof. The substrate 100 can have a single layer or multiple layers including the above-described materials. In the case where the substrate 100 has multiple layers, the substrate 100 can include an inorganic layer. In an embodiment, the substrate 100 can have multiple layers including an organic material / inorganic material / organic material.

[0108] The buffer layer 110 can improve the smoothness of the top surface of the substrate 100. The buffer layer 110 can include an oxide layer such as silicon oxide (SiO x ), a nitride layer such as silicon nitride (SiN x ) or silicon oxynitride (SiON), or a combination thereof, but is not limited thereto.

[0109] A barrier layer (not shown) can be located between the substrate 100 and the buffer layer 110. The barrier layer can prevent or minimize the penetration of impurities from the substrate 100 into the silicon semiconductor layer. The barrier layer can include an inorganic material and / or an organic material such as an oxide or a nitride, and can have a single layer or multiple layers including an inorganic material and an organic material.

[0110] A first semiconductor layer AS of the first thin film transistor TFT1 including a silicon semiconductor can be disposed on the buffer layer 110. The first semiconductor layer AS can include a source region S1 and a drain region D1, and the source region S1 and the drain region D1 can have electrical conductivity caused by doping impurities and can be spaced apart from each other with a channel region C1 interposed therebetween. The source region S1 and the drain region D1 can correspond to a source electrode and a drain electrode of the first thin film transistor TFT1, respectively. The positions of the source region S1 and the drain region D1 can be exchanged.

[0111] A gate electrode GE1 of the first thin film transistor TFT1 can be located on the first semiconductor layer AS, and a first insulating layer 111 can be located between the first semiconductor layer AS and the gate electrode GE1.

[0112] ​The first insulating layer 111 can include an inorganic material including an oxide or a nitride. For example, the first insulating layer 111 can include at least one of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2), or a combination thereof, but is not limited thereto.

[0113] The gate electrode GE1 of the first thin film transistor TFT1 can overlap or face the channel region C1 of the first semiconductor layer AS, and can include at least one of molybdenum (Mo), copper (Cu), titanium (Ti), and aluminum (Al), or a combination thereof, but is not limited thereto. The gate electrode GE1 can have a single layer or multiple layers including at least one of the above-described materials.

[0114] The first electrode CE1 of the first capacitor Cst and the third electrode CE3 of the second capacitor Cbt can be located on the same layer as the gate electrode GE1 of the first thin film transistor TFT1.

[0115] The second insulating layer 112 can be located on the gate electrode GE1 of the first thin film transistor TFT1, the first electrode CE1 of the first capacitor Cst, and the third electrode CE3 of the second capacitor Cbt.

[0116] The second insulating layer 112 can include an inorganic material including an oxide, a nitride, or a combination thereof, but is not limited thereto. For example, the second insulating layer 112 can include at least one of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2), or a combination thereof, but is not limited thereto.

[0117] The second electrode CE2 of the first capacitor Cst can be located on the second insulating layer 112 so as to overlap or face the first electrode CE1 of the first capacitor Cst. The second electrode CE2 can include at least one of Mo, Cu, and Ti, or a combination thereof, but is not limited thereto. The second electrode CE2 can have a single layer or multiple layers including at least one of the above-described materials.

[0118] The third insulating layer 113 can be located on the second electrode CE2 of the first capacitor Cst. The third insulating layer 113 can include an inorganic material including an oxide, a nitride, or a combination thereof, but is not limited thereto. For example, the third insulating layer 113 can include at least one of silicon oxide (SiO2), silicon nitride (SiN xat least one of silicon oxide (SiOx), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2), or a combination thereof.

[0119] Although Figure 5 The first capacitor Cst is shown as being spaced apart from the first thin film transistor TFT1 in the first direction DI1, but the first capacitor Cst can overlap or face the first thin film transistor TFT1. For example, the second electrode CE2 can be arranged on an upper portion of the gate electrode GE1 of the first thin film transistor TFT1 to overlap or face the gate electrode GE1. The gate electrode GE1 of the first thin film transistor TFT1 can function as both the gate electrode and the first electrode CE1 of the first capacitor Cst.

[0120] The second semiconductor layer AO of the second thin film transistor TFT2 including an oxide semiconductor can be located on the third insulating layer 113. The second semiconductor layer AO can include a source region S2 and a drain region D2, and the source region S2 and the drain region D2 can have conductivity and can be spaced apart from each other with a channel region C2 interposed therebetween. The oxide semiconductor can include a zinc (Zn)-based material such as a Zn oxide, an indium (In)-Zn oxide, a gallium (Ga)-In-Zn oxide, or a combination thereof, but is not limited thereto. For example, the second semiconductor layer AO can include an In-Ga-Zn-O (IGZO) semiconductor, an In-tin (Sn)-Zn-O (ITZO) semiconductor, or an In-Ga-Sn-Zn-O (IGTZO) semiconductor in which a metal such as In, Ga, or Sn is included in a ZnO, but is not limited thereto. The source region S2 and the drain region D2 of the second semiconductor layer AO can be formed by controlling a carrier concentration of the oxide semiconductor and by making the oxide semiconductor conductive. For example, the source region S2 and the drain region D2 can be formed by increasing the carrier concentration by virtue of application of a plasma treatment on the oxide semiconductor, and the plasma treatment uses a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof.

[0121] The first gate electrode GEa can be located below the second semiconductor layer AO of the second thin film transistor TFT2, and the second gate electrode GEb can be located above the second semiconductor layer AO of the second thin film transistor TFT2. For example, the second thin film transistor TFT2 can include a double gate electrode. The third insulating layer 113 can be located between the first gate electrode GEa and the second semiconductor layer AO of the second thin film transistor TFT2. The first gate electrode GEa of the second thin film transistor TFT2 can be formed of the same material as the second electrode CE2 of the first capacitor Cst and formed on the same layer. At least the channel region C2 of the second semiconductor layer AO can overlap or face the first gate electrode GEa of the second thin film transistor TFT2.

[0122] The fourth insulating layer 114 can be located between the second semiconductor layer AO and the second gate electrode GEb of the second thin film transistor TFT2. The second gate electrode GEb can overlap or face the channel region C2 of the second semiconductor layer AO. The fourth insulating layer 114 can be formed with the same mask process as the second gate electrode GEb. The fourth insulating layer 114 can be formed to have the same shape as the shape of the second gate electrode GEb.

[0123] The fourth insulating layer 114 can include an inorganic material including an oxide, a nitride, or a combination thereof, but is not limited thereto. For example, the fourth insulating layer 114 can include at least one of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2), or a combination thereof, but is not limited thereto. The second gate electrode GEb can include at least one of Mo, Cu, Ti, and Al, or a combination thereof, but is not limited thereto. The second gate electrode GEb can have a single layer or a plurality of layers including at least one of the above-described materials.

[0124] The fourth electrode CE4 of the second capacitor Cbt can be formed on the third insulating layer 113 so as to overlap or face the third electrode CE3. The fourth electrode CE4 of the second capacitor Cbt can include an oxide semiconductor. The fourth electrode CE4 of the second capacitor Cbt can extend from the second semiconductor layer AO of the second thin film transistor TFT2 and can overlap or face the third electrode CE3. The second insulating layer 112 and the third insulating layer 113 can be disposed between the third electrode CE3 and the fourth electrode CE4.

[0125] The fifth insulating layer 115 can cover the second thin film transistor TFT2. The fifth insulating layer 115 can be disposed on the second gate electrode GEb, and the driving voltage line PL and the first connection electrode 167 can be disposed on the fifth insulating layer 115.

[0126] The fifth insulating layer 115 can include an inorganic material including an oxide, a nitride, or a combination thereof, but is not limited thereto. For example, the fifth insulating layer 115 can include at least one of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2), or a combination thereof, but is not limited thereto.

[0127] The driving voltage line PL and the first connection electrode 167 can include a material having high conductivity, such as a metal or a conductive oxide. For example, the driving voltage line PL and the first connection electrode 167 can have a single layer or multiple layers including at least one of Al, Cu, and Ti, or a combination thereof, but are not limited thereto. The driving voltage line PL and the first connection electrode 167 can have, for example, three layers of Ti / Al / Ti, which can be arranged sequentially.

[0128] The first connection electrode 167 can be connected to the first semiconductor layer AS via a contact hole H1. The contact hole H1 can pass through the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fifth insulating layer 115, and can expose a portion of the first semiconductor layer AS. A portion of the first connection electrode 167 can be inserted into the contact hole H1, and thus can be electrically connected to the first semiconductor layer AS.

[0129] The sixth insulating layer 116 can be a planarization layer that can be arranged on the driving voltage line PL and the first connection electrode 167. The sixth insulating layer 116 can include an organic material, such as benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). As another example, the sixth insulating layer 116 can include an inorganic material. The sixth insulating layer 116 can function as a protective layer for covering the first thin film transistor TFT1 and the second thin film transistor TFT2, and an upper portion of the sixth insulating layer 116 can be planar. The sixth insulating layer 116 can include a single layer or multiple layers.

[0130] The data line DL and the second connection electrode 177 can be located on the sixth insulating layer 116. A portion of the data line DL can overlap or face the driving voltage line PL. The second connection electrode 177 can be connected to the first connection electrode 167 via a contact hole H2 defined in the sixth insulating layer 116. The data line DL and the second connection electrode 177 can include a conductive material, such as a metal or a conductive oxide. For example, the data line DL and the second connection electrode 177 can include a single layer or multiple layers including at least one of Al, Cu, and Ti. The seventh insulating layer 117 can be arranged on the data line DL and the second connection electrode 177.

[0131] The organic light emitting device OLED can be arranged on the seventh insulating layer 117. The organic light emitting device OLED can include a pixel electrode 310, an opposite electrode 330, and an intermediate layer 320 located between the pixel electrode 310 and the opposite electrode 330, which can form an emission layer.

[0132] The pixel electrode 310 can be connected to the second connection electrode 177 via a contact hole H3 defined in the seventh insulating layer 117, and can be connected to the first thin film transistor TFT1 through the second connection electrode 177 and the first connection electrode 167.

[0133] The eighth insulating layer 118 can be a pixel definition layer which can be located on the seventh insulating layer 117. The eighth insulating layer 118 can have an opening corresponding to each of the plurality of pixels PX (i.e., an opening OP in which a portion of the pixel electrode 310 can be exposed), thereby defining the pixels PX. The eighth insulating layer 118 can increase a distance between an end portion of the pixel electrode 310 and an end portion of the opposite electrode 330 which can be disposed on the pixel electrode 310, thereby preventing an arc from being generated at the end portion of the pixel electrode 310. The eighth insulating layer 118 can be formed of an organic material such as polyimide or HMDSO.

[0134] The pixel electrode 310 can be disposed on the seventh insulating layer 117, and can include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), aluminum zinc oxide (AZO), or a combination thereof, but is not limited thereto. In another embodiment, the pixel electrode 310 can include a reflective layer including silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, but is not limited thereto. In another embodiment, the pixel electrode 310 can further include a layer formed of, for example, ITO, IZO, ZnO, In2O3, or a combination thereof, on / under the above-described reflective layer.

[0135] As noted above, the intermediate layer 320 of the organic light emitting device OLED can include an emission layer. The emission layer can include a polymer or a small molecular weight organic material which can emit light having a specific color. The emission layer can include a red emission layer, a green emission layer, or a blue emission layer. As another example, the emission layer can have a multi-layer structure which can be stacked with a red emission layer, a green emission layer, and a blue emission layer so as to emit white light, or a single layer structure including a red emission material, a green emission material, and a blue emission material. The emission layer can include a first functional layer located under the emission layer and / or a second functional layer located on the emission layer. The first functional layer and / or the second functional layer can include a layer formed to continuously extend over each of the plurality of pixel electrodes 310. The layer can be patterned to correspond to each of the plurality of pixel electrodes 310.

[0136] The first functional layer can have a single layer structure or a multi-layer structure. For example, in the case where the first functional layer can include a polymer material, the first functional layer which can be a hole transport layer (HTL) can have a single layer structure which can include poly(3,4)-ethylenedioxythiophene (PEDOT), polyaniline (PANI), or a combination thereof, but is not limited thereto. In the case where the first functional layer can include a small molecular weight material, the first functional layer can include, for example, a hole injection layer (HIL) and an HTL.

[0137] In other embodiments, the second functional layer can be omitted. For example, in the case where the first functional layer and the emission layer can include a polymer material, the second functional layer can be formed such that the organic light emitting device OLED can have excellent operating characteristics. The second functional layer can have a single layer structure or a multi-layer structure. The second functional layer can include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0138] The counter electrode 330 can be disposed to face the pixel electrode 310 with the intermediate layer 320 interposed therebetween. The counter electrode 330 can include a conductive material of a small work function. For example, the counter electrode 330 can include a (semi-)transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, calcium (Ca), or an alloy thereof, but is not limited thereto. As another example, the counter electrode 330 can include a layer such as ITO, IZO, ZnO, In2O3, or a combination thereof, which can be located on a (semi-)transparent layer including the above-described materials, but is not limited thereto. The counter electrode 330 can be located on the intermediate layer 320 and the eighth insulating layer 118. The counter electrode 330 can include a common electrode, and the common electrode can be formed as a single body disposed across each of a plurality of organic light emitting devices OLED in the display area DA and facing each of a plurality of pixel electrodes 310.

[0139] A spacer for preventing the mask from being imprinted can be disposed on the eighth insulating layer 118. Various functional layers such as a polarizing layer for reducing reflection of external light, a black matrix, a color filter, and / or a touch screen layer having a touch electrode can be provided on the thin film encapsulation layer.

[0140] Because the organic light emitting device OLED can be easily damaged by moisture or oxygen from the outside, the encapsulation layer 400 can cover the organic light emitting device OLED to protect the organic light emitting device OLED. The encapsulation layer 400 can cover the display area DA and can extend beyond the display area DA. As shown in FIG. 4A, the encapsulation layer 400 can include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430. Figure 5

[0141] The first inorganic encapsulation layer 410 can cover the counter electrode 330, and can include silicon oxide, silicon nitride, and / or silicon oxynitride, but is not limited thereto. Other layers including a capping layer can be located between the first inorganic encapsulation layer 410 and the counter electrode 330. As shown in FIG. 4A, the first inorganic encapsulation layer 410 can include a first layer 411, a second layer 412, and a third layer 413. Figure 5 ​As shown in FIG. 4, the top surface of the first inorganic encapsulation layer 410 can be uneven, because the first inorganic encapsulation layer 410 can be formed according to the profile of other components thereunder. The organic encapsulation layer 420 can cover the first inorganic encapsulation layer 410. Unlike the first inorganic encapsulation layer 410, the top surface of the organic encapsulation layer 420 can be substantially flat. The top surface of the organic encapsulation layer 420 can be substantially flat at a portion thereof corresponding to the display area DA. The organic encapsulation layer 420 can include at least one material selected from the group consisting of PET, PEN, PC, PI, polyvinyl sulfonate, polyoxymethylene (POM), and HMDSO, or a combination thereof, but is not limited thereto. The second inorganic encapsulation layer 430 can cover the organic encapsulation layer 420, and can include silicon oxide, silicon nitride, and / or silicon oxynitride. The second inorganic encapsulation layer 430 can be in contact with the first inorganic encapsulation layer 410 outside the display area DA, such that the organic encapsulation layer 420 can not be exposed to the outside.

[0142] In this way, the encapsulation layer 400 can include the first inorganic encapsulation layer 410, the organic encapsulation layer 420, and the second inorganic encapsulation layer 430. Accordingly, even in the case where a crack can occur in the encapsulation layer 400, a crack can not occur between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420 or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430. Accordingly, the formation of a path through which moisture or oxygen from the outside can penetrate into the display area DA can be prevented, or can be minimized.

[0143] The polarizing plate 520 can be located on the encapsulation layer 400 by using an optically clear adhesive (OCA) 510. The polarizing plate 520 can reduce external light reflection. For example, in the case where external light can pass through the polarizing plate 520 and can be reflected from the top surface of the opposite electrode 330 and then pass through the polarizing plate 520 again, the phase of the external light can change as the external light passes through the polarizing plate 520 a second time. As a result, the phase of the reflected light can be different from that of the external light entering the polarizing plate 520, such that destructive interference occurs, and as such, external light reflection can be reduced and visibility can be improved. For example, as shown in FIG. 5, the OCA 510 and the polarizing plate 520 can cover the opening of the seventh insulating layer 117. However, the display apparatus herein can not always include the polarizing plate 520. The polarizing plate 520 can be omitted or replaced with other configurations as appropriate. For example, the polarizing plate 520 can be omitted, and external light reflection can be reduced by using a black matrix and a color filter. Figure 5

[0144] ​As mentioned above, the buffer layer 110 can include an inorganic material, and the first to sixth insulating layers 111 to 116 can be referred to as inorganic insulating layers 125. The inorganic insulating layers 125 can include at least one of the first to sixth insulating layers 111 to 116. A case in which the inorganic insulating layers 125 can not include the fourth insulating layer 114 is discussed below. As discussed above, the inorganic insulating layers 125 can include a recess corresponding to the bending area BA. The recess can indicate an area in which a portion of the inorganic insulating layers 125 can be removed in a downward direction (-DI3 direction) and another portion thereof is retained. For example, the buffer layer 110 can be continuous in the first area 1A, the bending area BA, and the second area 2A. The inorganic insulating layers 125 can have an opening 125OP corresponding to the bending area BA. Accordingly, the opening 125OP of the inorganic insulating layers 125 can define the recess corresponding to the bending area BA. The inorganic insulating layers 125 can include a recess having a shape different from the illustrated shape. There can be various modifications, for example, a portion of a top surface (+DI3 direction) of the buffer layer 110 can be removed, and in other cases, a bottom surface (-DI3 direction) of the first insulating layer 111 can not be removed. Figure 5 As mentioned above, the buffer layer 110 can include an inorganic material, and the first to sixth insulating layers 111 to 116 can be referred to as inorganic insulating layers 125. The inorganic insulating layers 125 can include at least one of the first to sixth insulating layers 111 to 116. A case in which the inorganic insulating layers 125 can not include the fourth insulating layer 114 is discussed below. As discussed above, the inorganic insulating layers 125 can include a recess corresponding to the bending area BA. The recess can indicate an area in which a portion of the inorganic insulating layers 125 can be removed in a downward direction (-DI3 direction) and another portion thereof is retained. For example, the buffer layer 110 can be continuous in the first area 1A, the bending area BA, and the second area 2A. The inorganic insulating layers 125 can have an opening 125OP corresponding to the bending area BA. Accordingly, the opening 125OP of the inorganic insulating layers 125 can define the recess corresponding to the bending area BA. The inorganic insulating layers 125 can include a recess having a shape different from the illustrated shape. There can be various modifications, for example, a portion of a top surface (+DI3 direction) of the buffer layer 110 can be removed, and in other cases, a bottom surface (-DI3 direction) of the first insulating layer 111 can not be removed.

[0145] The recess corresponding to the bending area BA can overlap or face the bending area BA. For example, an area of the recess can be greater than an area of the bending area BA. To this end, in Figure 5 the recess, a width GW can be greater than a width of the bending area BA. In this regard, an area of the recess can be defined as an area of an opening having a smallest area among a plurality of openings of the inorganic insulating layers 125 which can respectively define the same or similar recesses.

[0146] The organic material layer 180 can fill at least a portion of the recess. For example, the organic material layer 180 can overlap or face the bending area BA. In such a case, the organic material layer 180 can extend beyond the bending area BA.

[0147] As discussed above herein, the wire 40 can extend from the first area 1A to the second area 2A via the bending area BA. The wire 40 can be positioned on the organic material layer 180. In a case in which the organic material layer 180 and the recess can not be provided, the wire 40 can be positioned on the inorganic insulating layers 125. As discussed, the wire 40 can transmit an electrical signal into the display area DA. A conductive portion of the wire 40 can be simultaneously formed of the same material as a material of each electrode discussed herein.

[0148] As discussed above herein, the wire 40 can extend from the first area 1A to the second area 2A via the bending area BA. The wire 40 can be positioned on the organic material layer 180. In a case in which the organic material layer 180 and the recess can not be provided, the wire 40 can be positioned on the inorganic insulating layers 125. As discussed, the wire 40 can transmit an electrical signal into the display area DA. A conductive portion of the wire 40 can be simultaneously formed of the same material as a material of each electrode discussed herein. Figure 1 As discussed above, the substrate 100 can be bent in the bending area BA. To this end, the display device 10 can be initially manufactured in a state in which the substrate 100 can be substantially flat. The substrate 100 can be bent in the bending area BA, such that the display device 10 can substantially have a Figure 1The shape shown in the substrate 100. In the case where the substrate 100 can be bent in the bending area BA, tensile stress can be applied to the wiring 40.

[0149] In the case where the substrate 100 can be bent and the inorganic insulating layer 125 can not include a groove in the bending area BA so as to have a continuous same shape from the first area 1A to the second area 2A and the wiring 40 can be located on the inorganic insulating layer 125, large tensile stress can be applied to the wiring 40. The hardness of the inorganic insulating layer 125 can be higher than that of the organic material layer 180. Thus, there can be a high possibility that a crack can occur in the inorganic insulating layer 125 in the bending area BA. In this case, a crack can occur in the wiring 40 and the possibility that the wiring 40 can be disconnected can increase.

[0150] However, according to the embodiments herein, as described above, the inorganic insulating layer 125 can include a groove in the bending area BA and the portion of the wiring 40 corresponding to the bending area BA can be located on the organic material layer 180, while the organic material layer 180 can fill at least a portion of the groove of the inorganic insulating layer 125. Thus, as a result, the possibility that a crack can occur in the inorganic insulating layer 125 can be reduced. This is because the hardness of the organic material layer 180 can be lower than that of the inorganic insulating layer 125. Thus, the organic material layer 180 can absorb the tensile stress that can be generated due to the bending of the substrate 100, thereby making it possible to effectively minimize the concentration of the tensile stress on the wiring 40.

[0151] The organic material layer 180 can include the same material as that of the organic material layer formed in the display area DA. For example, in the case where the seventh insulating layer 117 can be formed of an organic material, the organic material layer 180 can be simultaneously formed of the same material. In another example, in the case where the eighth insulating layer 118 can be formed of an organic material, the organic material layer 180 can be simultaneously formed of the same material. In another example, in the case where the organic encapsulation layer 420 of the encapsulation layer 400 can be formed of an organic material, the organic material layer 180 can be simultaneously formed of the same material. For example, the organic material layer 180 can also be formed separately from the seventh insulating layer 117.

[0152] The display device 10 can include a plurality of conductive layers connected to each of the wire portions of the wiring 40. The conductive layers can be disposed in the first area 1A or the second area 2A, thereby making it possible for each of the wire portions of the wiring 40 to be located on a different layer. The plurality of conductive layers can be electrically connected to each of the wire portions of the wiring 40. In Figure 5In this configuration, multiple conductive layers 213A and 213B may be formed of the same material as the gate electrode GE1 of the first thin-film transistor TFT1 and disposed on the same layer, i.e., on the first insulating layer 111. Each conductor portion of the wiring 40 may be connected to a third connection electrode 214A disposed on the fifth insulating layer 115, and the third connection electrode 214A may contact the conductive layer 213A via contact holes formed in the second insulating layer 112, the third insulating layer 113, and the fifth insulating layer 115. The conductive layer 213A may be located in the first region 1A, and the conductive layer 213B may be located in the second region 2A. The positions of the multiple conductive layers 213A and 213B are not limited to those described above, such that the multiple conductive layers 213A and 213B may be located on the top surface of one of the multiple constituent layers of the inorganic insulating layer 125.

[0153] The conductive layer 213A can be electrically connected to the thin-film transistor in the display area DA. Therefore, each conductor portion of the wiring 40 can be electrically connected to the thin-film transistor in the display area DA via the conductive layer 213A. The conductive layer 213B in the second region 2A can be electrically connected to the thin-film transistor in the display area DA via each conductor portion of the wiring 40. Therefore, the plurality of conductive layers 213A and 213B can be located outside the display area DA and electrically connected to components in the display area DA, and / or extend in a direction toward the display area DA such that at least a portion of the plurality of conductive layers 213A and 213B is arranged in the display area DA.

[0154] Each conductor portion of the wiring 40 that can cross the bending region BA may include a stretchable material, thereby preventing defects such as cracks in each conductor portion of the wiring 40 that could lead to an open circuit. The plurality of conductive layers 213A and 213B may be formed using materials having lower elongation characteristics than each conductor portion of the wiring 40 and having electrical / physical properties different from those of each conductor portion of the wiring 40. Therefore, the efficiency of electrical signal transmission can be improved, and the occurrence of defects such as cracks can be reduced. For example, the plurality of conductive layers 213A and 213B may include Mo, and each conductor portion of the wiring 40 may include Al. Each conductor portion of the wiring 40 or the plurality of conductive layers 213A and 213B may, depending on the situation, have multiple layers.

[0155] In the conductive layer 213B in the second region 2A, with Figure 5 Unlike other conductive layers, at least a portion of the upper part of the conductive layer 213B may not be covered by the seventh insulating layer 117 and may be exposed to the outside, thereby enabling the conductive layer 213B to be electrically connected to various electronic components or printed circuit boards.

[0156] Each of the wire portions of the above-described wiring 40 can be connected to the conductive layer 213B of the second region 2A via a fourth connection electrode 214B. The fourth connection electrode 214B can be similarly formed as the third connection electrode 214A.

[0157] The fourth connection electrode 214B can be connected to other fourth connection electrodes that can be spaced apart from each other via a connection wire portion (see Figure 2 40D). The connection wire portion 40D can be disposed on the fifth insulating layer 115, and the uppermost side of the fourth connection electrode 214B can be disposed on the fifth insulating layer 115. Each of the wire portions of the wiring 40 can be located on the sixth insulating layer 116.

[0158] The positions of the first wire portion 40A, the second wire portion 40B, and the third wire portion 40C, and the position of the connection wire portion 40D can not be limited to the above description. For example, the first wire portion 40A, the second wire portion 40B, and the third wire portion 40C can be located on different layers from the connection wire portion 40D. For example, in a case where the connection wire portion 40D can be disposed on one of the first insulating layer 111 to the sixth insulating layer 116, the first wire portion 40A, the second wire portion 40B, and the third wire portion 40C can be disposed on another one of the first insulating layer 111 to the sixth insulating layer 116. The connection wire portion 40D and the first wire portion 40A, the second wire portion 40B, and the third wire portion 40C can be disposed on different insulating layers, such that at least one of the first wire portion 40A, the second wire portion 40B, and the third wire portion 40C can be prevented from being connected to the connection wire portion 40D. In other words, all three of the first wire portion 40A, the second wire portion 40B, and the third wire portion 40C can not be connected to the connection wire portion 40D.

[0159] The above-described connection wire portion 40D can be connected to the third connection electrode 214A and the fourth connection electrode 214B. In a case where a plurality of connection wire portions 40D can be provided, the plurality of connection wire portions 40D can be arranged to be spaced apart from each other and disposed on an insulating layer on which the plurality of connection wire portions 40D can be disposed, such that the connection wire portions 40D can not be connected to each other while not overlapping or intersecting each other.

[0160] A stress neutralization layer (SNL) 600 can be located outside the display area DA. For example, the SNL 600 can be located on each of the wire portions of the wiring 40 to at least correspond to the bending area BA.

[0161] In a case where the main body including the plurality of layers can be bent, a neutral stress plane can exist. In a case where the SNL 600 can not be provided, depending on the bending of the substrate 100, an excessive tensile stress can be applied to each of the conductor portions of the wiring 40 in the bending area BA. This can be because the position of each of the conductor portions of the wiring 40 can not correspond to the neutral stress plane. However, since the SNL 600 can be provided and the thickness and modulus thereof can be adjusted, such that the position of the neutral stress plane in the main body (such as the substrate 100, the wiring 40, and the SNL 600) can be adjusted to address the neutral stress plane. For example, the neutral stress plane can be shifted closer to the wiring 40 via the SNL 600, such that the tensile stress applied to the wiring 40 can be minimized.

[0162] The SNL 600 can extend to the end portion of the substrate 100 of the display device 10. For example, in the second area 2A, at least a portion of the wiring 40, the conductive layer 213B, and / or other conductive layers electrically connected thereto can not be covered by the seventh insulating layer 117 or the eighth insulating layer 118, but can be electrically connected to various electronic elements or a printed circuit board. Thus, the portion including the wiring 40, the conductive layer 213B, and / or other conductive layers electrically connected thereto can be electrically connected to various electronic elements or a printed circuit board. It can be necessary to protect such an electrical connection portion from impurities such as external moisture. Thus, the SNL 600 can cover the electrical connection portion, and thus can function as a protective layer thereof. To this end, for example, the SNL 600 can extend to the end portion or the peripheral portion of the substrate 100 of the display device 10.

[0163] In Figure 5 In the above, the top surface of the SNL 600 in the display area DA coincides with the top surface of the polarizing plate 520. However, embodiments can not be limited thereto. For example, the tip end portion of the SNL 600 in the display area DA can cover a portion of the top surface of the end portion of the polarizing plate 520. As another example, the end portion of the SNL 600 in the display area DA can not be in contact with the polarizing plate 520 and / or the OCA 510. During or after the SNL 600 can be formed, a gas generated in the SNL 600 can be prevented from moving toward the display area DA and degrading the organic light emitting device OLED.

[0164] In a case where the top surface of the SNL 600 in the display area DA coincides with the top surface of the polarizing plate 520, or the tip end portion of the SNL 600 in the display area DA covers a portion of the top surface of the end portion of the polarizing plate 520, or the end portion of the SNL 600 in the display area DA is in contact with the OCA 510, the thickness of the portion of the SNL 600 in the display area DA can be greater than the thickness of another portion of the SNL 600. The SNL 600 can be formed via coating or curing of a liquid or paste-like material. Accordingly, the volume of the SNL 600 during the curing process can be reduced. In a case where the portion of the SNL 600 in the display area DA can be in contact with the polarizing plate 520 and / or the OCA 510, the position of the corresponding portion of the SNL 600 can become fixed, and thus the volume of the remaining portion of the SNL 600 can be reduced. As a result, the thickness of the portion of the SNL 600 in the display area DA can be greater than the thickness of another portion of the SNL 600.

[0165] Touch electrodes (not shown) including various patterns of functions for a touch screen can be located on the encapsulation layer 400. In order to protect the touch electrodes, a touch protection layer for covering the touch electrodes can be disposed. The display device 10 can include a protection film (not shown) for protecting the bottom surface of the substrate 100 (i.e., -DI3 direction). The protection film can include an opening corresponding to the bending area BA.

[0166] Referring to Figure 6 As described above, each wire portion of the wiring 40 can cross the bending area BA and be connected in portions in the first area 1A and the second area 2A. As it is, the wiring 40 can be arranged in the bending area BA and be perpendicular to the bending axis BAX.

[0167] The wiring 40 can be arranged in various forms. For example, portions in which signals having the same polarity pass through the wiring 40 can be formed into a group. The plurality of groups in which signals having the same polarity pass through can be symmetrically disposed with respect to each other based on an arbitrary (or imaginary) center line CE of the display device 10, the center line CE can be parallel to each wire portion of the wiring 40 while passing through the center of the second area 2A. The wiring 40 can be divided into a plurality of first groups 40A-1 and 40B-1 forming the wiring 40 to which signals having a negative polarity can be transmitted, a plurality of second groups 40A-2 and 40B-2 forming the wiring 40 to which signals having a positive polarity can be transmitted, and a plurality of third groups 40A-3 and 40B-3 forming the wiring 40 to which signals to be changed to a negative polarity or a positive polarity can be transmitted. At least one pair of the plurality of first groups 40A-1 and 40B-1, the plurality of second groups 40A-2 and 40B-2, and the plurality of third groups 40A-3 and 40B-3 can be disposed in pairs and arranged symmetrically with respect to each other based on the center line CE. For example, as shown in FIG. 6, the first group 40A-1 and the second group 40A-2 can be disposed in pairs and arranged symmetrically with respect to each other based on the center line CE, and the first group 40B-1 and the second group 40B-2 can be disposed in pairs and arranged symmetrically with respect to each other based on the center line CE. Figure 6As shown in FIG. 1, the plurality of third groups 40A-3 and 40B-3 can be closest to the center line CE, the plurality of second groups 40A-2 and 40B-2 can be arranged outside the plurality of third groups 40A-3 and 40B-3, and the plurality of first groups 40A-1 and 40B-1 can be arranged outside the plurality of second groups 40A-2 and 40B-2. The plurality of third groups 40A-3 and 40B-3, the plurality of second groups 40A-2 and 40B-2, and the plurality of first groups 40A-1 and 40B-1 can be sequentially arranged from the center line CE to the end of the second region 2A. This layout can be applied to the display device 10-1 of FIG. 1. Figure 6 In the above case, the wirings 40 to which signals having the same polarity can be transmitted are arranged at both sides of the center line CE, so that the electrical stability can be obtained. The layout of the wirings 40 described above can not be limited to the above description, but can include a configuration in which one pair of the plurality of first groups 40A-1 and 40B-1 to the plurality of third groups 40A-3 and 40B-3, another pair of the plurality of first groups 40A-1 and 40B-1 to the plurality of third groups 40A-3 and 40B-3, and still another pair of the plurality of first groups 40A-1 and 40B-1 to the plurality of third groups 40A-3 and 40B-3 are sequentially arranged.

[0168] In this regard, the first conductor portion 40A and the second conductor portion 40B of the wiring 40 can be symmetrically arranged with respect to each other based on the center line CE. The first conductor portion 40A and the second conductor portion 40B can include the plurality of first groups 40A-1 and 40B-1 to the plurality of third groups 40A-3 and 40B-3. The first group 40A-1 of the first conductor portion 40A and the first group 40B-1 of the second conductor portion 40B, the second group 40A-2 of the first conductor portion 40A and the second group 40B-2 of the second conductor portion 40B, and the third group 40A-3 of the first conductor portion 40A and the third group 40B-3 of the second conductor portion 40B can be symmetrically arranged with respect to each other based on the center line CE.

[0169] Two different portions of the wiring 40 to which the same signal can be applied can be connected to each other via a connection conductor portion 40D. To this end, a plurality of connection conductor portions 40D can be provided. The plurality of connection conductor portions 40D can be arranged apart from each other in a direction toward the terminal portion 20. In a case where the connection conductor portion 40D can be located in the peripheral region PA of the first region 1A, the plurality of connection conductor portions 40D can be arranged apart from each other between the display region DA and the bending region BA. The plurality of connection conductor portions 40D can be arranged in a zigzag configuration on a plane. The lengths of portions of the plurality of connection conductor portions 40D can be different from each other.

[0170] Figure 7 A view showing a configuration of a layout of a display device 10-1 according to another embodiment is illustrated.

[0171] Referring toFigure 7 Unlike the display device 10 shown in FIGS. 1 to 3, Figure 1 and Figure 2 Unlike the display device 10 shown in FIGS. 1 to 3, Figure 7 The display device 10-1 shown in FIG. 4 can include a data distribution circuit 160 and a test circuit 170.

[0172] The data distribution circuit 160 can be disposed between the data driving circuit 150 and the display area DA, and can transmit data signals from the data driving circuit 150 to the data lines DL. The data distribution circuit 160 can time-division the data signals applied through one output line FL of the data driving circuit 150 to distribute the time-divisioned data signals to the plurality of data lines DL.

[0173] The test circuit 170 can apply test signals to the data lines DL. The test circuit 170 can be connected to terminals (see 21 and 22 of FIG. 4) through a part of the wiring 40 via the conductive layer or the conductive layer in the peripheral area PA. The test circuit 170 can apply various test signals within the display area DA. Figure 2

[0174] Two different conductive line portions of the wiring 40 connectable to the test circuit 170 can be connected to each other via a connection conductive line portion 40D.

[0175] Figure 8 A schematic cross-sectional view showing a bending portion BA of a display device according to another embodiment is illustrated.

[0176] The inorganic insulating layer 125 can have an opening OP125 corresponding to the bending area BA. The opening OP125 of the inorganic insulating layer 125 can include an area in which layers located below the inorganic insulating layer 125 can be exposed. For example, the buffer layer 110, the first to third insulating layers 111 to 113, the fifth and sixth insulating layers 115 and 116 can have a plurality of openings corresponding to the bending area BA, and collectively define the opening OP125 of the inorganic insulating layer 125. The plurality of openings corresponding to the bending area BA can be understood as a plurality of openings which can overlap the bending area BA. The area of the plurality of openings can be greater than the area of the bending area BA. To this end, in Figure 8 the width GW of the opening OP125 can be greater than the width of the bending area BA. The area of the plurality of openings can be defined as the area of the opening having the smallest area of the plurality of openings of the first to third insulating layers 111 to 113, the fifth and sixth insulating layers 115 and 116. In Figure 8 the area of the opening OP125 can be defined by the area of the opening 110a of the buffer layer 110.

[0177] ​Because the hardness of the inorganic insulating layer 125 can be higher than the hardness of the organic material layer 180, the possibility that a crack can occur in the inorganic insulating layer 125 in the bending region BA without the opening 110a can be very high. In the case where a crack can occur in the inorganic insulating layer 125, the possibility that such a crack can propagate into the wiring 40 can increase. However, as described herein, the formation of the opening OP125 in the inorganic insulating layer 125 can reduce the possibility that a crack occurs in the inorganic insulating layer 125. The opening 110a formed in the buffer layer 110 in the bending region BA can further reduce the possibility that the crack described above is formed in the inorganic insulating layer 125.

[0178] Figure 9 A view shows a plan view of a display device 10-2 according to another embodiment.

[0179] The data drive circuit 150 can be arranged in the second region 2A of the substrate 100. The data drive circuit 150 can be formed as a COP and arranged on the substrate 100.

[0180] The data drive circuit 150 can be connected to the data line DL arranged in the display region DA via the third conductive line portion 40C. The data drive circuit 150 can be connected to the plurality of terminals 21 and 22. An FPCB (not shown) can be connected to the plurality of terminals 21 and 22, and thus signals can be input from the outside to the plurality of terminals 21 and 22. As described above, the display device 10-2 can include a connection conductive line portion 40D. The connection conductive line portion 40D can connect one first conductive line portion 40A and one second conductive line portion 40B that can be respectively connected to the first driver 11A and the second driver 11B in order to simultaneously transmit a commonly used signal or the same signal among a plurality of signals transmitted to the first driver 11A and the second driver 11B.

[0181] Figure 10 A view shows a perspective view of a display device 10-3 according to another embodiment.

[0182] Referring to Figure 10 , the display device 10-3 can be similar to the display device of at least one of Figures 1-9 . The substrate 100 of the display device 10-3 can include a first region 1A, a second region 2A, and a bending region BA. The substrate 100 can have a rectangular shape.

[0183] As shown in Figure 10 , the substrate 100 can be bent around a bending axis BAX in the bending region BA.

[0184] The display region DA and the peripheral region PA can be located in the first region 1A. The display region DA can have a quadrangular shape. For example, the display region DA can have a rectangular shape.

[0185] As in Figure 2 , the display device 10-3 can include a wire part and a connection wire part.

[0186] As in Figure 2 , the display device 10-3 can include a first driver and a second driver. The above-described connection wire part can connect wire parts respectively connectable to the first driver and the second driver to each other.

[0187] Figure 11 A view shows a perspective view of a display device 10-4 according to another embodiment.

[0188] Referring to Figure 11 , the display device 10-4 can include a first area 1A, a second area 2A, and a bending area BA. The first area 1A can have a polygonal shape. For example, as shown in Figure 11 , the first area 1A can have a quadrilateral shape. The second area 2A and the bending area BA can be formed similarly to such areas shown in Figure 1 .

[0189] As shown in Figures 1-9 , a wire part can be disposed in the display device 10-4.

[0190] In the display device according to one or more embodiments, the size of the connection part can be reduced, and various signals can be transmitted simultaneously and precisely. The size of the display device according to one or more embodiments can be minimized, in which the connection at the connection part can be accommodated in its reduced space without interfering with the signal transmission.

[0191] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope as defined by the following claims.

Claims

1. A display device, comprising: The display includes a display area and a non-display area; A first driver, located in the non-display area; A second driver is located in the non-display area and is spaced apart from the first driver; A bend, the bend being connected to the display; A connector is attached to the bend. A plurality of first conductive lines and a plurality of second conductive lines, wherein the plurality of first conductive lines are connected to a first driver, the plurality of second conductive lines are connected to a second driver, and the plurality of first conductive lines and the plurality of second conductive lines are arranged in the non-display area; and A connecting wire portion connects one of the plurality of first wire portions and one of the plurality of second wire portions to each other. Wherein, the connecting wire is connected to the first wire at a first point and to the second wire at a second point, one of the first point and the second point is connected to a terminal and the other of the first point and the second point is not connected to any terminal, such that the first wire and the second wire are subjected to the same signal.

2. The display device as claimed in claim 1, wherein, The connecting wire portion is arranged in the connector.

3. The display device as claimed in claim 1, further comprising: A data driving circuit is disposed in the connector.

4. The display device as claimed in claim 1, wherein, The display area has a circular shape.

5. The display device as claimed in claim 1, wherein, The first conductor portion and the second conductor portion are arranged on the same layer, and The connecting wire portion is arranged on a different layer than the same layer on which the first wire portion and the second wire portion are arranged.

6. The display device as claimed in claim 1, wherein, At least one of the first conductor portion and the second conductor portion and the connecting conductor portion are arranged in different directions relative to each other.

7. The display device as claimed in claim 6, wherein, At least one of the first guide portion and the second guide portion extends perpendicularly to the bending axis of the bent portion, and The connecting wire portion extends parallel to the bending axis of the bending portion.

8. The display device as claimed in claim 1, wherein, The plurality of first guide wire portions and the plurality of second guide wire portions are arranged symmetrically relative to each other based on the center line of the display device.

9. The display device as claimed in claim 8, wherein, Among the plurality of first conductor sections and the plurality of second conductor sections, the conductor sections to which signals of the same polarity are transmitted are symmetrical about each other based on the center line.

10. A display device, comprising: A substrate having a first region, a second region, and a bend located between the first region and the second region; At least one insulating layer, the insulating layer being located on the bend, the insulating layer including an opening corresponding to the bend; A plurality of conductive portions extending from the first region through the bend into the second region, and arranged on at least one of the insulating layers to overlap with the opening; An organic material layer is located between at least one of the insulating layers and the plurality of conductive portions, and the organic material layer fills the opening; as well as A portion of the plurality of wire sections is connected to the first driver in the first region. Another portion of the plurality of wire sections is connected to the second driver in the first region, and The connecting wire is connected at a first point to one of the portions of the plurality of wires, and at a second point to one of the portions of the plurality of wires, a second wire. One of the first and second points is connected to a terminal, and the other of the first and second points is not connected to any terminal, such that the first wire and the second wire are subjected to the same signal.

11. The display device as claimed in claim 10, wherein, The connecting wire portion is located in the second region.

12. The display device as claimed in claim 10, wherein, The connecting wire portion is arranged differently from the plurality of wire portions on at least one of the insulating layers.

13. The display device as claimed in claim 10, wherein, A portion of the plurality of conductor portions and another portion of the plurality of conductor portions are arranged symmetrically relative to each other based on the center line of the display device, the center line extending between the plurality of conductor portions to equally divide the plurality of conductor portions on opposite sides of the center line of the display device.

14. The display device as claimed in claim 13, wherein, Among the plurality of conductor sections, the conductor sections to which signals of the same polarity are transmitted are symmetrical about each other based on the center line.

15. The display device as claimed in claim 10, wherein, The connecting wire portion is configured as multiple, and The plurality of connecting wire portions are spaced apart from each other in a plane to connect, respectively, a portion of the plurality of wire portions in the first region connected to the first driver to another portion of the plurality of wire portions in the first region connected to the second driver.

16. The display device as claimed in claim 10, wherein, The first region has a circular shape.

17. The display device of claim 10, further comprising: A data driving circuit, located in the second region.

18. The display device as claimed in claim 10, wherein, Each of the plurality of conductor sections and the connecting conductor section are arranged in different directions relative to each other.

19. The display device as claimed in claim 18, wherein, Each of the plurality of conductor portions extends perpendicularly to the bending axis of the bend portion, and The connecting wire portion extends parallel to the bending axis of the bending portion.

20. A display device, comprising: A substrate having a first region, a second region, and a bend located between the first region and the second region; At least one insulating layer, the at least one insulating layer being located on the substrate, the at least one insulating layer including an opening corresponding to the bend; A plurality of conductor portions extend from the first region through the bend to the second region and are arranged on at least one of the insulating layers to overlap at least a portion of the opening; as well as An organic material layer is located between at least one of the insulating layers and the plurality of conductive portions, and the organic material layer fills the opening. A portion of the plurality of wire sections is connected to the first driver in the first region. Another portion of the plurality of wire sections is connected to the second driver in the first region. The portion and the other portion of the plurality of conductors are connected to each other, and The connecting wire is connected at a first point to one of the portions of the plurality of wires, and at a second point to one of the portions of the plurality of wires, a second wire. One of the first and second points is connected to a terminal, and the other of the first and second points is not connected to any terminal, such that the first wire and the second wire are subjected to the same signal.

21. The display device as claimed in claim 20, wherein, The portion and the other portion of the plurality of conductors are respectively connected to each other via a plurality of connecting conductors, and extend perpendicularly to the bending axis of the bend. The connecting wire portion extends parallel to the bending axis of the bending portion.

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