Semiconductor device and method for manufacturing the same

Abstract

Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a first gate pattern and a second gate pattern which are separated from each other in a first direction on a substrate and extend in the first direction; a separation pattern which is provided between the first gate pattern and the second gate pattern and is in direct contact with the first gate pattern and the second gate pattern, and extends in a second direction intersecting the first direction; a third gate pattern which is separated from the first gate pattern in the second direction and extends in the first direction; and an interlayer dielectric layer which is provided between the first gate pattern and the third gate pattern. The separation pattern includes a material different from that of the interlayer dielectric layer. A bottom surface of the separation pattern has an uneven structure.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0094554 filed on August 2, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present inventive concept relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a fin field effect transistor and a method for manufacturing the same. Background Art

[0003] Metal oxide semiconductor field effect transistors (MOSFETs) are semiconductor devices widely used in very large scale integrated circuits. As semiconductor devices have become increasingly integrated with the development of the electronics industry, MOSFETs have been scaled down to meet the reduced design requirements of semiconductor devices. This scaling down of MOSFETs can degrade the operating characteristics of semiconductor devices. Therefore, various studies have been conducted to develop methods for manufacturing semiconductor devices that have excellent performance while overcoming the problems associated with high integration of semiconductor devices. Summary of the Invention

[0004] Example embodiments of the inventive concepts provide a semiconductor device having enhanced reliability and also provide a method of manufacturing the semiconductor device, wherein the method may improve yield.

[0005] According to example embodiments of the present inventive concepts, a semiconductor device may include: a first gate pattern and a second gate pattern spaced apart from each other in a first direction on a substrate, each of the first gate pattern and the second gate pattern extending in the first direction; a separation pattern disposed between and in direct contact with the first and second gate patterns, the separation pattern extending in a second direction intersecting the first direction; a third gate pattern spaced apart from the first gate pattern in a second direction, the third gate pattern extending in the first direction; and an interlayer dielectric layer disposed between the first and third gate patterns. The separation pattern may include a material different from that of the interlayer dielectric layer. A bottom surface of the separation pattern may have an uneven structure.

[0006] According to example embodiments of the present inventive concepts, a semiconductor device may include: a first active fin and a second active fin protruding from a substrate and spaced apart from each other; a device isolation layer covering a top surface of the substrate and exposing the top and side surfaces of the first active fin and the top and side surfaces of the second active fin; a first gate pattern covering the top and side surfaces of the first active fin; a second gate pattern spaced apart from the first gate pattern in a first direction and covering the top and side surfaces of the second active fin; a first interlayer dielectric layer covering the side surfaces of the first gate pattern; and a first separation pattern disposed on the device isolation layer between the first and second gate patterns, the first separation pattern being in direct contact with the first and second gate patterns. The first separation pattern may include a material different from that of the first interlayer dielectric layer. The first separation pattern may include: a first separation segment disposed between the first and second gate patterns; and a first portion extending from the first separation segment and located outside one sidewall of the first gate pattern.

[0007] According to example embodiments of the present inventive concepts, a semiconductor device may include: first and second gate patterns spaced apart from each other in a first direction on a substrate; a first interlayer dielectric layer in contact with a sidewall of the first gate pattern; a separation pattern disposed between and in direct contact with the first and second gate patterns; a first source / drain pattern positioned adjacent to the first gate pattern; a second source / drain pattern positioned adjacent to the second gate pattern; and a contact plug in direct contact with top surfaces of the first and second source / drain patterns. The separation pattern may include a material different from that of the first interlayer dielectric layer. The bottom surface of the contact plug may have an uneven structure.

[0008] According to an example embodiment of the present invention, a method for manufacturing a semiconductor device may include: preparing a substrate, the substrate including a separation mask opening region extending in a first direction and a contact region intersecting the separation mask opening region, the separation mask opening region including a separation region and an overlapping region overlapping the contact region; forming an initial gate pattern on the substrate, the initial gate pattern spanning the separation region located on a side of the contact region; forming an interlayer dielectric layer, the interlayer dielectric layer being located on the contact region and covering a sidewall of the initial gate pattern; removing the initial gate pattern from the separation region, and etching a portion of the interlayer dielectric layer to form a first gate pattern and a second gate pattern and simultaneously forming a separation trench on the separation mask opening region; forming a separation pattern filling the separation trench, the separation pattern including a material different from that of the interlayer dielectric layer; replacing at least a portion of the separation pattern with a buried dielectric pattern on the overlapping region; forming a contact hole by removing the interlayer dielectric layer from the contact region and removing the buried dielectric pattern from the overlapping region; and forming a contact plug in the contact hole.

[0009] According to an example embodiment of the present inventive concept, a method for manufacturing a semiconductor device may include: preparing a substrate including a separation mask opening region extending in a first direction and a contact region intersecting the separation mask opening region, the separation mask opening region including a separation region and an overlapping region overlapping the contact region; forming an initial gate pattern on the substrate, the initial gate pattern spanning the separation region located on a side of the contact region; forming an interlayer dielectric layer located on the contact region and covering a sidewall of the initial gate pattern; removing the initial gate pattern from the separation region, and etching a portion of the interlayer dielectric layer to form a first gate pattern and a second gate pattern while simultaneously forming a separation trench on the separation mask opening region; forming a sacrificial pattern in the separation trench located on the separation region; forming a buried dielectric pattern in the separation trench located on the overlapping region; and replacing the sacrificial pattern with the separation pattern. The separation pattern may include a material different from that of the interlayer dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present inventive concepts will become more apparent by describing in detail example embodiments of the present inventive concepts with reference to the accompanying drawings, in which:

[0011] Figure 1A shows a plan view showing a semiconductor device according to an example embodiment of the inventive concept;

[0012] Figure 1B FIG. 1 shows an exemplary embodiment of the present invention. Figure 1A sectional views taken along line AA', line BB' and line CC';

[0013] Figure 1C FIG. 1 shows an exemplary embodiment of the present invention. Figure 1A A sectional view taken along line D-D';

[0014] Figures 2A to 8A Shows the display manufacturing Figure 1A A plan view of a semiconductor device method;

[0015] Figures 2B to 8B Shows the display manufacturing Figure 1B A cross-sectional view of a method for a semiconductor device;

[0016] Figure 9A shows a plan view showing a semiconductor device according to an example embodiment of the inventive concept;

[0017] Figure 9B FIG. 1 shows an exemplary embodiment of the present invention. Figure 9A sectional views taken along line AA', line BB' and line CC';

[0018] Figure 10 FIG. 1 shows an exemplary embodiment of the present invention. Figure 9A sectional views taken along line AA', line BB' and line CC';

[0019] Figures 11A to 11E Shows the display manufacturing Figure 9B or Figure 10 A cross-sectional view of a method for a semiconductor device;

[0020] Figure 12A shows a plan view showing a semiconductor device according to an example embodiment of the inventive concept;

[0021] Figure 12B FIG. 1 shows an exemplary embodiment of the present invention. Figure 12A sectional views taken along line AA', line BB' and line CC';

[0022] Figure 13A shows a plan view showing a semiconductor device according to an example embodiment of the inventive concept;

[0023] Figure 13B FIG. 1 shows an exemplary embodiment of the present invention. Figure 13A sectional views taken along line AA', line BB' and line CC';

[0024] Figure 14 FIG. 1 shows an exemplary embodiment of the present invention. Figure 13A sectional views taken along line AA', line BB' and line CC';

[0025] Figure 15A shows a plan view showing a semiconductor device according to an example embodiment of the inventive concept;

[0026] Figure 15B FIG. 1 shows an exemplary embodiment of the present invention. Figure 15A sectional views taken along line AA', line BB' and line CC';

[0027] Figure 16A shows a plan view showing a semiconductor device according to an example embodiment of the inventive concept;

[0028] Figure 16B FIG. 1 shows an exemplary embodiment of the present invention. Figure 16A sectional views taken along line AA', line BB' and line CC';

[0029] Figure 17 FIG. 1 shows an exemplary embodiment of the present invention. Figure 16Asectional views taken along line AA', line BB' and line CC';

[0030] Figure 18A shows a plan view showing a semiconductor device according to an example embodiment of the inventive concept;

[0031] Figure 18B FIG. 1 shows an exemplary embodiment of the present invention. Figure 18A sectional views taken along line AA', line BB' and line CC';

[0032] Figure 19A shows a plan view showing a semiconductor device according to an example embodiment of the inventive concept;

[0033] Figure 19B FIG. 1 shows an exemplary embodiment of the present invention. Figure 19A sectional views taken along line AA', line BB', and line CC'; and

[0034] Figure 20 FIG. 1 shows an exemplary embodiment of the present invention. Figure 9A Cross-sectional views taken along line AA', line BB' and line CC'.

[0035] Since Figures 1 to Figure 20 The figures in the drawings are for illustrative purposes, and therefore the elements in the figures are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for the purpose of clarity. DETAILED DESCRIPTION

[0036] Example embodiments of the present inventive concept will now be described in detail with reference to the accompanying drawings to help clearly explain the present inventive concept.

[0037] Figure 1A A plan view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated. Figure 1B FIG. 1 shows an exemplary embodiment of the present invention. Figure 1A Cross-sectional views taken along line AA', line BB' and line CC'. Figure 1C FIG. 1 shows an exemplary embodiment of the present invention. Figure 1A A cross-sectional view taken along line D-D'. Figure 1A In FIG. 1 , there is a diagram that may correspond to a portion of a static random access memory (SRAM) device or to a portion of a logic / peripheral circuit area.

[0038] Reference Figures 1A to 1C, a substrate 1 may be provided. The substrate 1 may be, for example, a single crystal silicon wafer or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate 1 may be a silicon substrate including silicon (Si) (e.g., single crystal silicon (Si), polycrystalline silicon (Si), amorphous silicon (Si) or a combination thereof), and / or may include other materials such as silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide (InSb), lead telluride compound (PbTe), gallium phosphide (GaP), indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs) or gallium antimonide (GaSb). The substrate 1 may include a separation mask opening region SMR and contact regions CR1 and CR2. When viewed in a plan view, the separation mask opening region SMR may have a strip shape extending in a first direction x. The contact regions CR1 and CR2 may include a first contact region CR1 and a second contact region CR2 separated from each other in the first direction x. When viewed in a plan view, the first contact region CR1 and the second contact region CR2 may each have a strip shape extending in a second direction y intersecting the first direction x. When viewed in a plan view, the separation mask opening region SMR may overlap the contact regions CR1 and CR2. The first overlapping region OR1 may be defined as a region where the separation mask opening region SMR overlaps the first contact region CR1. The second overlapping region OR2 may be defined as a region where the separation mask opening region SMR overlaps the second contact region CR2.

[0039] The first active fin AF1 and the second active fin AF2 may protrude from the top surface of the substrate 1. When viewed in a plan view, the first active fin AF1 and the second active fin AF2 may each have a straight line shape extending in the first direction x and may be spaced apart from each other in the second direction y. The first active fin AF1 and the second active fin AF2 may be arranged parallel to each other. The device isolation layer 3 may cover the top surface of the substrate 1 and the lower side surfaces of the first active fin AF1 and the second active fin AF2, and thus may surround and define the first active fin AF1 and the second active fin AF2. The device isolation layer 3 may have a single-layer or multi-layer structure including one or more selected from, for example, a silicon oxide (SiO2) layer, a silicon nitride (Si3N4) layer, and a silicon oxynitride (SiON) layer. The device isolation layer 3 may have a top surface lower than the top surface of the first active fin AF1 and the top surface of the second active fin AF2.

[0040] The gate patterns GP0 to GP5 may each span the first active fin AF1 and / or the second active fin AF2. The zeroth gate pattern GP0 and the fifth gate pattern GP5, which are spaced apart from each other in the first direction x, may each span all of the first active fin AF1 and the second active fin AF2. The first gate pattern GP1 and the second gate pattern GP2 may be located between the zeroth gate pattern GP0 and the fifth gate pattern GP5 and may be spaced apart from each other in the second direction y. The third gate pattern GP3 may be disposed between the first gate pattern GP1 and the fifth gate pattern GP5. The fourth gate pattern GP4 may be disposed between the second gate pattern GP2 and the fifth gate pattern GP5. The third gate pattern GP3 and the fourth gate pattern GP4 may be spaced apart from each other in the second direction y. The first gate pattern GP1 and the third gate pattern GP3 may each span the first active fin AF1. The second gate pattern GP2 and the fourth gate pattern GP4 may each span the second active fin AF2. The gate patterns GP0 to GP5 are neither disposed on the separation mask opening region SMR nor on the first contact region CR1 and the second contact region CR2.

[0041] Each of the gate patterns GP0 to GP5 may include a gate dielectric layer GO, a gate electrode MG, and a gate cap pattern CAP. The gate dielectric layer GO may include one or more selected from, for example, a silicon oxide (SiO2) layer and a high-k dielectric layer having a dielectric constant greater than that of the silicon oxide (SiO2) layer. The high-k dielectric layer may include a metal oxide layer, such as a hafnium oxide (HfO2) layer, a lanthanum oxide (La2O3) layer, a zirconium oxide (ZrO2) layer, a tantalum oxide (Ta2O5) layer, a titanium oxide (TiO2) layer, or an aluminum oxide (Al2O3) layer. The gate electrode MG may include, for example, one or more selected from a polysilicon (p-Si) layer doped with impurities, a metal nitride layer (such as a titanium nitride (TiN) layer, a tungsten nitride (WN) layer, a molybdenum nitride (MoN) layer, and a tantalum nitride (TaN) layer), and a metal layer (such as a tungsten (W) layer, a copper (Cu) layer, a titanium (Ti) layer, a tantalum (Ta) layer, a molybdenum (Mo) layer, and an aluminum (Al) layer). The gate cap pattern CAP may include a silicon nitride (Si3N4) layer.

[0042] The separation pattern SP may be positioned between the first gate pattern GP1 and the second gate pattern GP2 to separate the first and second gate patterns GP1 and GP2, and between the third and fourth gate patterns GP3 and GP4 to separate the third and fourth gate patterns GP3 and GP4. The separation pattern SP may be located on the separation mask opening region SMR of the substrate 1. The separation pattern SP may be located on the device isolation layer 3 between the adjacent first and second active fins AF1 and AF2. The separation pattern SP may contact the device isolation layer 3. For example, a portion of the separation pattern SP sandwiched between the first and second gate patterns GP1 and GP2 may contact the device isolation layer 3 to electrically isolate the first and second gate patterns GP1 and GP2, and a portion of the separation pattern SP sandwiched between the third and fourth gate patterns GP3 and GP4 may contact the device isolation layer 3 to electrically isolate the third and fourth gate patterns GP3 and GP4. The separation pattern SP may have a top surface located at the same height as the top surfaces of the gate patterns GP0 to GP5.

[0043] The separation pattern SP may include a first protruding segment P1, a first separation segment S1, a second protruding segment P2, a second separation segment S2, and a third protruding segment P3. The first separation segment S1 may be located between the first gate pattern GP1 and the second gate pattern GP2 and may directly contact the first and second gate patterns GP1 and GP2. The first separation segment S1 may also directly contact the device isolation layer 3, thereby preventing the formation of a gate bridge between the first and second gate patterns GP1 and GP2. The second separation segment S2 may be located between the third and fourth gate patterns GP3 and GP4 and may directly contact the third and fourth gate patterns GP3 and GP4. The second separation segment S2 may also directly contact the device isolation layer 3, thereby preventing the formation of a gate bridge between the third and fourth gate patterns GP3 and GP4. The first separation segment S1 may be located on the first separation region SR1 of the substrate 1. The second separation segment S2 may be located on the second separation region SR2 of the substrate 1.

[0044] The first protruding segment P1 may be connected to the first separation segment S1 and may protrude toward the first overlapping region OR1. The second protruding segment P2 may be disposed between the first separation segment S1 and the second separation segment S2 and may connect the first and second separation segments S1 and S2. The first separation segment S1 may be disposed between the first protruding segment P1 and the second protruding segment P2 and may connect the first and second protruding segments P1 and P2. The third protruding segment P3 may be connected to the second separation segment S2 and may protrude toward the second overlapping region OR2. The second separation segment S2 may be disposed between the second protruding segment P2 and the third protruding segment P3 and may connect the second and third protruding segments P2 and P3. The first protruding segment P1 may be located on the first overlapping region OR1 of the substrate 1. The third protruding segment P3 may be located on the second overlapping region OR2 of the substrate 1. On the substrate 1, the second protruding segment P2 may be located in the intermediate region MR between the first separation region SR1 and the second separation region SR2. The separation mask opening region SMR may include the first and second overlapping regions OR1 and OR2, the first and second separation regions SR1 and SR2, and the intermediate region MR.

[0045] The first separation segment S1, the second protruding segment P2, and the second separation segment S2 may have their top surfaces located at the same height (e.g., coplanar). The first protruding segment P1 and the third protruding segment P3 may have their top surfaces lower than the top surfaces of the first separation segment S1, the second protruding segment P2, and the second separation segment S2. The first separation segment S1 and the second separation segment S2 may have their bottom surfaces located at the same height and may contact the device isolation layer 3. The first protruding segment P1, the second protruding segment P2, and the third protruding segment P3 may have their bottom surfaces located at the same height. The bottom surfaces of the first protruding segment P1, the second protruding segment P2, and the third protruding segment P3 may be higher than the bottom surfaces of the first separation segment S1 and the second separation segment S2. For example, the second protruding segment P2 may extend from the first separation segment S1 in a direction away from the first protruding segment P1, and the top surface of the second protruding segment P2 may be coplanar with the top surface of the first separation segment S1. For example, the third protruding segment P3 may extend from the second separation segment S2 in a direction away from the second protruding segment P2, and the third protruding segment P3 may have the same thickness as the first protruding segment P1. The thickness of the second protruding segment P2 may be greater than the thickness of the third protruding segment P3. The thickness is measured in the third direction z.

[0046] The gate patterns GP0 to GP5 may have their sidewalls covered by spacers SC. The spacers SC may have a single-layer or multi-layer structure including one or more selected from, for example, a silicon oxide (SiO2) layer, a silicon nitride (Si3N4) layer, and a silicon oxynitride (SiON) layer. Source / drain patterns SD1 and SD2 may be disposed on the active fins AF1 and AF2 on the sides of the gate patterns GP0 to GP5. The first source / drain pattern SD1 may be located on the first active fin AF1, and the second source / drain pattern SD2 may be located on the second active fin AF2. The first source / drain pattern SD1 and the second source / drain pattern SD2 may each include a semiconductor material selected from, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), etc., doped with n-type or p-type impurities. The first source / drain pattern SD1 and the second source / drain pattern SD2 may have a hexagonal shape, but the present inventive concept is not limited thereto.

[0047] The spaces between the gate patterns GP0 to GP5 may be filled with a first interlayer dielectric layer IL1. The first interlayer dielectric layer IL1 may be formed of a material having an etch selectivity relative to the material of the gate cap pattern CAP, such as silicon oxide (SiO2). The first interlayer dielectric layer IL1 may cover the source / drain patterns SD1 and SD2. Figure 1C As shown in FIG, above the first source / drain pattern SD1, a first interlayer dielectric layer IL1 may be disposed between the first gate pattern GP1 and the third gate pattern GP3. A second interlayer dielectric layer IL2 may cover the gate patterns GP0 to GP5, the separation pattern SP, and the first interlayer dielectric layer IL1. The second interlayer dielectric layer IL2 may be formed of a material having an etch selectivity relative to the material of the gate cap pattern CAP, such as silicon oxide (SiO2). In an example embodiment of the present inventive concept, the first interlayer dielectric layer IL1 and the second interlayer dielectric layer IL2 may be formed of the same material, such as silicon oxide (SiO2). However, the present inventive concept is not limited thereto.

[0048] In the first contact region CR1, the first contact plug CT1 may penetrate the first interlayer dielectric layer IL1 and the second interlayer dielectric layer IL2 and may contact one of the first source / drain patterns SD1 and one of the second source / drain patterns SD2. In the second contact region CR2, the second contact plug CT2 may penetrate the first interlayer dielectric layer IL1 and the second interlayer dielectric layer IL2 and may contact the other of the first source / drain patterns SD1 and the other of the second source / drain patterns SD2. A buried dielectric pattern FL may be interposed between the second interlayer dielectric layer IL2 and the upper surface of the first contact plug CT1. The buried dielectric pattern FL may include, for example, a silicon oxide (SiO2) layer. To facilitate the creation of the contact hole CH during the process of forming the first and second contact plugs CT1 and CT2, the first interlayer dielectric layer IL1, the second interlayer dielectric layer IL2, and the buried dielectric pattern FL may be formed of the same material and thus may have the same etching rate. The first contact plug CT1 may be formed next to the first separation segment S1. For example, the first contact plug CT1 may extend in the second direction y and may be adjacent to the first separation segment S1 of the separation pattern SP.

[0049] The first protruding segment P1 of the separation pattern SP may contact the bottom surface of the first contact plug CT1. For example, the separation pattern SP may extend in the first direction x, and a portion of the separation pattern SP (e.g., the first protruding segment P1) may contact the bottom surface of the first contact plug CT1. The third protruding segment P3 of the separation pattern SP may contact the bottom surface of the second contact plug CT2. One sidewall of the first protruding segment P1 may be spaced apart from one sidewall of the first contact plug CT1 adjacent to the one sidewall of the first protruding segment P1. The width of the first contact plug CT1 in the first direction x may be greater than the width of the first protruding segment P1 in the first direction x. One sidewall of the third protruding segment P3 may be spaced apart from one sidewall of the second contact plug CT2 adjacent to the one sidewall of the third protruding segment P3. The width of the second contact plug CT2 in the first direction x may be greater than the width of the third protruding segment P3 in the first direction x.

[0050] The bottom surface SPS of the separation pattern SP may have an uneven structure. Between the first gate pattern GP1 and the second gate pattern GP2, the bottom surface SPS of the separation pattern SP may have a first depth DP1 from the bottom surface of the second interlayer dielectric layer IL2. For example, the first depth DP1 may be measured from the top surface of the first separation segment S1 to the bottom surface of the first separation segment S1 in the third direction z. Below the first contact plug CT1, the bottom surface SPS of the separation pattern SP may have a second depth DP2 from the bottom surface of the second interlayer dielectric layer IL2. For example, the second depth DP2 may be measured from the top surface of the first separation segment S1 to the bottom surface of the first protruding segment P1 in the third direction z. The first depth DP1 may be greater than the second depth DP2. The first protruding segment P1, the second protruding segment P2, and the third protruding segment P3 may be referred to as a first portion P1, a second portion P2, and a third portion P3, respectively.

[0051] The semiconductor device according to example embodiments of the present inventive concepts does not have gate bridges on the separation regions SR1 and SR2, nor does it have contact connection failures on the overlapped regions OR1 and OR2, which can improve the reliability of the semiconductor device. For example, no gate bridges are formed between the first gate pattern GP1 and the second gate pattern GP2 located on the first separation region SR1, and between the third gate pattern GP3 and the fourth gate pattern GP4 located on the second separation region SR2. The first contact plug CT1 and the second contact plug CT2 located on the overlapped regions OR1 and OR2, respectively, can be seamlessly connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. The gate patterns GP0 to GP5, the active fins AF1 and AF2, and the source / drain patterns SD1 and SD2 can form a plurality of fin field-effect transistors (FinFETs).

[0052] Figures 2A to 8A Shows the display manufacturing Figure 1A A plan view of a semiconductor device method. Figures 2B to 8B Shows the display manufacturing Figure 1B A cross-sectional view of a method for manufacturing a semiconductor device. Figures 2B to 8B Shown are respectively along Figures 2A to 8A Cross-sectional views taken along line AA', line BB' and line CC'.

[0053] Reference Figure 2A and Figure 2B, a substrate 1 can be prepared. The substrate 1 can be, for example, a single crystal silicon (Si) wafer or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate 1 can be a silicon substrate including silicon (Si) (for example, single crystal silicon (Si), polycrystalline silicon (Si), amorphous silicon (Si), or a combination thereof), and / or can include other materials such as silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide (InSb), lead telluride (PbTe), gallium phosphide (GaP), indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs), or gallium antimonide (GaSb). The substrate 1 can include a separation mask opening region SMR, a first contact region CR1, and a second contact region CR2. The separation mask opening region SMR may include a first overlapping region OR1 and a second overlapping region OR2 overlapping the first and second contact regions CR1 and CR2, respectively; a first separation region SR1 and a second separation region SR2 adjacent to the first overlapping region OR1 and the second overlapping region OR2, respectively; and an intermediate region MR located between the first separation region SR1 and the second separation region SR2. The substrate 1 may be etched to form the first and second active fins AF1 and AF2. A device isolation layer 3 may be formed on the substrate 1 and etched to have a top surface lower than the top surfaces of the first and second active fins AF1 and AF2. Thus, the device isolation layer 3 may cover the top surface of the substrate 1 and the underside surfaces of the first and second active fins AF1 and AF2, and may therefore surround and define the first and second active fins AF1 and AF2. When viewed in plan, each of the first and second active fins AF1 and AF2 may be formed to have a linear shape extending in the first direction x. The separation mask opening region SMR may be located between the first and second active fins AF1 and AF2. Each of the first and second contact regions CR1 and CR2 may have a bar shape extending in the second direction y and may cross the first and second active fins AF1 and AF2.

[0054] Reference Figure 3A and Figure 3BA dielectric layer, a conductive layer, and a capping layer may be sequentially formed on a substrate 1 and then patterned to form dummy gate patterns DGP0, DGP1, DGP2, and DGP3. Each of the dummy gate patterns DGP0, DGP1, DGP2, and DGP3 includes a dummy gate dielectric layer DGO, a dummy gate electrode DG, and a dummy gate capping pattern DCP stacked sequentially. Each of the dummy gate patterns DGP0, DGP1, DGP2, and DGP3 may have a straight line shape extending in a second direction y to span the first active fin AF1 and the second active fin AF2. The dummy gate dielectric layer DGO may include, for example, a silicon oxide (SiO2) layer. The dummy gate electrode DG may include, for example, a polycrystalline silicon (p-Si) layer. The dummy gate capping pattern DCP may include, for example, a silicon nitride (Si3N4) layer. Spacers SC may be formed to cover the corresponding sidewalls of the dummy gate patterns DGP0, DGP1, DGP2, and DGP3. Each spacer SC may have a single-layer or multi-layer structure including one or more selected from, for example, a silicon oxide (SiO2) layer, a silicon nitride (Si3N4) layer, and a silicon oxynitride (SiON) layer. The first active fin AF1 and the second active fin AF2 may be exposed at their top surfaces and upper sidewalls on the sides of the spacer SC between the dummy gate patterns DGP0, DGP1, DGP2, and DGP3. The dummy gate patterns DGP0, DGP1, DGP2, and DGP3 may intersect the first active fin AF1 and the second active fin AF2 to cover the top surfaces and upper sidewalls of the first active fin AF1 and the second active fin AF2.

[0055] Reference Figure 4A and Figure 4B, upper portions of the first and second active fins AF1 and AF2 exposed between the dummy gate patterns DGP0, DGP1, DGP2, and DGP3 may be removed to reduce the height of the top surfaces of the first and second active fins AF1 and AF2. The first and second active fins AF1 and AF2 may thus have top surfaces located at a height similar to that of the top surface of the device isolation layer 3. A selective epitaxial growth (SEG) process may be performed to form first and second source / drain patterns SD1 and SD2 on the first and second active fins AF1 and AF2, respectively. The first and second source / drain patterns SD1 and SD2 may have pentagonal shapes, but the present inventive concept is not limited thereto. The first and second source / drain patterns SD1 and SD2 may each include a semiconductor material selected from, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), and the like. The first source / drain pattern SD1 and the second source / drain pattern SD2 may be doped with impurities having the same or different conductivity types. For example, during the SEG process, the first source / drain pattern SD1 and the second source / drain pattern SD2 may be doped with n-type impurities or p-type impurities, or may be doped with n-type impurities or p-type impurities, respectively, through an ion implantation process. A first interlayer dielectric layer IL1 may be formed on the substrate 1, and a chemical mechanical polishing (CMP) process or an etch-back process may be performed to expose the top surfaces of the dummy gate patterns DGP0, DGP1, DGP2, and DGP3. The first interlayer dielectric layer IL1 may thus have a top surface coplanar with the top surfaces of the dummy gate patterns DGP0, DGP1, DGP2, and DGP3. The dummy gate patterns DGP0, DGP1, DGP2, and DGP3 may be divided into a zeroth dummy gate pattern DGP0, a first dummy gate pattern DGP1, a second dummy gate pattern DGP2, and a third dummy gate pattern DGP3.

[0056] Reference Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B, the dummy gate patterns DGP0, DGP1, DGP2 and DGP3 can be removed to expose the inner sidewalls of the spacers SC, the device isolation layer 3 located between the exposed inner sidewalls of the spacers SC, and the top surface and upper sidewalls of the active fins AF1 and AF2 located between the exposed inner sidewalls of the spacers SC. A dielectric layer can be conformally formed on the substrate 1 so that the dielectric layer can cover the inner sidewalls of the spacers SC, the device isolation layer 3 located between the exposed sidewalls of the spacers SC, and the top surface and upper sidewalls of the active fins AF1 and AF2 located between the exposed sidewalls of the spacers SC. A conductive layer can be formed to fill the space between the spacers SC, after which an etch-back process can be performed on the conductive layer and the dielectric layer. Therefore, a gate dielectric layer GO and a gate electrode MG can be formed between the spacers SC. A gate cap layer can be formed, and then an etch-back process can be performed to form a gate cap pattern CAP on the gate dielectric layer GO and the gate electrode MG. The materials used to form the gate cap pattern CAP, the gate dielectric layer GO and the gate electrode MG can be the same as those described above with reference to Figures 1A to 1C The materials described are the same. Therefore, the zeroth dummy gate pattern DGP0 can be changed to the zeroth gate pattern GP0, and the third dummy gate pattern DGP3 can be changed to the fifth gate pattern GP5. The first dummy gate pattern DGP1 can be changed to the first initial gate pattern PGP1, and the second dummy gate pattern DGP2 can be changed to the second initial gate pattern PGP2. The zeroth gate pattern GP0, the first initial gate pattern PGP1, the second initial gate pattern PGP2, and the fifth gate pattern GP5 can have the same structure.

[0057] Reference Figure 5A 、 Figure 5B 、 Figure 6A and Figure 6B , a separation mask pattern SM may be formed on the first interlayer dielectric layer IL1. The separation mask pattern SM may be formed by a photolithography process. The separation mask pattern SM may include a separation mask opening SMO. The separation mask opening SMO may be positioned to coincide with the separation mask opening region SMR.

[0058] The separation mask opening SMO may be formed to span the first and second preliminary gate patterns PGP1 and PGP2. The separation mask opening SMO may expose the first and second preliminary gate patterns PGP1 and PGP2 located on the first and second separation regions SR1 and SR2, and may also expose a portion of the first interlayer dielectric layer IL1 located on sides of the first and second preliminary gate patterns PGP1 and PGP2. The separation mask pattern SM may cover the zeroth gate pattern GP0 and the fifth gate pattern GP5.

[0059] An etching process such as isotropic / anisotropic etching can be performed to remove the first initial gate pattern PGP1 and the second initial gate pattern PGP2 exposed to the separation mask opening SMO. In this case, the first interlayer dielectric layer IL1 can also be partially etched. Since the zeroth gate pattern GP0 and the fifth gate pattern GP5 are covered by the separation mask pattern SM, they may not be etched during the etching process. Therefore, a separation trench ST can be formed to expose the device isolation layer 3 located on the first separation region SR1 and the second separation region SR2. The first interlayer dielectric layer IL1 may partially remain on the first and second overlapping regions OR1 and OR2 and the intermediate region MR. For example, the portions of the first initial gate pattern PGP1 and the second initial gate pattern PGP2 located on the first and second separation regions SR1 and SR2 may be completely removed. Due to differences in etching rates, the first interlayer dielectric layer IL1 located on the first and second overlapping regions OR1 and OR2 and the intermediate region MR may not be completely etched. The bottom surface of the separation trench ST may have an uneven structure. The separation trench ST may have sidewalls of the zeroth gate pattern GP0 and the fifth gate pattern GP5 that are not exposed but covered by a portion of the first interlayer dielectric layer IL1. The portion of the first interlayer dielectric layer IL1 that covers the sidewalls of the zeroth gate pattern GP0 and the fifth gate pattern GP5 may be located at an area that is not exposed by the separation mask opening SMO and thus may not be etched during the formation of the separation trench ST.

[0060] Because the first and second preliminary gate patterns PGP1 and PGP2 are removed from the first and second separation regions SR1 and SR2, the first preliminary gate pattern PGP1 can be divided into the first and second gate patterns GP1 and GP2 separated from each other in the second direction y, and the second preliminary gate pattern PGP2 can be divided into the third and fourth gate patterns GP3 and GP4 separated from each other in the second direction y. The separation mask pattern SM can be removed to expose the first interlayer dielectric layer IL1. For example, a gate cutting process can be applied here to separate the first preliminary gate pattern PGP1 into the first and second gate patterns GP1 and GP2, and to separate the second preliminary gate pattern PGP2 into the third and fourth gate patterns GP3 and GP4.

[0061] Taking into account the process margin caused by misalignment, the separation mask opening SMO can be formed not only in the first separation region SR1 and the second separation region SR2, but also in the first and second overlapping regions OR1 and OR2 and the middle region MR. Even with a slight misalignment, the first and second initial gate patterns PGP1 and PGP2 can be exposed on the first separation region SR1 and the second separation region SR2 of the substrate 1. For example, the first and second initial gate patterns PGP1 and PGP2 can be completely removed to the extent that the device isolation layer 3 in the separation trench ST is reached. Therefore, the first and second gate patterns GP1 and GP2 can be completely separated by the separation trench ST in the first separation region SR1. In addition, the third and fourth gate patterns GP3 and GP4 can be completely separated by the separation trench ST in the second separation region SR2. As a result, gate bridges at locations where the first and second gate patterns GP1 and GP2 are partially connected to each other, or where the third and fourth gate patterns GP3 and GP4 are partially connected to each other, can be prevented.

[0062] Reference Figure 7A and Figure 7B , a dielectric layer may be formed on the substrate 1 to fill the separation trench ST, and then an etch-back process may be performed to form a separation pattern SP in the separation trench ST while exposing the top surface of the first interlayer dielectric layer IL1. Thus, the separation pattern SP may have a top surface coplanar with the top surface of the first interlayer dielectric layer IL1. The bottom surface of the separation pattern SP may have an uneven structure and may contact the device isolation layer 3 located on the first separation region SR1 and the second separation region SR2 of the substrate 1. The separation pattern SP may be formed of a material having an etching selectivity relative to the material of the first interlayer dielectric layer IL1, such as silicon nitride (Si3N4).

[0063] Reference Figure 8A and Figure 8B, a second interlayer dielectric layer IL2 may be formed on the substrate 1 having the separation pattern SP formed thereon. The second interlayer dielectric layer IL2 may include a material having an etching selectivity relative to the material of the separation pattern SP (such as silicon oxide (SiO2)). A mask pattern may be separately formed on the second interlayer dielectric layer IL2, and the second interlayer dielectric layer IL2 may be etched using the mask pattern. At least a portion of the separation pattern SP may be removed from the first overlapping region OR1 and the second overlapping region OR2, so that a first recess RC1 and a second recess RC2 may be formed on the separation pattern SP. The separation pattern SP may partially remain on the bottom surface of the first recess RC1 and the second recess RC2. A buried dielectric layer may be formed to fill the first recess RC1 and the second recess RC2, and then an etch-back process may be performed to expose the top surface of the second interlayer dielectric layer IL2 and simultaneously form a buried dielectric pattern FL in the first recess RC1 and the second recess RC2. The buried dielectric pattern FL may be formed of a material that is the same as or similar to that of the first interlayer dielectric layer IL1 , such as silicon oxide (SiO 2 ).

[0064] Mask patterns may be formed on the second interlayer dielectric layer IL2 and the buried dielectric pattern FL, respectively, and the mask patterns may be used to etch the buried dielectric pattern FL and the first interlayer dielectric layer IL1. Figure 1A and Figure 1B , on the first overlapping region OR1 and the second overlapping region OR2, the buried dielectric pattern FL and the first interlayer dielectric layer IL1 may be etched to form contact holes CH. In this case, the upper portions of the source / drain patterns SD1 and SD2 may also be removed. A conductive layer may be formed on the entire surface of the substrate 1 to fill the contact holes CH, and then an etch-back process or a chemical mechanical polishing (CMP) process may be performed to form contact plugs CT1 and CT2. Thus, a structure such as Figure 1A and Figure 1B The semiconductor device shown in .

[0065] In a method of manufacturing a semiconductor device according to an example embodiment of the present inventive concept, at least a portion of the separation pattern SP may be removed in advance to form the recesses RC1 and RC2 on the overlapping regions OR1 and OR2, and the recesses RC1 and RC2 may be filled with a buried dielectric pattern FL including a material that is the same as or similar to that of the first interlayer dielectric layer IL1, which may solve problems associated with etching difficulties in forming the contact holes CH.

[0066] If at least a portion of the separation pattern SP is not removed from the overlapping regions OR1 and OR2 beforehand, the separation pattern SP may remain on the overlapping regions OR1 and OR2 when the contact hole CH is formed. As a result, both contact plugs CT1 and CT2 may be disconnected. In this case, each of the contact plugs CT1 and CT2 may not connect to the first source / drain pattern SD1 and the second source / drain pattern SD2, which may lead to process defects such as contact connection failure. In contrast, according to the present inventive concept, at least a portion of the separation pattern SP is removed from the overlapping regions OR1 and OR2 beforehand, thereby avoiding this problem and improving production yield. However, if the portion of the separation pattern SP removed from the overlapping regions OR1 and OR2 is too small, each of the contact plugs CT1 and CT2 may not connect to, or may only weakly connect to, the first source / drain pattern SD1 and the second source / drain pattern SD2. It is desirable to remove a sufficient amount of the separation pattern SP from the overlapping regions OR1 and OR2 to improve production yield. For example, in an exemplary embodiment of the present inventive concept, the separation pattern SP may be removed from the first and second overlapped regions OR1 and OR2 to such an extent that at least the lowermost portions of the first and second recesses RC1 and RC2 are lower than the uppermost portions of the first and second source / drain patterns SD1 and SD2. Therefore, even if some portions of the separation pattern SP remain on the first and second overlapped regions OR1 and OR2, the first and second contact plugs CT1 and CT2 formed in the contact holes CH including the upper portions of the removed source / drain patterns SD1 and SD2 may both be connected to the first and second source / drain patterns SD1 and SD2. Therefore, contact connection failures on the overlapped regions OR1 and OR2 may be prevented, and the reliability of the semiconductor device may be improved.

[0067] Figure 9A A plan view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated. Figure 9B FIG. 1 shows an exemplary embodiment of the present invention. Figure 9A Cross-sectional views taken along line AA', line BB' and line CC'.

[0068] Reference Figure 9A and Figure 9B , the semiconductor device according to the present example embodiment may be constructed so that the separation pattern SP may not include Figure 1A and Figure 1B. For example, in the process of forming the first recess RC1 and the second recess RC2, the separation pattern SP may not remain on the bottom surface of the first recess RC1 and the second recess RC2, or in the process of forming the contact hole CH, the first protrusion segment P1 and the third protrusion segment P3 may be removed. The separation pattern SP may include a first separation segment S1, a second separation segment S2, and a second protrusion segment P2 connecting the first separation segment S1 and the second separation segment S2. The first separation segment S1 and the second separation segment S2 may have their bottom surfaces in direct contact with the device isolation layer 3. Therefore, no gate bridge is formed on the separation regions SR1 and SR2. The contact plugs CT1 and CT2 may have their bottom surfaces in direct contact with the first interlayer dielectric layer IL1. The separation pattern SP may not exist on the overlapping regions OR1 and OR2 of the substrate 1. As shown along Figure 9B As shown in the cross-sectional view taken along line CC' of FIG, the bottom surface of the first contact plug CT1 may have an uneven structure. For example, a portion of the first contact plug CT1 may protrude downward between the first source / drain pattern SD1 and the second source / drain pattern SD2. The bottom surface of the second contact plug CT2 may also have an uneven structure. The lowest end of the bottom surface of the first contact plug CT1 may have a height H2 that is the same as the height H1 of the bottom surface of the second protruding section P2, wherein the heights H1 and H2 are measured from the top surface of the substrate 1 in the third direction z. Other configurations may be the same as those in reference to FIG. Figures 1A to 1C The constructions in question are the same or similar.

[0069] It can be achieved by Figure 8A and Figure 8B When the separation pattern SP is etched as shown in FIG, the separation pattern SP is completely removed from the overlapping regions OR1 and OR2, and then subsequent processes are performed to manufacture Figure 9A and Figure 9B The semiconductor device is formed. Furthermore, the contact hole CH may be formed to have a curved bottom surface due to the etch rate difference between the first interlayer dielectric layer IL1 and the source / drain patterns SD1 and SD2. Therefore, the first contact plug CT1 may be modified in shape. With this modified shape, the first contact plug CT1 may have a larger contact area with the source / drain patterns SD1 and SD2, and thus may be less likely to have a contact connection failure. Other process steps may be the same or similar to those discussed above.

[0070] Figure 10 FIG. 1 shows an exemplary embodiment of the present invention. Figure 9A Cross-sectional views taken along line AA', line BB' and line CC'.

[0071] Reference Figure 9A and Figure 10, the semiconductor device according to this example embodiment may not include Figure 1A and Figure 1B The first protruding segment P1 and the third protruding segment P3 shown in FIG. The buried dielectric pattern FL may remain below the contact plugs CT1 and CT2 located on the overlapping regions OR1 and OR2. The buried dielectric pattern FL may be in direct contact with the bottom surfaces of the contact plugs CT1 and CT2. Other configurations may be similar to those of FIG. Figures 1A to 1C The constructions in question are the same or similar.

[0072] It can be achieved by Figure 8A and Figure 8B When the separation pattern SP is etched as shown in FIG, the separation pattern SP is completely removed from the overlapping regions OR1 and OR2, the buried dielectric pattern FL is partially retained on the bottom surface of the contact hole CH when the contact hole CH is formed, and then subsequent processes are performed to manufacture Figure 10 The semiconductor device is fabricated using a semiconductor device. Other process steps may be the same or similar to those discussed above. Through the above process, a first interlayer dielectric layer IL1 may be disposed between the first contact plug CT1 located above the substrate 1 and the device isolation layer 3, between the second contact plug CT2 located above the substrate 1 and the device isolation layer 3, and between the second protruding segment P2 located above the substrate 1 and the device isolation layer 3. A different interlayer dielectric layer may be formed in place of the first interlayer dielectric layer IL1 in these areas. In an exemplary embodiment of the present inventive concept, the second protruding segment P2 may be adjacent to one sidewall of the first gate pattern GP1, the first contact plug CT1 may be adjacent to the other sidewall of the first gate pattern GP1 and spaced apart from the second protruding segment P2. A third interlayer dielectric layer may be disposed between the second protruding segment P2 and the substrate 1 and between the first contact plug CT1 and the substrate 1. A buried dielectric pattern FL may be disposed between the first contact plug CT1 and the third interlayer dielectric layer, wherein the bottom surface of the buried dielectric pattern FL may be located at the same height as the bottom surface of the second protruding segment P2. The third interlayer dielectric layer may be replaced by the first interlayer dielectric layer IL1 or may include a material different from that of the first interlayer dielectric layer IL1.

[0073] The following describes the production Figure 9B or Figure 10 Method for a semiconductor device.

[0074] Figures 11A to 11E Shows the display manufacturing Figure 9B or Figure 10 A cross-sectional view of a method for manufacturing a semiconductor device.

[0075] Reference Figure 11A , you can Figure 6BA sacrificial layer 20 is formed on the entire surface of the substrate 1 in a state of being formed, and as a result, the sacrificial layer 20 can fill the separation trench ST. The sacrificial layer 20 can be, for example, a spin-on hard mask (SOH) layer or a spin-on carbon (SOC) layer. A first mask pattern 22 can be formed on the sacrificial layer 20, and the first mask pattern 22 can have an opening 22o overlapping the overlapping regions OR1 and OR2.

[0076] Reference Figure 11B The first mask pattern 22 may be used as an etching mask to etch the sacrificial layer 20 so that the sacrificial layer 20 may be removed from the overlapping regions OR1 and OR2 and a sacrificial pattern 20a may be formed. In the separation trench ST, the sacrificial pattern 20a may be located on the separation regions SR1 and SR2 and the middle region MR.

[0077] Reference Figure 11B and Figure 11C , a buried dielectric layer may be formed on the entire surface of the substrate 1, so that the buried dielectric layer may fill the area of ​​the separation trench ST where the sacrificial pattern 20a is not present. A chemical mechanical polishing (CMP) process or an etch-back process may be performed to remove the sacrificial pattern 20a, the first mask pattern 22, and the buried dielectric layer located above the separation mask pattern SM. In this case, the reduced sacrificial pattern 20a may remain in the separation trench ST, and a buried dielectric pattern FL may be formed in the separation trench ST. In the separation trench ST, the buried dielectric pattern FL may be disposed on the overlapping regions OR1 and OR2, and the sacrificial pattern 20a may be disposed on the separation regions SR1 and SR2 and the middle region MR.

[0078] Reference Figure 11C and Figure 11D , the sacrificial pattern 20a can be removed from the separation trench ST. For example, the sacrificial pattern 20a can include a spin-on hard mask (SOH) layer or a spin-on carbon (SOC) layer and can be easily removed by oxygen etching or any other suitable etching process. Therefore, the device isolation layer 3 can be exposed on the separation regions SR1 and SR2, and the first interlayer dielectric layer IL1 can be exposed on the middle region MR. The second trench ST2 can be defined as the area where the sacrificial pattern 20a is removed.

[0079] Reference Figure 11D and Figure 11E , a dielectric layer may be formed on the substrate 1 to fill the second separation trenches ST2 , and then an etch-back process may be performed to form separation patterns SP in the second separation trenches ST2 .

[0080] The separation mask pattern SM may become the second interlayer dielectric layer (see Figure 8B IL2). Then, refer to Figure 9B, the buried dielectric pattern FL and the first interlayer dielectric layer IL1 may be etched to form contact holes CH, and the contact holes CH may be filled with a conductive layer to form contact plugs CT1 and CT2. Finally, Figure 9B When the buried dielectric pattern FL is partially retained during the formation of the contact hole CH and then subsequent processes are performed, a semiconductor device can be manufactured. Figure 10 The other process steps may be the same or similar to the process steps discussed above. Figures 11A to 11E The described process can be provided by using a large etching difference between a carbon-rich spin-on hard mask (SOH) material (or a spin-on carbon (SOC) material) for the sacrificial pattern 20a and a silicon oxide (SiO2) material for the buried dielectric pattern FL. Figure 9B or Figure 10 An alternative method for a semiconductor device.

[0081] Figure 12A A plan view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated.

[0082] Figure 12B FIG. 1 shows an exemplary embodiment of the present invention. Figure 12A Cross-sectional views taken along line AA', line BB' and line CC'.

[0083] Reference Figure 12A and Figure 12B , the semiconductor device according to the present example embodiment may be constructed such that the substrate 1 may include a third contact region CR3 disposed between the first contact region CR1 and the second contact region CR2 and separated from the first contact region CR1 and the second contact region CR2. The separation mask opening region SMR may intersect with all of the first contact region CR1, the second contact region CR2, and the third contact region CR3. Therefore, the separation mask opening region SMR may include a third overlapping region OR3 in addition to the first overlapping region OR1 and the second overlapping region OR2. The third overlapping region OR3 may be located between the first overlapping region OR1 and the second overlapping region OR2. The first separation region SR1 may be located between the first overlapping region OR1 and the third overlapping region OR3. The second separation region SR2 may be located between the second overlapping region OR2 and the third overlapping region OR3. The third overlapping region OR3 may be located Figure 1B For example, you can use Figure 12B The third overlapping region OR3 in the Figure 1B The middle region MR.

[0084] The separation pattern SP may include a first protruding segment P1, a second protruding segment P2, and a third protruding segment P3, and may further include a first separation segment S1 and a second separation segment S2 located between the first protruding segment P1, the second protruding segment P2, and the third protruding segment P3. The first protruding segment P1, the second protruding segment P2, and the third protruding segment P3 may have the same thickness and height. For example, the second protruding segment P2 may extend laterally from the first separation segment S1 in a direction away from the first protruding segment P1, the top surface of the second protruding segment P2 may be coplanar with the top surface of the first protruding segment P1, and the bottom surface of the second protruding segment P2 may be higher than the bottom surface of the first separation segment S1. For example, the third protruding segment P3 may extend from the second separation segment S2 in a direction away from the second protruding segment P2, and the third protruding segment P3 may have the same thickness as the first protruding segment P1. The first protruding segment P1, the second protruding segment P2, and the third protruding segment P3 may be thinner than the first separation segment S1 and the second separation segment S2. The semiconductor device may further include a third contact plug CT3 located between the first separation segment S1 and the second separation segment S2. The first protruding section P1, the second protruding section P2, and the third protruding section P3 may be in contact with the bottom surfaces of the first contact plug CT1, the third contact plug CT3, and the second contact plug CT2, respectively. Figures 1A to 1C The described constructions are the same or similar.

[0085] Figure 12A and Figure 12B The manufacture of the semiconductor device shown in FIG. 1 may include the following steps: Figure 8B When the first recess RC1 and the second recess RC2 are formed as shown in FIG, a third recess is formed by etching the separation pattern SP located on the middle region MR, performing subsequent processes, and Figure 1B The third contact plug CT3 is formed on the middle region MR of the Figure 12B The third contact plug CT3 is formed on the third overlapping region OR3. Figure 1A and Figure 1B, no gate bridge is formed between the first gate pattern GP1 and the second gate pattern GP2 located on the first separation region SR1, and between the third gate pattern GP3 and the fourth gate pattern GP4 located on the second separation region SR2. The first contact plug CT1, the second contact plug CT2, and the third contact plug CT3 located on the first overlapped region OR1, the second overlapped region OR2, and the third overlapped region OR3, respectively, can all be connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 without any fault. For example, the first contact plug CT1, the second contact plug CT2, and the third contact plug CT3 formed on the first contact region CR1, the second contact region CR2, and the third contact region CR3 (and each of the first contact plug CT1, the second contact plug CT2, and the third contact plug CT3 connects the first source / drain pattern SD1 and the second source / drain pattern SD2) do not have any connection faults on the first overlapped region OR1, the second overlapped region OR2, and the third overlapped region OR3, respectively.

[0086] Figure 13A A plan view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated. Figure 13B FIG. 1 shows an exemplary embodiment of the present invention. Figure 13A Cross-sectional views taken along line AA', line BB' and line CC'.

[0087] Reference Figure 13A and Figure 13B The semiconductor device according to the present example embodiment may be configured such that the separation pattern SP may include a first separation pattern SP1 and a second separation pattern SP2 that are separated from each other. The first separation pattern SP1 may be disposed on the first separation region SR1 and interposed between the first gate pattern GP1 and the second gate pattern GP2. The second separation pattern SP2 may be disposed on the second separation region SR2 and interposed between the third gate pattern GP3 and the fourth gate pattern GP4. Figure 12B The first protruding segment P1, the second protruding segment P2 and the third protruding segment P3 may not exist on the first overlapping region OR1, the second overlapping region OR2 and the third overlapping region OR3. Figure 12A and Figure 12B The constructs discussed are identical or similar.

[0088] Figure 13A and Figure 13B The semiconductor device shown in FIG. 1 can be manufactured similarly to Figure 12A and Figure 12B For example, Figure 13A and Figure 13B The manufacture of the semiconductor device shown in FIG. 1 may include the following steps: Figure 8BWhen the first recess RC1 and the second recess RC2 are formed as shown in FIG, the third recess is formed together with the first recess RC1 and the second recess RC2 by completely removing the separation pattern SP from the first overlapping region OR1, the second overlapping region OR2, and the third overlapping region OR3 so as not to leave the first protruding segment P1, the second protruding segment P2, and the third protruding segment P3, and then subsequent processes are performed. Figure 12A and Figure 12B No gate bridge is formed between the first gate pattern GP1 and the second gate pattern GP2 located on the first separation region SR1, and between the third gate pattern GP3 and the fourth gate pattern GP4 located on the second separation region SR2. The first contact plug CT1, the second contact plug CT2, and the third contact plug CT3 located on the first overlapped region OR1, the second overlapped region OR2, and the third overlapped region OR3, respectively, can be connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 without any malfunction.

[0089] Figure 14 FIG. 1 shows an exemplary embodiment of the present invention. Figure 13A Cross-sectional views taken along line AA', line BB' and line CC'.

[0090] Reference Figure 13A and Figure 14 , the semiconductor device according to the present example embodiment may further include buried dielectric patterns FL contacting the bottom surfaces of the corresponding first contact plugs CT1, second contact plugs CT2, and third contact plugs CT3. Other configurations may be similar to those described with reference to FIG. Figure 13B For example, the separation pattern SP may include a first separation pattern SP1 and a second separation pattern SP2 separated from each other, and the first protruding segment P1, the second protruding segment P2, and the third protruding segment P3 may not exist on the first overlapping region OR1, the second overlapping region OR2, and the third overlapping region OR3. Figure 14 The semiconductor device shown in FIG. 1 can be manufactured similarly to Figure 10 Therefore, similar to the manufacturing of the semiconductor device shown in Figure 13A and Figure 13B , no gate bridge is formed between the first gate pattern GP1 and the second gate pattern GP2 located on the first separation region SR1, and between the third gate pattern GP3 and the fourth gate pattern GP4 located on the second separation region SR2. The first contact plug CT1, the second contact plug CT2, and the third contact plug CT3 on the first overlapped region OR1, the second overlapped region OR2, and the third overlapped region OR3, respectively, can be connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 without any malfunction.

[0091] Figure 15AA plan view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated. Figure 15B FIG. 1 shows an exemplary embodiment of the present invention. Figure 15A Cross-sectional views taken along line AA', line BB' and line CC'.

[0092] Reference Figure 15A and Figure 15B , the semiconductor device according to the present example embodiment may be configured such that the substrate 1 may not include Figure 12A and Figure 12B In addition, the semiconductor device may not include the second contact region CR2. Figure 12A and Figure 12B The second contact plug CT2 is formed. Figure 12A and Figure 12B The second overlapping region OR2 can be Figure 15A and Figure 15B The separation pattern SP may include a third protruding segment P3 located on the edge region ER, and the third protruding segment P3 may have a top surface coplanar with the top surfaces of the first separation segment S1 and the second separation segment S2. The third protruding segment P3 may be thicker than the first protruding segment P1 and the second protruding segment P2. Other configurations may be the same as those in reference Figure 12A and Figure 12B The construction in question is the same or similar. Therefore, similar to Figure 12A and Figure 12B , no gate bridge is formed between the first gate pattern GP1 and the second gate pattern GP2 located on the first separation region SR1 and between the third gate pattern GP3 and the fourth gate pattern GP4 located on the second separation region SR2. The first contact plug CT1 and the third contact plug CT3 on the first overlapped region OR1 and the third overlapped region OR3, respectively, can be connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 without any malfunction.

[0093] Figure 16A A plan view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated. Figure 16B FIG. 1 shows an exemplary embodiment of the present invention. Figure 16A Cross-sectional views taken along line AA', line BB' and line CC'.

[0094] Reference Figure 16A and Figure 16B, the semiconductor device according to the present example embodiment may be constructed such that the separation pattern SP may include a first separation pattern SP1 and a second separation pattern SP2 separated from each other. The first separation pattern SP1 may be disposed on the first separation region SR1 and interposed between the first gate pattern GP1 and the second gate pattern GP2. The second separation pattern SP2 may include a second separation segment S2 disposed on the second separation region SR2, and further include a third protruding segment P3 disposed on the edge region ER and connected to the second separation segment S2. The first contact plug CT1 and the third contact plug CT3 may have their bottom surfaces in direct contact with the first interlayer dielectric layer IL1. The separation pattern SP may not include Figure 15A and Figure 15B The first protruding section P1 and the second protruding section P2 shown in FIG. Other configurations can be compared with those in FIG. Figure 15A and Figure 15B The construction in question is the same or similar. Therefore, similar to Figure 15A and Figure 15B , no gate bridge is formed between the first gate pattern GP1 and the second gate pattern GP2 located on the first separation region SR1 and between the third gate pattern GP3 and the fourth gate pattern GP4 located on the second separation region SR2. The first contact plug CT1 and the third contact plug CT3 located on the first overlapped region OR1 and the third overlapped region OR3, respectively, can be connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 without any malfunction.

[0095] Figure 17 FIG. 1 shows an exemplary embodiment of the present invention. Figure 16A Cross-sectional views taken along line AA', line BB' and line CC'.

[0096] Reference Figure 17 , the first contact plug CT1 and the third contact plug CT3 may have their bottom surfaces in direct contact with the buried dielectric pattern FL. The buried dielectric patterns FL on the first overlapping region OR1 and the third overlapping region OR3 may have their bottom surfaces located at the same height as the bottom surface of the third protruding segment P3 of the second separation pattern SP2 on the edge region ER. Other configurations may be the same as those in reference Figure 16B The construction in question is the same or similar. Therefore, similar to Figure 16A and Figure 16B, no gate bridge is formed between the first gate pattern GP1 and the second gate pattern GP2 located on the first separation region SR1 and between the third gate pattern GP3 and the fourth gate pattern GP4 located on the second separation region SR2. The first contact plug CT1 and the third contact plug CT3 located on the first overlapped region OR1 and the third overlapped region OR3, respectively, can be connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 without any malfunction.

[0097] Figure 18A A plan view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated. Figure 18B FIG. 1 shows an exemplary embodiment of the present invention. Figure 18A Cross-sectional views taken along line AA', line BB' and line CC'.

[0098] Reference Figure 18A and Figure 18B , the semiconductor device according to the present example embodiment may be configured such that the substrate 1 may not include Figure 15A and Figure 15B In addition, the semiconductor device may not include the third contact region CR3. Figure 15A and Figure 15B The third contact plug CT3 is formed. Figure 15A and Figure 15B The third overlapping region OR3 can be Figure 18A and Figure 18B The separation pattern SP may include a second protruding segment P2 and a third protruding segment P3 located on the middle region MR and the edge region ER, respectively, and the second protruding segment P2 and the third protruding segment P3 may have their top surfaces coplanar with the top surfaces of the first separation segment S1 and the second separation segment S2. The second protruding segment P2 and the third protruding segment P3 may be thicker than the first protruding segment P1. Other configurations may be the same as those in reference Figure 15A and Figure 15B The construction in question is the same or similar. Therefore, similar to Figure 15A and Figure 15B , no gate bridge is formed between the first gate pattern GP1 and the second gate pattern GP2 located on the first separation region SR1 and between the third gate pattern GP3 and the fourth gate pattern GP4 located on the second separation region SR2. The first contact plug CT1 located on the first overlapped region OR1 can be connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 without malfunction.

[0099] Figure 19A A plan view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated. Figure 19B FIG. 1 shows an exemplary embodiment of the present invention. Figure 19A Cross-sectional views taken along line AA', line BB' and line CC'.

[0100] Reference Figure 19A and Figure 19B , the semiconductor device according to the present example embodiment may be configured such that the separation pattern SP may not include Figure 18A and Figure 18B The first contact plug CT1 may have a bottom surface located at the same height as the bottom surfaces of the second and third protruding sections P2 and P3. Other configurations may be the same as those of reference Figure 18A and Figure 18B The construction in question is the same or similar. Therefore, similar to Figure 18A and Figure 18B , no gate bridge is formed between the first gate pattern GP1 and the second gate pattern GP2 located on the first separation region SR1 and between the third gate pattern GP3 and the fourth gate pattern GP4 located on the second separation region SR2. The first contact plug CT1 located on the first overlapped region OR1 can be connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 without malfunction.

[0101] Figure 20 FIG. 1 shows an exemplary embodiment of the present invention. Figure 9A Cross-sectional views taken along line AA', line BB' and line CC'.

[0102] Reference Figure 20 , the remaining sacrificial pattern 20r can be placed Figure 9B The remaining sacrificial pattern 20r may be disposed between the separation pattern SP and the device isolation layer 3. For example, the remaining sacrificial pattern 20r may be disposed between the device isolation layer 3 and the first separation segment S1 of the separation pattern SP, and between the device isolation layer 3 and the second separation segment S2 of the separation pattern SP. The remaining sacrificial pattern 20r may include a material different from that of the separation pattern SP. The remaining sacrificial pattern 20r may include a material having an etching selectivity relative to the separation pattern SP. The remaining sacrificial pattern 20r may include, for example, a spin-on hard mask (SOH) layer or a spin-on carbon (SOC) layer. Therefore, the remaining sacrificial pattern 20r (or sacrificial pattern 20a) may include a material having an etching selectivity relative to the material of the first interlayer dielectric layer IL1.

[0103] The remaining sacrificial pattern 20r may be referred to as an auxiliary separation pattern. For example, the remaining sacrificial pattern 20r may help divide the gate patterns GP1, GP2, GP3, and GP4. Alternatively, the remaining sacrificial pattern 20r and the separation pattern SP may be integrally connected to form a separation pattern as a whole. In this case, the remaining sacrificial pattern 20r may be referred to as a first separation pattern, and the separation pattern SP may be referred to as a second separation pattern. Other configurations may be similar to those described with reference to FIG. Figure 9B The construction in question is the same or similar. Therefore, similar to Figure 9A and Figure 9B , no gate bridge is formed between the first gate pattern GP1 and the second gate pattern GP2 located on the first separation region SR1 and between the third gate pattern GP3 and the fourth gate pattern GP4 located on the second separation region SR2. The first contact plug CT1 and the second contact plug CT2 located on the first overlapped region OR1 and the second overlapped region OR2, respectively, can be connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 without any malfunction.

[0104] Figure 20 The manufacture of a semiconductor device may include the following steps: Figure 11C and Figure 11D When the sacrificial pattern 20a is removed in the step of , a portion of the sacrificial pattern 20a is left to form a residual sacrificial pattern 20r, and subsequent processes are performed. Other process steps may be the same as those in reference Figures 11A to 11E The process steps discussed are the same or similar.

[0105] The remaining sacrificial pattern 20r may be placed Figure 13B 、 Figure 16B and Figure 19B Between the separation pattern SP and the device isolation layer 3 in the example shown in FIG.

[0106] According to the inventive concept, the reliability of a semiconductor device can be improved.

[0107] In a method for manufacturing a semiconductor device according to the present invention, at least a portion of a separation pattern can be removed from an overlapping region in advance, and a buried dielectric pattern can be formed of a material similar to that of an interlayer dielectric layer. Therefore, process defects such as contact connection failure can be prevented. As a result, productivity can be improved.

[0108] Although the present invention has been described in conjunction with some specific example embodiments of the present invention shown in the drawings, it will be understood by those skilled in the art that various changes and modifications may be made to the example embodiments without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A semiconductor device, comprising: a first gate pattern and a second gate pattern spaced apart from each other in a first direction on the substrate, each of the first gate pattern and the second gate pattern extending in the first direction; a separation pattern disposed between the first gate pattern and the second gate pattern and in direct contact with the first gate pattern and the second gate pattern, the separation pattern extending in a second direction intersecting the first direction; a third gate pattern, spaced apart from the first gate pattern in the second direction, the third gate pattern extending in the first direction; as well as an interlayer dielectric layer disposed between the first gate pattern and the third gate pattern, wherein the separation pattern comprises a material different from that of the interlayer dielectric layer, and A bottom surface of the separation pattern has an uneven structure.

2. The semiconductor device according to claim 1, further comprising a contact plug adjacent to one sidewall of the first gate pattern, wherein The contact plug extends in the first direction and is adjacent to the separation pattern, A portion of the separation pattern extends to contact a bottom surface of the contact plug, A bottom surface of the separation pattern has a first depth between the first gate pattern and the second gate pattern, A bottom surface of the separation pattern has a second depth below the contact plug, and The first depth is greater than the second depth.

3. The semiconductor device according to claim 1 , further comprising a contact plug adjacent to one sidewall of the first gate pattern, in, The contact plug extends in the first direction and is adjacent to the separation pattern, and Separation patterns include: a first separation segment disposed between the first gate pattern and the second gate pattern; and The first portion extends from the first separation segment and is located below the contact plug, and the first portion contacts the bottom surface of the contact plug.

4. The semiconductor device according to claim 3, wherein The bottom surface of the first separation section is lower than the bottom surface of the first portion, The top surface of the first separation section is higher than the top surface of the first portion, and The thickness of the first separation section is greater than the thickness of the first portion.

5. The semiconductor device according to claim 3, wherein A sidewall of the first portion is spaced apart from a sidewall of the contact plug, and the sidewall of the first portion is adjacent to the sidewall of the contact plug. The semiconductor device according to claim 3 , wherein: The separation pattern further includes a second portion extending from the first separation segment in a direction away from the first portion, The top surface of the second portion is coplanar with the top surface of the first portion, and The bottom surface of the second portion is higher than the bottom surface of the first separation section. 7 . The semiconductor device according to claim 6 , further comprising a fourth gate pattern spaced apart from the third gate pattern in the first direction, in, The separation pattern further includes a second separation segment contacting the second portion, and the second separation segment is located between the third gate pattern and the fourth gate pattern.

8. The semiconductor device according to claim 7, wherein The top surface of the second separation section is coplanar with the top surface of the first separation section, and The bottom surface of the second separation stage is at the same height as that of the bottom surface of the first separation stage.

9. The semiconductor device according to claim 7, wherein The separation pattern further includes a third portion extending from the second separation segment in a direction away from the second portion, and The third portion has the same thickness as that of the first portion.

10. A semiconductor device, comprising: a first active fin and a second active fin protruding from the substrate and spaced apart from each other; a device isolation layer covering the top surface of the substrate and exposing the top surface and side surfaces of the first active fin and the top surface and side surfaces of the second active fin; a first gate pattern covering a top surface and side surfaces of the first active fin; a second gate pattern spaced apart from the first gate pattern in the first direction and covering a top surface and side surfaces of the second active fin; a first interlayer dielectric layer covering a side surface of the first gate pattern; as well as a first separation pattern, disposed on the device isolation layer between the first gate pattern and the second gate pattern, the first separation pattern being in direct contact with the first gate pattern and the second gate pattern; wherein the first separation pattern comprises a material different from that of the first interlayer dielectric layer, and The first separation pattern includes: a first separation segment disposed between the first gate pattern and the second gate pattern; and a first portion extending from the first separation segment and located outside one sidewall of the first gate pattern. wherein the top surface of the first portion is coplanar with the top surface of the first separation section, and The bottom surface of the first portion is higher than the bottom surface of the first separation section.

11. The semiconductor device according to claim 10, further comprising: a third gate pattern disposed on the substrate and spaced apart from the first gate pattern in a second direction crossing the first direction; as well as a fourth gate pattern, spaced apart from the third gate pattern in the first direction, The first separation pattern further includes a second separation segment contacting the first portion, and the second separation segment is located between the third gate pattern and the fourth gate pattern.

12. The semiconductor device according to claim 11, wherein The top surface of the second separation section is coplanar with the top surface of the first separation section, and The bottom surface of the second separation stage is at the same height as that of the bottom surface of the first separation stage.

13. The semiconductor device according to claim 11, wherein The first separation pattern further includes a second portion extending from the second separation segment in a direction away from the first portion, and The bottom surface of the second portion is higher than the bottom surface of the second separation section.

14. The semiconductor device according to claim 10 , further comprising a contact plug adjacent to the first gate pattern and extending in the first direction, in, The first portion contacts a bottom surface of the contact plug.

15. The semiconductor device according to claim 10, further comprising: a contact plug adjacent to the other sidewall of the first gate pattern and spaced apart from the first portion; a second interlayer dielectric layer disposed between the first portion and the substrate and between the contact plug and the substrate; as well as a buried dielectric pattern disposed between the contact plug and the second interlayer dielectric layer, Wherein, a bottom surface of the buried dielectric pattern is at the same height as a bottom surface of the first portion.

16. The semiconductor device according to claim 10, further comprising: a third gate pattern spaced apart from the first gate pattern in a second direction crossing the first direction; a fourth gate pattern spaced apart from the third gate pattern in the first direction; as well as The second separation pattern is disposed between the third gate pattern and the fourth gate pattern, and the second separation pattern is separated from the first separation pattern.

17. A semiconductor device, comprising: a first gate pattern and a second gate pattern spaced apart from each other in a first direction on the substrate; a first interlayer dielectric layer in contact with a sidewall of the first gate pattern; a separation pattern disposed between the first gate pattern and the second gate pattern and in direct contact with the first gate pattern and the second gate pattern; a first source / drain pattern positioned adjacent to the first gate pattern; a second source / drain pattern positioned adjacent to the second gate pattern; as well as a contact plug directly contacting a top surface of the first source / drain pattern and a top surface of the second source / drain pattern, wherein the separation pattern comprises a material different from that of the first interlayer dielectric layer, The bottom surface of the contact plug has an uneven structure, and The separation pattern includes a first separation segment disposed between the first gate pattern and the second gate pattern; and a first portion extending laterally from the first separation segment and spaced apart from the contact plug.

18. The semiconductor device according to claim 17, wherein A bottom surface of the first portion is at the same height as that of the lowermost end of the contact plug.

19. The semiconductor device according to claim 17, wherein The top surface of the first portion is coplanar with the top surface of the first separation section, and The bottom surface of the first portion is higher than the bottom surface of the first separation section.

20. The semiconductor device according to claim 17, further comprising: The remaining sacrificial pattern is disposed between the separation pattern and the substrate.

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