Light emitting diode element and method of manufacturing the same

Abstract

A light emitting diode element and a manufacturing method thereof are disclosed. The light emitting diode element includes a semiconductor stack, a first current blocking pattern and a second current blocking pattern formed on the semiconductor stack and separated from each other, and a plurality of electrodes formed on the semiconductor stack and electrically connected to the semiconductor stack. One of the plurality of electrodes is located on the first current blocking pattern. The second current blocking pattern does not overlap the plurality of electrodes.

Description

Technical Field

[0001] This invention relates to a light-emitting diode (LED) element and a method for manufacturing the same, and particularly to an LED element having a current blocking pattern and a related manufacturing method. Background Technology

[0002] Light-emitting diodes (LEDs) have excellent characteristics such as low power consumption, low heat generation, long operating life, shock resistance, small size, and fast response speed, making them suitable for various lighting and display applications.

[0003] Traditional LEDs use compound semiconductor materials, generating light by combining holes in P-type semiconductors with electrons in N-type semiconductors to produce photons. In existing LEDs, current crowding is prone to occur near the electrodes. Therefore, some LEDs use a transparent conductive layer and a current-blocking layer to achieve a more even current distribution and improve luminous efficiency. Summary of the Invention

[0004] The present invention discloses a light-emitting diode element, comprising: a semiconductor stack; a first current blocking pattern and a second current blocking pattern formed on the semiconductor stack and separated from each other; and a plurality of electrodes formed on the semiconductor stack and electrically connected to the semiconductor stack; wherein one of the plurality of electrodes is located on the first current blocking pattern; and the second current blocking pattern does not overlap with the plurality of electrodes.

[0005] The present invention discloses a light-emitting diode element, comprising: a substrate including a first edge and a second edge opposite to the first edge; a semiconductor stack located on the substrate; a first current blocking pattern and a second current blocking pattern formed on the semiconductor stack and separated from each other; and an electrode formed on the semiconductor stack and the first current blocking pattern; wherein the first current blocking pattern is aligned with the first edge and the second current blocking pattern is aligned with the second edge.

[0006] The present invention discloses a light-emitting diode element, comprising: a substrate including an upper surface, a first edge and a second edge opposite to the first edge; a semiconductor stack located on the substrate; a current blocking pattern formed on the semiconductor stack and located at the first edge; and an electrode formed on the current blocking pattern; wherein the upper surface includes a surrounding area not covered by the semiconductor stack, and the current blocking pattern covers one sidewall of the semiconductor stack and the surrounding area. Attached Figure Description

[0007] Figure 1This is a top view of an LED element 1 according to an embodiment of the present invention;

[0008] Figure 2 This is a cross-sectional view of LED component 1;

[0009] Figures 3A to 3H This is a cross-sectional schematic diagram of LED component 1 at various manufacturing stages;

[0010] Figures 4A to 4H This is a top view of LED component 1 at various manufacturing stages;

[0011] Figure 5 This is a schematic diagram of LED element 2 according to another embodiment of the present invention;

[0012] Figure 6 The top view of LED element 2 in a wafer WF2 before the cutting and fabrication process has been performed;

[0013] Figure 7 A top view of an LED element 3 in a wafer WF3, according to another embodiment of the present invention, before the cutting and fabrication process has been performed;

[0014] Figure 8A for Figure 7 A cross-sectional view along line segment XX;

[0015] Figure 8B As another embodiment of the present invention Figure 7 A cross-sectional view along line segment XX.

[0016] Symbol Explanation

[0017] LED components 1, 2, and 3

[0018] 10, 10a~10h LED units

[0019] 102 base

[0020] 104 First Semiconductor Layer

[0021] 106 Emissive Layer

[0022] 108 Second Semiconductor Layer

[0023] 112 Transparent conductive layer

[0024] 20, 20' First electrode

[0025] 201, 201' First pad

[0026] 202, 202' First Extension

[0027] 30, 30' Second electrode

[0028] 301, 301' Second pad

[0029] 302, 302' Second Extension

[0030] 36a First solder pad

[0031] 36b Second solder pad

[0032] 50 Insulation Structure

[0033] 501, 502 openings

[0034] 60 Connecting electrodes

[0035] 182 Upper surface

[0036] CB1, CB2, CB3, CB4, CB5, CB6, CB7, CB8, CB9, CB10, CB11, CB12, CBB, CBB1, CBB2, CBB3, CBB4 Current blocking blocks

[0037] CE1, CE2, CE3, CE4, CE5, CE6, CE7, CE8 edge

[0038] CL Pre-cutting line

[0039] MS1, MS2, MS3, MS4, MS5, MS8, MS9 high platform

[0040] SCRB cutting channel

[0041] TRCH trench

[0042] WF1, WF2, WF3 chips Detailed Implementation

[0043] In the following description, exemplary embodiments of the present invention will be illustrated in detail to enable those skilled in the art to fully understand the spirit of the invention. The present invention is not limited to the following embodiments, but may be implemented in other forms. In this specification, some identical symbols denote elements having the same or similar structure, function, or principle, and can be deduced by those skilled in the art from the teachings of this specification. For the sake of brevity, elements with the same symbols will not be repeated.

[0044] Figure 1 This is a top view of a light-emitting diode (LED) element 1 according to an embodiment of the present invention. Figure 2 for Figure 1 A cross-sectional view of LED element 1 along line segment A-A'.

[0045] Please refer to Figure 1 and Figure 2 The LED element 1 includes a substrate 102 and a plurality of light-emitting diode units (LED units) 10 (10a, 10b) disposed on the substrate 102. Each LED unit 10 includes a first semiconductor layer 104, a light-emitting layer 106, a second semiconductor layer 108, current blocking layers CB1, CB2 and CB3, a transparent conductive layer 112, a first electrode 20, a second electrode 30 and a connecting electrode 60. The connecting electrodes 60 electrically connect the LED units 10 to achieve series and / or parallel connection to form an LED array. The LED unit 10 is connected to an external power supply or external electronic components in a flip-chip manner using pads 36a and 36b.

[0046] Figures 3A to 3H for Figure 2 A cross-sectional schematic diagram of LED element 1 at various manufacturing stages. Figures 4A to 4H for Figure 1 A partial top view of the various manufacturing processes of LED element 1 on a wafer WF1.

[0047] Please see Figure 3A The substrate 102 may be a growth substrate, including a gallium arsenide (GaAs) substrate and a gallium phosphide (GaP) substrate for growing gallium indium phosphide (AlGaInP), or a sapphire (Al2O3) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, and an aluminum nitride (AlN) substrate for growing indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN). In one embodiment, the substrate 102 is a transparent sapphire substrate. The upper surface 182 of the substrate 102 has a patterned structure; in another embodiment, the upper surface 182 of the substrate may also be planar. A first semiconductor layer 104, a light-emitting layer 106, and a second semiconductor layer 108 are sequentially stacked on the upper surface 182 of the substrate 102 to form a semiconductor stack. For example, in one embodiment of the present invention, a semiconductor stack can be formed on the substrate 102 by means of metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE) or ion plating, such as sputtering or evaporation.

[0048] In one embodiment, the semiconductor stack may further include a buffer structure (not shown) located between the first semiconductor layer 104 and the substrate 102. The buffer structure can reduce the aforementioned lattice mismatch and suppress dislocations, thereby improving epitaxial quality. The material of the buffer layer includes semiconductor materials, such as III-V group semiconductor materials GaN, AlGaN, or AlN. In one embodiment, the buffer structure includes multiple sublayers (not shown). The sublayers may include the same material or different materials. In one embodiment, the buffer structure includes two sublayers, wherein the first sublayer is grown by sputtering and the second sublayer is grown by MOCVD. In one embodiment, the buffer layer further includes a third sublayer. The third sublayer is grown by MOCVD, and the growth temperature of the second sublayer is higher or lower than the growth temperature of the third sublayer. In one embodiment, the first, second, and third sublayers include the same material, such as AlN. In one embodiment of the present invention, the first semiconductor layer 104 and the second semiconductor layer 108, for example, a cladding layer or a confinement layer, have different conductivity types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer 104 is an n-type semiconductor, and the second semiconductor layer 108 is a p-type semiconductor. A light-emitting layer 106 is formed between the first semiconductor layer 104 and the second semiconductor layer 108. Electrons and holes combine in the light-emitting layer 106 under the drive of an electric current, converting electrical energy into light energy to emit light. The wavelength of the light emitted by the LED element 1 or the semiconductor stack can be adjusted by changing the physical properties and chemical composition of one or more layers in the semiconductor stack.

[0049] The materials of the semiconductor stack include Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y)P is a group III-V semiconductor material, where 0≤x, y≤1; x+y≤1. Depending on the material of the light-emitting layer, when the semiconductor stack material is of the AlInGaP series, it can emit red light with wavelengths between 610nm and 650nm or yellow light with wavelengths between 550nm and 570nm. When the semiconductor stack material is of the InGaN series, it can emit blue or deep blue light with wavelengths between 400nm and 490nm or green light with wavelengths between 490nm and 550nm. When the semiconductor stack material is of the AlGaN series, it can emit UV light with wavelengths between 400nm and 250nm. The light-emitting layer 106 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). The material of the light-emitting layer 106 can be an i-type, p-type, or n-type semiconductor.

[0050] Next, please refer to the following: Figure 3B as well as Figure 4A After etching, the semiconductor stack creates separate platforms MS1 and MS2. In this specification, for the sake of simplicity and ease of understanding, not all parts and blocks are labeled; those with general knowledge in the industry can infer their meaning from the teachings in this specification. For example, Figure 4A Only two platforms, MS1 and MS2, are marked. Other platforms with the same outline as MS1 and MS2 but without markings are also platforms. The area outside the platforms exposes the first semiconductor layer 104, as... Figure 3B As shown.

[0051] Next, please refer to the following: Figure 3C as well as Figure 4B After another etching process, the semiconductor stack on the wafer WF1 produces separate LED units 10 (10a, 10b). As... Figure 4B As shown, LED units 10a and 10b respectively include platforms MS1 and MS2. The area outside the LED units 10 exposes the upper surface 182 of the substrate 102, as... Figure 3CAs shown, the region between LED units 10, including the semiconductor stack sidewalls of two adjacent LED units 10 facing each other and the upper surface 182 of the substrate 102, forms a trench TRCH. In subsequent fabrication processes, the multiple LED units 10, after being electrically connected, constitute a single LED element 1. Then, a dicing and separation fabrication process is performed on the wafer WF1 to separate each LED element 1. At this time, the trench TRCH around each LED element 1 serves as the dicing trace SCRB for the dicing and separation fabrication process.

[0052] Please also refer to Figure 3D as well as Figure 4C Next, a current blocking pattern CB1 and CBB are formed on the LED unit 10 and the trench TRCH. For example, the current blocking pattern CB1 and CBB are formed by depositing an insulating material layer (not shown) on the LED unit 10. The insulating material is, for example, silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, aluminum oxide, or a combination or stack of the above materials. The insulating material layer can be a single layer or a stack of multiple layers. For example, the insulating material layer is a distributed Bragg reflector structure composed of alternating stacks of insulating materials with different refractive indices. Next, a patterning step of the insulating material layer is performed, which can be done using a photolithography process and an etching process to pattern the insulating material layer, resulting in... Figure 3D and Figure 4C The current blocking blocks CB1 and CBB are located on the second semiconductor layer 108 of the LED unit 10a. The current blocking block CB1 is located on the trench TRCH, covering the upper surface 182 of the substrate 102 inside the trench TRCH and extending to the semiconductor stack sidewall of the LED unit 10a and part of the second semiconductor layer 108.

[0053] Please also refer to Figure 3E as well as Figure 4D Next, a transparent conductive layer 112 is formed on the LED unit 10. The transparent conductive layer 112 covers the current blocking pattern CB1 and a portion of the current blocking pattern CBB. Figure 4DViewed from above, the transparent conductive layer 112 on each LED unit 10 is recessed within the corresponding raised platforms MS1 and MS2. Therefore, the boundary of a transparent conductive layer 112 maintains a fixed distance from the boundary of a corresponding raised platform MS1 or MS2. However, this is just an example, and the invention is not limited thereto. The transparent conductive layer 112 can be a metal or a transparent conductive material. The transparent conductive layer 112 can be a thin electrode layer with light transmittance formed of metal. The transparent conductive material is transparent to the light emitted by the light-emitting layer 106 and includes materials such as indium tin oxide (ITO), zinc oxide (ZnO), zinc aluminum oxide (AZO), zinc gallium oxide (GZO), or indium zinc oxide (IZO).

[0054] Next, please refer to the following: Figure 3F as well as Figure 4E Next, an electrode layer is formed on the LED unit 10, which is patterned to form a first electrode 20, a second electrode 30, and a connecting electrode 60. The electrode layer is made of metals, such as chromium (Cr), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), rhodium (Rh), or platinum (Pt), or alloys or stacks of the above materials. The first electrode 20 is formed on the first semiconductor layer 104 of the LED unit 10b, and includes a first pad 201 and a first extension 202 extending from the first pad 201. The first electrode 20 is electrically connected to the first semiconductor layer 104. The second electrode 30 is formed on the transparent conductive layer 112 of the LED unit 10a, and is electrically connected to the transparent conductive layer 112 and the second semiconductor layer 108, and includes a second pad 301 and a second extension 302 extending from the second pad 301. On each of the other LED units 10, a first extension 202 electrically connected to its first semiconductor layer 104 and a second extension 302 electrically connected to its second semiconductor layer 108 are also provided. A connecting electrode 60 is formed on the current blocking block CBB, connecting the first extension electrode 202 on one LED unit 10 and the second extension electrode 302 on an adjacent LED unit 10, thus forming a series-connected LED array. In another embodiment, the connecting electrode 60 connects the first extension 202 on two adjacent LED units 10, and / or the connecting electrode 60 connects the second extension 302 on two adjacent LED units 10, thus forming different LED arrays such as parallel or series-parallel connections.

[0055] Next, please refer to the following: Figure 3G as well as Figure 4FNext, an insulating structure 50 is formed on each LED unit 10 and on the trench TRCH, which is patterned to have openings 501 and 502 corresponding to the first pad 201 and the second pad 301, respectively. The insulating structure 50 comprises silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, aluminum oxide, or combinations or stacks of the above materials. The insulating structure 50 can be a single layer or a stack of multiple layers. In one embodiment, the insulating structure 50 is a distributed Bragg reflector composed of multiple sublayers of insulating materials with different refractive indices stacked alternately. In flip-chip applications, this can increase the light emission of the light-emitting surface of the LED element 1. In another embodiment, an insulating structure (not shown) is included on the surface opposite to the upper surface 182 of the substrate 102, i.e., on the lower surface of the substrate 102. The insulating structure can be a distributed Bragg reflector composed of multiple sublayers of insulating materials with different refractive indices stacked alternately.

[0056] Please also refer to Figure 3H as well as Figure 4G Next, a first solder pad 36a and a second solder pad 36b are formed on the insulating structure 50. The first solder pad 36a is disposed on the LED unit 10b and electrically connected to the lower first electrode 20 through an opening 501, while the second solder pad 36b is disposed on the LED unit 10a and electrically connected to the lower second electrode 30 through an opening 502. In one embodiment, the first solder pad 36a and the second solder pad 36b are used to bond with circuitry on a carrier board (not shown) to achieve connection with external electronic components or an external power supply. In another embodiment, the first solder pad 36a and the second solder pad 36b may be omitted, and connection with external electronic components or an external power supply is achieved through the first electrode 20 and the second electrode 30.

[0057] Next, please refer to Figure 4H The wafer WF1 undergoes a dicing process. In this step, the wafer WF1 is divided into multiple independent LED elements 1 along the dicing traces SCRB around each LED element 1 using predetermined dicing lines CL. In one embodiment, a laser is used to irradiate the lower surface of the substrate 102 and focus it inside the substrate 102, causing a modified region (not shown) to form inside the substrate 102 at a position corresponding to the predetermined dicing line CL or at positions on both sides of the predetermined dicing line CL. Then, an external force is applied to form cracks along the crystal plane of the substrate 102 from the modified region, separating the substrate 102 and the insulating structure 50 above it to form independent LED elements 1.

[0058] Figure 1 and Figure 2 Showing from Figure 4HThe LED element 1 is segmented from the substrate. After undergoing the cutting and separation manufacturing process, the LED element 1 has four edges CE1, CE2, CE3, and CE4. Edge CE1 is opposite to edge CE3, and edge CE2 is opposite to edge CE4. In this embodiment, the edges of the LED element 1 are the edges of the substrate 102.

[0059] from Figure 1 and Figure 2 It can be seen that LED element 1 is composed of two LED units 10 (10a, 10b) connected in series electrically. Figure 1 The connecting electrode 60 partially overlaps with LED units 10a and 10b and spans the trench TRCH between LED units 10a and 10b, electrically connecting LED units 10a and 10b together. The second electrode 30 is the anode of LED element 1, having a second pad portion 301 and a second extension portion 302. The first electrode 20 serves as the cathode of LED element 1, having a first pad portion 201 and a first extension portion 202. In this embodiment, LED element 1 includes two LED units 10; in other embodiments, LED element 1 may include more LED units 10 connected in series and / or in parallel. In other embodiments, the first electrode 20 does not have a first extension portion 202 and / or the second electrode 30 does not have a second extension portion 302.

[0060] Before the chip WF1 was divided into independent LED elements 1, as Figure 4H As shown, the current blocking pattern CBB crosses the dicing trace SCRB, is located on two adjacent LED elements 1, and contacts the upper surface 182 of the substrate 102 within the dicing trace SCRB, becoming a cross-boundary current blocking pattern. Then, in the dicing process, not only is the substrate 102 cut along the dicing trace SCRB, but the current blocking pattern CBB is also cut. After the dicing and separation process is completed, the LED element 1 has a surrounding area that surrounds LED units 10a and 10b along the substrate 102. In this embodiment, the wafer WF1 uses the trench TRCH around each LED element 1 as the dicing trace SCRB, and the bottom of the trench TRCH is the upper surface 182 of the substrate 102. Therefore, the surrounding area in this embodiment is formed by the exposed upper surface 182 of the substrate 102 around the LED element 1, is not covered by the semiconductor stack, and surrounds the semiconductor stack. As... Figure 1 As shown, the current blocking block CBB left over from LED element 1 becomes current blocking block CB2, while another current blocking block CBB left over from LED element 1 becomes current blocking block CB3. CB2 and CB3 are located in the surrounding area and can be viewed from... Figure 1It is understood that current blocking pattern CB2 shares edge CE3 with substrate 102, while current blocking pattern CB3 shares edge CE1 with substrate 102. That is, current blocking pattern CB2 is approximately flush with edge CE3, while current blocking pattern CB3 is approximately flush with CE1. In one embodiment of the present invention, "current blocking pattern sharing an edge with substrate," "current blocking pattern flush with edge," or "current blocking pattern approximately flush with edge" means that, viewed from one side, one sidewall of the current blocking pattern is connected to one sidewall of the substrate; in one embodiment, the sidewall of the current blocking pattern is connected to the sidewall of the substrate and is coplanar. In another embodiment, CB2 and CB3 are located on the surrounding area, one edge of current blocking pattern CB2 is adjacent to edge CE3, one edge of current blocking pattern CB3 is adjacent to edge CE1, one of current blocking patterns CB2 and CB3 is not flush with its adjacent edge, and the other current blocking pattern is flush with its adjacent edge. In another embodiment, neither current blocking block CB2 nor current blocking block CB3 is flush with its adjacent edge, and neither the sidewall of current blocking block CB2 nor the sidewall of current blocking block CB3 is connected to one sidewall of the substrate.

[0061] Current blocking blocks CB2 and CB3 are located on the trench TRCH between LED units 10. Current blocking block CB2 overlaps with the connecting electrode 60, and from a top view, the width of current blocking block CB2 is greater than the width of the connecting electrode 60. When the LED units 10 are electrically connected, current blocking block CB2 is used to ensure the insulation between the connecting electrode 60 and the semiconductor stack sidewalls of the LED unit 10, preventing the connecting electrode 60 and the first extension 202 and second extension 302 connected thereto from short-circuiting the first semiconductor layer 104 in LED unit 10a to the first semiconductor layer 104 in LED unit 10b. Current blocking block CB3 does not overlap with any electrode.

[0062] Please see Figure 4CThe current blocking pattern CBB spans the slit track SCRB, preventing short circuits caused by over-etching, which could lead to the subsequent connection electrode 60 being mistakenly connected to the LED unit 10. In one embodiment, the method for patterning the insulating layer can employ wet etching, using an etching solution to remove the insulating layer not protected by the photoresist, leaving the insulating layer to form the current blocking patterns CBB and CB1. However, in the prior art, during the wet etching process of the insulating layer, the etching rate of the insulating layer located in the slit track and trench is relatively fast, easily resulting in over-etching. This causes the insulating layer that should have been retained to be partially removed, for example, starting from the predetermined boundary of the current blocking pattern along the trench and slit track. If over-etching occurs, the insulating material layer in the cut path and trench may disappear, causing the area covered by the final current barrier pattern to be smaller than originally intended. This fails to ensure electrical insulation between the connection electrode and the LED unit near the trench, resulting in the connection electrode incorrectly short-circuiting to the first semiconductor layer of the LED unit. The closer the connection electrode is to the edge of the LED element, that is, the closer the predetermined boundary of the current barrier pattern below it is to the cut path, the higher the probability of this problem. After the individual LED element 1 is completed, the current barrier pattern CB2 will be able to properly electrically isolate the connection electrode 60 from the LED units 10a and 10b.

[0063] Because the current blocking pattern CBB extends across the dicing path SCRB onto another LED element 1, a current blocking pattern CB3 is left on each LED element 1 after dicing. The current blocking pattern CB3 does not overlap with any electrodes; that is, it does not have any electrodes on it. The current blocking pattern CB3 shares edge CE1 with the substrate 102.

[0064] Figure 5 This invention shows an LED element 2 according to another embodiment of the invention. Unlike LED element 1, LED element 2 comprises six sequentially connected LED units 10 (10c-10h) arranged in a 2×3 matrix. Figure 6 This is a partial top view of the display chip WF2, which, after being cut along the predetermined dicing line CL in the dicing track SCRB, can produce multiple... Figure 5 LED component 2. Figure 5 and Figure 6The diagram illustrates the following: platforms MS3, MS4, MS5, MS8; current blocking blocks CB4, CB5, CB6, CB7, CB8, CB9, CB10, CBB1, CBB2; transparent conductive layer 112; first electrode 20'; second electrode 30'; connecting electrode 60; predetermined cutting line CL; cutting path SCRB; trench TRCH; and edges CE5, CE6, CE7, CE8. Although... Figure 5 and Figure 6 Not all components are labeled, but those skilled in the art can infer their meaning from the teachings of LED component 1 described above.

[0065] In this embodiment, the first electrode 20' on the LED unit 10h includes a first pad 201' and a first extension 202', and the second electrode 30' on the LED unit 10c includes a second pad 301' and a second extension 302'. In another embodiment, the first electrode 20' on the LED unit 10h does not include the first extension 202', and / or the second electrode 30' on the LED unit 10c does not include the second extension 302'. The first pad 201' and the second pad 301' can be used for wiring bonding to connect the LED element 2 to an external power supply or external electronic components.

[0066] from Figure 5 It is understood that LED element 2 comprises six LED units 10 connected in series, having four edges CE5, CE6, CE7, and CE8. Edge CE5 is opposite to edge CE7, and edge CE6 is opposite to edge CE8. In this embodiment, the edges of LED element 2 are the edges of substrate 102. The six LEDs are arranged in a 2×3 matrix. Current blocking blocks CB7 and CB9 are approximately flush with edge CE5, while current blocking blocks CB6 and CB8 are approximately flush with edge CE7. Like LED element 1, LED element 2 has a surrounding region that surrounds LED units 10c to 10h along substrate 102. The surrounding region is formed by the exposed upper surface 182 of substrate 102 around LED element 2, is not covered by the semiconductor stack, and surrounds the semiconductor stack. Current blocking blocks CB6, CB7, CB8, and CB9 are located on the surrounding region. In another embodiment, current blocking blocks CB6, CB7, CB8 and CB9 are located on the surrounding area, with one edge of current blocking blocks CB7 and CB9 adjacent to edge CE5 but not aligned with edge CE5; and one edge of current blocking blocks CB6 and CB8 adjacent to edge CE7 but not aligned with edge CE7.

[0067] exist Figure 6In the chip WF2, current blocking patterns CBB1 and CBB2 are both cross-boundary current blocking patterns, each crossing the dicing track SCRB. Therefore, after the chip WF2 is diced, Figure 5 In the diagram, current blocking block CB7 is composed of a portion of current blocking block CBB1, while current blocking block CB6 is composed of a portion of another current blocking block CBB1; similarly, Figure 5 The current blocking block CB9 is composed of a portion of the current blocking block CBB2, while the current blocking block CB8 is composed of a portion of another current blocking block CBB2.

[0068] as Figure 5 As shown, current blocking blocks CB7 and CB8 do not overlap with any electrodes; that is, they do not have any electrodes. Current blocking block CB6 spans the trench TRCH between LED units 10d and 10e, and current blocking block CB7 spans the trench TRCH between LED units 10c and 10f. CB8 and CB9 also span the trench TRCH between adjacent LED units 10. In another embodiment, a reflective layer (not shown) is included on the surface opposite to the upper surface 182 of the substrate 102, i.e., on the lower surface of the substrate 102. The reflective layer may be made of metal or insulating material. The reflective layer includes a distributed Bragg reflection structure composed of alternating stacks of insulating materials with different refractive indices. The reflective layer may also include an omnidirectional reflector (ODR) composed of a distributed Bragg reflection structure and a metal layer.

[0069] Similar to LED element 1, LED element 2 has cross-current barrier patterns CBB1 and CBB2 in its manufacturing process, which can prevent short circuits caused by the connection electrode 60 formed on top of the current barrier patterns CB6 and CB9 due to over-etching, which could lead to the connection electrode 60 being mistakenly connected to the LED unit 10. For example, the connection electrode 60 mistakenly short-circuits the LED unit 10d to the first semiconductor layer 104 in the LED unit 10e.

[0070] Unlike the previous embodiment where LED elements 1 and 2 use trenches (TRCH) between each LED element as scaffold bounding rings (SCRBs) in the wafer, in another embodiment (not shown), instead of forming trenches (TRCH) between LED elements as SCRBs during the LED element fabrication process, the first semiconductor layers 104 of each LED element are connected, and a width of the first semiconductor layer 104 connecting adjacent LED elements is reserved as the SCRB. Current blocking patterns (e.g., CBB, CBB1, and CBB2 in the previous embodiment) spanning the SCRBs are located on the first semiconductor layers 104 connected within the SCRBs. In subsequent dicing processes, the current blocking patterns, first semiconductor layers, and substrate are cut along the SCRBs using predetermined dicing lines (CL), separating the LED elements. The edges of the cut current blocking patterns and the edges of the first semiconductor layer 104 are flush with the edges of the LED elements. Alternatively, viewed from one side, one sidewall of the cut current blocking pattern is connected to the sidewall of the first semiconductor layer 104 and the sidewall of the substrate 102, and the sidewalls are either coplanar or not coplanar.

[0071] The present invention is not limited to LED elements having LED series / parallel arrays, but can also be applied to LED elements having a single LED unit, such as LED element 3 in another embodiment of the present invention. Figure 7 This shows a partial top view of a chip WF3, which is cut along the dicing path SCRB with a predetermined dicing line CL to form several LED elements 3. (Example) Figure 7 As shown, the area enclosed by the predetermined cutting line CL is the top view of an LED element 3. Figure 8A show Figure 7 In the diagram, a cross-sectional view along line segment XX.

[0072] like Figure 7 and Figure 8AAs shown, LED element 3 includes a substrate 102, a first semiconductor layer 104, a light-emitting layer 106, and a second semiconductor layer 108 sequentially formed on the substrate 102, a platform MS9, current blocking patterns CB11, CB12, CBB3, CBB4, a transparent conductive layer 112, a first electrode 20, a second electrode 30, an insulating structure 50, a first pad 36a, and a second pad 36b. Similar to LED element 1, the area other than the platform MS9 is the exposed upper surface of the first semiconductor layer 104. The first electrode 20 is disposed on the first semiconductor layer 104 and includes a first pad portion 201 and a first extension portion 202. The current blocking pattern CB11 is located on the second semiconductor layer 108, the transparent conductive layer 112 is located on the current blocking pattern CB11 and the second semiconductor layer 108, and the second electrode 30 is disposed on the transparent conductive layer 112 and includes a second pad portion 301 and a second extension portion 302. An insulating structure 50 covers the platform MS9, the dicing channel SCRB, and the first semiconductor layer 104. It includes openings 501 and 502 respectively disposed above the first pad 201 and the second pad 301, such that the first bonding pad 36a is electrically connected to the first semiconductor layer 104 via the opening 501, and the second bonding pad 36b is electrically connected to the second semiconductor layer 108 via the opening 502. The LED element 3 utilizes the first bonding pad 36a and the second bonding pad 36b to connect with circuitry on a carrier board (not shown) to achieve connection with external electronic components or an external power supply. The structure, materials, and manufacturing processes of each layer of the LED element 3 can be taught through the relevant descriptions of the LED element 1 in the foregoing embodiment, and will not be repeated here.

[0073] In this embodiment, the first electrode 20 is disposed along two opposite sides of the LED element 3, that is, along the cut lines SCRB on both sides of the LED element 3. The current blocking pattern CB12 is disposed below the first pad portion 201, and the current blocking patterns CBB3 and CBB4 are separately disposed below the first extension portion 202. The current blocking patterns CB12, CBB3, and CBB4 isolate the first electrode 20 from contact with the first semiconductor layer 104, allowing the first electrode 20 to contact the first semiconductor layer 104 at intervals, thereby increasing the current distribution effect. Furthermore, when the light-emitting layer 106 irradiates the current blocking patterns CB12, CBB3, and CBB4, the refractive index characteristics of the materials of the current blocking patterns CB12, CBB3, and CBB4 provide a path to extract the light, reducing the proportion of light absorbed by the first electrode 20.

[0074] As in the aforementioned embodiments, during the fabrication of the LED element 3, trenches are formed between each LED element 3 in the wafer WF3 as dicing paths (SCRBs), and each LED element 3 is separated along the SCRBs by a predetermined cutting line CL. Each individually cut LED element 3 includes a surrounding area formed by the upper surface 182 of the exposed substrate 102 around the LED element 3. However, when patterning the insulating material layer to form a current blocking pattern, the etch rate of the insulating material layer in and around the dicing path is relatively fast, easily leading to over-etching. When over-etching occurs, the boundary of the current blocking pattern may recede below the first extension 202, causing the area where the first electrode 20 was originally isolated from the first semiconductor layer 104 by the current blocking pattern to become partially or completely in contact with the first semiconductor layer 104. This will affect the current distribution effect and also affect the light emission of the LED element 3. In this embodiment, by extending the current blocking patterns CBB3 and CBB4 across the dicing trace SCRB and covering the upper surface 182 of the substrate 102, the boundary retreat of the current blocking patterns CBB3 and CBB4 below the electrodes due to over-etching can be avoided, thus preventing them from affecting the photoelectric characteristics of the LED element 3. Therefore, after the cutting is completed to form the independent LED element 3, the cut current blocking patterns CBB3 and CBB4 extend from below the first extension 202, covering the sidewalls of the first semiconductor layer 104 and the upper surface 182 of the substrate 102, as shown below. Figure 8A As shown. Furthermore, as with the LED element 1 in the aforementioned embodiment, the cut current blocking patterns CBB3 and CBB4 are located on the surrounding area, with their edges flush with the edge of the LED element 3. Alternatively, viewed from one side, one sidewall of the cut current blocking patterns CBB3 and CBB4 is connected to the sidewall of the substrate 102, wherein the sidewalls are either coplanar or non-coplanar. In this embodiment, the edge of the LED element 3 is the edge of the substrate 102. In another embodiment, the cut current blocking patterns CBB3 and CBB4 are located on the surrounding area, with their edges not flush with the edge of the LED element 3.

[0075] Figure 8B LED element 3' in another embodiment Figure 7 A cross-sectional view along line segment XX. Figure 8B and Figure 8A The difference is that, Figure 8BThe SCRBs surrounding each LED element 3' are not formed as trenches (TRCH). Instead, the first semiconductor layers 104 of adjacent LED elements 3' are connected, and a wide area is reserved on these connected first semiconductor layers 104 as the SCRB. Current blocking patterns CBB3 and CBB4 are located on these connected first semiconductor layers 104, and the first electrode 20 is formed on the current blocking patterns CBB3 and CBB4. In subsequent cutting processes, the current blocking patterns CBB3, the first semiconductor layers 104, and the substrate 102 are cut along the SCRBs with a predetermined cutting line CL, separating each LED element 3' to form an independent LED element 3'. Each LED element 3' includes a surrounding area, which is formed by the exposed upper surface of the first semiconductor layer 104 around the LED element 3'. The cut current blocking patterns CBB3 and CBB4 are located on the surrounding area, and their edges and the edges of the first semiconductor layer 104 are flush with the edges of the LED elements 3'. Alternatively, viewed from one side, one sidewall of the cut current blocking blocks CBB3 and CBB4 is connected to the sidewall of the first semiconductor layer 104 and the sidewall of the substrate 102, wherein the sidewalls are coplanar.

[0076] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Anyone skilled in the art can modify and vary the above embodiments without departing from the technical principles and spirit of the invention. Therefore, all equivalent changes and modifications made in accordance with the claims of this invention should be considered within the scope of this invention.

Claims

1. A light-emitting diode element, characterized in that, Include: The base includes a first edge and a second edge relative to the first edge; A semiconductor stack is formed on the substrate, wherein the semiconductor stack includes a plurality of light-emitting diode units, the plurality of light-emitting diode units including a first light-emitting diode unit and a second light-emitting diode unit; A trench is formed between the first light-emitting diode unit and the second light-emitting diode unit, wherein the trench exposes the substrate; A first current blocking block and a second current blocking block are formed on the trench. In the top view of the light-emitting diode element, the first current blocking block and the second current blocking block are separated from each other. A connecting electrode is formed on the first light-emitting diode unit and the second light-emitting diode unit and is electrically connected to the first light-emitting diode unit and the second light-emitting diode unit; The first electrode is located on the first light-emitting diode unit; The second electrode is located on the second light-emitting diode unit; The first bonding pad connects to the first electrode; and The second pad connects to the second electrode; In the top view of the light-emitting diode element, the first current blocking block overlaps with the connecting electrode.

2. The light-emitting diode element as described in claim 1, wherein: In the top view of the light-emitting diode element, the area of ​​the first current blocking block is larger than the area of ​​the second current blocking block.

3. The light-emitting diode element as described in claim 2, wherein: The first light-emitting diode unit and the second light-emitting diode unit each include a first semiconductor layer, a second semiconductor layer and a light-emitting layer. The first semiconductor layer is formed on the substrate, the second semiconductor layer is formed on the first semiconductor layer, and the light-emitting layer is disposed between the first semiconductor layer and the second semiconductor layer. The connection electrode is electrically connected to the first semiconductor layer of the first light-emitting diode unit and the second semiconductor layer of the second light-emitting diode unit.

4. The light-emitting diode element as claimed in claim 3, wherein the connecting electrode includes a first extension and a second extension, the first extension being electrically connected to the first semiconductor layer of the first light-emitting diode unit, the second extension being electrically connected to the second semiconductor layer of the second light-emitting diode unit, and the connecting electrode connecting the first extension and the second extension.

5. The light-emitting diode element of claim 4, further comprising a transparent conductive layer formed between the first current blocking pattern and the second extension.

6. The light-emitting diode element as claimed in claim 4, wherein: The first current blocking pattern is formed between the first semiconductor layer and the first extension of the first light-emitting diode unit.

7. The light-emitting diode element as claimed in claim 1, wherein: The substrate includes an upper surface, which includes a surrounding area; In the top view of the light-emitting diode element, the surrounding region surrounds the semiconductor stack; The first current blocking block and the second current blocking block are formed on the surrounding area.

8. The light-emitting diode element as claimed in claim 1, wherein: The base includes a first edge and a second edge relative to the first edge, each of the first edge and the second edge including a sidewall; The first current blocking block and the second current blocking block each include a side wall; In the cross-sectional view of the light-emitting diode element, the sidewall of the first edge is connected to the sidewall of the first current blocking block, and the sidewall of the second edge is connected to the sidewall of the second current blocking block.

9. The light-emitting diode element as claimed in claim 1, further comprising: An insulating structure is formed on the first light-emitting diode unit, the second light-emitting diode unit, the connecting electrode, and the trench.

10. The light-emitting diode element as claimed in claim 1, wherein: The substrate includes a first edge and a second edge relative to the first edge; The first current blocking pattern is adjacent to the first edge, and the second current blocking pattern is adjacent to the second edge.

11. The light-emitting diode element as claimed in claim 1, wherein, In the top view of the light-emitting diode element, the first current blocking pattern is aligned with the first edge, and the second current blocking pattern is aligned with the second edge.

12. The light-emitting diode element as claimed in claim 1 or 11, wherein: The substrate also includes a third edge connecting the first edge and the second edge, wherein the length of the first edge is greater than the length of the third edge.

13. The light-emitting diode element as claimed in claim 1, wherein the first current blocking pattern is not aligned with the second edge, and the second current blocking pattern is not aligned with the first edge.

14. The light-emitting diode element of claim 1, wherein the first current blocking pattern is not adjacent to the second edge, and the second current blocking pattern is not adjacent to the first edge.

15. A light-emitting diode element, characterized in that, Include: The substrate includes an upper surface, a first edge, and a second edge relative to the first edge; A semiconductor stack is located on the substrate, wherein the semiconductor stack includes a first semiconductor layer and a platform region, the first semiconductor layer is formed on the substrate, the platform region is formed on a first portion of the first semiconductor layer, wherein the platform region includes a second semiconductor layer and a light-emitting layer, the second semiconductor layer is formed on the first semiconductor layer, the light-emitting layer is formed between the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer includes a second portion exposed by the platform region; A first current blocking pattern is formed on the second portion of the first semiconductor layer and located at the first edge; and The first electrode is formed on the first current blocking block; In the top view of the light-emitting diode element, the upper surface includes a surrounding region that surrounds the semiconductor stack, the platform region includes an edge, the first current blocking pattern includes an edge facing the edge of the platform region, the first current blocking pattern partially covers the second portion of the first semiconductor layer and the surrounding region, and the edge of the platform region and the edge of the first current blocking pattern are separated.

16. The light-emitting diode element as claimed in claim 15, wherein: The first edge includes a sidewall, and the first current blocking block includes a sidewall; In the cross-sectional view of the light-emitting diode element, the sidewall of the first edge is connected to the sidewall of the first current blocking block.

17. The light-emitting diode element of claim 15, further comprising: A second current blocking pattern is formed on the second portion of the first semiconductor layer and located at the second edge; and The second electrode is formed on the second current blocking block; in, In the top view of the light-emitting diode element, the second current blocking pattern partially covers the surrounding area and the second portion of the first semiconductor layer.

18. The light-emitting diode element as claimed in claim 17, wherein: The substrate further includes a third edge that connects the first edge and the second edge, wherein the length of the first edge is greater than the length of the third edge; The first current blocking block is aligned with the first edge, and the second current blocking block is aligned with the second edge.

19. The light-emitting diode element as claimed in claim 15, wherein, The first semiconductor layer includes a sidewall, and the first current blocking pattern covers the sidewall of the first semiconductor layer.

20. The light-emitting diode element of claim 17, further comprising: A third current blocking pattern is formed on the second portion of the first semiconductor layer and located at the first edge; in, The first electrode is formed on the third current blocking pattern, which partially covers the second portion of the first semiconductor layer and the surrounding area.

21. The light-emitting diode element of claim 20, further comprising: A fourth current blocking pattern is formed on the second portion of the first semiconductor layer and located at the second edge; in, The second electrode is formed on the fourth current blocking pattern, wherein the fourth current blocking pattern partially covers the second portion of the first semiconductor layer and the surrounding area.

Images