Measuring current in constant on-time regulator

Abstract

A current monitor includes current sense logic and a processor. The current sense logic senses an inductor current at a predetermined time point during operation of a constant on-time regulator. The processor determines an output current of the constant on-time regulator based on the inductor current sensed at the predetermined time point. The predetermined time point corresponds to one-half of an on-time period of the constant on-time regulator. The output current can be determined during continuous conduction mode (CCM) or discontinuous conduction mode (DCM). During DCM mode, the processor determines the output current of the constant on-time regulator based on a skip time.

Description

Technical Field

[0001] The example embodiments disclosed herein typically involve current in a sensing circuit. Background Technology

[0002] A buck regulator is a circuit used to perform DC voltage conversion. It uses a switching circuit controlled by a pulse-width modulation (PWM) signal to perform the conversion. In operation, the buck regulator controls the duty cycle of the PWM signal to generate the desired output voltage through an LC circuit coupled to the load. A larger duty cycle results in a larger DC output voltage, and vice versa.

[0003] It has been shown that measuring the output voltage of a buck regulator is much easier than measuring its output current. One method for measuring the output current involves using a sensing resistor coupled to a capacitor in an LC circuit. The sensing resistor increases the cost and complexity of the buck regulator and is inefficient in terms of power. Furthermore, the sensing resistor may increase ripple in the output voltage, which can reduce the regulator's transient response. Summary of the Invention

[0004] A brief overview of various exemplary embodiments is given below. Some simplifications and omissions may be made in this overview, which are intended to highlight and describe some aspects of the various exemplary embodiments, and not to limit the scope of the invention. Detailed descriptions of exemplary embodiments suitable for making and using the concepts of the invention by those skilled in the art will be provided in later sections.

[0005] According to one or more embodiments, a current monitor includes current sensing logic configured to sense an inductor current at a predetermined time point during operation of a constant on-time regulator; and a processor configured to determine an output current of the constant on-time regulator based on the inductor current sensed at the predetermined time point, wherein the predetermined time point corresponds to half of the on-time period of the constant on-time regulator. The constant on-time regulator can operate in continuous conduction mode (CCM), and the output current is equal to the inductor current sensed at half the on-time period. A transistor coupled to the inductor of the constant on-time regulator can be turned on during the on-time period to generate an inductor current.

[0006] The constant on-time regulator can operate in discontinuous conduction mode (DCM). The processor can determine the output current by calculating the average of the output current based on the on-time period, the off-time period, the jump period, and the inductor current sensed at half the on-time period. The current monitor may include at least one timer / counter logic configured to (a) determine the number of integer periods present during a combined period including the on-time period and the off-time period, (b) determine the fraction of integer periods present during the combined period, (c) determine the number of integer periods present during the jump period, and (d) determine the fraction of integer periods present during the jump period, wherein the processor is configured to calculate the average of the output current based on (a) through (d) and the inductor current sensed at half the on-time period.

[0007] At least one timer / counter logic can determine a fraction of the integer period in (b) by determining the voltage stored in the capacitor during the combination period, which is between the initial voltage and the timer voltage corresponding to the full integer period. At least one timer / counter logic can determine a fraction of the integer period in (d) by determining the voltage stored in the capacitor during the jump period, which is between the initial voltage and the timer voltage corresponding to the full integer period. The integer period can be less than the on-time period. The constant on-time regulator can be a buck regulator or a boost regulator.

[0008] According to one or other embodiments, a method for monitoring the operation of a circuit includes: identifying a predetermined time point for a constant on-time regulator; detecting the start of an on-time period of the constant on-time regulator; sensing an inductor current at the predetermined time point of the on-time period; and determining an output current of the constant on-time regulator based on the inductor current sensed at the time point, wherein the predetermined time point corresponds to half of the on-time period, and the inductor current is sensed at the halfway point of the on-time period. The constant on-time regulator can operate in continuous conduction mode (CCM), and the output current is equal to the inductor current sensed at the halfway point of the on-time period. A transistor coupled to the inductor of the constant on-time regulator can be turned on during the on-time period to generate an inductor current.

[0009] A constant on-time regulator can operate in discontinuous conduction mode (DCM). Determining the output current may include calculating an average value of the output current based on the on-time period, the off-time period, and the jump period, as well as an inductor current sensed at half the on-time period. The method may include (a) determining the number of integer periods present during a combined period including the on-time and off-time periods, (b) determining a fraction of the integer periods present during the combined period, (c) determining the number of integer periods present during the jump period, (d) determining a fraction of the integer periods present during the jump period, and calculating an average value of the output current based on (a) through (d) and the inductor current sensed at half the on-time period.

[0010] Determining the fraction of the integer period in (b) may include determining the voltage stored in the capacitor during the combined period, which is between the initial voltage and the timer voltage corresponding to the full integer period. Determining the fraction of the integer period in (d) may include determining the voltage stored in the capacitor during the jump period, which is between the initial voltage and the timer voltage corresponding to the full integer period. The integer period may be less than the on-time period. The constant on-time regulator may be a buck regulator or a boost regulator. Attached Figure Description

[0011] Additional objects and features of the invention will become more apparent from the following detailed description and appended claims when considered in conjunction with the accompanying drawings. Although several exemplary embodiments are shown and described, similar reference numerals identify similar parts in each drawing, wherein:

[0012] Figure 1 An example of a constant on-time buck regulator is shown;

[0013] Figure 2 The waveform of the constant on-time buck regulator is shown;

[0014] Figure 3 An embodiment of a method for determining the output current of a regulator operating in continuous conduction mode (CCM) is shown;

[0015] Figure 4 An example of CCM mode operation of the current monitor is shown;

[0016] Figure 5 Another embodiment of a current monitor for CCM mode operation is shown;

[0017] Figure 6A and Figure 6B An embodiment of the signal generator is shown. Figure 6C It shows the result of Figure 6A and Figure 6BExamples of waveforms generated by a signal generator;

[0018] Figure 7A and Figure 7B Additional embodiments of the signal generator are shown;

[0019] Figure 8A An additional embodiment of the signal generator is shown. Figure 8B It shows the result of Figure 8B Examples of waveforms generated by a signal generator;

[0020] Figure 9 An example of a waveform generated during discontinuous conduction mode (DCM) operation is shown;

[0021] Figure 10 It shows that it can include the use of Figure 9 Different periods of the waveform;

[0022] Figure 11 An example of counter / timer logic is shown;

[0023] Figure 12A and Figure 12B It shows the result of Figure 11 Examples of waveforms generated by counter / timer logic;

[0024] Figure 13 An example of a timer start signal for counter / timer logic is shown;

[0025] Figure 14 The following is illustrated for determining operation in DCM mode. Figure 1 An embodiment of a method for regulating the output current of a regulator;

[0026] Figure 15 Another embodiment of the counter / timer logic is shown; and

[0027] Figure 16 An embodiment of a constant on-time boost regulator is shown; Detailed Implementation

[0028] It should be understood that the accompanying drawings are merely schematic and not drawn to scale. It should also be understood that the same reference numerals are used in all the drawings to denote the same or similar parts.

[0029] The specification and accompanying drawings illustrate the principles of various exemplary embodiments. Therefore, it should be understood that those skilled in the art will be able to design various arrangements that, while not explicitly described or shown herein, embody the principles of the invention and are included within its scope. Furthermore, all examples described herein are primarily intended for educational purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventors to promote the art, and should be construed as not being limited to such specific examples and conditions. Additionally, unless otherwise indicated (e.g., “otherwise” or “or alternative”), as used herein, the term “or” means non-exclusive or (i.e., and / or). Moreover, the various exemplary embodiments described herein are not necessarily mutually exclusive, as some exemplary embodiments can be combined with one or more other exemplary embodiments to form new exemplary embodiments. For example, descriptors such as “first,” “second,” and “third” do not imply a limitation on the order of the elements discussed, but are used to distinguish one element from the next and are generally interchangeable. For example, the value of a maximum or minimum value can be a predetermined value and is set to different values ​​based on the application.

[0030] Figure 1 An example of a constant on-time (COT) buck regulator 100 for generating current to drive a load is shown. The load may vary depending on the intended application. For example, when the load is a battery, the COT buck regulator can generate a fundamentally triangular waveform at a predetermined frequency for charging the battery. In one embodiment, the load may be a microprocessor control unit (MCU) driven by current from the COT buck regulator. The load is represented in the figure by resistor R. L It is shown schematically.

[0031] refer to Figure 1 The COT buck regulator 100 includes a driver 10, a switching circuit 20, an inductor 30, a capacitor 40, and a feedback circuit 50. The driver 10 generates signals for controlling the switches in the switching circuit 20. The driver can perform this function based on a feedback signal from the feedback circuit 50. In one embodiment, the driver 10 may include logic or dedicated circuitry that responds to the feedback signal to generate a desired output current waveform with a predetermined frequency. Unlike other types of regulators, the frequency of the output current waveform can be adjusted, for example, based on load fluctuations or other requirements.

[0032] Switching circuit 20 may include a first switch 21 and a second switch 22. For example, when driver 10 outputs separate control signals to the first and second switches, the first and second switches may be MOSFETs having the same conductivity, for example. In another embodiment, for example, when driver 10 outputs a single control signal to control both switches, the MOSFETs may have different conductivity. In the latter case, the first switch 21 (sometimes referred to as a high-side switch or power transistor) may be a PMOS transistor, and the second switch 22 (sometimes referred to as a low-side switch or power transistor) may be an NMOS transistor. Because buck regulator 100 is a constant on-time regulator, driver 10 may output a switching signal to turn on the first switch 21 at a fixed time period, for example, the on-time of the first switch 21 is known and has a constant time period. The on-time period may be set, for example, based on the intended application, such as the current requirements of the load. To meet these requirements, driver 10 may generate an output current waveform having a frequency that is adjusted by adjusting the off-time of the duty cycle of the first switch 21 (and proportional to the variable on-time of the second switch 22, which is connected to a reference potential, such as ground).

[0033] Inductor 30 is coupled to switching circuit 20 and load R L The capacitor 40 is connected in parallel with the inductor. The capacitor 40 can filter the high-frequency (e.g., DC) components of the regulator output before being input to the load. The output voltage V of the voltage regulator is adjusted by switching the first switch 21 and the second switch 22. OUT and current I OUT Inductor 30 is connected to the power supply voltage V. IN and from the power supply voltage V IN disconnect.

[0034] The switching of transistors 21 and 22 causes ripple in the inductor current of the voltage regulator. Primarily due to the equivalent series resistance in the output capacitor 40, the ripple affects the output voltage V. OUT This is evident in the ripple in the inductor current. Ripple in the inductor current can interfere with the stability of the regulator output or otherwise disrupt the noise of the regulator output, potentially reducing the performance of circuits driven by the regulator output.

[0035] Feedback circuitry 50 may be included in part to compensate for ripple in the regulator output. Ripple compensation can be achieved by generating a control signal CS2, which may, for example, be a pulse-width modulation (PWM) signal with a fixed on-time and an adjustable off-time. The on-time controls the duration for which the first switch 21 is on, and may correspond to the on-time T of the duty cycle controlling the switching in the switching circuit 20. ONThe off-time control measures the duration for which the first switch 21 is turned off, which can correspond to the off-time T of the duty cycle. OFF The second switch 22 is in the off state when the first switch 21 is on, and in the on state when the first switch 21 is off. Therefore, it can be said that the first switch 21 and the second switch 22 are a half-bridge configuration.

[0036] Unlike the on-time of the first switch 21, the off-time of the first switch 21 is adjustable. The feedback circuit 50 adjusts the off-time T. OFF This is done to reduce ripple and thus stabilize the voltage regulator's output. Furthermore, adjusting the off-time of the first switch 21 generates a proportional change in the frequency of the regulator's output signal.

[0037] The feedback circuit 50 can be configured in various ways to generate a control signal CS2 for the driver 10. Figure 1 In this embodiment, the feedback circuit 50 includes a comparator 52, an integrator 51, and an on-time controller 53. The integrator 51 converts the output voltage V of the regulator into a signal. OUT With reference voltage V REF A comparison is made. When the first switch 21 is turned on (e.g., during the on-time T...), ON During the cycle, the reference voltage can be set lower than the feedback voltage V. FB The value of the ripple valley in the reference voltage V. REF It can be turned off at time T OFF During the period, the slope increases, and the feedback voltage V FB Crossover. Feedback voltage V FB Based on the regulator's output voltage V OUT For example, V FB It can be equal to V OUT Or it could be V OUT The gradual reduction pattern is determined, for example, by a voltage divider coupled to the output of the inductor. When the feedback voltage V FB The rising slope and the reference voltage V REF When they intersect, comparator 51 generates an input signal (V) for integrator 52. DIFF ).

[0038] Integrator 52 includes receiving a signal (V) from ripple generator 55. RIPPLE The first input and the second input (V) corresponding to the output of comparator 51 DIFF The signal from ripple generator 55 can represent the ripple in the regulator's output voltage, which is proportionally represented in the feedback voltage VFB. An integrator integrates the difference between the ripple voltage VRIPPLE and the output voltage VDIFF of comparator 51 to generate a control signal CS1 for the on-time controller 53. The on-time controller 53 can be, for example, a single-trigger multivariable generator.

[0039] In operation, when the output voltage VDIFF of comparator 51 is less than the difference between the reference voltage VREF and the feedback voltage VFB, the on-time controller 53 outputs a high PWM signal CS2. Then, as long as the PWM signal CS2 remains high, the driver 10 generates a first signal to turn on power transistor 21 and a second signal to turn off power transistor 22. As a result, the current flowing into inductor 30 increases, and the regulator's output voltage VOUT increases proportionally. The on-time controller 52 holds the PWM signal CS2 high for a fixed time period to ensure a constant on-time of the regulator. The feedback circuit 50 then adjusts the off-time of power transistor 21 based on changes in the feedback voltage VFB.

[0040] Increasing the inductor current and thus the regulator's output voltage VOUT causes the feedback voltage VFB to increase. When the feedback voltage VFB increases to a point where the comparator 51's output voltage VDIFF is greater than the difference between the reference voltage VREF and the feedback voltage VFB, the value of the first control signal CS1 causes the on-time controller 53 to output a low PWM signal CS2. The driver 10 then adjusts the off-time of the first power transistor 21 (and the on-time of the second power transistor 22) based on the low value of the PWM signal CS2. This, in turn, causes the inductor current to decrease with the regulator's output. This process is repeated when the feedback voltage VFB drops to a point where VDIFF is less than the difference between the reference voltage VREF and the feedback voltage VFB.

[0041] Figure 2 This illustrates the operation when in continuous conduction mode (CCM). Figure 1 An example of waveforms generated in a COT buck regulator. In CCM mode, the voltage gain is independent of the load, the input current is continuous and ripple-free, and the ripple component of the inductor current is lower than the average value of the inductor current. As a result, for at least some applications, regulators operating in CCM mode may be more efficient than those in other modes. Figure 2 The waveforms in the waveforms can form the basis of one embodiment of a method for understanding the current in a COT buck regulator in a sensing CCM mode.

[0042] refer to Figure 2 This method relies on a fixed on-time of the buck regulator 100 to sense the current input to the inductor 30. More specifically, similar to the case of a COT buck regulator, Figure 2 The full-on-time waveform in the middle has an on-time period T. ON This corresponds to the constant on-time of power transistor 21 in the switching circuit. (In this sense, the on-time of the COT buck regulator can be considered as feedforward controlled). The constant on-time period TON This increases the current entering inductor 30, as indicated by the rising portion of the inductor current ripple waveform. During the constant (or full) conduction time period T... ON At the end of the period, power transistor 21 will be off during the off-time period T. OFF Turn off. This reduces the current flowing into inductor 30, as indicated by the falling portion of the inductor current ripple waveform. (Because in this embodiment, the COT buck regulator operates in CCM mode, the triangular waveform of the inductor ripple current does not include the jump time.)

[0043] Because the full conduction time T of power transistor 21 ON It is a known fixed constant value, so half a point of the full conduction time period (e.g., T) ON / 2) is also a known fixed constant value, and corresponds to Figure 2 The half-conduction time period is defined as follows. Because the current entering the inductor 30 increases linearly (or at least substantially so) when the power transistor 21 is turned on, the end of the half-conduction time period corresponds to the inductor ripple current I. MID The midpoint of the inductor ripple current is shown by the dashed line. The midpoint of the inductor ripple current is equal to the average current of the inductor. Therefore, the current of the COT buck regulator can be determined based on the half-conduction time period of the power transistor 21.

[0044] Figure 3 It shows the method for using based on Figure 2 An embodiment of a method for waveform sensing of current in a COT buck regulator 100. At 310, the method includes determining the full on-time period (T0) of a power transistor 21 that controls the current to inductor 30. ON As mentioned earlier, T ON The period is a known constant value determined, for example, based on the expected application of the regulator, such as load requirements. At 320, the half-conduction period (T) is identified based on the full-conduction period. ON / 2). At 330, for example, the start of the conduction time period is detected based on the non-zero inductor current. At 340, the half-conduction time period (T) corresponding to the inductor current ripple waveform is determined. ON / 2) termination point (I MID At 350, based on Figure 2 Current I in MID Determine the output current of the COT buck regulator. In one embodiment, this output current can be considered as the average output current of the COT buck regulator (e.g., I0). OUT ), for example, I OUT =I MID .

[0045] Figure 4The diagram shows the method for determining the output current I of the COT buck regulator. OUT An embodiment of the current monitor 400. The regulator may include, for example... Figure 1 and Figure 2 The half-bridge switching circuit in the regulator 100, or the regulator itself, can be a different COT buck regulator or even a COT boost regulator.

[0046] refer to Figure 4 The current monitor 400 includes current sensing logic 410, a switch 420, an analog-to-digital converter 430, and a digital signal processor 440 for outputting information indicating the output current of the regulator. The current sensing logic 410 measures the current flowing at a predetermined point in the buck regulator continuously or when the power transistor 21 is turned on. For example, the current sensing logic 410 can measure the current output from the power transistor 21 during the period when the transistor 21 is turned on based on input signals 401 and 402 (e.g., when one or more of these input signals have non-zero values) and a control signal CS3 output from the driver 10. Input signals 401 and 402 can correspond to the source and drain voltages of the high-side switch, respectively. In the case of discontinuous operation of the current sensing logic, the control signal CS3 can enable the current sensing logic when the high-side power transistor 21 is turned on and disable the current sensing logic when the power transistor 21 is turned off. The sensed current can correspond to... Figure 2 The inductor current ripple waveform is shown below. In one embodiment, the controller may generate control signals CS3 and / or CS4, as mentioned below.

[0047] Switch 420 can control when to sample the sensed current output from current sensing logic 410. The state of switch 420 can be determined based on control signal CS4, which can be, for example, in conjunction with... Figure 2 The semi-conduction time period T in ON The time at which the termination point of / 2 coincides is asserted. Because the buck regulator is a constant on-time regulator, the half-on-time period T... ON / 2 is a known, fixed, constant period, determined, for example, based on the designer of the buck regulator and / or the requirements of the circuit driven by the regulator output. The control signal CS4 causes switch 420 to close at the beginning of the half-conductance time period TON / 2 and open at the end of the half-conductance time period TON / 2. The time at which the switch opens (e.g., at the end of the half-conductance time period) corresponds to... Figure 2 The current IMID in the middle can be equal to or used as the basis for determining the midpoint current IMID, which in turn provides an indication of the average output (ripple) inductor current IOUT.

[0048] The current value output when switch 420 is closed or during the midpoint of the current IMIDI can be converted into a digital current value IDIGITAL by analog-to-digital converter 430. This digital current value IDIGITAL can be processed by digital signal processor 440 to generate an indication of the monitored output current IOUT of the COT buck regulator. In one embodiment, digital signal processor 440 can perform an extrapolation algorithm to generate an indication of the monitored output current (e.g., average output current) IOUT. Digital signal processor 440 can perform various types of processing. Examples include averaging the readback current over a certain period or writing data to internal memory so that the system can obtain historical data. In one embodiment, no digital signal processing is performed. In this case, the real-time raw data can be stored and updated in each read cycle.

[0049] In one embodiment, the current sensing logic 410 may include a capacitor that is charged based on a current sensed by one or more of the input signals 401 and 402. Charging and discharging the current in such a capacitor increases and decreases the voltage stored in the capacitor. Increasing and decreasing the capacitor voltage can provide a proportional indication of the inductor current. In another embodiment, the current sensing logic may include software driven by instructions stored in memory. The total on-time period (T) ON And therefore the semi-conduction time period T ON / 2 can be programmed into memory or a database for use or access by these instructions. Therefore, the instruction can cause the processor (or other processing logic) to... Figure 2 The dashed line in the figure indicates the method for determining the half-conduction time period T. ON The current I present at the end of / 2 MID .

[0050] Figure 5 Another embodiment of a monitor 500 for sensing the current of a COT buck regulator is shown. In this embodiment, the half-bridge switching circuit is replaced by a single switch (transistor) 580 coupled to the inductor 30. Alternatively, the monitor 500 could be similar to... Figure 4 It operates in a monitor-like manner. For example, switch 520 operates during the on-time period T. ON It closes at the beginning and during the half-conduction time period T. ON It can be opened at / 2, or it can be opened during the semi-conduction time period T. ON Closing at a time consistent with / 2, so as to close at Figure 2 The midpoint I of the output ripple current MD The current measured by the current sensing logic 510 is sampled at the point. The analog-to-digital converter 530 converts the midpoint current I... MIDThe signal is converted into a digital signal, which is then processed by a digital signal processor 540 to generate the output current I of the COT buck regulator. OUT Instructions.

[0051] Figure 6A and Figure 6B It shows the use for Figure 4 and Figure 5 Examples of signal generators that generate control signals are described in various embodiments. See also: Figure 6A The signal generator includes a current source 602, a capacitor 604, and a comparator 606. The current source 602 is coupled to the capacitor 604 through node N1. The non-inverting input of the comparator 604 is coupled to node N1, and the inverting input of the comparator 604 is coupled to the reference voltage V. REF The reference voltage V REF Can be entered into Figure 1 The reference voltages of the non-inverting inputs of comparator 51 are the same or different.

[0052] refer to Figure 6B The signal generator includes a current source 612, a capacitor 614, and a comparator 616. The current source 612 is coupled to the capacitor 614 via node N2. The non-inverting input of the comparator 614 is coupled to node N2, and the inverting input of the comparator 614 is coupled to the reference voltage V. REF The reference voltage V REF Can be entered into Figure 1 The reference voltages of the non-inverting inputs of comparator 51 are the same or different.

[0053] exist Figure 6A and Figure 6B In this circuit, capacitors 602 and 612 can have the same capacitance C, and the current (2I) output from current source 612 can be twice the current (I) output from current source 602. When the ramp signal generated by I / C becomes greater than the reference voltage, T... ON Time is generated. In this embodiment, the comparator 614 output has a half-cycle (T) ON The ramp signal 618 ( / 2) and the comparator 604 can output a full-cycle (T) signal. ON The ramp signal 608 is used to control the slope signal 608, respectively. Figure 4 The switch 420 and transistor 21 in the middle and Figure 5 The switch 520 and transistor 680 in the middle, such as Figure 6C As shown in the image. T ON The value can be calculated, for example, based on equation (1).

[0054]

[0055] Figure 7A and Figure 7B The diagram shows the methods for generating separately. Figure 4 and Figure 5 An additional embodiment of the signal generator for the control signal in the embodiment is provided. See also... Figure 7A The signal generator includes a current source 622, a capacitor 624, and a comparator 626. The current source 622 is coupled to the capacitor 624 through node N1′. The non-inverting input of the comparator 624 is coupled to node N1′, and the inverting input of the comparator 624 is coupled to the reference voltage V. REF The reference voltage V REF Can be entered into Figure 1 The reference voltages of the non-inverting inputs of comparator 51 are the same or different.

[0056] refer to Figure 7B The signal generator includes a current source 632, a capacitor 634, and a comparator 636. The current source 632 is coupled to the capacitor 634 via node N2′. The non-inverting input of the comparator 634 is coupled to node N2′, and the inverting input of the comparator 634 is coupled to the reference voltage V. REF The reference voltage V REF Can be entered into Figure 1 The reference voltages of the non-inverting inputs of comparator 51 are the same or different.

[0057] exist Figure 7A and Figure 7B In this embodiment, the capacitance (2C) of capacitor 624 is twice the capacitance (C) of capacitor 634, and current sources 622 and 632 output the same current (I). As a result, comparator 624 can output a current with a half-cycle (T). ON / 2) ramp signal, and comparator 634 can output a full-cycle (T) ramp signal. ON The ramp signal is used to control the ramp signal separately. Figure 4 The switch 420 and transistor 21 in the middle and Figure 5 The switch 520 and transistor 680 in the middle, such as Figure 6C As shown in the image.

[0058] Figure 8A It shows the method for generating Figure 4 and Figure 5 An additional embodiment of the signal generator for the control signal in the embodiment is provided. See also... Figure 8A The signal generator includes a current source 642, a capacitor 644, and a comparator 646. The current source 642 is coupled to the capacitor 644 via node N. The non-inverting input of the comparator 646 is coupled to node N, and the inverting input of the comparator 644 is coupled to the reference voltage V. REF The reference voltage V REF Can be entered into Figure 1The reference voltages at the non-inverting inputs of comparator 51 are the same or different. Current source 642 outputs current (I), and capacitor 644 has capacitance C. In operation, comparator 646 outputs a continuous ramp signal, each with a voltage T. ON The period is 2 / 2. Therefore, the first ramp signal 648 can control... Figure 4 Switch 420 and Figure 5 The switch 520 and the second ramp signal 658 can control... Figure 4 transistor 21 and Figure 5 Transistor 680 in the middle, such as Figure 8B As shown in the image.

[0059] Figure 9 This demonstrates the operation in a discontinuous conduction mode (DCM), which can be referred to as a skip mode. Figure 1 An example of the waveform generated in a COT buck regulator. In DCM mode, the voltage gain depends on the load, the input current is pulsating, and the ripple component of the inductor current is high, with a higher root mean square (RMS) value than in CCM mode. Figure 2 The waveform in can also be derived from Figure 1 The waveforms are generated by the current monitor in the circuit, or may be generated by different circuits. These waveforms can form the basis for understanding one embodiment of a method for sensing the current in a COT buck regulator in DCM mode.

[0060] Figure 1 The COT buck regulator can be driven in DCM mode to improve efficiency under low load current conditions. During the inductor current discharge phase, when the inductor current reaches zero (e.g., at zero crossing), the low-side switch 22 is turned off. As a result, both the high-side switch 21 and the low-side switch 22 remain off until the output voltage monitoring circuit detects that another charging pulse is about to be generated. This generates Figure 9 The waveform in the image.

[0061] refer to Figure 9 The waveform in DCM mode can be similar to the waveform generated in CCM mode, except that the inductor current ripple waveform includes waveforms generated by the time period T. SKIP A series of discontinuous triangular waveforms separated by space. For example... Figure 2 As shown, T SKIP The period causes the off time T of switch 21 to be... OFF The off time of this switch is longer than in CCM mode. The interval between the half-conduction time waveforms is also based on T. SKIP It increases cyclically.

[0062] When the COT buck regulator operates in DCM mode, due to T SKIP Period, midpoint I of the sensed inductor current MIDThe average output current of the regulator is not directly represented. Instead, it can be calculated by dividing the total charge transferred to the output by the total period T. TOTAL =T ON +T OFF +T SKIP The average output current is determined as shown in equation (2). Figure 10 In the examples, these times are relative to Figure 9 The waveform is plotted.

[0063]

[0064] T in DCM mode ON Period, T OFF Period and T SKIP The period can be determined in various ways. Example embodiments for determining these periods are discussed below. Once T... ON The period is determined, and the midpoint I of the inductor current is... MID The output current can be calculated by the processor or other logic coupled to the COT buck regulator based on equation (2). (It should also be noted that equation (2) can be used to determine the output current in CCM mode, for example, T in CCM mode.) SKIP =0, in this case, I OUT =I MID As mentioned above)

[0065] Figure 11 An embodiment of asynchronous timer / counter logic is shown, which can determine the output current I of the COT buck regulator in DCM mode for calculation using equation (2). OUT The cycle. A COT buck regulator can be, for example... Figure 1 The regulator shown may be a COT buck regulator with a different structure. For ease of explanation, this will be discussed in this context. Figure 1 COT step-down regulator.

[0066] The asynchronous timer / counter logic counts multiple predetermined periods T to determine the two periods in equation (2). The first period of the two periods corresponds to the combined period (T). ON +T OFF The second period of the two cycles corresponds to T. SKIP Period. In one embodiment, the period T can be less than T0. ON Period, T OFF Period and T SKIPEach of the cycles is calculated to allow for the calculation of fractional integer cycles that may occur during COT buck regulator operation in DCM mode. This will become more apparent with reference to Figure 12 discussed below. In one embodiment, the predetermined cycle T may be greater than at least one of the combined cycles or skip cycles presented above.

[0067] refer to Figure 11 The asynchronous timer / counter logic includes a comparator 1110, a timer current source 1120, a capacitor 1130, a counter 1140, an analog-to-digital converter 1150, and digital processing logic 1160. The comparator 1110 continuously compares the charging voltage stored in the capacitor 1130 with a reference voltage V. timer A comparison is made. Capacitor 1130 is based on the charging current I from current source 1120. timer The capacitor is charged at a predetermined rate. The charging current I of capacitor 1130 can be predetermined. timer and capacitor C timer The value is used to set the duration of the time period T.

[0068] During operation, when the comparator's output signal S1 is logic 0, switch SW1 closes, indicating the capacitor voltage C. charge Less than the reference voltage V timer When switch SW1 is closed, it can control current source 1120 to start outputting current I to capacitor 1130. timer (In one embodiment, controller 1170 may, at least initially, control the output of current from current source 1120 and / or the state of switch SW1). When current I timer When capacitor 1130 begins to charge, the charging voltage V of capacitor 1130 is... CAP The input is capacitively coupled to comparator 1110.

[0069] Capacitor 1130 is charged to equal the reference voltage V. timer The time period during which the voltage is applied constitutes the period T. Figure 12A An example is shown in the figure, where V CAP =V timer Required charging time T charge It equals one time period T. When V CAP =V timer When the counter 1110 outputs a signal S1 with a logic value of 1 to the counter 1140, the signal S1 increments by 1 to indicate that one cycle T has been counted. The value of T can be determined based on equation (3).

[0070]

[0071] A logic 1 value for signal S1 opens switch SW1, allowing the voltage stored in capacitor 1130 to discharge through the ground connection. When the capacitor voltage drops to zero, switch SW1 closes again, and the capacitor begins to recharge.

[0072] At this point, the inductor current can be monitored. When the inductor current reaches zero, this indicates the combination period (T). ON +T OFF The expiration date has passed. At this time, controller 1170 generates signal S2 to close switch SW2. At this time, closing switch SW2 affects the capacitor voltage V. CAP Sampling is performed. If V is closed when switch SW2 is closed... CAP If a = 0, then an integer number of time periods T have been counted without any fractional periods. Therefore, the analog-to-digital converter 1150 will output a signal to the digital processing logic 1160 indicating that no fractional periods have been counted, for example, a = 0. The output of the counter 1140 indicates that an integer number of time periods have been counted. Then, the digital processing logic 1160 calculates (T) based on the integer value of the counted periods T. ON +T OFF The combined value of ).

[0073] If V is closed when switch SW2 is closed (e.g., when the inductor current crosses zero) CAP If ≠0, then 0 < V CAP <V timer Where 0 is the initial voltage. In this case, the analog-to-digital converter 1150 converts the capacitor voltage V... CAP This is converted into a number (a) corresponding to the fractional part of period T, for example, aT. This conversion is possible because V at this point... CAP The score (V) FRAC ) corresponds to the proportional fraction of T, for example Figure 12A As shown in the figure. In another embodiment, the initial voltage may be different from 0 (e.g., a small voltage or a certain voltage limit).

[0074] Figure 12B This shows the combination (T) ON +T OFF This example illustrates how asynchronous timer / counter logic counts two full cycles (counter value = 2) and a fractional cycle a*T (fraction = a) during a period. As previously mentioned, the start of this combined cycle may correspond to the first zero-crossing of the inductor current, and the end of this cycle may correspond to the second zero-crossing of the inductor current. Controller 1170 can monitor these zero-crossings to generate signal S1 for closing switches SW1 and SW2, as previously indicated. Once the inductor current begins to increase again after the second zero-crossing value, controller 1170 can change the value of signal S2 to open switch SW2, and repeat the process.

[0075] Figure 11 The asynchronous timer / counter logic can be implemented in various ways to determine the output current of the COT buck regulator operating in DCM mode. As previously mentioned relative to... Figure 12A and Figure 12B The indicated combination (T) ON +T OFF The number of periods T in a periodic cycle does not have to be a single integer; that is, in some cases, in addition to an integer number of periods T, there can be a fractional part of period T. SKIP The same may be true during the cycle.

[0076] In one embodiment, the same asynchronous timer / counter logic can be used to determine the combination (T). ON +T OFF ) and T SKIP The fraction T value in the period. In another embodiment, different asynchronous timer / counter logic can be used (e.g., such as...). Figure 11 As shown in the figure, one is used to determine the combination (T) ON +T OFF The number of integer periods T and fractional periods in the periodicity, another factor used to determine T. SKIP The integer period T and the fractional period in the periodicity.

[0077] Figure 13 An example timing diagram for generating the output current of a COT buck regulator using either a single asynchronous timer / counter logic or a separate asynchronous timer / counter logic is shown above. When using only a single asynchronous timer / counter logic, the controller 1170 can be programmed to monitor the three zero-crossings of the inductor current ripple.

[0078] The first zero crossing can correspond to driver 10 ( Figure 1 The controller 1170 generates a control signal to turn on switch 21 at the time when the control signal is generated. When this occurs, the controller 1170 can generate a first pulse signal P1, which may correspond, for example, to the combination (T) ON +T OFF At the start of the cycle, switch SW1 is closed (see...) Figure 11 The signal S1. As a result, the inductor current ripple begins to correlate with the supply voltage V. IN The generated current increases proportionally with a predetermined slope. Simultaneously, counter 1140 begins counting integer intervals T during this time period.

[0079] The second zero crossing can correspond to the inductor current in combination (T) ON +T OFFThe time when the cycle ends reaches zero. When this occurs, controller 1170 can generate a second control signal S2 to close switch SW2 (see...). Figure 11 As a result, the analog-to-digital converter 1150 determines the fractional period aT present at the end of the combination period (if any). Digital processing logic 1160 receives the fractional period value a from the analog-to-digital converter 1150 and the final integer n periods T from the counter 1140. Furthermore, when a second zero-crossing is detected, the controller 1170 can generate a second pulse signal P2 to start T. SKIP The beginning of the cycle. At T SKIP The same asynchronous timer / counter can be used in the cycle because capacitor 1130 (see...) Figure 11 It has been discharged and therefore reset to zero.

[0080] The third zero crossing can correspond to the next combination (T) ON +T OFF The start of a cycle can be detected, for example, when the inductor current ripple begins to rise again. The next combination (T) ON +T OFF The start of the cycle and T SKIP The cycle ends in unison. At this time, the controller 1170 can generate a third pulse signal P3, which closes the switch SW2 again to allow the analog-to-digital converter 1150 to input the signal corresponding to T. SKIP The value of a fractional period during the period (if any) (based on the stored capacitor voltage). This fractional period can be represented by bT and is determined by digital processing logic 1160 based on the output of converter 1150. Meanwhile, the output of counter 1140 corresponds to the value at T. SKIP The integer (m) value of the period T during the period counting.

[0081] In T SKIP At the end of the cycle, the output current I of the COT buck regulator in DCM mode OUT It can be determined based on equation (4):

[0082]

[0083] Where n is in (T) ON +T OFF The integer of the T-period count during the period, a is in (T) ON +T OFF The fraction of the count during period T, where m is in T SKIP The integer of the period T during which the count is performed, and b is in T. SKIP The fraction of T periods counted during the period. midThe value of Imid is determined to be the current value that coincides with the midpoint of the inductor ripple current during the TON period. Since TON is a known fixed value, the value of Imid can be determined as previously described in this document.

[0084] In another embodiment, separate asynchronous timer / counter logic can be executed to determine (T) separately. ON +T OFF ) and T SKIP The values ​​of n, a, m, and b in the cycle. In this case, a single controller 1170 can be used to control the timer / counter logic, or a separate controller can be used.

[0085] Figure 14 A method for monitoring the current in a constant on-time regulator is shown, which may be, for example, a constant on-time regulator operating in DCM mode as previously described. The method may employ the operation described herein for DCM mode operation. At 1410, the method includes identifying half of the on-time period of the COT regulator. At 1420, the inductor current present at half the on-time period is determined (in the manner previously described). At 1430, the number (n) of integer periods during the combined on-time and off-time periods is determined. At 1440, a fraction (a) of the integer periods during the combined on-time and off-time periods is determined, if such a fraction exists. At 1450, the number (m) of integer periods present during the jump period is determined. At 1460, a fraction (b) of the integer periods during the jump period is determined, if such a fraction exists. At 1470, the output current of the COT regulator is determined based on the inductor current during half the on-time period and the values ​​n, a, m, and b.

[0086] Figure 15 This shows what can be used to determine the output current I of a COT buck regulator. OUT Another embodiment of the asynchronous timer / counter logic 1500. For example, when using different timer / counter logics to combine (T) separately. ON +T OFF ) and T SKIP When determining the value of equation (4) based on the period, an asynchronous timer / counter logic 1400 can be used. In this case, Figure 11 The timer / counter logic can be used in combination (T) ON +T OFF The period, and the asynchronous timer / counter logic 1400 can be T SKIP Used during the cycle.

[0087] For example, when the load current is relatively small (e.g., below a predetermined value) and a higher level of efficiency is desired, it can be used Figure 15 This embodiment. Because analog-to-digital converters introduce inefficiencies, Figure 15 The embodiment can omit the analog-to-digital converter 1150 and its corresponding switch SW2. By omitting these features, the asynchronous timer / counter logic 1400 can be used only in CCM mode (T ON +T OFF During the cycle and in DCM mode, T SKIP The period is determined by an integer value of the period T. In the latter case, Figure 11 The timer / counter logic can be used in combination (T) ON +T OFF The period, and the asynchronous timer / counter logic 1400 can be T SKIP Used during the cycle. In addition to the analog-to-digital converter 1150 and the second switch SW2, the timer / counter logic 1400 can have... Figure 11 It includes the same features as the timer / counter logic of the controller 1170.

[0088] Even without considering (T) ON +T OFF ) and / or T SKIP The fraction of T in the period, Figure 15 The asynchronous timer / counter logic can also generate accurate It when the load current is small. OUT This is because low load current may be accompanied by a longer T value. SKIP Period, for example, ratio combination (T) ON +T OFF The period is longer. As a result, the integer value of m will be relatively large. When m is greater than a predetermined number, the fractional value of b becomes irrelevant and can therefore be ignored in order to determine the output current I of the COT buck regulator. OUT Therefore, according to one embodiment, the average output current I of the COT buck regulator OUT It can be determined by equation (5), which corresponds to equation (4) when b = 0. It can be based on the known T. ON The fixed value is used to determine the current I in the same manner as previously described. MID .

[0089]

[0090] As Figure 15 The replacement can be used when the load current is small and m is greater than the predetermined value. Figure 11 The asynchronous timer / counter logic. In this case, the controller 1170 can generate a disable signal to turn off the analog-to-digital converter 1150. This allows the values ​​of n, a, and m in equation (5) to be calculated using a single timer / counter logic.

[0091] Figure 16 An embodiment of a COT boost regulator is shown, which can be similar to... Figure 1 The COT buck regulator, in addition to the inductor coupled to the regulator's input, includes an inductor 1510, a switching circuit 1520, and a driver 1530. In operation, the driver 1530 can turn on the first transistor 1521 in the switching circuit to allow the inductor's output to power the load (RL) after being filtered by the capacitor CL. As in the COT buck regulator embodiment, the low-side transistor 1522 is turned on during the on-time TON and turned off during the off-time TOFF. Conversely, the high-side transistor 1521 is turned on during the off-time TOFF of transistor 1522 and turned off during the on-time TON of transistor 1522.

[0092] In addition to these features, the feedback circuit 1540 includes a first comparator 1541, an integrator 1542, and an on-time (T) ON Controller 1543. These features and ripple generator 1544 can be used with Figure 1 The feedback circuit 50 operates in a similar manner. The same waveforms, timer / counter logic, and other circuitry (e.g., Figures 2 to 14 This can be used to determine the average input current I of the COT boost regulator. IN Furthermore, the methods and current monitor embodiments described herein can be applied in a similar manner to determine... Figure 16 The input current of the COT boost regulator.

[0093] The processors, controllers, generators, drivers, comparators, current sensing logic, integrators, converters, counters, and other signal generation and signal processing features disclosed herein can be implemented in logic, including, for example, hardware, software, or both. When implemented at least partially in hardware, the processors, controllers, generators, current sensing logic, drivers, comparators, integrators, converters, counters, and other signal generation and signal processing features can be any of a variety of integrated circuits, including but not limited to application-specific integrated circuits, field-programmable gate arrays, combinations of logic gates, system-on-a-chip, microprocessors, or another type of processing or control circuitry.

[0094] When implemented at least partially in software, the processor, controller, generator, driver, comparator, integrator, current sensing logic, converter, counter, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions executable, for example, by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or any other element besides those described herein. Because the algorithms underlying the formation of the method (or the operation of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operation of the method embodiments can transform the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods described herein.

[0095] Advantages, benefits, solutions to problems, and any elements that may bring about or make more significant any advantage, benefit, or solution shall not be construed as critical, essential, or fundamental features or elements of any or all claims. The invention is defined solely by the appended claims, which include any modifications made during the pending period of this application and all equivalents of those claims.

[0096] While various exemplary embodiments have been described in detail with specific reference to certain exemplary aspects of the invention, it should be understood that the invention is capable of having other exemplary embodiments, and its details can be modified in various obvious ways. It will be apparent to those skilled in the art that variations and modifications can be made within the spirit and scope of the invention. Therefore, the foregoing disclosure, description, and drawings are for illustrative purposes only and are not intended to limit the invention in any way, which is defined only by the claims.

Claims

1. A current monitor, characterized in that, include: Current sensing logic is configured to sense the inductor current at predetermined time points during the operation of a constant on-time regulator. and A processor configured to determine the output current of the constant on-time regulator based on the inductor current sensed at the predetermined time point, wherein the predetermined time point corresponds to half of the on-time period of the constant on-time regulator, which operates in discontinuous conduction mode (DCM). At least one timer / counter logic; the processor is configured to determine the output current by calculating an average value of the output current based on the on-time period, the off-time period, and the jump period, as well as the inductor current sensed at half of the on-time period; The at least one timer / counter logic is configured to: (a) Determine the number of integer periods that exist during a combined period including the on-time period and the off-time period; (b) Determine the fraction of integer periods that exist during the combined period; (c) Determine the number of integer periods that exist during the said jump period; as well as (d) Determine the fraction of the integer period present during the said jump period, The processor is configured to calculate the average value of the output current based on (a) to (d) and the inductor current sensed at half the conduction time period.

2. The current monitor according to claim 1, characterized in that, The constant on-time regulator operates in continuous on-mode (CCM), and the output current is equal to the inductor current sensed at half the on-time period.

3. The current monitor according to claim 2, characterized in that, The transistor of the inductor coupled to the constant on-time regulator is turned on during the on-time period to generate the inductor current.

4. The current monitor according to claim 1, characterized in that, The at least one timer / counter logic is configured to determine the fraction of the integer period in (b) by determining the voltage stored in the capacitor during the combined period, the voltage being between the initial voltage and the timer voltage corresponding to the full integer period.

5. The current monitor according to claim 1, characterized in that, The at least one timer / counter logic is configured to determine the fraction of the integer period in (d) by determining the voltage stored in the capacitor during the jump period, the voltage being between the initial voltage and the timer voltage corresponding to the full integer period.

6. The current monitor according to claim 1, characterized in that, The integer period is less than the conduction time period.

7. A method for monitoring the operation of a circuit, characterized in that, include: Identify the predetermined time point of the constant on-time regulator; Detect the start of the conduction time period of the constant conduction time regulator; The inductor current is sensed at the predetermined time point of the conduction time period; as well as The output current of the constant on-time regulator is determined based on the inductor current sensed at the predetermined time point, wherein the predetermined time point corresponds to half of the on-time period, and the inductor current is sensed at half of the on-time period. The constant on-time regulator operates in discontinuous conduction mode (DCM); The output current is determined by calculating the average value of the output current based on the on-time period, the off-time period, the jump period, and the inductor current sensed at half of the on-time period. The method further includes: (a) Determine the number of integer periods that exist during a combined period including the on-time period and the off-time period; (b) Determine the fraction of integer periods that exist during the combined period; (c) Determine the number of integer periods present during the said jump period; and (d) Determine the fraction of the integer period present during the said jump period, The average value of the output current is calculated based on (a) to (d) and the inductor current sensed at half of the conduction time period.

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