Display Devices

Abstract

A display device includes a display panel, a gate driving unit, a data driving unit and an emission driving unit. The display panel includes a first type of switching element and a second type of switching element different from the first type. The gate driving unit generates a gate signal based on a vertical start signal and a gate clock signal, and provides the gate signal to the display panel. The data driving unit provides a data voltage to the display panel. The emission driving unit provides an emission signal to the display panel. The driving frequency of the display panel has different values ​​according to an input image. The gate clock signal has an activation period of different lengths according to the driving frequency.

Description

Technical Field

[0001] Example embodiments of the inventive concepts relate to a display device. More particularly, example embodiments of the inventive concepts relate to a display device that reduces power consumption and enhances display quality. Background Art

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines and a plurality of pixels. The display panel driver includes a gate driver, a data driver, an emission driver and a drive controller. The gate driver outputs a gate signal to the gate line. The data driver outputs a data voltage to the data line. The emission driver outputs an emission signal to the emission line. The drive controller controls the gate driver, the data driver and the emission driver.

[0003] When an image displayed on the display panel is a static image or the display panel operates in a normally-on mode, the driving frequency of the display panel may be reduced to reduce power consumption.

[0004] When the driving frequency of the display panel changes, display quality may be degraded due to a brightness difference between images according to the driving frequency. Summary of the invention

[0005] Technical issues

[0006] Example embodiments of the inventive concept provide a display device capable of reducing power consumption and enhancing display quality.

[0007] Technical Solution

[0008] In an example embodiment of a display device according to the present invention, the display device includes a display panel, a gate driver, a data driver, and an emission driver. The display panel includes pixels, and the pixels include a first type of switching element and a second type of switching element different from the first type. The gate driver is configured to generate a gate signal based on a vertical start signal and a gate clock signal, and output the gate signal to the display panel. The data driver is configured to output a data voltage to the display panel. The emission driver is configured to output an emission signal to the display panel. The driving frequency of the display panel varies according to an input image. The gate clock signal has an activation period, and the activation period has a length that varies according to the driving frequency.

[0009] In example embodiments, as the driving frequency decreases, the length of the activation period of the gate clock signal may increase.

[0010] In example embodiments, the activation period length of the vertical start signal may vary according to the driving frequency.

[0011] In example embodiments, as the driving frequency decreases, the activation period length of the vertical start signal may increase.

[0012] In example embodiments, the gate signal may include a data write gate signal. An activation period length of the data write gate signal may vary according to a driving frequency.

[0013] In an example embodiment, in the low frequency driving mode, the gate clock signal may swing between a high level and a low level in a write frame for writing data to a pixel. In the low frequency driving mode, the gate clock signal may remain at a low level in a hold frame for holding data written to a pixel.

[0014] In an example embodiment, in the low frequency driving mode, the gate clock signal may swing between a high level and a low level in a write frame for writing data to a pixel. In the low frequency driving mode, the gate clock signal may remain at a high level in a hold frame for holding data written to a pixel.

[0015] In example embodiments, the first type switching element may be a polysilicon thin film transistor. The second type switching element may be an oxide thin film transistor.

[0016] In an example embodiment, the first type of switching element may be a P-type transistor. The second type of switching element may be an N-type transistor.

[0017] In an example embodiment, a pixel may include: a first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second pixel switching element including a control electrode to which a first data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node; a third pixel switching element including a control electrode to which a second data write gate signal is applied, an input electrode connected to the first node, and an output electrode connected to the third node; a fourth pixel switching element including a control electrode to which a data initialization gate signal is applied, an input electrode to which an initialization voltage is applied, and an output electrode connected to the first node; a fifth pixel switching element including a control electrode to which an emission signal is applied, an input electrode to which a high power voltage is applied, and an output electrode connected to the second node; a sixth pixel switching element including a control electrode to which an emission signal is applied, an input electrode connected to the third node, and an output electrode connected to an anode electrode of an organic light emitting element; a seventh pixel switching element including a control electrode to which an organic light emitting element initialization gate signal is applied, an input electrode to which an initialization voltage is applied, and an output electrode connected to the anode electrode of the organic light emitting element; and a storage capacitor including a first electrode to which a high power voltage is applied and a second electrode connected to the first node. The organic light emitting element may include an anode electrode connected to the output electrode of the sixth pixel switching element and a cathode electrode to which a low power voltage is applied.

[0018] In example embodiments, the first pixel switching element, the second pixel switching element, the fifth pixel switching element, and the sixth pixel switching element may be polysilicon thin film transistors. The third pixel switching element, the fourth pixel switching element, and the seventh pixel switching element may be oxide thin film transistors.

[0019] In an example embodiment, a pixel may include: a first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second pixel switching element including a control electrode to which a first data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node; a third pixel switching element including a control electrode to which a second data write gate signal is applied, an input electrode connected to the first node, and an output electrode connected to the third node; a fourth pixel switching element including a control electrode to which a data initialization gate signal is applied, an input electrode to which an initialization voltage is applied, and an output electrode connected to the first node; a fifth pixel switching element including a control electrode to which an emission signal is applied, an input electrode to which a high power voltage is applied, and an output electrode connected to the second node; a sixth pixel switching element including a control electrode to which an emission signal is applied, an input electrode connected to the third node, and an output electrode connected to an anode electrode of an organic light emitting element; a seventh pixel switching element including a control electrode to which an emission signal is applied, an input electrode to which an initialization voltage is applied, and an output electrode connected to the anode electrode of an organic light emitting element; and a storage capacitor including a first electrode to which a high power voltage is applied and a second electrode connected to the first node. The organic light emitting element may include an anode electrode connected to an output electrode of the sixth pixel switching element and a cathode electrode to which a low power voltage is applied. In an example embodiment, the first pixel switching element, the second pixel switching element, the fifth pixel switching element, the sixth pixel switching element, and the seventh pixel switching element may be polysilicon thin film transistors. The third pixel switching element and the fourth pixel switching element may be oxide thin film transistors.

[0020] In an example embodiment, the display panel driver may be configured to drive the first type switching element and the second type switching element at a high driving frequency in the high frequency driving mode. The display panel driver may be configured to drive the first type switching element and the second type switching element at a low driving frequency in the low frequency driving mode.

[0021] In an example embodiment, the display panel driver may be configured to drive the first type of switching element and the second type of switching element at a high driving frequency in the high frequency driving mode. The display panel driver may be configured to drive the first type of switching element at a high driving frequency in the hybrid driving mode, and drive the second type of switching element at a low driving frequency less than the high driving frequency.

[0022] In an exemplary embodiment of a display device according to the present invention, the display device includes a display panel, a gate driver, a data driver, and an emission driver. The display panel includes pixels, and the pixels include a first type of switching element and a second type of switching element different from the first type. The gate driver is configured to output a gate signal to the display panel. The data driver is configured to output a data voltage to the display panel. The emission driver is configured to output an emission signal to the display panel. The driving frequency of the display panel can vary according to the input image. The high power voltage applied to the pixel can vary according to the driving frequency.

[0023] In example embodiments, as the driving frequency decreases, the level of the high power voltage may decrease.

[0024] In example embodiments, the high power voltage applied to the pixel may vary according to the driving frequency. Over time, the high power voltage may gradually change to a target level.

[0025] In an example embodiment of a display device according to the concept of the present invention, the display device includes a display panel, a gate driver, a data driver and an emission driver. The display panel includes pixels, and the pixels include a first type of switching element and a second type of switching element different from the first type. The gate driver is configured to output a gate signal to the display panel. The data driver is configured to output a data voltage to the display panel. The emission driver is configured to output an emission signal to the display panel. The driving frequency of the display panel can vary according to the input image. The gate turn-on voltage that defines the high level of the gate signal can vary according to the driving frequency.

[0026] In example embodiments, as the driving frequency decreases, the level of the gate-on voltage may increase.

[0027] Technical Effects

[0028] According to the display device, a gate clock signal having an activation period length varying according to a driving frequency may be applied to the gate driver. Therefore, a brightness difference between images of the display panel according to the driving frequency may be compensated, so that the display quality of the display panel may be enhanced.

[0029] In addition, a high power voltage having a level that varies according to the driving frequency can be applied to the pixel. Therefore, a brightness difference between images of the display panel according to the driving frequency can be compensated, so that the display quality of the display panel can be enhanced.

[0030] In addition, a gate-on voltage having a level varying according to the driving frequency may be applied to the gate driver. Therefore, a brightness difference between images of the display panel according to the driving frequency may be compensated, so that the display quality of the display panel may be enhanced.

[0031] Therefore, display quality degradation generated in a low-frequency driving mode can be resolved, so that power consumption of the display device can be reduced and the display quality of the display panel can be enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a block diagram illustrating a display device according to an example embodiment of the inventive concept.

[0033] Figure 2 It is shown Figure 1 Circuit diagram of a pixel of a display panel.

[0034] Figure 3 is shown applied to Figure 2 Timing diagram of the pixel input signal.

[0035] Figure 4a is shown in low frequency drive mode applied to Figure 2 A timing diagram of signals of pixels of a display panel.

[0036] Figure 4b is shown in the low frequency hybrid drive mode applied to Figure 2 A timing diagram of signals of pixels of a display panel.

[0037] Figure 5 It shows that according to Figure 1 The driving frequency of the display panel is applied to Figure 1 1. A table showing an activation period of a vertical start signal and an activation period of a gate clock signal of a gate driver.

[0038] Figure 6a is shown in the high frequency drive mode applied to Figure 1 Timing diagram of the vertical start signal and gate clock signal of the gate driver.

[0039] Figure 6b is shown in low frequency drive mode applied to Figure 1 Timing diagram of the vertical start signal and gate clock signal of the gate driver.

[0040] Figure 7a is shown in the high frequency drive mode applied to Figure 2 A timing diagram of the input signals to the pixels of the display panel.

[0041] Figure 7b is shown in low frequency drive mode applied to Figure 2 A timing diagram of the input signals to the pixels of the display panel.

[0042] Figure 8is a timing diagram illustrating a vertical start signal and a gate clock signal applied to a gate driver in a low frequency driving mode of a display panel according to an example embodiment of the inventive concept.

[0043] Fig. 9 is a timing diagram illustrating a vertical start signal and a gate clock signal applied to a gate driver in a low frequency driving mode of a display panel according to an example embodiment of the inventive concept.

[0044] Fig.10 is a table showing levels of high power voltages applied to pixels according to driving frequencies of display panels according to example embodiments of the inventive concepts.

[0045] Fig.11 It shows that when the high power voltage is not compensated according to the driving frequency Fig.10 A timing diagram of the gate voltage of the first pixel switching element of the display panel.

[0046] Fig.12 is shown when compensating the high power voltage according to the driving frequency Fig.10 FIG. 1 is an example timing diagram of a high power voltage of a display panel.

[0047] Fig.13 is shown when compensating the high power voltage according to the driving frequency Fig.10 FIG. 1 is an example timing diagram of a high power voltage of a display panel.

[0048] Fig.14 is a table showing a gate-on voltage applied to a gate driver according to a driving frequency of a display panel according to an example embodiment of the inventive concept.

[0049] Fig.15 is a graph showing that when the gate on voltage is compensated according to the driving frequency Fig.14 Timing diagram of the gate turn-on voltage of the gate driver.

[0050] Fig.16 is a circuit diagram illustrating a pixel of a display panel according to an example embodiment of the inventive concept.

[0051] Fig.17 is a circuit diagram illustrating a pixel of a display panel according to an example embodiment of the inventive concept.

[0052] Fig.18 is shown applied to Fig.17 A timing diagram of the input signals to the pixels of the display panel. DETAILED DESCRIPTION

[0053] Hereinafter, the inventive concept will be explained in detail with reference to the accompanying drawings.

[0054] Figure 1is a block diagram illustrating a display device according to an example embodiment of the inventive concept.

[0055] Reference Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0056] The display panel 100 has a display area on which an image is displayed and a peripheral area adjacent to the display area.

[0057] The display panel 100 includes a plurality of gate lines GWPL, GWNL, GIL, and GBL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of pixels electrically connected to the gate lines GWPL, GWNL, GIL, and GBL, the data lines DL, and the emission lines EL. The gate lines GWPL, GWNL, GIL, and GBL may extend in a first direction D1, the data lines DL may extend in a second direction D2 crossing the first direction D1, and the emission lines EL may extend in the first direction D1.

[0058] The drive controller 200 receives input image data IMG and input control signal CONT from an external device (not shown). For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0059] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0060] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0061] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0062] The driving controller 200 generates a data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.

[0063] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400 .

[0064] The driving controller 200 generates a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the emission driver 600 .

[0065] The gate driver 300 generates gate signals driving the gate lines GWPL, GWNL, GIL, and GBL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may sequentially output the gate signals to the gate lines GWPL, GWNL, GIL, and GBL.

[0066] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0067] In example embodiments, the gamma reference voltage generator 400 may be provided in the driving controller 200 or in the data driver 500 .

[0068] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200 and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into a data voltage having an analog type using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

[0069] The emission driver 600 generates an emission signal to drive the emission line EL in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal to the emission line EL.

[0070] Figure 2 It is shown Figure 1 1 is a circuit diagram of a pixel of the display panel 100. Figure 3 is shown applied to Figure 2 Timing diagram of the pixel input signal.

[0071] Reference Figures 1 to 3 The display panel 100 includes a plurality of pixels. Each pixel includes an organic light emitting element OLED.

[0072] The pixel receives data write gate signals GWP and GWN, data initialization gate signal GI, organic light emitting element initialization gate signal GB, data voltage VDATA and emission signal EM, and the organic light emitting element OLED of the pixel emits light corresponding to the level of data voltage VDATA to display an image.

[0073] In this example embodiment, the pixel may include a first type of switching element and a second type of switching element different from the first type. For example, the first type of switching element may be a polysilicon thin film transistor. For example, the first type of switching element may be a low temperature polysilicon (LTPS) thin film transistor. For example, the second type of switching element may be an oxide thin film transistor. For example, the first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor.

[0074] For example, the data write gate signal may include a first data write gate signal GWP and a second data write gate signal GWN. The first data write gate signal GWP may be applied to a P-type transistor so that the first data write gate signal GWP has a low-level activation signal corresponding to the data write timing. The second data write gate signal GWN may be applied to an N-type transistor so that the second data write gate signal GWN has a high-level activation signal corresponding to the data write timing.

[0075] At least one of the pixels may include first to seventh pixel switching elements T1 to T7 , a storage capacitor CST, and an organic light emitting element OLED.

[0076] The first pixel switching element T1 includes a control electrode connected to the first node N1, an input electrode connected to the second node N2, and an output electrode connected to the third node N3.

[0077] For example, the first pixel switch element T1 may be a polysilicon thin film transistor. For example, the first pixel switch element T1 may be a P-type thin film transistor. The control electrode of the first pixel switch element T1 may be a gate electrode, the input electrode of the first pixel switch element T1 may be a source electrode, and the output electrode of the first pixel switch element T1 may be a drain electrode.

[0078] The second pixel switching element T2 includes a control electrode to which the first data write gate signal GWP is applied, an input electrode to which the data voltage VDATA is applied, and an output electrode connected to the second node N2.

[0079] For example, the second pixel switch element T2 may be a polysilicon thin film transistor. For example, the second pixel switch element T2 may be a P-type thin film transistor. The control electrode of the second pixel switch element T2 may be a gate electrode, the input electrode of the second pixel switch element T2 may be a source electrode, and the output electrode of the second pixel switch element T2 may be a drain electrode.

[0080] The third pixel switching element T3 includes a control electrode to which the second data write gate signal GWN is applied, an input electrode connected to the first node N1, and an output electrode connected to the third node N3.

[0081] For example, the third pixel switch element T3 may be an oxide thin film transistor. For example, the third pixel switch element T3 may be an N-type thin film transistor. The control electrode of the third pixel switch element T3 may be a gate electrode, the input electrode of the third pixel switch element T3 may be a source electrode, and the output electrode of the third pixel switch element T3 may be a drain electrode.

[0082] The fourth pixel switching element T4 includes a control electrode to which the data initialization gate signal GI is applied, an input electrode to which the initialization voltage VI is applied, and an output electrode connected to the first node N1.

[0083] For example, the fourth pixel switch element T4 may be an oxide thin film transistor. For example, the fourth pixel switch element T4 may be an N-type thin film transistor. The control electrode of the fourth pixel switch element T4 may be a gate electrode, the input electrode of the fourth pixel switch element T4 may be a source electrode, and the output electrode of the fourth pixel switch element T4 may be a drain electrode.

[0084] The fifth pixel switching element T5 includes a control electrode to which the emission signal EM is applied, an input electrode to which the high power voltage ELVDD is applied, and an output electrode connected to the second node N2.

[0085] For example, the fifth pixel switch element T5 may be a polysilicon thin film transistor. For example, the fifth pixel switch element T5 may be a P-type thin film transistor. The control electrode of the fifth pixel switch element T5 may be a gate electrode, the input electrode of the fifth pixel switch element T5 may be a source electrode, and the output electrode of the fifth pixel switch element T5 may be a drain electrode.

[0086] The sixth pixel switching element T6 includes a control electrode to which the emission signal EM is applied, an input electrode connected to the third node N3, and an output electrode connected to the anode electrode of the organic light emitting element OLED.

[0087] For example, the sixth pixel switch element T6 may be a polysilicon thin film transistor. For example, the sixth pixel switch element T6 may be a P-type thin film transistor. The control electrode of the sixth pixel switch element T6 may be a gate electrode, the input electrode of the sixth pixel switch element T6 may be a source electrode, and the output electrode of the sixth pixel switch element T6 may be a drain electrode.

[0088] The seventh pixel switching element T7 includes a control electrode to which the organic light emitting element initialization gate signal GB is applied, an input electrode to which the initialization voltage V1 is applied, and an output electrode connected to the anode electrode of the organic light emitting element OLED.

[0089] For example, the seventh pixel switch element T7 may be an oxide thin film transistor. For example, the seventh pixel switch element T7 may be an N-type thin film transistor. The control electrode of the seventh pixel switch element T7 may be a gate electrode, the input electrode of the seventh pixel switch element T7 may be a source electrode, and the output electrode of the seventh pixel switch element T7 may be a drain electrode.

[0090] The storage capacitor CST includes a first electrode to which the high power voltage ELVDD is applied and a second electrode connected to the first node N1.

[0091] The organic light emitting element OLED includes an anode electrode and a cathode electrode to which a low power voltage ELVSS is applied.

[0092] exist Figure 3 During the first period DU1, the first node N1 and the storage capacitor CST are initialized in response to the data initialization gate signal GI. During the second period DU2, the threshold voltage |VTH| of the first pixel switch element T1 is compensated, and the data voltage VDATA compensated for the threshold voltage |VTH| is written to the first node N1 in response to the first data write gate signal GWP and the second data write gate signal GWN. During the third period DU3, the anode electrode of the organic light emitting element OLED is initialized in response to the organic light emitting element initialization gate signal GB. During the fourth period DU4, the organic light emitting element OLED emits light in response to the emission signal EM, so that the display panel 100 displays an image.

[0093] Although the emission cut-off period of the emission signal EM corresponds to the first period DU1, the second period DU2, and the third period DU3 in the present exemplary embodiment, the inventive concept is not limited thereto. The emission cut-off period of the emission signal EM may be set to include the data writing period DU2. The emission cut-off period of the emission signal EM may be longer than the sum of the first period DU1, the second period DU2, and the third period DU3.

[0094] During the first period DU1, the data initialization gate signal GI may have an activation level. For example, the activation level of the data initialization gate signal GI may be a high level. When the data initialization gate signal GI has an activation level, the fourth pixel switching element T4 is turned on so that the initialization voltage VI may be applied to the first node N1. The data initialization gate signal GI[N] of the current stage may be generated based on the scan signal SCAN[N-1] of the previous stage.

[0095] During the second period DU2, the first data write gate signal GWP and the second data write gate signal GWN may have an activation level. For example, the activation level of the first data write gate signal GWP may be a low level, and the activation level of the second data write gate signal GWN may be a high level. When the first data write gate signal GWP and the second data write gate signal GWN have an activation level, the second pixel switch element T2 and the third pixel switch element T3 are turned on. In addition, the first pixel switch element T1 is turned on in response to the initialization voltage VI. The first data write gate signal GWP[N] of the current stage may be generated based on the scan signal SCAN[N] of the current stage. The second data write gate signal GWN[N] of the current stage may be generated based on the scan signal SCAN[N] of the current stage.

[0096] A voltage obtained by subtracting the absolute value |VTH| of the threshold voltage of the first pixel switching element T1 from the data voltage VDATA may be charged in the storage capacitor CST along a path generated through the first pixel switching element T1 , the second pixel switching element T2 , and the third pixel switching element T3 .

[0097] During the third period DU3, the organic light emitting element initialization gate signal GB may have an activation level. For example, the activation level of the organic light emitting element initialization gate signal GB may be a high level. When the organic light emitting element initialization gate signal GB has an activation level, the seventh pixel switch element T7 is turned on so that the initialization voltage V1 may be applied to the anode electrode of the organic light emitting element OLED. The organic light emitting element initialization gate signal GB[N] of the current stage may be generated based on the scan signal SCAN[N+1] of the next stage.

[0098] During the fourth period DU4, the emission signal EM may have an activation level. The activation level of the emission signal EM may be a low level. When the emission signal EM has an activation level, the fifth pixel switching element T5 and the sixth pixel switching element T6 are turned on. In addition, the first pixel switching element T1 is turned on by the voltage stored in the storage capacitor CST.

[0099] The driving current flows through the fifth pixel switching element T5, the first pixel switching element T1, and the sixth pixel switching element T6 to drive the organic light emitting element OLED. The intensity of the driving current can be determined by the level of the data voltage VDATA. The brightness of the organic light emitting element OLED is determined by the intensity of the driving current. The driving current ISD flowing through the path from the input electrode of the first pixel switching element T1 to the output electrode of the first pixel switching element T1 is determined as shown in the following equation 1.

[0100] [Equation 1]

[0101]

[0102] In Equation 1, μ is the mobility of the first pixel switch element T1. Cox is the capacitance per unit area of ​​the first pixel switch element T1. W / L is the width-to-length ratio of the first pixel switch element T1. VSG is the voltage between the input electrode (or the second node N2) of the first pixel switch element T1 and the control electrode (or the first node N1) of the first pixel switch element T1. |VTH| is the threshold voltage of the first pixel switch element T1.

[0103] The voltage VG of the first node N1 after compensating the threshold voltage |VTH| during the second period DU2 may be expressed as Equation 2 below.

[0104] [Equation 2]

[0105] VG=VDATA-|VTH|

[0106] When the organic light emitting element OLED emits light during the fourth period DU4 , the driving voltage VOV and the driving current ISD may be expressed as the following Equations 3 and 4. In Equation 3, VS is the voltage of the second node N2 .

[0107] [Equation 3]

[0108] VOV=VS-VG-|VTH|=ELVDD-(VDATA-|VTH|)-|VTH|=ELVDD-VDATA

[0109] [Equation 4]

[0110]

[0111] The threshold voltage |VTH| is compensated during the second period DU2 so that when the organic light emitting element OLED emits light during the fourth period DU4 , the driving current ISD may be determined regardless of the threshold voltage |VTH| of the first pixel switching element T1 .

[0112] In this example embodiment, when the image displayed on the display panel 100 is a static image or the display panel is operated in the always-on mode, the driving frequency of the display panel 100 can be reduced to reduce power consumption. When all of the switching elements of the pixels of the display panel 100 are polysilicon thin film transistors, flickering may occur due to the leakage current of the pixel switching elements in the low-frequency driving mode. Therefore, some of the pixel switching elements may be designed using oxide thin film transistors. In this example embodiment, the third pixel switching element T3, the fourth pixel switching element T4, and the seventh pixel switching element T7 may be oxide thin film transistors. The first pixel switching element T1, the second pixel switching element T2, the fifth pixel switching element T5, and the sixth pixel switching element T6 may be polysilicon thin film transistors.

[0113] Figure 4a is shown in low frequency drive mode applied to Figure 2 A timing diagram of signals of pixels of a display panel. Figure 4b is shown in the low frequency hybrid drive mode applied to Figure 2 A timing diagram of signals of pixels of a display panel.

[0114] Reference Figures 1 to 4b , the display panel 100 may be driven in a first mode and a second mode. In the first mode, the display panel driver may drive at least one of the first type of switching elements (e.g., T2, T5, and T6) and at least one of the second type of switching elements (e.g., T3 and T4) at a high driving frequency. In the second mode, the display panel driver may drive at least one of the first type of switching elements (e.g., T2, T5, and T6) at a high driving frequency, and drive at least one of the second type of switching elements (e.g., T3 and T4) at a low driving frequency that is less than the high driving frequency.

[0115] The first mode may be a high frequency driving mode. The second mode may be a low frequency hybrid driving mode.

[0116] However, in the second mode, all of the second type of switching elements may not be driven at a low driving frequency. The second type of switching element (e.g., T7) may be an element for initializing the organic light emitting element, so that the seventh pixel switching element T7 may be driven at a high driving frequency like the fifth pixel switching element T5 and the sixth pixel switching element T6 in the second mode.

[0117] Alternatively, in the third mode, the display panel driver may drive at least one of the first type switching elements and at least one of the second type switching elements at a low driving frequency.

[0118] The first mode may be a high frequency driving mode. The third mode may be a low frequency driving mode.

[0119] The display panel driver (eg, the driving controller 200) may analyze the input image. The display panel driver may determine whether the input image is a moving image or a still image.

[0120] When the input image is a moving image, the display panel 100 may be driven in the high frequency driving mode. When the input image is a static image, the display panel 100 may be driven in the low frequency hybrid driving mode or in the low frequency driving mode.

[0121] Figure 4a Signal indicating low frequency driving mode. In the low frequency driving mode, the emission signal EM, the first data writing gate signal GWP, the data initialization gate signal GI, the second data writing gate signal GWN and the organic light emitting element initialization gate signal GB can be driven at a low driving frequency.

[0122] exist Figure 4a The high driving frequency may be 60 Hz, and the low driving frequency may be 1 Hz. Here, in the low frequency driving mode, in one second, the write operation WRITE is performed in one frame, and the hold operation HOLD is performed in fifty-nine frames.

[0123] Figure 4b Signal indicating low frequency hybrid driving mode. In the low frequency hybrid driving mode, the emission signal EM, the first data write gate signal GWP and the organic light emitting element initialization gate signal GB may be driven at a high driving frequency, and the data initialization gate signal GI and the second data write gate signal GWN may be driven at a low driving frequency.

[0124] exist Figure 4b In the low-frequency hybrid driving mode, the high driving frequency may be 60 Hz, and the low driving frequency may be 1 Hz. Here, in the low-frequency hybrid driving mode, in one second, a write operation WRITE is performed in one frame, and a hold operation HOLD is performed in fifty-nine frames. In the hold operation HOLD, the organic light emitting element may be repeatedly turned on and off.

[0125] The low frequency driving mode may be better than the low frequency hybrid driving mode in terms of energy saving, but depending on the input image, the user may visually perceive flicker in the low frequency driving mode. Therefore, the display panel 100 may be selectively driven in the low frequency driving mode and the low frequency hybrid driving mode.

[0126] Figure 5 It shows that according to Figure 1 The driving frequency of the display panel is applied to Figure 1 1. A table showing an activation period of a vertical start signal and an activation period of a gate clock signal of a gate driver. Figure 6ais shown in the high frequency drive mode applied to Figure 1 Timing diagram of the vertical start signal and gate clock signal of the gate driver. Figure 6b is shown in low frequency drive mode applied to Figure 1 Timing diagram of the vertical start signal and gate clock signal of the gate driver. Figure 7a is shown in the high frequency drive mode applied to Figure 2 A timing diagram of the input signals to the pixels of the display panel. Figure 7b is shown in low frequency drive mode applied to Figure 2 A timing diagram of the input signals to the pixels of the display panel.

[0127] Reference Figures 1 to 7b , the driving frequency of the display panel 100 may vary according to the input images I1, I2, and I3. For example, the driving frequency of the display panel 100 may be determined to be one of 60 Hz, 30 Hz, 20 Hz, 10 Hz, 2 Hz, and 1 Hz according to the input image.

[0128] The gate driver 300 may generate gate signals based on the vertical start signal FLM and the gate clock signal CLK and output the gate signals to the display panel 100. For example, the gate signals may include data write gate signals GWP and GWN, data initialization gate signal GI, and organic light emitting element initialization gate signal GB.

[0129] In the present example embodiment, the gate clock signal CLK may have an active period of a length varying according to a driving frequency. As the driving frequency decreases, the length of the active period of the gate clock signal CLK may become longer.

[0130] When the display panel 100 is driven at a high driving frequency, Figure 2 The conduction time of the third pixel switch element T3 will be insufficient, and Figure 2 The turned-off fourth pixel switch element T4 leaks current, so that the brightness of the image represented by the pixel is reduced.

[0131] When the length of the activation period of the gate clock signal CLK increases, the length of the activation period of the data write gate signals GWP and GWN, the length of the activation period of the data initialization gate signal GI, and the length of the activation period of the organic light emitting element initialization gate signal GB can increase.

[0132] When the length of the activation period of the gate clock signal CLK increases, the length of the activation period of the second data write gate signal GWN applied to the third pixel switch element T3 can be increased. Therefore, in the low-frequency driving mode (or in the low-frequency hybrid driving mode), the turn-on time of the third pixel switch element T3 can be sufficient, so that the brightness of the image represented by the pixel can be prevented from being reduced.

[0133] In addition, when the length of the activation period of the gate clock signal CLK increases, the length of the activation period of the first data write gate signal GWP applied to the second pixel switch element T2 can increase. Therefore, in the low-frequency driving mode (or in the low-frequency hybrid driving mode), the turn-on time of the second pixel switch element T2 can be sufficient, so that the brightness of the image represented by the pixel can be prevented from being reduced.

[0134] exist Figure 5 , y1 may be equal to or greater than 1, y2 may be equal to or greater than y1, y3 may be equal to or greater than y2, y4 may be equal to or greater than y3, and y5 may be equal to or greater than y4.

[0135] In the present example embodiment, the vertical start signal FLM may have an activation period having a length varying according to a driving frequency. As the driving frequency decreases, the length of the activation period of the vertical start signal FLM may increase.

[0136] When the length of the activation period of the gate clock signal CLK increases, the length of the activation period of the vertical start signal FLM may be set to increase to normally operate the gate driver 300. A single activation period of the vertical start signal FLM may be longer than that of the gate clock signal CLK.

[0137] exist Figure 5 , x1 may be equal to or greater than 1, x2 may be equal to or greater than x1, x3 may be equal to or greater than x2, x4 may be equal to or greater than x3, and x5 may be equal to or greater than x4.

[0138] According to the present exemplary embodiment, the gate clock signal CLK having an active period of length varying according to the driving frequency may be applied to the gate driver 300. Therefore, the brightness difference between images of the display panel 100 according to the driving frequency may be compensated, so that the display quality of the display panel 100 may be enhanced.

[0139] Therefore, the display quality degradation in the low-frequency driving mode (or the low-frequency hybrid driving mode) can be solved, so that the power consumption of the display device can be reduced and the display quality of the display panel 100 can be enhanced.

[0140] Figure 8is a timing diagram illustrating a vertical start signal and a gate clock signal applied to a gate driver in a low frequency driving mode of a display panel according to an example embodiment of the inventive concept.

[0141] In addition to the gate clock signal, the display device according to the present exemplary embodiment is similar to the reference Figures 1 to 7b The display devices of the previously described exemplary embodiments are substantially the same. Therefore, the same reference numerals will be used to refer to the same Figures 1 to 7b The present invention relates to components that are the same as or similar to those described in the previous example embodiments, and any repeated explanation regarding the above elements will be omitted.

[0142] Reference Figures 1 to 5 and Figures 7a to 8 , the driving frequency of the display panel 100 may vary according to the input images I1 and I2. For example, the driving frequency of the display panel 100 may be determined to be one of 60 Hz, 30 Hz, 20 Hz, 10 Hz, 2 Hz, and 1 Hz according to the input image.

[0143] The gate driver 300 may generate gate signals based on the vertical start signal FLM and the gate clock signal CLK and output the gate signals to the display panel 100. For example, the gate signals may include data write gate signals GWP and GWN, data initialization gate signal GI, and organic light emitting element initialization gate signal GB.

[0144] In the present example embodiment, the gate clock signal CLK may have an active period of a length varying according to a driving frequency. As the driving frequency decreases, the length of the active period of the gate clock signal CLK may increase.

[0145] In the low frequency driving mode, the gate clock signal CLK can swing between high and low levels in a writing frame for writing data into a pixel. In the low frequency driving mode, the gate clock signal CLK can maintain a low level in a holding frame for maintaining data written into a pixel.

[0146] According to the present exemplary embodiment, the gate clock signal CLK having an activation period of length varying according to the driving frequency may be applied to the gate driver 300. Therefore, the brightness difference between images of the display panel 100 according to the driving frequency may be compensated, so that the display quality of the display panel 100 may be enhanced.

[0147] In the holding frame of the low-frequency driving mode (or the low-frequency hybrid driving mode), the gate clock signal may not swing but maintain a low level in the holding frame, so that the power consumption of the display device can be further reduced.

[0148] Therefore, display quality degradation generated in the low-frequency driving mode may be resolved, so that power consumption of the display device may be reduced and the display quality of the display panel 100 may be enhanced.

[0149] Fig. 9 is a timing diagram illustrating a vertical start signal and a gate clock signal applied to a gate driver in a low frequency driving mode of a display panel according to an example embodiment of the inventive concept.

[0150] In addition to the gate clock signal, the display device according to the present exemplary embodiment is similar to the reference Figures 1 to 7b The display devices of the previously described exemplary embodiments are substantially the same. Therefore, the same reference numerals will be used to refer to the same Figures 1 to 7b The present invention relates to components that are the same as or similar to those described in the previous example embodiments, and any repeated explanation regarding the above elements will be omitted.

[0151] Reference Figures 1 to 5 , Figure 7a , Figure 7b and Fig. 9 , the driving frequency of the display panel 100 may vary according to the input images I1 and I2. For example, the driving frequency of the display panel 100 may be determined to be one of 60 Hz, 30 Hz, 20 Hz, 10 Hz, 2 Hz, and 1 Hz according to the input image.

[0152] The gate driver 300 may generate gate signals based on the vertical start signal FLM and the gate clock signal CLK and output the gate signals to the display panel 100. For example, the gate signals may include data write gate signals GWP and GWN, data initialization gate signal GI, and organic light emitting element initialization gate signal GB.

[0153] In the present example embodiment, the gate clock signal CLK may have an activation period of a length varying according to a driving frequency. As the driving frequency decreases, the length of the activation period of the gate clock signal CLK may increase.

[0154] In the low frequency driving mode, the gate clock signal CLK can swing between high and low levels in a writing frame for writing data into a pixel. In the low frequency driving mode, the gate clock signal CLK can maintain a high level in a holding frame for maintaining data written into a pixel.

[0155] According to the present exemplary embodiment, the gate clock signal CLK having an activation period of length varying according to the driving frequency may be applied to the gate driver 300. Therefore, the brightness difference between images of the display panel 100 according to the driving frequency may be compensated, so that the display quality of the display panel 100 may be enhanced.

[0156] In the holding frame of the low-frequency driving mode (or the low-frequency hybrid driving mode), the gate clock signal may not swing but maintain a high level in the holding frame, so that the power consumption of the display device can be further reduced.

[0157] Therefore, display quality degradation generated in the low-frequency driving mode may be resolved, so that power consumption of the display device may be reduced and the display quality of the display panel 100 may be enhanced.

[0158] Fig.10 is a table showing levels of the high power voltage ELVDD applied to pixels according to driving frequencies of the display panel 100 according to example embodiments of the inventive concepts. Fig.11 is a graph showing that when the high power voltage ELVDD is not compensated according to the driving frequency Fig.10 1 is a timing diagram of the gate voltage of the first pixel switching element T1 of the display panel 100. Fig.12 is a diagram showing the compensation of the high power voltage ELVDD according to the driving frequency. Fig.10 FIG. 1 is a timing diagram of an example of the high power voltage ELVDD of the display panel 100. FIG. Fig.13 is a diagram showing the compensation of the high power voltage ELVDD according to the driving frequency. Fig.10 FIG. 1 is a timing diagram of an example of the high power voltage ELVDD of the display panel 100. FIG.

[0159] In addition to adjusting the level of the high power voltage applied to the pixel to enhance the display quality, the display device according to the present exemplary embodiment is different from the reference Figures 1 to 7b The display device of the previously described exemplary embodiment is substantially the same. Therefore, the same reference numerals will be used to represent the same Figures 1 to 7b The present invention relates to components that are the same as or similar to those described in the previous example embodiments, and any repeated explanation regarding the above elements will be omitted.

[0160] Reference Figures 1 to 4b and Figures 10 to 13 The driving frequency of the display panel 100 may vary according to the input image. For example, the driving frequency of the display panel 100 may be determined to be one of 60 Hz, 30 Hz, 20 Hz, 10 Hz, 2 Hz, and 1 Hz according to the input image.

[0161] In the present exemplary embodiment, the high power voltage ELVDD applied to the pixels of the display panel 100 may vary according to the driving frequency. As the driving frequency decreases, the level of the high power voltage ELVDD may decrease. Fig.10For example, for a driving frequency of 60 Hz, the high power voltage ELVDD is 4.6 V, for a driving frequency of 30 Hz, the high power voltage ELVDD is 4.4 V, for a driving frequency of 20 Hz, the high power voltage ELVDD is 4.3 V, for a driving frequency of 10 Hz, the high power voltage ELVDD is 4.2 V, for a driving frequency of 2 Hz, the high power voltage ELVDD is 4.1 V, and for a driving frequency of 1 Hz, the high power voltage ELVDD is 4.0 V. However, the inventive concept may not be limited to a specific value of the driving frequency and a specific level of the high power voltage ELVDD.

[0162] like Fig.11 As shown in , over time, the level of the gate voltage Vg of the first pixel switch element T1 of the display panel 100 gradually decreases due to the leakage current. When the level of the gate voltage Vg of the first pixel switch element T1 decreases, the voltage Vsg between the source electrode and the gate electrode of the first pixel switch element T1 increases. When the voltage Vsg between the source electrode and the gate electrode of the first pixel switch element T1 increases, the drain current Id of the first pixel switch element T1 increases. When the drain current Id of the first pixel switch element T1 increases, the brightness of the pixel increases unexpectedly.

[0163] When the display panel 100 is driven in the high-frequency driving mode, the gate voltage Vg of the first pixel switch element T1 is refreshed at a high frequency. However, when the display panel 100 is driven in the low-frequency driving mode (or the low-frequency hybrid driving mode), the gate voltage Vg of the first pixel switch element T1 is refreshed at a low frequency, so that a brightness difference between the high-frequency driving mode and the low-frequency driving mode (or the low-frequency hybrid driving mode) of the pixel is generated.

[0164] In the low frequency driving mode of the display panel 100, when the high power voltage ELVDD decreases, although the gate voltage Vg decreases, the voltage Vsg between the source electrode and the gate electrode does not increase. Therefore, when the high power voltage ELVDD is appropriately adjusted, the brightness difference of the pixel according to the change of the driving frequency can be prevented.

[0165] exist Fig.12 For example, when the driving frequency is changed from a high frequency (60 Hz) to a lower frequency (10 Hz), the level of the high power voltage ELVDD may be reduced to a target level. Fig.13 For example, when the driving frequency changes from a high frequency (60 Hz) to a lower frequency (10 Hz), the level of the high power voltage ELVDD may gradually decrease to a target level over time. When the level of the high power voltage ELVDD gradually decreases to the target level, the falling curve of the level of the high power voltage ELVDD may further approach Fig.11The falling curve of the level of the gate voltage Vg of the first pixel switching element T1 makes it possible to further effectively prevent the brightness difference of the pixel according to the change of the driving frequency.

[0166] According to the present exemplary embodiment, the high power voltage ELVDD having a level varying according to the driving frequency may be applied to the pixel. Therefore, the brightness difference between images of the display panel 100 according to the driving frequency may be compensated, so that the display quality of the display panel 100 may be enhanced.

[0167] Therefore, display quality degradation generated in the low-frequency driving mode (or in the low-frequency hybrid driving mode) can be resolved, so that power consumption of the display device can be reduced and the display quality of the display panel 100 can be enhanced.

[0168] Fig.14 is a table showing a gate-on voltage VGH applied to the gate driver 300 according to a driving frequency of the display panel 100 according to an example embodiment of the inventive concept. Fig.15 is a graph showing that when the gate on voltage is compensated according to the driving frequency Fig.14 1 is a timing diagram of a gate-on voltage VGH of the gate driver 300.

[0169] In addition to adjusting the level of the gate-on voltage applied to the pixel to enhance the display quality, the display device according to the present example embodiment is different from the reference Figures 1 to 7b The display devices of the previously described exemplary embodiments are substantially the same. Therefore, the same reference numerals will be used to refer to the same Figures 1 to 7b The present invention relates to components that are the same as or similar to those described in the previous example embodiments, and any repeated explanation regarding the above elements will be omitted.

[0170] refer to Figures 1 to 4b as well as Fig.14 and Fig.15 The driving frequency of the display panel 100 may vary according to the input image. For example, the driving frequency of the display panel 100 may be determined to be one of 60 Hz, 30 Hz, 20 Hz, 10 Hz, 2 Hz, and 1 Hz according to the input image.

[0171] In this example embodiment, the gate-on voltage VGH applied to the gate driver 300 may vary according to the driving frequency. As the driving frequency decreases, the level of the gate-on voltage VGH may increase. Fig.14For example, for a driving frequency of 60 Hz, the gate-on voltage VGH is 7.0 V, for a driving frequency of 30 Hz, the gate-on voltage VGH is 7.1 V, for a driving frequency of 20 Hz, the gate-on voltage VGH is 7.2 V, for a driving frequency of 10 Hz, the gate-on voltage VGH is 7.3 V, for a driving frequency of 2 Hz, the gate-on voltage VGH is 7.4 V, and for a driving frequency of 1 Hz, the gate-on voltage VGH is 7.5 V. However, the inventive concept may not be limited to a specific value of the driving frequency and a specific level of the gate-on voltage VGH.

[0172] When the display panel 100 is driven at a high driving frequency, Figure 2 The conduction time of the third pixel switch element T3 will be insufficient, and Figure 2 The turned-off fourth pixel switch element T4 leaks current, so that the brightness of the image represented by the pixel is reduced.

[0173] When the level of the gate-on voltage VGH increases, the high levels of the data write gate signals GWP and GWN, the data initialization gate signal GI, and the organic light emitting element initialization gate signal GB may increase.

[0174] When the level of the gate-on voltage VGH increases, the high level of the second data write gate signal GWN applied to the third pixel switch element T3 can increase. Therefore, the driving force of the third pixel switch element T3 can be increased in the low-frequency driving mode (or in the low-frequency hybrid driving mode), so that the brightness of the image represented by the pixel can be prevented from decreasing.

[0175] According to the present exemplary embodiment, the gate-on voltage VGH having a level varying according to the driving frequency may be applied to the gate driver 300. Therefore, the brightness difference between images of the display panel 100 according to the driving frequency may be compensated, so that the display quality of the display panel 100 may be enhanced.

[0176] Therefore, display quality degradation generated in the low-frequency driving mode (or in the low-frequency hybrid driving mode) can be resolved, so that power consumption of the display device can be reduced and the display quality of the display panel 100 can be enhanced.

[0177] Fig.16 is a circuit diagram illustrating a pixel of the display panel 100 according to an example embodiment of the inventive concept.

[0178] Except for the pixel structure, the display device according to the present exemplary embodiment is different from the reference Figures 1 to 7b The display devices of the previously described exemplary embodiments are substantially the same. Therefore, the same reference numerals will be used to refer to the same Figures 1 to 7bThe present invention relates to components that are the same as or similar to those described in the previous example embodiments, and any repeated explanation regarding the above elements will be omitted.

[0179] Reference Figure 1 , Figures 3 to 7b and Fig.16 , at least one of the pixels may include first to seventh pixel switching elements T1 to T7 , a storage capacitor CST, and an organic light emitting element OLED.

[0180] The pixel structure of this exemplary embodiment may be similar to that of the seventh pixel switching element T7 except that the control electrode of the seventh pixel switching element T7 is connected to the control electrode of the sixth pixel switching element T6. Figure 2 The pixel structure is basically the same.

[0181] The emission signal EM is applied to the control electrode of the seventh pixel switch element T7 which is an N-type transistor, so that the seventh pixel switch element T7 is turned on when the emission signal EM has a high level ( Figure 3 DU1 to DU3 in FIG. 1 ). Thus, the organic light emitting element OLED can be initialized.

[0182] In the present example embodiment, the emission signal EM is applied to the seventh pixel switching element T7 , the organic light emitting element initialization gate signal GB may not be generated, and the gate line for applying the organic light emitting element initialization gate signal GB may be omitted.

[0183] Fig.17 is a circuit diagram illustrating a pixel of the display panel 100 according to an example embodiment of the inventive concept. Fig.18 is shown applied to Fig.17 1 is a timing diagram of input signals to pixels of the display panel 100.

[0184] Except for the pixel structure, the display device according to the present exemplary embodiment is different from the reference Figures 1 to 7b The display devices of the previously described exemplary embodiments are substantially the same. Therefore, the same reference numerals will be used to refer to the same Figures 1 to 7b The present invention relates to components that are the same as or similar to those described in the previous example embodiments, and any repeated explanation regarding the above elements will be omitted.

[0185] Reference Figure 1 , Figures 3 to 7b as well as Fig.17 and Fig.18 , at least one of the pixels may include first to seventh pixel switching elements T1 to T7 , a storage capacitor CST, and an organic light emitting element OLED.

[0186] In the present exemplary embodiment, the seventh pixel switching element T7 includes a control electrode to which the organic light emitting element initialization gate signal GB is applied, an input electrode to which the initialization voltage V1 is applied, and an output electrode connected to the anode electrode of the organic light emitting element.

[0187] For example, the seventh pixel switch element T7 may be a polysilicon thin film transistor. For example, the seventh pixel switch element T7 may be a P-type thin film transistor.

[0188] exist Fig.18 During the first period DU1, the first node N1 and the storage capacitor CST are initialized in response to the data initialization gate signal GI. During the second period DU2, the threshold voltage |VTH| of the first pixel switch element T1 is compensated, and the data voltage VDATA compensated for the threshold voltage |VTH| is written to the storage capacitor CST in response to the first data write gate signal GWP and the second data write gate signal GWN. During the third period DU3, the anode electrode of the organic light emitting element OLED is initialized in response to the organic light emitting element initialization gate signal GB. During the fourth period DU4, the organic light emitting element OLED emits light in response to the emission signal EM, so that the display panel 100 displays an image.

[0189] In the present example embodiment, the activation level of the organic light emitting element initialization gate signal GB may be a low level.

[0190] In this example embodiment, some of the pixel switching elements may be designed using oxide thin film transistors. In this example embodiment, the third pixel switching element T3 and the fourth pixel switching element T4 may be oxide thin film transistors. The first pixel switching element T1, the second pixel switching element T2, the fifth pixel switching element T5, the sixth pixel switching element T6, and the seventh pixel switching element T7 may be polysilicon thin film transistors.

[0191] Industrial Applicability

[0192] According to the display device of the inventive concept as explained above, power consumption of the display device can be reduced, and display quality of the display panel can be enhanced.

[0193] Although several example embodiments of the inventive concept have been described, it will be readily appreciated by those skilled in the art that many modifications can be made in the example embodiments without materially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.

[0194] <Description of Reference Numerals>

[0195] 100: Display panel 200: Drive controller

[0196] 300: Gate driver 400: Gamma reference voltage generator

[0197] 500: Data driver 600: Transmitter driver

Claims

1. A display device, comprising: A display panel comprising pixels, the pixels comprising a first type of switching element and a second type of switching element different from the first type; a gate driver configured to generate a gate signal based on a vertical start signal and a gate clock signal, and output the gate signal to the display panel; a data driver configured to output a data voltage to the display panel; as well as an emission driver configured to output an emission signal to the display panel, wherein the driving frequency of the display panel varies according to the input image, and wherein the gate clock signal has an activation period, and the activation period has a length that varies according to the driving frequency, Wherein, in the low-frequency driving mode, in a writing frame for writing data into the pixel, the gate clock signal swings between a high level and a low level, and Wherein, in the low-frequency driving mode, in a holding frame for keeping the data written into the pixel, the gate clock signal maintains the low level.

2. The display device according to claim 1, wherein: As the driving frequency decreases, the length of the active period of the gate clock signal increases.

3. The display device according to claim 2, wherein: The length of the activation period of the vertical start signal varies according to the driving frequency.

4. The display device according to claim 3, wherein: As the driving frequency decreases, the active period length of the vertical start signal increases.

5. The display device according to claim 2, wherein: The gate signal includes a data write gate signal, and The length of the activation period of the data writing gate signal varies according to the driving frequency.

6. The display device according to claim 1, wherein: The switching element of the first type is a polysilicon thin film transistor, and The switching element of the second type is an oxide thin film transistor.

7. The display device according to claim 6, wherein: The switching element of the first type is a P-type transistor, and The switching element of the second type is an N-type transistor.

8. The display device according to claim 6, wherein: The pixels include: A first pixel switching element including a control electrode connected to the first node, an input electrode connected to the second node, and an output electrode connected to the third node; a second pixel switching element, comprising a control electrode to which a first data writing gate signal is applied, an input electrode to which the data voltage is applied, and an output electrode connected to the second node; a third pixel switching element, comprising a control electrode to which a second data writing gate signal is applied, an input electrode connected to the first node, and an output electrode connected to the third node; a fourth pixel switching element, comprising a control electrode to which a data initialization gate signal is applied, an input electrode to which an initialization voltage is applied, and an output electrode connected to the first node; a fifth pixel switching element including a control electrode to which the emission signal is applied, an input electrode to which a high power voltage is applied, and an output electrode connected to the second node; a sixth pixel switching element, comprising a control electrode to which the emission signal is applied, an input electrode connected to the third node, and an output electrode connected to an anode electrode of an organic light emitting element; a seventh pixel switching element, comprising a control electrode to which an organic light emitting element initialization gate signal is applied, an input electrode to which the initialization voltage is applied, and an output electrode connected to the anode electrode of the organic light emitting element; and a storage capacitor including a first electrode to which the high power voltage is applied and a second electrode connected to the first node, and The organic light emitting element includes the anode electrode connected to the output electrode of the sixth pixel switching element and a cathode electrode to which a low power voltage is applied.

9. The display device according to claim 8, wherein: The first pixel switching element, the second pixel switching element, the fifth pixel switching element and the sixth pixel switching element are polysilicon thin film transistors, and Wherein, the third pixel switching element, the fourth pixel switching element and the seventh pixel switching element are oxide thin film transistors.

10. The display device according to claim 8, wherein: The first pixel switching element, the second pixel switching element, the fifth pixel switching element, the sixth pixel switching element and the seventh pixel switching element are polysilicon thin film transistors, and The third pixel switching element and the fourth pixel switching element are the oxide thin film transistors.

11. The display device according to claim 6, wherein: The pixels include: A first pixel switching element including a control electrode connected to the first node, an input electrode connected to the second node, and an output electrode connected to the third node; a second pixel switching element, comprising a control electrode to which a first data writing gate signal is applied, an input electrode to which the data voltage is applied, and an output electrode connected to the second node; a third pixel switching element, comprising a control electrode to which a second data writing gate signal is applied, an input electrode connected to the first node, and an output electrode connected to the third node; a fourth pixel switching element, comprising a control electrode to which a data initialization gate signal is applied, an input electrode to which an initialization voltage is applied, and an output electrode connected to the first node; a fifth pixel switching element including a control electrode to which the emission signal is applied, an input electrode to which a high power voltage is applied, and an output electrode connected to the second node; a sixth pixel switching element, comprising a control electrode to which the emission signal is applied, an input electrode connected to the third node, and an output electrode connected to an anode electrode of an organic light emitting element; a seventh pixel switching element, comprising a control electrode to which the emission signal is applied, an input electrode to which the initialization voltage is applied, and an output electrode connected to the anode electrode of the organic light emitting element; and a storage capacitor including a first electrode to which the high power voltage is applied and a second electrode connected to the first node, and The organic light emitting element includes the anode electrode connected to the output electrode of the sixth pixel switching element and a cathode electrode to which a low power voltage is applied.

12. The display device according to claim 1, wherein: The display panel driver is configured to drive the switching elements of the first type and the switching elements of the second type at a high driving frequency in a high frequency driving mode, and The display panel driver is configured to drive the switching elements of the first type and the switching elements of the second type at a low driving frequency in a low frequency driving mode.

13. The display device according to claim 1, wherein: The display panel driver is configured to drive the switching elements of the first type and the switching elements of the second type at a high driving frequency in a high frequency driving mode, and The display panel driver is configured to drive the first type of switching elements at the high driving frequency and drive the second type of switching elements at a low driving frequency lower than the high driving frequency in a hybrid driving mode.

14. A display device, comprising: A display panel comprising pixels, the pixels comprising a first type of switching element and a second type of switching element different from the first type; a gate driver configured to generate a gate signal based on a vertical start signal and a gate clock signal, and output the gate signal to the display panel; a data driver configured to output a data voltage to the display panel; as well as an emission driver configured to output an emission signal to the display panel, wherein the driving frequency of the display panel varies according to the input image, and wherein the gate clock signal has an activation period, and the activation period has a length that varies according to the driving frequency, Wherein, in the low-frequency driving mode, in a writing frame for writing data into the pixel, the gate clock signal swings between a high level and a low level, and Wherein, in the low-frequency driving mode, in a holding frame for keeping the data written into the pixel, the gate clock signal maintains the high level.

15. A display device, comprising: A display panel comprising pixels, the pixels comprising a first type of switching element and a second type of switching element different from the first type; a gate driver configured to output a gate signal to the display panel; a data driver configured to output a data voltage to the display panel; as well as an emission driver configured to output an emission signal to the display panel, wherein the driving frequency of the display panel varies according to an input image, the driving frequency includes a first driving frequency and a second driving frequency lower than the first driving frequency, and During a period of being driven by the second driving frequency, a high power voltage applied to the pixel is gradually reduced.

16. The display device according to claim 15, wherein: The high power voltage applied to the pixel varies according to the driving frequency, and Wherein, as time goes by, the high power voltage gradually changes to a target level.

17. A display device, comprising: A display panel comprising pixels, the pixels comprising a first type of switching element and a second type of switching element different from the first type; a gate driver configured to output a gate signal to the display panel; a data driver configured to output a data voltage to the display panel; as well as an emission driver configured to output an emission signal to the display panel, The driving frequency of the display panel varies according to an input image, and the driving frequency includes a first driving frequency and a second driving frequency lower than the first driving frequency. As the driving frequency decreases, the level of the gate-on voltage defining the high level of the gate signal increases, and During a period of being driven by the second driving frequency, the level of the gate-on voltage remains unchanged.

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