Arithmetic device and method

Abstract

The present disclosure belongs to the field of computer, and more particularly relates to an operation device and method, the operation device comprising: an operation control module, used for receiving or determining block information; an operation module, used for obtaining a block matrix by block processing an operation matrix according to the block information, and obtaining a transpose matrix of the block matrix by transposing the block matrix according to an operation instruction. The device and method provided by the present disclosure can realize the operation of a matrix of any size within constant time complexity by using a single instruction. Compared with the traditional operation operation implementation method, the operation time complexity is reduced, and the operation operation is also more simple and efficient.

Description

Technical Field

[0001] The present disclosure belongs to the field of computer technology, and more specifically, to a computing device and method. Background Art

[0002] Matrix transposition is a basic mathematical operation used frequently in various fields. In addition to the common matrix transposition (which swaps the rows and columns of a matrix), special matrix transposition operations such as row transposition, column transposition, inverse transposition, 90° left flip, and 90° right flip are also very common in matrix operations. Currently, the common method for using a computer to perform a matrix transposition (including unconventional transpositions, hereinafter referred to as transposition) is to use a general-purpose processor to write a two-layer loop to exchange data at different addresses, with a time complexity of O(n^2). Matrix transposition operations with such a high time complexity can become a bottleneck for improving performance in complex systems, especially when the number of matrix elements is large. Summary of the Invention

[0003] In view of the above problems, the purpose of the present disclosure is to provide a computing device and method for solving at least one of the above technical problems.

[0004] To achieve the above objectives, as one aspect of the present disclosure, a computing device is provided, comprising:

[0005] An operation control module, used for receiving or determining block information;

[0006] The operation module is used to divide the operation matrix into blocks according to the block information to obtain a block matrix, and to transpose the block matrix according to the operation instruction to obtain a transposed matrix of the block matrix.

[0007] In some embodiments, the operation module is further configured to perform a merging operation after the block and transposition operations, and merge the transposed matrices of the block matrices to obtain the transposed matrix of the operation matrix.

[0008] In some embodiments, the operation instructions include a normal transpose instruction, a row transpose instruction, a column transpose instruction, a reverse transpose instruction, a 90° left flip transpose instruction, and a 90° right flip transpose instruction.

[0009] In some embodiments, the computing device further comprises:

[0010] An address storage module, configured to store address information of the operation matrix; and

[0011] A data storage module, used for storing the operation matrix and the transposed matrix after the operation;

[0012] The operation control module is used to receive the address information and block information of the operation matrix, or to extract the address information of the operation matrix from the address storage module, and obtain the block information according to the analysis of the address information of the operation matrix;

[0013] The operation module is used to obtain the address information and block information of the operation matrix from the operation control module, extract the operation matrix from the data storage module according to the address information of the operation matrix, and perform block, transposition and merging operations on the operation matrix to obtain the transposed matrix of the operation matrix, and feed the transposed matrix of the operation matrix back to the data storage module.

[0014] In some embodiments, the operation module includes a matrix blocking unit, a matrix operation unit, and a matrix merging unit, wherein:

[0015] a matrix blocking unit, configured to obtain address information and blocking information of an operation matrix from the operation control module, extract the operation matrix from the data storage module according to the address information of the operation matrix, and block the operation matrix according to the blocking information to obtain n block matrices;

[0016] a matrix operation unit, configured to obtain the n block matrices and perform a transpose operation on the n block matrices according to the operation instruction to obtain a transposed matrix of the n block matrices;

[0017] A matrix merging unit is used to obtain and merge the transposed matrices of the n block matrices to obtain the transposed matrix of the operation matrix, and feed back the transposed matrix of the operation matrix to the data storage module, wherein n is a natural number; wherein the matrix merging unit merges the transposed matrices of the n block matrices according to the merging method corresponding to the transposed method obtained by the operation instruction.

[0018] In some embodiments, the operation module further includes a cache unit for caching the n block matrices for acquisition by the matrix operation unit.

[0019] In some embodiments, the operation control module includes an instruction processing unit, an instruction cache unit, and a matrix judgment unit, wherein:

[0020] An instruction cache unit, used for storing the operation instructions to be executed;

[0021] an instruction processing unit, configured to obtain the operation instruction from the instruction cache unit, decode the operation instruction, and obtain address information of the operation matrix from the address storage module according to the decoded operation instruction;

[0022] The matrix judgment unit is used to analyze the address information of the operation matrix to obtain the block information.

[0023] In some embodiments, the operation control module also includes a dependency processing unit for determining whether the decoded operation instruction and the address information of the operation matrix conflict with the previous operation; if there is a conflict, the decoded operation instruction and the address information of the operation matrix are temporarily stored; if there is no conflict, the decoded operation instruction and the address information of the operation matrix are transmitted to the matrix judgment unit.

[0024] In some embodiments, the operation control module further includes an instruction queue memory for caching the decoded operation instructions and address information of the operation matrix in which the conflict exists, and when the conflict is eliminated, transmitting the cached decoded operation instructions and address information of the operation matrix to the matrix judgment unit.

[0025] In some embodiments, the instruction processing unit includes an instruction fetch unit and a decode unit, wherein:

[0026] an instruction fetch unit, configured to fetch the operation instruction from the instruction cache unit and transmit the operation instruction to the decoding unit;

[0027] A decoding unit is used to decode the operation instruction, extract the address information of the operation matrix from the address storage module according to the decoded operation instruction, and transmit the decoded operation instruction and the extracted address information of the operation matrix to the dependency processing unit.

[0028] In some embodiments, the computing device further comprises:

[0029] A data storage module, used for storing the operation matrix and the transposed matrix after the operation;

[0030] The input and output module is used to input the operation matrix data into the data storage module, and is also used to obtain the transposed matrix after operation from the data storage module and output the transposed matrix after operation.

[0031] In some embodiments, the computing device further includes: an address storage module for storing address information of the computing matrix; the address storage module includes a scalar register stack or a general memory unit; the data storage module includes a high-speed cache memory or a general memory unit; the address information of the computing matrix is ​​the starting address information and matrix size information of the matrix.

[0032] According to another aspect of the present disclosure, a calculation method is provided, comprising the following steps:

[0033] The operation control module receives or determines the block information;

[0034] The operation module divides the operation matrix into blocks according to the block information to obtain a block matrix, and transposes the block matrix according to the operation instruction to obtain a transposed matrix of the block matrix.

[0035] In some embodiments, after the transposition operation step, the method further includes: a merging operation, in which the operation module merges the transposed matrices of the block matrices to obtain the transposed matrix of the operation matrix.

[0036] In some embodiments, the operation instructions include a normal transpose instruction, a row transpose instruction, a column transpose instruction, a reverse transpose instruction, a 90° left flip transpose instruction, and a 90° right flip transpose instruction.

[0037] In some embodiments, the step of determining the block information by the operation control module includes:

[0038] The operation control module extracts address information of the operation matrix from the address storage module; and

[0039] The operation control module determines the block information according to the address information of the operation matrix.

[0040] In some embodiments, the step of the operation control module extracting the address information of the operation matrix from the address storage module includes:

[0041] The instruction fetch unit extracts the operation instruction and sends the operation instruction to the decoding unit;

[0042] The decoding unit decodes the operation instruction, obtains the address information of the operation matrix from the address storage module according to the decoded operation instruction, and sends the decoded operation instruction and the address information of the operation matrix to the dependency processing unit;

[0043] The dependency processing unit analyzes whether there is a data dependency between the decoded operation instruction and the previous instruction that has not yet been executed; if there is a dependency, the address information of the decoded operation instruction and the corresponding operation matrix needs to wait in the instruction queue memory until there is no data dependency between it and the previous instruction that has not been executed.

[0044] In some embodiments, the operation module performs block division, transposition, and merging operations on the operation matrix according to the block information to obtain a transposed matrix of the operation matrix, including:

[0045] The matrix block unit of the operation module extracts the operation matrix from the data storage module according to the address information of the operation matrix; and divides the operation matrix into n block matrices according to the block information;

[0046] The matrix operation unit of the operation module performs transposition operation on the n block matrices according to the operation instruction to obtain transposed matrices of the n block matrices; and

[0047] The matrix merging unit of the operation module merges the transposed matrices of the n block matrices to obtain the transposed matrix of the operation matrix and feeds it back to the data storage module;

[0048] Wherein, n is a natural number.

[0049] In some embodiments, the operation module combines the transposed matrices of the n block matrices to obtain the transposed matrix of the operation matrix, and feeds the transposed matrix back to the data storage module, including:

[0050] The matrix merging unit receives the transposed matrix of each block matrix. When the number of received transposed matrices of the block matrices reaches the total number of blocks, the matrix merging unit performs a matrix merging operation on all blocks to obtain the transposed matrix of the operation matrix; and feeds the transposed matrix back to the specified address of the data storage module.

[0051] The input-output module directly accesses the data storage module and reads the transposed matrix of the operation matrix obtained by operation from the data storage module.

[0052] The computing device and method proposed in this disclosure can partition a computational matrix into blocks, perform transposition operations on each of the block matrices to obtain the transposed matrices of the multiple block matrices, and finally combine the transposed matrices of the multiple block matrices to obtain the transposed matrix of the computational matrix. This allows the transposition of matrices of any size to be performed within constant time complexity using a single instruction. Compared to traditional matrix transposition methods, this reduces the time complexity of the operation while also making the matrix transposition operation simpler and more efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 It is a structural diagram of the computing device proposed in this disclosure.

[0054] Figure 2 It is a schematic diagram of the information flow of the computing device proposed in this disclosure.

[0055] Figure 3 It is a structural diagram of the computing module in the computing device proposed in the present disclosure.

[0056] Figure 4 This is a schematic diagram of the matrix operation performed by the operation module proposed in the present disclosure.

[0057] Figure 5 This is another schematic diagram of the operation module proposed in the present disclosure performing matrix operations.

[0058] Figure 6It is a structural diagram of the operation control module in the operation device proposed in this disclosure.

[0059] Figure 7 Schematic diagram of the detailed structure of a computing device proposed in one embodiment of the present disclosure.

[0060] Figure 8 It is a flowchart of an operation method proposed in another embodiment of the present disclosure.

[0061] Figure 9 Schematic diagram of another structure of the computing device proposed in the present disclosure.

[0062] Figure 10 This is another information flow diagram of the computing device proposed in this disclosure.

[0063] Figure 11 It is a structural diagram of the iterative block unit proposed in this disclosure.

[0064] Figure 12 This is another structural diagram of the matrix operation unit proposed in the present disclosure.

[0065] Figure 13 This is another structural diagram of the iterative merging operation unit proposed in the present disclosure. DETAILED DESCRIPTION

[0066] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0067] The present disclosure provides a computing device, comprising:

[0068] An operation control module, used for receiving or determining block information;

[0069] The operation module is used to divide the operation matrix into blocks according to the block information to obtain a block matrix, and to transpose the block matrix according to the operation instruction to obtain a transposed matrix of the block matrix.

[0070] The operation module is further configured to perform a merging operation after the block and transposition operations, and to merge the transposed matrices of the block matrices to obtain the transposed matrix of the operation matrix.

[0071] The operation module performs a transposition operation on the matrix according to the transposition method obtained by the operation instruction. The operation instruction includes a conventional transposition instruction (a conventional transposition is to mirror-reverse all elements of matrix A around a ray 45 degrees to the lower right starting from the element of the first row and the first column, thus obtaining the transposition of A), a row transposition instruction, a column transposition instruction, a reverse transposition instruction, a 90° left flip transposition instruction, a 90° right flip transposition instruction, etc. The operation instruction includes at least the instruction type, data type, matrix first address, number of matrix rows, number of matrix columns, and target storage address. The specific format is shown in Table 1.

[0072] Table 1 Operation instruction format

[0073]

[0074]

[0075] The following examples illustrate the operation instructions involved in the transposition operation of the present disclosure and their corresponding transposition methods.

[0076] Taking the operation instruction MTRAN as an example, a matrix transpose operation is performed on a given matrix. In a specific implementation, given a square matrix A, the transpose of the matrix A is calculated according to the following formula (taking a 4x4 matrix as an example).

[0077]

[0078] Taking the operation instruction MRTRAN as an example, a matrix operation is performed on a given matrix. In a specific implementation, given a square matrix A, the transpose of the matrix A is calculated according to the following formula (taking a 4x4 matrix as an example).

[0079]

[0080] Taking the operation instruction MCTRAN as an example, a matrix column transpose operation is performed on a given matrix. In a specific implementation, given a square matrix A, the transpose of the matrix A is calculated according to the following formula (taking a 4x4 matrix as an example).

[0081]

[0082] Taking the operation instruction of matrix inverse transpose MOTRAN as an example, the matrix inverse transpose operation is performed on a given matrix. In a specific implementation, given a square matrix A, the transpose of the matrix A is calculated according to the following formula (taking a 4x4 matrix as an example).

[0083]

[0084] Taking the operation instruction "Matrix Transpose 90° Left" MLTTRAN as an example, a matrix transpose operation is performed on a given matrix. In a specific implementation, given a square matrix A, the transpose of the matrix A is calculated according to the following formula (taking a 4x4 matrix as an example).

[0085]

[0086] Taking the operation instruction "90° right flip MRTTRAN" as an example, a matrix transpose operation is performed on a given matrix. In a specific implementation, given a square matrix A, the transpose of the matrix A is calculated according to the following formula (taking a 4x4 matrix as an example).

[0087]

[0088] Specifically, the block information may include at least one of block size information, block method information, and block merging information. The block size information indicates the size information of each block matrix obtained after the operation matrix is ​​divided into blocks. The block method information indicates the method for dividing the operation matrix into blocks. The block merging information indicates the method for re-merging the transposed matrix of the operation matrix after performing a transpose operation on each block matrix.

[0089] Because the computing device disclosed herein can divide the computational matrix into blocks, obtain the transposed matrices of the multiple block matrices by performing transposition operations on each of the multiple block matrices, and finally combine the transposed matrices of the multiple block matrices to obtain the transposed matrix of the computational matrix, it is possible to perform the transposition operation of matrices of any size within constant time complexity using a single instruction. Compared to traditional matrix transposition operation implementation methods, the present disclosure reduces the operation time complexity while also making the use of the matrix transposition operation simpler and more efficient.

[0090] like Figure 1-2 As shown, in some embodiments of the present disclosure, the computing device further includes: a computing control module 2 , a computing module 3 , an address storage module 1 and a data storage module 4 .

[0091] Specifically, the operation control module is used to receive or determine the block information;

[0092] The operation module is configured to perform block and transposition operations on the operation matrix to obtain a transposed matrix of the operation matrix; further, the operation module blocks the operation matrix according to the block information to obtain a block matrix, and transposes the block matrix according to the operation instruction to obtain a transposed matrix of the block matrix. Furthermore, the operation module is further configured to perform a merge operation after the block and transposition operations, merging the transposed matrices of the block matrices to obtain a transposed matrix of the operation matrix.

[0093] An address storage module, used for storing address information of the operation matrix; and

[0094] A data storage module, configured to store original matrix data, including the operation matrix, and store the transposed matrix after the operation;

[0095] Among them, the operation control module is used to receive the address information and block information of the operation matrix, or to extract the address information of the operation matrix from the address storage module, and obtain the block information according to the address information of the operation matrix; the operation module is used to obtain the address information and block information of the operation matrix from the operation control module, extract the operation matrix from the data storage module according to the address information of the operation matrix, block the operation matrix according to the block information, transpose the block matrix according to the operation instruction, and merge the matrix obtained after the transposition of the block matrix to obtain the transposed matrix of the operation matrix, and feed the transposed matrix of the operation matrix back to the data storage module.

[0096] like Figure 3 As shown, in some embodiments of the present disclosure, the above-mentioned operation module includes a matrix blocking unit, a matrix operation unit and a matrix merging unit, wherein:

[0097] The matrix blocking unit 31 is used to obtain the address information and blocking information of the operation matrix from the operation control module, extract the operation matrix from the data storage module according to the address information of the operation matrix, and perform block operation on the operation matrix according to the blocking information to obtain n block matrices;

[0098] A matrix operation unit 32 is used to obtain n block matrices and perform transposition operations on the n block matrices according to the transposition methods obtained by the operation instructions to obtain transposed matrices of the n block matrices;

[0099] The matrix merging unit 33 is used to obtain a corresponding merging method according to the transposition method obtained by the operation instruction (the merging method is the same as the corresponding transposition method, that is, each block is transposed as an element in the corresponding transposition method), obtain and merge the transposed matrices of n block matrices, and obtain the transposed matrix of the operation matrix, where n is a natural number.

[0100] For example, if Figure 4 As shown in the figure, for an operation matrix X stored in the data storage module, the matrix block unit of the operation module extracts the operation matrix X from the data storage module, performs block operation on the operation matrix X according to the block information, obtains four block matrices X1, X2, X3, and X4, and outputs them to the matrix operation unit; the matrix operation unit obtains these four block matrices from the matrix block unit, and performs transpose operation on these four block matrices respectively to obtain the transposed matrix X1 of the four block matrices T、X2 T 、X3 T 、X4 T , and output to the matrix merging unit; the matrix merging unit obtains the transposed matrix of the four block matrices from the matrix operation unit and merges them to obtain the transposed matrix X of the operation matrix T , we can further transform the transposed matrix X T Output to the data storage module.

[0101] like Figure 5 The figure shows the process of implementing a 90° left-flip matrix transposition (using a 4x4 matrix as an example) in some embodiments of the present disclosure. (This process involves performing a 90° left-flip matrix transposition within a block, and then performing a 90° left-flip transposition on all blocks. Other transposition operations are similar and will not be described here. Furthermore, the block division method is not unique and is provided here for illustrative purposes only.)

[0102] In some embodiments of the present disclosure, please continue to refer to Figure 3 As shown, the above-mentioned operation module further includes a cache unit 34 for caching n block matrices for acquisition by the matrix operation unit.

[0103] In some embodiments of the present disclosure, the above-mentioned matrix merging unit may further include a memory for temporarily storing the transposed matrix of the obtained block matrix. When the matrix operation unit completes the operation of all block matrices, the matrix merging unit can obtain the transposed matrix of all block matrices, and then select the corresponding merging method according to different transposition methods to merge the transposed matrices of n block matrices to obtain the transposed matrix, and write the output result back to the data storage module.

[0104] Those skilled in the art will appreciate that the matrix block unit, matrix operation unit, and matrix merging unit can be implemented in the form of hardware or in the form of software program modules. The matrix block unit and matrix merging unit may include one or more control elements, and the matrix operation unit may include one or more control elements and computing elements.

[0105] like Figure 6 As shown, in some embodiments of the present disclosure, the above-mentioned operation control module includes an instruction processing unit 22, an instruction cache unit 21 and a matrix judgment unit 23, wherein:

[0106] An instruction cache unit, used to store matrix operation instructions to be executed;

[0107] An instruction processing unit is used to obtain a matrix operation instruction from an instruction cache unit, decode the matrix operation instruction, and extract address information of the operation matrix from an address storage module according to the decoded matrix operation instruction;

[0108] The matrix judging unit is configured to judge whether the block division is needed according to the address information of the operation matrix, and obtain the block division information according to the judging result.

[0109] In some embodiments of the present disclosure, referring back to Figure 6 The operation control module further comprises a dependency processing unit 24 configured to judge whether the decoded matrix operation instruction and the address information of the operation matrix conflict with the previous operation, and if there is a conflict, temporarily store the decoded matrix operation instruction and the address information of the operation matrix; if there is no conflict, transmit the decoded matrix operation instruction and the address information of the operation matrix to the matrix judging unit.

[0110] In some embodiments of the present disclosure, referring back to Figure 6 The operation control module further comprises an instruction queue memory 25 configured to buffer the decoded matrix operation instruction and the address information of the operation matrix in conflict, and transmit the buffered decoded matrix operation instruction and the address information of the operation matrix to the matrix judging unit when the conflict is eliminated.

[0111] Specifically, when the matrix operation instruction accesses the data storage module, the previous and subsequent instructions may access the same block of storage space. In order to ensure the correctness of the instruction execution result, if the current instruction is detected to have a dependency relationship with the data of the previous instruction, the instruction must be waited in the instruction queue memory until the dependency relationship is eliminated.

[0112] In some embodiments of the present disclosure, referring back to Figure 6 The instruction processing unit comprises a fetch unit 221 and a decoding unit 222, wherein:

[0113] The fetch unit is configured to obtain the matrix operation instruction from the instruction cache unit, and transmit the matrix operation instruction to the decoding unit;

[0114] The decoding unit is configured to decode the matrix operation instruction, extract the address information of the operation matrix from the address storage module according to the decoded matrix operation instruction, and transmit the decoded matrix operation instruction and the extracted address information of the operation matrix to the dependency processing unit.

[0115] In some embodiments of the present disclosure, the operation device further comprises an input / output module configured to input the operation matrix to the data storage module, and obtain the transposed matrix after operation from the data storage module, and output the transposed matrix after operation.

[0116] In some embodiments of the present disclosure, the address information of the operation matrix is the starting address information of the matrix and the matrix size information.

[0117] In some embodiments of the present disclosure, the address information of the operation matrix is ​​the storage address of the matrix in the data storage module.

[0118] In some embodiments of the present disclosure, the address storage module is a scalar register file or a general memory unit; the data storage module is a high-speed scratchpad memory or a general memory unit.

[0119] In some embodiments of the present disclosure, the address storage module may be a scalar register file, which provides the scalar registers required during the computation process. The scalar registers store not only matrix addresses but also scalar data. When performing a block operation on a large matrix during transposition, the scalar data in the scalar registers can be used to record the number of matrix blocks.

[0120] In some embodiments of the present disclosure, the data storage module may be a high-speed scratchpad memory capable of supporting matrix data of different sizes.

[0121] In some embodiments of the present disclosure, the matrix judgment unit is used to judge the size of the matrix. If it exceeds a predetermined size threshold M, the matrix needs to be divided into blocks. The matrix judgment unit analyzes the judgment result to obtain the block information.

[0122] In some embodiments of the present disclosure, an instruction cache unit is used to store matrix operation instructions to be executed. During execution, instructions are also cached in the instruction cache unit. After an instruction is executed, if it is also the earliest uncommitted instruction in the instruction cache unit, the instruction will be committed. Once committed, the changes to the device state caused by the operation performed by this instruction will be irreversible. The instruction cache unit can be a reorder cache.

[0123] In some embodiments of the present disclosure, the matrix operation instruction is a matrix transposition operation instruction (referred to as the operation instruction), which includes an operation code and an operation field, wherein the operation code is used to indicate the function of the matrix transposition operation instruction, and the matrix operation control module confirms the matrix transposition operation by identifying the operation code, and the operation field is used to indicate the data information of the matrix transposition operation instruction, wherein the data information can be an immediate number or a register number. For example, when obtaining a matrix, the matrix starting address and matrix scale can be obtained in the corresponding register according to the register number, and then the matrix stored at the corresponding address in the data storage module can be obtained according to the matrix starting address and matrix scale.

[0124] In some embodiments, as Figure 7 As shown, the computing device of this embodiment includes an address storage module, a computing control module, a computing module, a data storage module and an input / output module 5, wherein

[0125] Optionally, the operation control module includes an instruction cache unit, an instruction processing unit, a dependency processing unit, an instruction queue memory and a matrix judgment unit, wherein the instruction processing unit further includes an instruction fetch unit and a decoding unit;

[0126] Optionally, the operation module includes a matrix blocking unit, a matrix cache unit, a matrix operation unit and a matrix merging unit;

[0127] Optionally, the address storage module is a scalar register file;

[0128] Optionally, the data storage module is a high-speed temporary memory; the input and output module is an IO memory access module.

[0129] The present disclosure uses a new operation structure to simply and efficiently implement the transposition operation of the matrix, thereby reducing the time complexity of this operation.

[0130] The present disclosure also provides a calculation method, comprising the following steps:

[0131] The operation control module receives or determines the block information;

[0132] The operation module divides the operation matrix into blocks according to the block information to obtain a block matrix, and transposes the block matrix according to the operation instruction to obtain a transposed matrix of the block matrix.

[0133] After the transposition operation step, the method may further include: a merging operation, in which the operation module merges the transposed matrices of the block matrices to obtain the transposed matrix of the operation matrix.

[0134] In some embodiments, as Figure 8 As shown, the computing method disclosed herein comprises the following steps:

[0135] Step 1: The operation control module extracts the address information of the operation matrix from the address storage module;

[0136] Step 2: The operation control module obtains the block information according to the address information of the operation matrix, and transmits the address information and the block information of the operation matrix to the operation module;

[0137] Step 3: The operation module extracts the operation matrix from the data storage module according to the address information of the operation matrix; and divides the operation matrix into n block matrices according to the block information;

[0138] Step 4: The operation module performs transposition operation on the n block matrices according to the operation instruction to obtain the transposed matrices of the n block matrices;

[0139] Step 5: The operation module merges the transposed matrices of the n block matrices to obtain the transposed matrix of the operation matrix and feeds it back to the data storage module;

[0140] wherein n is a natural number.

[0141] In some embodiments, the present embodiment proposes an operation method for performing transpose operation of large-scale matrix, specifically comprising the following steps:

[0142] Step 1, the operation control module extracts the address information of the operation matrix from the address storage module, specifically comprising the following steps:

[0143] Step 1-1, the instruction fetching unit extracts the operation instruction and sends the operation instruction to the decoding unit;

[0144] Step 1-2, the decoding unit decodes the operation instruction, obtains the address information of the operation matrix from the address storage module according to the decoded operation instruction, and sends the decoded operation instruction and the address information of the operation matrix to the dependency processing unit;

[0145] Step 1-3, the dependency processing unit analyzes whether there is a dependency relationship between the decoded operation instruction and the previous instruction which has not been executed and ended in data; specifically, the dependency processing unit can judge whether there is a to-be-written situation in the register required to be read by the operation instruction according to the address of the register, if so, there is a dependency relationship, and the operation instruction can be executed after the data is written back.

[0146] If there is a dependency relationship, the decoded operation instruction and the corresponding address information of the operation matrix need to be waited in the instruction queue storage until there is no longer a dependency relationship in data between the decoded operation instruction and the previous instruction which has not been executed and ended.

[0147] Step 2, the operation control module obtains the blocking information according to the address information of the operation matrix;

[0148] Specifically, after the dependency relationship does not exist, the instruction queue storage transmits the decoded operation instruction and the corresponding address information of the operation matrix to the matrix judgment unit to judge whether the matrix needs to be blocked, the matrix judgment unit obtains the blocking information according to the judgment result, and transmits the blocking information and the address information of the operation matrix to the matrix blocking unit;

[0149] Step 3, the operation module extracts the operation matrix from the data storage module according to the address information of the operation matrix; and divides the operation matrix into n block matrices according to the blocking information.

[0150] Specifically, the matrix blocking unit takes out the required operation matrix from the data storage module according to the transmitted address information of the operation matrix, and divides the operation matrix into n block matrices according to the transmitted blocking information, and transmits each block matrix to the matrix cache unit in turn after the blocking is completed.

[0151] Step 4: The operation module performs a transposition operation on the n block matrices according to the transposition mode obtained by decoding, and obtains a transposed matrix of the n block matrices;

[0152] Specifically, the matrix operation unit extracts the block matrices from the matrix cache unit in sequence, performs a transpose operation on each extracted block matrix, and then transfers the obtained transposed matrix of each block matrix to the matrix merging unit.

[0153] Step 5: The operation module merges the transposed matrices of the n block matrices to obtain the transposed matrix of the operation matrix, and feeds the transposed matrix back to the data storage module, which specifically includes the following steps:

[0154] Step 5-1: The matrix merging unit receives the transposed matrix of each block matrix. When the number of received transposed matrices of the block matrices reaches the total number of blocks, the matrix merging unit performs a matrix merging operation on all blocks according to the transposed mode obtained by decoding to obtain the transposed matrix of the operation matrix; and feeds the transposed matrix back to the specified address of the data storage module;

[0155] Step 5-2: The input-output module directly accesses the data storage module and reads the transposed matrix of the operation matrix obtained by the operation from the data storage module.

[0156] The present disclosure also provides another computing device, comprising:

[0157] An operation control module, used for receiving or determining block information;

[0158] The iterative operation module is used to perform iterative block division, transposition and iterative merging operations on the operation matrix according to the block information to obtain a transposed matrix of the operation matrix.

[0159] In some embodiments of the present disclosure, Figure 9-10 As shown, the computing device disclosed herein includes an address storage module, a data storage module, the computing control module and a computing module.

[0160] Wherein, the address storage module is used to store the address information of the operation matrix;

[0161] The data storage module is used to store the original matrix data and the transposed matrix after operation;

[0162] The operation control module is used to extract the address information of the operation matrix from the address storage module, and obtain the block information according to the address information of the operation matrix;

[0163] The operation module is the iteration operation module 3', configured to obtain address information and block information of the operation matrix from the operation control module, extract the operation matrix from the data storage module according to the address information of the operation matrix, and perform iteration block, transposition and iteration merging operation on the operation matrix according to the block information to obtain the transposed matrix of the operation matrix, and feed back the transposed matrix of the operation matrix to the data storage module.

[0164] The present disclosure can obtain the block matrix to be transposed conforming to the expected size by performing iteration block on the operation matrix, obtain the transposed matrix of the plurality of block matrices by performing transposition operation on the plurality of block matrices respectively, and finally perform iteration merging on the transposed matrix of the plurality of block matrices to obtain the transposed matrix of the operation matrix, so that the transposition operation of the matrix of any size can be completed in constant time complexity using a single instruction. Compared with the traditional matrix transposition operation implementation method, the operation time complexity is reduced, and the use of the matrix transposition operation is also simpler and more efficient.

[0165] As shown in Figure 9 In some embodiments of the present disclosure, the iteration operation module includes an iteration block unit 31', a matrix operation unit 32' and an iteration merging unit 33'.

[0166] As shown in Figure 11 The iteration block unit 31' is configured to obtain address information and block information of the operation matrix from the operation control module, and extract the operation matrix from the data storage module according to the address information of the operation matrix, and perform iteration block operation on the operation matrix according to the block information to obtain n block matrices, which includes a matrix judgment unit 311', a matrix block unit 312' and a cache unit 313'; the matrix block unit performs block operation on the operation matrix according to the block information, and sends the block matrix to the cache unit after the block operation; the matrix judgment unit is configured to receive the matrix information sent by the cache unit, and judge the size of the matrix; the cache unit can re-input the block matrix into the matrix judgment unit of the iteration block unit, if there is a block matrix exceeding the predetermined size threshold M, the block matrix exceeding the predetermined maximum size needs to be sent to the matrix block unit for further block operation, and the iteration is performed until the size of any block matrix meets the requirement of being less than or equal to the predetermined size threshold M.

[0167] As shown in Figure 12As shown, the matrix operation unit 32' is used to obtain n block matrices and perform transposition operations on the n block matrices respectively to obtain transposed matrices of the n block matrices. It includes an address mapping generation unit 321', an address counter 322' and an element exchange unit 323'; the address mapping generation unit is used to generate an address mapping table according to the input matrix scale information, address information, and transposition mode information (obtained by decoding the matrix transposition instruction); the element exchange unit is used to exchange the elements of the corresponding positions of the matrix according to the address mapping table; and the counter unit is used to determine whether the matrix has been completely processed.

[0168] like Figure 13 As shown, the iterative merging unit 33' is used to obtain and iteratively merge the transposed matrices of n block matrices to obtain the transposed matrix of the operation matrix, wherein n is a natural number; specifically, it is used to receive and temporarily cache the transposed block matrices, and after all the block matrices have completed the transposed operation, iteratively merge the transposed matrices of the n block matrices to obtain the transposed matrix of the operation matrix; it includes a cache unit 334', an address mapping generation unit 331', an address counter 332', a matrix merging unit 333' and a matrix judgment unit 335'; after the matrix operation unit completes the transposition of all the block matrices, the cache unit of the iterative merging unit receives and temporarily caches the transposed block matrices; the matrix merging unit receives the transposed block matrices and merges them, and the address mapping generation unit and the address counter treat each block matrix as an element and perform the element exchange operation as described in the matrix operation unit, that is, perform a batch operation of element exchange of the selected block matrices, and then use the matrix judgment unit to ensure that the merging is to the original unblocked scale.

[0169] In this embodiment, the iterative merging unit may further include an element exchange unit, that is, exchanging elements one by one at the corresponding address, and may also include a memory exchange unit, that is, exchanging matrix blocks (small matrix blocks that have been transposed) at the corresponding address in batches.

[0170] In this embodiment, the operation module may not include the matrix judgment unit. When the matrix blocking unit and the matrix merging unit perform iterative blocking and iterative merging, the matrix scale judgment is directly performed by the matrix judgment unit included in the operation control module.

[0171] In this embodiment, the structures of the iterative block division unit, the iterative merging unit and the matrix operation unit are not limited to Figure 11-13In other words, the matrix judgment unit in the computing device can be used in either a non-shared or shared manner, and the operation module can include an address mapping generation unit, an address counter, an element exchange unit, and a cache unit. These units can be used in either a non-shared or shared manner, and are not limited to the iterative blocking unit and the iterative merging unit, which each include an address mapping generation unit, an address counter, an element exchange unit, and a cache unit.

[0172] It should be noted that since matrix transposition and matrix merging are separated in terms of timing, that is, after all blocks have been transposed, the corresponding devices of the operation unit are idle, and the corresponding units can be reused for matrix merging. However, if applied to a pipeline, such as a three-stage pipeline, when a matrix has completed matrix transposition and is about to enter the matrix merging unit, the block of the next matrix to be transposed enters the operation unit, and the next matrix to be transposed enters the matrix block unit. In other words, the three units of block, operation, and merging are all occupied. Therefore, at this time, any small modules of the block unit, transposition unit, and merging unit cannot be reused.

[0173] Accordingly, the present disclosure also provides a calculation method, comprising the following steps:

[0174] The operation control module receives or determines the block information;

[0175] The iterative operation module performs iterative block division, transposition and iterative merging operations on the operation matrix according to the block information to obtain a transposed matrix of the operation matrix.

[0176] In some embodiments, the computing method includes:

[0177] The operation control module extracts the address information of the operation matrix from the address storage module;

[0178] The operation control module obtains the block information according to the address information of the operation matrix, and transmits the address information and the block information of the operation matrix to the operation module;

[0179] The operation module extracts the operation matrix from the data storage module according to the address information of the operation matrix; and iteratively divides the operation matrix into n block matrices that meet the transposition requirement according to the block information;

[0180] The operation module performs transposition operation on the n block matrices respectively to obtain the transposed matrices of the n block matrices; the operation module iteratively merges the transposed matrices of the n block matrices to obtain the transposed matrix of the operation matrix and feeds it back to the data storage module; wherein n is a natural number.

[0181] In the step of the iterative block unit performing iterative block operation on the operation matrix according to the block information:

[0182] The matrix blocking unit blocks the operation matrix according to the blocking information and sends the blocked matrix to the cache unit;

[0183] The cache unit inputs the block matrix into the matrix judgment unit. If the matrix judgment unit determines that there is a block matrix that exceeds the predetermined size threshold M, it is sent to the matrix blocking unit to continue the blocking operation. This is iterated until the size of any block matrix is ​​less than or equal to the predetermined size threshold M.

[0184] In the step of obtaining and iteratively merging the transposed matrices of the n block matrices by the iterative merging unit of the iterative operation module:

[0185] The cache unit receives the transposed block matrix;

[0186] The matrix merging unit receives and merges the transposed block matrices sent by the cache unit;

[0187] The address mapping generation unit and the element exchange unit treat each block matrix in the merged matrix as an element and perform element exchange operation;

[0188] The matrix judgment unit determines the scale of the matrix obtained by merging.

[0189] In the above embodiment, the block information can be obtained by analyzing the address information, or directly obtained from the input data, that is, the input data of the operation control module includes the block information.

[0190] The following is a further detailed description of the various components involved in the computing device disclosed herein:

[0191] The instruction fetch unit is responsible for fetching the next instruction to be executed from the instruction cache unit and passing it to the decode unit;

[0192] The decoding unit is responsible for decoding the operation instruction and sending the decoded operation instruction to the scalar register file, obtaining the address information of the operation matrix fed back by the scalar register file, and transmitting the decoded operation instruction and the obtained operation matrix address information to the dependency processing unit;

[0193] The dependency processing unit processes any storage dependencies that may exist between an operation instruction and the previous instruction. Matrix operation instructions access high-speed temporary storage, and previous and subsequent instructions may access the same storage space. To ensure the correctness of the instruction execution results, if the current operation instruction is detected to have a data dependency with the previous operation instruction, the operation instruction must be cached in the instruction queue memory until the dependency is eliminated. If the current operation instruction does not have a dependency with the previous operation instruction, the dependency processing unit directly transmits the address information of the operation matrix and the decoded operation instruction to the matrix judgment unit.

[0194] An instruction queue memory, which is used to cache conflicting decoded operation instructions and address information of corresponding operation matrices, taking into account the possible dependency between scalar registers corresponding to / specified by different operation instructions, and transmit the decoded operation instructions and address information of corresponding operation matrices to the matrix judgment unit when the dependency is satisfied;

[0195] The matrix judgment unit is used to judge the size of the matrix according to the address information of the operation matrix. If it exceeds the predetermined size threshold M, the matrix needs to be divided into blocks. The matrix judgment unit analyzes the block information based on the judgment result and transmits the address information of the operation matrix and the obtained block information to the matrix block unit.

[0196] The matrix block unit is responsible for extracting the operation matrix to be transposed from the high-speed register according to the address information of the operation matrix, and dividing the operation matrix into blocks according to the block information to obtain n block matrices. The matrix cache unit is used to cache the n block matrices after block division and transmit them to the matrix operation unit in sequence for transposition operation;

[0197] The matrix operation unit is responsible for sequentially extracting the block matrices from the matrix cache unit, performing transposition operations according to the matrix transposition method obtained by the decoding unit, and transmitting the transposed block matrices to the matrix merging unit;

[0198] The matrix merging unit is responsible for receiving and temporarily caching the transposed block matrices. After all block matrices have completed the transposition operation, the transposed matrices of the n block matrices are merged according to the matrix transposition method obtained by the decoding unit to obtain the transposed matrix of the operation matrix.

[0199] The scalar register file provides the scalar registers required by the device during the operation process and provides the address information of the operation matrix for the operation;

[0200] High-speed temporary storage module, this module is a temporary storage device dedicated to matrix data and can support matrix data of different sizes.

[0201] The IO memory access module is used to directly access the high-speed temporary memory and is responsible for reading or writing data from the high-speed temporary memory.

[0202] It should be noted that in the computing device and computing method disclosed herein, the computing control module can directly receive the address information and block information of the computing matrix, or be used to extract the address information of the computing matrix from the address storage module, and obtain the block information based on the address information of the computing matrix.

[0203] In addition, in some embodiments, the present disclosure also provides a chip, which includes the above-mentioned computing device.

[0204] In some embodiments, the present disclosure further provides a chip packaging structure, which includes the above-mentioned chip.

[0205] In some embodiments, the present disclosure further provides a board card, which includes the above-mentioned chip packaging structure.

[0206] In some embodiments, the present disclosure further provides an electronic device comprising the above-mentioned board.

[0207] Electronic devices include data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, mobile phones, driving recorders, navigation systems, sensors, cameras, servers, cloud servers, cameras, camcorders, projectors, watches, headphones, mobile storage, wearable devices, vehicles, household appliances, and / or medical devices.

[0208] The transportation vehicles include airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; and the medical equipment include magnetic resonance imaging (MRI), ultrasound machines and / or electrocardiographs.

[0209] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all optional embodiments, and the actions and modules involved are not necessarily required by this application.

[0210] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0211] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0212] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0213] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or in the form of software program modules.

[0214] If the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a memory and includes a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes various media that can store program codes, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0215] Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program. The program can be stored in a computer-readable memory, and the memory can include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0216] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above are only specific embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A computing device, comprising: An operation control module is used to determine block information, wherein the block information includes block size information, and the block size information represents size information of each block matrix obtained after the operation matrix is ​​divided into blocks; wherein, block information is obtained according to the address information of the operation matrix; an iterative operation module, configured to perform iterative block division, transposition, and iterative merging operations on the operation matrix according to the block information to obtain a transposed matrix of the operation matrix; wherein the transposition operation includes: obtaining n block matrices and performing transposition operations on the n block matrices respectively to obtain transposed matrices of the n block matrices; and the iterative merging operation includes: obtaining and iteratively merging the transposed matrices of the n block matrices to obtain a transposed matrix of the operation matrix, wherein n is a natural number; The iterative operation module includes: an iterative block unit, configured to perform iterative block operation on the operation matrix according to the block information to obtain n block matrices; The iterative blocking unit includes: a first matrix judgment unit, a matrix blocking unit and a first cache unit; wherein the matrix blocking unit is used to block the operation matrix according to the blocking information and send the block matrix to the first cache unit; the first cache unit is used to input the block matrix into the first matrix judgment unit; if there is a block matrix that exceeds a predetermined size threshold M, the block matrix that exceeds the predetermined size threshold M is sent to the matrix blocking unit to continue the blocking operation, and the iteration is performed until the size of any block matrix is ​​less than or equal to the predetermined size threshold M; Wherein, the iterative operation module further includes: a matrix operation unit, configured to obtain the n block matrices and perform transpose operations on the n block matrices respectively to obtain transposed matrices of the n block matrices; an iterative merging unit, configured to obtain and iteratively merge the transposed matrices of the n block matrices to obtain the transposed matrix of the operation matrix, wherein n is a natural number; The iterative merging unit includes a second cache unit, a second address mapping generation unit, a second address counter, a matrix merging unit and a second matrix judgment unit; wherein the second cache unit is used to receive the transposed block matrix; the matrix merging unit receives the transposed block matrix and merges it; the second address mapping generation unit and the second address counter are used to treat each block matrix as an element and perform an element exchange operation; and the second matrix judgment unit is used to determine the scale of the merged matrix.

2. The computing device according to claim 1, wherein: The matrix operation unit includes a first address mapping generation unit, a first address counter and an element exchange unit; wherein the first address mapping generation unit is used to generate an address mapping table based on the input matrix scale information and address information; the element exchange unit is used to exchange elements at corresponding positions in the matrix according to the address mapping table; and the first address counter is used to determine whether the matrix has been fully processed.

3. The computing device according to any one of claims 1 to 2, further comprising: An address storage module, used for storing address information of the operation matrix; as well as A data storage module, used for storing the operation matrix and the transposed matrix after the operation; The operation control module is used to extract the address information of the operation matrix from the address storage module, and obtain the block information according to the address information of the operation matrix; The iterative operation module is used to obtain the address information and block information of the operation matrix from the operation control module, extract the operation matrix from the data storage module according to the address information of the operation matrix, and perform iterative blocking, transposition and iterative merging operations on the operation matrix to obtain the transposed matrix of the operation matrix, and feed the transposed matrix of the operation matrix back to the data storage module.

4. The computing device according to claim 3, wherein: The operation control module includes: An instruction cache unit, used to store operation instructions to be executed; an instruction processing unit, configured to obtain the operation instruction from the instruction cache unit, decode the operation instruction, and obtain address information of the operation matrix from the address storage module according to the decoded operation instruction; a third matrix judgment unit, configured to analyze the address information of the operation matrix to obtain the block information; a dependency processing unit, configured to determine whether the decoded operation instruction and address information of the operation matrix conflict with a previous operation, and if so, temporarily store the decoded operation instruction and address information of the operation matrix; if not, transmit the decoded operation instruction and address information of the operation matrix to the third matrix determination unit; The instruction queue memory is used to cache the decoded operation instructions and address information of the operation matrix that have conflicts, and when the conflicts are resolved, transmit the cached decoded operation instructions and address information of the operation matrix to the third matrix judgment unit.

5. The computing device according to claim 3, wherein: The address storage module includes a scalar register file or a universal memory unit; the data storage module includes a high-speed temporary memory or a universal memory unit; the address information of the operation matrix is ​​the starting address information and matrix size information of the matrix.

6. The computing device according to claim 3, further comprising: The input-output module is used to input the operation matrix into the data storage module, and is also used to obtain the transposed matrix after operation from the data storage module and output the transposed matrix after operation.

7. A calculation method comprising: The operation control module determines block information, wherein the block information includes block size information, wherein the block size information represents size information of each block matrix obtained after the operation matrix is ​​divided into blocks, wherein the block information is obtained based on address information of the operation matrix; The iterative operation module performs iterative block division, transposition and iterative merging operations on the operation matrix according to the block information to obtain a transposed matrix of the operation matrix; wherein the transposition operation includes: obtaining n block matrices and performing transposition operations on the n block matrices respectively to obtain transposed matrices of the n block matrices; the iterative merging operation includes: obtaining and iteratively merging the transposed matrices of the n block matrices to obtain a transposed matrix of the operation matrix, wherein n is a natural number; The iterative block unit of the iterative operation module performs an iterative block operation on the operation matrix according to the block information to obtain n block matrices: the matrix block unit of the iterative block unit blocks the operation matrix according to the block information and sends the block matrix to the first cache unit of the iterative block unit; the first cache unit of the iterative block unit inputs the block matrix to the first matrix judgment unit of the iterative block unit, and if the first matrix judgment unit of the iterative block unit judges that there is a block matrix exceeding a predetermined scale threshold M, the block matrix exceeding the predetermined scale threshold M is sent to the matrix block unit of the iterative block unit to continue the block operation, and the iteration is repeated until the scale of any block matrix is ​​less than or equal to the predetermined scale threshold M; The iterative operation module performs iterative block division, transposition and iterative merging operations on the operation matrix according to the block information to obtain the transposed matrix of the operation matrix, which further includes: The matrix operation unit of the iterative operation module obtains the n block matrices and performs transposition operation on the n block matrices respectively to obtain transposed matrices of the n block matrices; The iterative merging unit of the iterative operation module obtains and iteratively merges the transposed matrices of the n block matrices to obtain the transposed matrix of the operation matrix, wherein n is a natural number; wherein, in the step of obtaining and iteratively merging the transposed matrices of the n block matrices by the iterative merging unit of the iterative operation module; The second cache unit of the iterative merging unit receives the transposed block matrix; The matrix merging unit of the iterative merging unit receives and merges the transposed block matrices sent by the cache unit of the iterative blocking unit; The second address mapping generation unit of the iterative merging unit and the second address counter of the iterative merging unit take each block matrix in the merged matrix as an element and perform an element exchange operation; The second matrix determination unit of the iterative blocking unit determines the scale of the matrix obtained by merging.

8. The calculation method according to claim 7, further comprising: The address storage module stores the address information of the operation matrix; The data storage module stores the operation matrix and the transposed matrix after the operation; The operation control module extracts the address information of the operation matrix from the address storage module, and obtains the block information according to the analysis of the address information of the operation matrix; The operation module obtains the address information and block information of the operation matrix from the operation control module, extracts the operation matrix from the data storage module according to the address information of the operation matrix, performs block, transposition and merging operations on the operation matrix to obtain the transposed matrix of the operation matrix, and feeds the transposed matrix of the operation matrix back to the data storage module.

9. A chip comprising the computing device according to any one of claims 1 to 6.

10. A chip packaging structure comprising the chip according to claim 9.

11. A board comprising the chip packaging structure according to claim 10.

12. An electronic device comprising the board according to claim 11.

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