Display device

Abstract

The present disclosure relates to a display device, the display device comprising: a substrate, comprising: a pixel region, comprising pixels; a peripheral region, adjacent to the pixel region; and a boundary, located between the pixel region and the peripheral region, the boundary comprising a rounded corner; a data driver, located in the peripheral region; a data line, through which a data signal is provided from the data driver to the pixel; and an initialization voltage supply line, located in the peripheral region and connected to the pixel, the initialization voltage supply line extending along the rounded corner of the boundary between the pixel region and the peripheral region. Along the rounded corner of the boundary, the initialization voltage supply line overlaps the data line along the thickness direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits from Korean Patent Application No. 10-2019-0094680, filed on August 5, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] As the information society evolves, various demands on display devices are increasing. For example, display devices are being adopted by various electronic devices such as smartphones, desktop personal computers ("PCs"), digital cameras, laptop computers, navigation devices, and smart TVs.

[0005] In a display panel of a display device, the display device may include a pixel region and a peripheral region surrounding the pixel region. A driver for driving a pixel circuit system in the pixel region may be located in the peripheral region of the display panel. A signal line connecting a data driver to a pixel in the pixel region may be arranged in a fan-out structure in the peripheral region. Summary of the invention

[0006] An embodiment of the present disclosure provides a display device in which a dead space is reduced at a corner in a peripheral area of ​​the display device by disposing an initialization voltage supply line above a signal line arranged in a fan-out structure.

[0007] These and other features, embodiments and advantages of the present disclosure will become immediately apparent to those of ordinary skill in the art upon reading the following detailed description.

[0008] According to one or more embodiments of the present disclosure, a display device includes: a substrate, including: a pixel region including pixels; a peripheral region adjacent to the pixel region; and a boundary located between the pixel region and the peripheral region, the boundary including a rounded corner; a data driver located in the peripheral region; a data line through which a data signal is provided from the data driver to the pixel; and an initialization voltage supply line located in the peripheral region and connected to the pixel, the initialization voltage supply line extending along the rounded corner of the boundary between the pixel region and the peripheral region. Along the rounded corner of the boundary, the initialization voltage supply line overlaps the data line along the thickness direction.

[0009] The peripheral region of the substrate may include a terminal region and a portion connecting the terminal region to the pixel region. The terminal region may be bendable relative to the rest of the peripheral region, and the bent substrate may be provided along the thickness direction with the terminal region overlapping the portion connecting the terminal region to the pixel region.

[0010] The data driver may be located in the terminal region.

[0011] The data line may be provided in plural, including a plurality of data lines having a fan-out structure extending outward in a direction from the data driver to the pixel region.

[0012] The initialization voltage supply line may overlap the data line having the fan-out structure.

[0013] The initialization voltage supply line may be provided as a plurality of lines, including a first initialization voltage supply line and a second initialization voltage supply line located in the peripheral region, and along the rounded corner of the boundary between the pixel region and the peripheral region, the first initialization voltage supply line and the second initialization voltage supply line may be parallel to each other at a constant interval.

[0014] The display device may further include a gate insulating layer, a first insulating layer, a second insulating layer, and a third insulating layer in order from the substrate.

[0015] The first insulating layer may be located between the gate insulating layer and the first initialization voltage supply line, and between the gate insulating layer and the second initialization voltage supply line.

[0016] The display device may further include a first initialization voltage line connected to the pixel region and extending from the pixel region to the peripheral region, and a first bridge line located in the peripheral region, the first bridge line connecting the first initialization voltage supply line to the first initialization voltage line.

[0017] The second insulating layer may be located between the first bridge line and the first initialization voltage source line and define a first contact hole, the first insulating layer and the second insulating layer may be located between the first bridge line and the first initialization voltage source line and define a second contact hole, the first bridge line may be connected to the first initialization voltage source line at the first contact hole, and the first bridge line may be connected to the first initialization voltage line at the second contact hole.

[0018] The second initialization voltage supply line may include an output terminal protruding toward the pixel region.

[0019] The display device may further include: a second initialization voltage line connected to the pixel region and extending from the pixel region to the peripheral region. The first insulating layer may be located between the output terminal of the second initialization voltage supply line and the second initialization voltage line and define a third contact hole, and the output terminal of the second initialization voltage supply line may be connected to the second initialization voltage line at the third contact hole.

[0020] The data line may be provided in plurality, including a first data line and a second data line both located in the peripheral region. In the peripheral region, the gate insulating layer may be located between the first data line and the second data line, and the second data line may be located between the gate insulating layer and the substrate.

[0021] The first data line and the second data line may extend parallel to each other.

[0022] The first data line may be provided in plurality including a plurality of first data lines, and the second data line may be provided in plurality including a plurality of second data lines. In the peripheral region, the plurality of first data lines and the plurality of second data lines may be alternately arranged.

[0023] The display device may further include a scan driver and an emission driver located in the peripheral area.

[0024] The scan driver may be located between the emission driver and the pixel area.

[0025] The initialization voltage supply line may be located between the scan driver and the pixel area.

[0026] The display device may further include: a first portion of an emission control line connected to the pixel area and extending from the pixel area to the peripheral area; a second portion of the emission control line connected to the emission driver; and a second bridge line connecting the first portion of the emission control line and the second portion of the emission control line to each other.

[0027] The display device may further include: a first portion of a scan line connected to the pixel area and extending from the pixel area to the peripheral area; a second portion of the scan line connected to the scan driver; and a third bridge line connecting the first portion of the scan line and the second portion of the scan line to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0029] Figure 1 is a plan view schematically showing an exemplary embodiment of a display device;

[0030] Figure 2 is a block diagram illustrating an exemplary embodiment of a pixel and a driver;

[0031] Figure 3 It shows Figure 1 An enlarged plan view of an exemplary embodiment of a portion P1 of FIG.

[0032] Figure 4 It shows Figure 3 A circuit diagram of an exemplary embodiment of a scanning stage of;

[0033] Figure 5 It shows that Figure 3 A diagram of an exemplary embodiment of a pixel shown in FIG.

[0034] Figure 6 It shows Figure 3 An enlarged plan view of pixels;

[0035] Figure 7 It is along Figure 6 A cross-sectional view taken along line II';

[0036] Figure 8 It is along Figure 6 A cross-sectional view taken along line II-II';

[0037] Fig. 9 It shows Figure 3 An enlarged plan view of an exemplary embodiment of a portion P2;

[0038] Fig.10 It is along Fig. 9 A cross-sectional view taken along line III-III';

[0039] Fig.11 It is along Fig. 9 A cross-sectional view taken along line IV-IV';

[0040] Fig.12 It is along Fig. 9 A cross-sectional view taken along line V-V';

[0041] Fig.13 It is along Fig. 9 A cross-sectional view taken along line VI-VI';

[0042] Fig.14 It is along Fig. 9 A cross-sectional view taken along line IV-IV';

[0043] Fig.15 It is along Fig. 9A cross-sectional view taken along line V-V';

[0044] Fig.16 It shows Figure 1 An enlarged plan view of another exemplary embodiment of a portion P1 of FIG.

[0045] Fig.17 It shows Fig.16 An enlarged plan view of portion P2_1. DETAILED DESCRIPTION

[0046] In the following description, for the purpose of explanation, many specific details are set forth so as to provide a thorough understanding of various exemplary embodiments or embodiments of the present disclosure. As used herein, "embodiment" and "embodiment" are interchangeable words, which are non-limiting examples of devices or methods using one or more of the inventions disclosed herein. However, it is apparent that various exemplary embodiments can be practiced without these specific details or using one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessary obscurity of various exemplary embodiments. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the scope of the present disclosure, the specific shape, configuration and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment.

[0047] Unless otherwise noted, the exemplary embodiments shown should be understood as providing exemplary features of details of variations of some ways in which the present disclosure may be implemented in practice. Therefore, unless otherwise noted, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the scope of the present disclosure.

[0048] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence and absence of cross hatching or shading do not convey or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the exemplary embodiments can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0049] When an element or layer is referred to as being associated with another element or layer, such as "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or directly coupled to another element or layer, or there may be intermediate elements or layers. However, when an element or layer is referred to as being associated with another element or layer, such as "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intermediate elements or layers. For this reason, the term "connected" may refer to physical, electrical and / or fluid connections with or without the presence of intermediate elements or layers.

[0050] In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes of the rectangular coordinate system, such as the x-axis, y-axis and z-axis, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y and Z, such as XYZ, XYY, YZ and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0051] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be named as the second element.

[0052] Spatially relative terms such as "below," "under," "below," "down," "above," "upper," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein for descriptive purposes, and thereby to describe the relationship between one element and (multiple) other elements as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element or feature described as "below" or "below" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both "above" and "below" orientations. Furthermore, the device may be otherwise positioned (rotated 90 degrees or in other orientations), and thus the spatially relative descriptors used herein may be interpreted accordingly.

[0053] The terms used herein are for the purpose of describing specific embodiments and are not intended to be restrictive. As used herein, the singular forms of "one", "a kind of" and "the (the)" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "include", "comprise", "include" and / or "include" indicate the presence of stated features, integral bodies, steps, operations, elements, components and / or their groups, but do not exclude the presence or increase of one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It is also noted that the terms "substantially", "approximately" and other similar terms as used herein are used as approximate terms, not as terms of degree, and are therefore used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0054] Various exemplary embodiments are described herein with reference to cross-sectional views and / or perspective views as schematic diagrams of ideal exemplary embodiments and / or intermediate structures. Therefore, deviations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the exemplary embodiments disclosed herein should not necessarily be interpreted as being limited to the specific illustrated shapes of the regions, but should include deviations in shapes caused by, for example, manufacturing. In this way, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are therefore not necessarily intended to be restrictive.

[0055] As a convention in the art, exemplary embodiments are described and shown in the accompanying drawings according to functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electrical (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, which can be provided or formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, blocks, units and / or modules can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs certain functions and processors (e.g., one or more programmed microprocessors and related circuit systems) that perform other functions. In addition, without departing from the scope of the present disclosure, each block, unit and / or module of the exemplary embodiment can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of the exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure is a part. Unless explicitly defined herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted as an ideal or overly formal meaning.

[0057] In a display device including rounded corners in a plan view, the size or dimension of the dead space may increase toward the lower end of the corner due to the planar area occupied by the signal lines extending from the scan driver, the emission driver and / or the initialization voltage supply line. Various line designs can reduce such dead space at the corner.

[0058] Figure 1 is a plan view schematically showing an exemplary embodiment of the display device 1 .

[0059] refer to Figure 1 The display device 1 may include: a display unit 10, which is disposed on a substrate SUB; a scan driver SDV, which is used to provide one or more electrical signals such as scan signals to a plurality of pixels PXL (for example, a plurality of pixels PXL) along a signal line such as a scan line; an emission driver EDV, which is used to provide one or more electrical signals such as emission control signals to the pixels PXL along a signal line such as an emission control line; a data driver DDV, which is used to provide one or more electrical signals such as data signals to the pixels PXL along a signal line such as a data line; a timing controller TC (see Figure 2 ); signal lines such as a driving voltage supply line VDDL; and signal lines such as a common voltage supply line VSSL. The timing controller TC controls the scan driver SDV, the emission driver EDV, and the data driver DDV. The various drivers mentioned above can drive or control the pixels PXL (e.g., a plurality of pixels PXL) provided in a plurality by one or more electrical signals, thereby generating light, emitting light, displaying an image, etc.

[0060] The substrate SUB may include, for example, SiO 2glass, metal and / or organic material, or made of the above materials. According to an exemplary embodiment of the present disclosure, the substrate SUB may include a flexible material or be made of a flexible material. In an exemplary embodiment, for example, the substrate SUB may include but is not limited to a flexible plastic material such as polyimide, or be made of a flexible plastic material such as polyimide. According to another exemplary embodiment, the plastic material may be polyethersulfone ("PES"), polyacrylate ("PAR"), polyetherimide ("PEI"), polyethylene naphthalate ("PEN"), polyethylene terephthalate ("PET"), polyphenylene sulfide ("PPS"), polyacrylate, polyimide, polycarbonate ("PC"), cellulose triacetate ("TAC") and cellulose acetate propionate ("CAP"), cycloolefin polymers, cycloolefin copolymers, etc.

[0061] The substrate SUB may be implemented as a single body having a substantially rectangular shape in a plan view. The substrate SUB defines a single and continuous plane area. The substrate SUB and the layers disposed thereon may define a display panel of the display device 1, but are not limited thereto.

[0062] As signal lines, the display unit 10 may include a plurality of scan lines S (e.g., a plurality of scan lines S) provided transversely extending along a first direction DR1, a plurality of emission control lines E (e.g., a plurality of emission control lines E), a plurality of first initialization voltage lines V1 (e.g., a plurality of first initialization voltage lines V1), and a plurality of second initialization voltage lines V2 (e.g., a plurality of second initialization voltage lines V2). A plurality of pixels PXL (e.g., a plurality of pixels PXL) provided are connected to corresponding data lines D among a plurality of data lines D extending in a second direction DR2 intersecting the first direction DR1. Each pixel PXL may be driven or controlled to emit light, such as red, green, blue, or white light, wherein the light is used to display an image. The pixel PXL may include, for example, a light-emitting element that generates and emits light, such as an organic light-emitting diode OLED.

[0063] The display device 1 may be disposed in a plane defined by the first direction DR1 and the second direction DR2, but is not limited thereto. The third direction DR3 may intersect each of the first direction DR1 and the second direction DR2. The thickness of the display device 1 and its components may be defined along the third direction DR3.

[0064] The substrate SUB includes a pixel area PXA and a peripheral area PPA adjacent to the pixel area PXA. The pixel area PXA is a plane area (e.g., a display area) in which pixels PXL for displaying an image are arranged. The pixel PXL will be described later. The peripheral area PPA is a plane area (e.g., a non-display area) in which the pixels PXL are not arranged and the image is not displayed. The pixel area PXA and its elements may define the display unit 10, but are not limited thereto. The display unit 10 may correspond to the pixel area PXA.

[0065] One or more drivers for driving the pixels PXL and signal lines (not shown) connecting the pixels PXL to the drivers are provided in the peripheral area PPA. The peripheral area PPA corresponds to the frame of the display device 1 that is completed (e.g., in a final assembled form, after a manufacturing process is completed, etc.). The plane size (e.g., width) of the frame can be determined depending on the corresponding plane size (e.g., width) of the peripheral area PPA. The width of the peripheral area PPA can be intercepted in the direction from the pixel area PXA to the outer edge of the display device 1, but is not limited thereto.

[0066] The substrate SUB may have various shapes. In an exemplary embodiment, for example, the substrate SUB may include or define various planar shapes, such as a closed polygon including a straight edge as an outer edge, a circle and / or an ellipse including a curved edge as an outer edge, and a semicircle or semi-ellipse including a straight edge and a curved edge as an outer edge. When the substrate SUB defines or includes a plurality of planar regions, each planar region may be implemented as any one of various planar shapes such as a closed polygon including a straight edge as a boundary, a circle and / or an ellipse including a curved edge as a boundary, and a semicircle or semi-ellipse including a straight edge and a curved edge as a boundary. The boundary may have rounded corners.

[0067] When the substrate SUB is implemented as various planar shapes, one or more corners of each shape can be a curve. In an exemplary embodiment, for example, the corner defined by the straight lines of the straight edges intersecting each other can be replaced by the corner defined by the curve with a predetermined curvature. That is, the opposite ends of the vertices (e.g., corners) of the rectangular shape can be connected to two straight lines adjacent thereto, respectively, and the vertices can be formed or defined by the curve with a predetermined curvature. The curvature can change depending on the position. In an exemplary embodiment, for example, the curvature can change depending on the starting position of the curve (e.g., its end) and the length of the curve. In the following description, the corner of the substrate SUB defined by the curve can be referred to as an angle.

[0068] The substrate SUB may further include an additional area ADA protruding from one side of the pixel area PXA. The additional area ADA may be further referred to as a pad area, a terminal area, etc. According to an exemplary embodiment of the present disclosure, the additional area ADA may have a planar shape protruding from a horizontal portion of the peripheral area PPA. The additional area ADA may be bendable relative to a boundary between the additional area ADA and the horizontal portion of the peripheral area PPA. The additional area ADA may be bendable relative to a bending line BDL. Because the additional area ADA is bendable, and is thus, for example, arranged to overlap with the horizontal portion of the peripheral area PPA, the width of the border at the horizontal portion of the peripheral area PPA may be reduced.

[0069] The data driver DDV may be disposed in the additional area ADA. It should be understood that the elements that may be disposed in the additional area ADA are not limited thereto. According to an exemplary embodiment of the present disclosure, in addition to Figure 1 As shown in the case shown in , the additional area ADA may also be disposed at or extend from other parts of the peripheral area PPA, and may be bent to overlap with other parts of the peripheral area PPA to reduce the width of the frame of the display device 1. That is, the bent substrate SUB is provided with the additional area ADA overlapping with a part of the peripheral area PPA other than the additional area ADA along the thickness direction.

[0070] The pixel area PXA has a shape corresponding to the shape of the substrate SUB. Figure 1 , contours of corners (eg, rounded or curved) and sides connecting the corners to each other of the substrate SUB correspond to contours of corresponding corners and sides of the pixel area PXA.

[0071] The peripheral area PPA is disposed on at least one side of the pixel area PXA or extends from at least one side of the pixel area PXA. According to an exemplary embodiment of the present disclosure, the peripheral area PPA may surround the pixel area PXA in a plan view. According to an exemplary embodiment of the present disclosure, the peripheral area PPA may include a horizontal portion extending laterally along a width direction of the display device 1 (e.g., along a first direction DR1) and a vertical portion extending longitudinally along a longitudinal direction of the display device 1 (e.g., along a second direction DR2). A pair of vertical portions of the peripheral area PPA are disposed opposite to each other and are spaced apart from each other along the width direction relative to the pixel area PXA.

[0072] The pixel PXL is arranged in the pixel area PXA of the substrate SUB. Each pixel PXL may be the smallest unit for emitting light, displaying an image, etc., and more than one pixel PXL may be arranged in the pixel area PXA. Each pixel PXL may include an organic light emitting element that generates and / or emits white light and / or colored light. Each pixel PXL may emit one of red light, green light, and blue light, but the present disclosure is not limited thereto. Each pixel PXL may emit light of colors such as cyan, magenta, and yellow.

[0073] The pixels PXL may be arranged in a matrix form along rows extending along the first direction DR1 and columns extending along the second direction DR2. However, the arrangement of the pixels PXL is not particularly limited thereto and may be arranged in various forms. In an exemplary embodiment, for example, a first portion of the pixels PXL may be arranged such that the first direction DR1 is a row direction, but a second portion of the pixels PXL different from the first portion thereof may be arranged in a direction different from the first direction DR1 (e.g., a direction oblique or inclined relative to the first direction DR1 as the row direction).

[0074] The scan driver SDV may be disposed in a vertical portion of the peripheral area PPA. Since a pair of vertical portions of the peripheral area PPA are disposed to be spaced apart along the width direction of the pixel area PXA, the scan driver SDV may be disposed in at least one vertical portion of the peripheral area PPA. The scan driver SDV may extend longitudinally along the longitudinal direction of the peripheral area PPA.

[0075] According to an exemplary embodiment of the present disclosure, the scan driver SDV may be directly mounted on the substrate SUB. When the scan driver SDV is directly mounted on the substrate SUB, the scan driver SDV may be provided or formed together during the process of providing or forming the pixel PXL. However, the location and / or method of forming the scan driver SDV is not limited thereto. The scan driver SDV may be provided or formed on a chip separate from the substrate SUB, and may be provided on or connected to a substrate SUB such as a chip on glass. Alternatively, the scan driver SDV may be mounted on a printed circuit board separate from the substrate SUB, and may be connected to the substrate SUB by a connecting member.

[0076] Like the scan driver SDV, the emission driver EDV may also be disposed in a vertical portion of the peripheral area PPA. The emission driver EDV and the scan driver SDV may be disposed in the same vertical portion. The emission driver EDV may be disposed in at least one vertical portion of the peripheral area PPA. The emission driver EDV may extend longitudinally in a longitudinal direction of the peripheral area PPA.

[0077] According to an exemplary embodiment of the present disclosure, the emission driver EDV may be directly mounted on the substrate SUB. When the emission driver EDV is directly mounted on the substrate SUB, the emission driver EDV may be provided or formed together with the pixel PXL during the same process of providing or forming the pixel PXL. However, the location and / or method of providing or forming the emission driver EDV is not limited thereto. The emission driver EDV may be provided or formed on a separate chip and connected to the substrate SUB to become a chip on glass. Alternatively, the emission driver EDV may be mounted on a printed circuit board to be connected to the substrate SUB through a connecting member.

[0078] According to an exemplary embodiment of the present disclosure, the scan driver SDV and the emission driver EDV are adjacent to each other in the same vertical portion of the peripheral area. As an example, a pair of scan driver SDV and emission driver EDV are provided in two vertical portions of the peripheral area PPA, but the present disclosure is not limited thereto. The arrangement may be changed in various ways. In an exemplary embodiment, for example, the scan driver SDV may be arranged at one vertical portion of the peripheral area PPA, and the emission driver EDV may be arranged at another vertical portion of the peripheral area PPA (for example, in vertical portions different from each other). Alternatively, the scan driver SDV may be arranged at two vertical portions of the peripheral area PPA, and the emission driver EDV may be arranged at only one vertical portion of the peripheral area PPA.

[0079] The data driver DDV may be disposed in the peripheral area PPA. Specifically, the data driver DDV may be disposed in a horizontal portion of the peripheral area PPA. The data driver DDV may extend laterally in a width direction of the peripheral area PPA.

[0080] According to an exemplary embodiment of the present disclosure, positions of the scan driver SDV, the emission driver EDV, and / or the data driver DDV may be interchanged as needed.

[0081] The timing controller TC may be connected to the scan driver SDV, the emission driver EDV, and the data driver DDV in various ways by providing a plurality of conductive lines (e.g., lines) and / or signal lines. The position of the timing controller TC is not specifically limited herein. In an exemplary embodiment, for example, the timing controller TC may be mounted on a printed circuit board of the display device 1, and may be connected to the scan driver SDV, the emission driver EDV, and the data driver DDV through a flexible printed circuit board of the display device 1. The printed circuit board may be disposed at various positions, such as corresponding to an edge of the substrate SUB or facing the rear surface of the substrate SUB in its plan view.

[0082] The terminal unit is disposed at one end of the substrate SUB and includes a plurality of terminals 51, 52, 53, 54, 56, and 57. The terminal unit is disposed in the additional area ADA, for example, to define the additional area ADA as a terminal area. The peripheral area PPA of the substrate SUB includes a terminal area having a width smaller than that of the rest of the substrate SUB along the first direction DR1. As the additional area ADA, the terminal area of ​​the peripheral area PPA may be bendable relative to the rest of the peripheral area PPA of the substrate SUB.

[0083] The terminal unit may not be covered by the insulating layer of the display device 1 to be exposed, and may be electrically connected to a controller (not shown) such as a flexible printed circuit board and / or an integrated circuit ("IC") chip. The controller converts an electrical signal such as an image signal transmitted from the outside of the display panel into an electrical signal such as an image data signal, and transmits the converted electrical signal to the data driver DDV through the terminal 51. In addition, the controller may receive a vertical synchronization signal, a horizontal synchronization signal, and a clock signal as electrical signals to generate a control signal for controlling the driving of the scan driver SDV, the emission driver EDV, and the data driver DDV, thereby transmitting such electrical signals to the scan driver SDV, the emission driver EDV, and the data driver DDV through the terminals 51, 55, and 56. The controller transmits electrical signals such as a first initialization voltage and a second initialization voltage to the first initialization voltage line V1 and the second initialization voltage line V2 through the terminals 53 and 54, respectively. The controller transfers a driving voltage (eg, a first power voltage ELVDD) and a common voltage (eg, a second power voltage ELVSS) as electrical signals to a driving voltage supply line VDDL and a common voltage supply line VSSL through terminals 52 and 57, respectively.

[0084] The first initialization voltage supply line VI1 is disposed in the peripheral area PPA and supplies the first initialization voltage to one electrode of the fourth transistor of the pixel PXL. That is, the first initialization voltage supply line VI1 is connected to the pixel PXL. The second initialization voltage supply line VI2 is disposed in the peripheral area PPA and supplies the second initialization voltage to one electrode of the seventh transistor of the pixel PXL. That is, the second initialization voltage supply line VI2 is connected to the pixel PXL.

[0085] According to an exemplary embodiment of the present disclosure, the first initialization voltage supply line VI1 and the second initialization voltage supply line VI2 may be disposed in a vertical portion of the peripheral area PPA. In a pair of vertical portions of the peripheral area PPA spaced apart from each other along the width direction of the pixel area PXA, the first initialization voltage supply line VI1 and the second initialization voltage supply line VI2 may be disposed in two vertical portions of the peripheral area PPA. The first initialization voltage supply line VI1 and the second initialization voltage supply line VI2 may extend longitudinally along the longitudinal direction of the peripheral area PPA.

[0086] The driving voltage supply line VDDL is disposed in the peripheral area PPA. In an exemplary embodiment, for example, the driving voltage supply line VDDL may be disposed between the data driver DDV and the display unit 10. The driving voltage supply line VDDL supplies a driving voltage to the pixel PXL.

[0087] The common voltage supply line VSSL is disposed on the peripheral area PPA and supplies a common voltage to the cathode electrode of the organic light emitting element of the pixel PXL. In an exemplary embodiment, for example, the common voltage supply line VSSL may extend longitudinally along the edge of the substrate SUB excluding the terminal unit in a ring shape with one side (e.g., a side corresponding to the additional area ADA) opened.

[0088] The display unit 10 has a substantially quadrilateral planar shape, and its boundary includes one or more rounded corners 10C. The boundary may be defined between the pixel area PXA and the peripheral area PPA, but is not limited thereto. The ends of the scan driver SDV, the emission driver EDV, the first initialization voltage supply line VI1, the second initialization voltage supply line VI2, and the common voltage supply line VSSL may be bent along the rounded corner 10C of the display unit 10. In an exemplary embodiment, along the rounded corner 10C of the boundary, the first initialization voltage supply line VI1 and the second initialization voltage supply line VI2 are arranged in parallel with each other at a constant interval therebetween.

[0089] Figure 2 is a block diagram illustrating an exemplary embodiment of a pixel PXL and a driver on a single substrate SUB.

[0090] refer to Figure 2 , a display device 1 according to an exemplary embodiment of the present disclosure includes a pixel PXL, a driver, and wires (eg, conductive wires, signal wires, etc.).

[0091] A plurality of pixels PXL are provided in the display unit 10, such as by Figure 2 The driver includes a scan driver SDV, an emission driver EDV, a data driver DDV and a timing controller TC. Figure 2In the figure, for the convenience of illustration, the positions of the scan driver SDV, the emission driver EDV, the data driver DDV and the timing controller TC are shown, and in practice they may be arranged at other positions within the display device 1 .

[0092] The lines provide signals from the driver to each pixel PXL, and include a scan line S, a data line D, an emission control line E, a power line PL provided in plural (e.g., a plurality of power lines PL), and a first initialization power line and a second initialization power line (not shown). The scan line S includes a plurality of scan lines S1 to Sn (e.g., Figure 2 The scanning lines S1, S2, S3, S4, ... Sn shown in FIG. 1 ), and the emission control line E includes a plurality of emission control lines E1 to En (for example, in FIG. 1 ). Figure 2 , the emission control lines E1, E2, E3, E4, ... En shown in FIG. 1 ). The data lines D1 to Dm (for example, in FIG. 1 ) Figure 2 , D1, D2, D3, D4, ... Dm) and power lines PL shown in FIG. 1 are connected to the pixel PXL. The pixel PXL is positioned in the pixel area PXA. The pixel PXL is connected to the scan lines S1 to Sn, the emission control lines E1 to En, the data lines D1 to Dm, and the first initialization power line and the second initialization power line (not shown). When the scan signal is supplied from the scan lines S1 to Sn, the pixel PXL receives the data signal from the data lines D1 to Dm. The pixel PXL receiving the data signal controls the amount of current flowing from the first power supply voltage ELVDD to the second power supply voltage ELVSS via the organic light emitting element (not shown).

[0093] The scan driver SDV supplies the scan signal to the scan lines S1 to Sn in response to the first gate control signal GCS1 from the timing controller TC. In an exemplary embodiment, for example, the scan driver SDV may sequentially supply the scan signal to the scan lines S1 to Sn. By sequentially supplying the scan signal to the scan lines S1 to Sn, the pixels PXL on the same horizontal line are sequentially selected.

[0094] The emission driver EDV supplies the emission control signal to the emission control lines E1 to En in response to the second gate control signal GCS2 from the timing controller TC. In an exemplary embodiment, for example, the emission driver EDV may sequentially supply the emission control signal to the emission control lines E1 to En.

[0095] The width of the emission control signal may have a width greater than that of the scan signal. In an exemplary embodiment, for example, the emission control signal supplied to the i-th emission control line Ei may overlap with the scan signal supplied to the (i-1)-th scan line S(i-1) and the scan signal supplied to the i-th scan line Si for at least a period of time.

[0096] In addition, the emission control signal can be set to a gate-off voltage (e.g., a high level voltage) so that the transistor included in the pixel PXL can be turned off, and the scan signal can be set to a gate-on voltage (e.g., a low level voltage) so that the transistor included in the pixel PXL can be turned on.

[0097] The data driver DDV supplies data signals to the data lines D1 to Dm in response to the data control signal DCS. The data signals supplied to the data lines D1 to Dm are supplied to the pixels PXL selected by the scan signal.

[0098] The timing controller TC supplies gate control signals GCS1 and GCS2 generated based on a timing signal supplied from an external device to the scan driver SDV and the emission driver EDV, respectively, and supplies a data control signal DCS to the data driver DDV.

[0099] The gate control signals GCS1 and GCS2 each include a start pulse and a clock signal. The start pulse is used to control the timing of the first scanning signal or the first emission control signal. The clock signal is used to shift the start pulse.

[0100] The data control signal DCS includes a source start pulse and a clock signal. The source start pulse is used to control the starting point of data sampling. The clock signal is used to control the sampling operation.

[0101] Figure 3 The diagram shows the connection relationship between the pixel PXL, the line and the driver. Figure 1 An enlarged plan view of an exemplary embodiment of a portion P1 of FIG. Figure 1 A plane area indicated by P1 in FIG. 1 is a portion of a lower end portion of the pixel area PXA and a portion of a lower end portion of the peripheral area PPA. Figure 4 It shows Figure 3 A circuit diagram of an exemplary embodiment of a scanning stage.

[0102] exist Figure 3 In order to facilitate the illustration of the relationship between the lines, as an example, one scan line S connected to a single pixel PXL among a plurality of scan lines S and a single emission control line E connected to a single pixel PXL among a plurality of emission control lines E are shown, which are indicated by "S" and "E", respectively. In addition, only a portion of the data line D and the power line are depicted, wherein the data line D is indicated by "D". Figure 3 , the substrate SUB is divided into a pixel area PXA and a peripheral area PPA, and the pixels PXL are disposed in the pixel area PXA.

[0103] Pixel rows each including a pixel PXL may extend along the first direction DR1 and be arranged along the second direction DR2 such that the pixel rows are parallel to the first direction DR1. Pixel columns each including a pixel PXL may extend along the second direction DR2 and be arranged along the first direction DR1 such that the pixel columns are parallel to the second direction DR2. That is, the pixels PXL may be arranged in a matrix form. The pixels PXL will be described later.

[0104] The boundary of the pixel area PXA has straight sides and curved sides and rounded corners. The substrate SUB may have rounded corners corresponding to the rounded corners 10C of the display unit 10 and / or the rounded corners of the boundary between the pixel area PXA and the peripheral area PPA. The pixel area PXA may include rounded corners corresponding to the rounded corners of the display unit 10 and / or the substrate SUB.

[0105] Assuming that the axis parallel to the first direction DR1 is the x-axis, in the pixel area PXA except for the corners, the positions of the outermost pixels PXL along the x-axis and the number of pixels PXL in each pixel row are equal. Figure 3 , the top three pixel rows are shown with the leftmost pixels PXL aligned with each other along the second direction DR2 (e.g., the outermost is closest to the peripheral area PPA). Such a position of the outermost pixels PXL along the first direction DR1 can be considered a reference or reference position. Therefore, the pixel rows corresponding to the areas of the peripheral area PPA along the second direction DR2 except for the corners can have the same length L along the first direction DR1.

[0106] In contrast, in the area corresponding to the corner of the pixel area PXA, the number of pixels PXL of each pixel row decreases or decreases along the second direction DR2 toward the additional area ADA. The position of the outermost pixel PXL of the pixel row along the x-axis becomes farther away from the reference, for example, the position of the outermost pixel PXL of each pixel row in the pixel area PXA other than the corner. In other words, the pixel row closer to the lower side of the display device 1 (for example, away from the center of the pixel area PXA) along the second direction DR2 has a reduced length L along the first direction DR1, so that the boundary of the plane area of ​​the pixel area PXA can have rounded corners. Therefore, different pixel rows corresponding to the corners of the pixel area PXA can have different numbers of pixels PXL therein. At the corners of the pixel area PXA, as the pixel row is closer to the center of the pixel area PXA, the pixel row can include more pixels PXL.

[0107] Although only one side of the pixel area PXA (eg, Figure 1 ), but it should be understood that the other side of the pixel area PXA (e.g., Figure 1The right side of the pixel row (in the right side) may be provided or formed in the same manner so that the shape of the pixel area PXA is symmetrical about the central axis extending along the second direction DR2. As the distance between the pixel row and the center of the pixel area PXA increases, the length L of the pixel row along the first direction DR1 decreases, but the length L may not decrease at the same ratio (or the number of pixels PXL arranged in the pixel row may not decrease at the same ratio). The number of pixels PXL arranged in each pixel row may change depending on the curvature of the corner of the pixel area PXA.

[0108] A driver may be disposed in the peripheral area PPA, and a line may connect the pixel PXL with the driver.

[0109] The driver includes a scan driver SDV connected to the pixel PXL through a scan line S. The scan driver SDV is disposed adjacent to the pixel area PXA.

[0110] The scan driver SDV according to an exemplary embodiment of the present disclosure includes a plurality of scan stages SST (e.g., a plurality of scan stages SST). Each scan stage SST is connected to one scan line S among a plurality of scan lines S. The scan line S connects the output terminal of the scan stage SST to the scan signal input terminal of the outermost pixel PXL of the pixel row. The scan stage SST is driven as soon as it receives a clock signal. Such a scan stage SST can be implemented with substantially the same circuit.

[0111] The scanning driver SDV may have a boundary having a curved shape corresponding to the corner of the pixel area PXA. In an exemplary embodiment, for example, the scanning stage SST may be arranged along the edge of the pixel area PXA. Therefore, a virtual line (e.g., Figure 3 The dotted line in the figure) can have a curved shape with a predetermined curvature.

[0112] The scanning stages SST may be respectively associated with pixel rows of the pixel area PXA, and may supply scan signals to the pixels PXL arranged in the pixel rows.

[0113] As in Figure 4 As shown in , the scan driver SDV may include a plurality of scan stages SST that are cascaded, and the scan stages SST may output scan signals to the scan lines S sequentially.

[0114] As in Figure 4 As shown in , each scanning stage SST includes a pull-up node NQ, a pull-down node NQB, a pull-up transistor TU turned on when the pull-up node NQ has a gate-on voltage, a pull-down transistor TD turned on when the pull-down node NQB has a gate-on voltage, and a node controller NC for controlling the charging / discharging of the pull-up node NQ and the pull-down node NQB.

[0115] The node controller NC may be connected to a start terminal ST to which a start signal or an output signal from a previous stage is input, a reset terminal RT to which an output signal from a next stage is input, a gate-on voltage terminal VGHT to which a gate-on voltage is applied, and a gate-off voltage terminal VGLT to which a gate-off voltage is applied. The node controller NC controls the charging and discharging of the pull-up node NQ and the pull-down node NQB according to the start signal or the output signal input to the start terminal ST from the previous stage. In order to stably control the output from the scanning stage SST, the node controller NC causes the pull-down node NQB to have a gate-off voltage when the pull-up node NQ has a gate-on voltage, and the pull-up node NQ has a gate-off voltage when the pull-down node NQB has a gate-on voltage. To this end, the node controller NC may include a plurality of transistors.

[0116] When the scanning stage SST is pulled up, that is, when the pull-up node NQ has a gate-on voltage, the pull-up transistor TU is turned on to output the clock signal input to the clock signal CT to the output terminal OT. When the scanning stage SST is pulled down, that is, when the pull-down node NQB has a gate-on voltage, the pull-down transistor TD is turned on to output the gate-off voltage at the gate-off voltage terminal VGLT to the output terminal OT.

[0117] The pull-up transistor TU and the pull-down transistor TD of the scan driver SDV and the plurality of transistors of the node controller NC may be implemented as thin film transistors. Figure 4 In the example shown in FIG. 1 , the n-type semiconductor transistor is implemented as an n-type semiconductor transistor having n-type semiconductor characteristics, but the exemplary embodiments of the present disclosure are not limited thereto. In an exemplary embodiment, for example, the pull-up transistor TU and the pull-down transistor TD of the scan driver SDV and the plurality of transistors of the node controller NC may be implemented as p-type semiconductor transistors having p-type semiconductor characteristics.

[0118] Return to reference Figure 3 , the scan line S set in the pixel area PXA may be parallel to the first direction DR1. The scan line S in the peripheral area PPA may be parallel to the first direction DR1 or inclined relative to the first direction DR1. Because the corner of the peripheral area PPA is curved, the scanning stage SST is also arranged along the curved angle of the peripheral area PPA. Therefore, the scan line S in the peripheral area PPA may be bent at a specific position and may have an angle inclined relative to the first direction DR1. Because the position at the output terminal of the scanning stage SST is different from the position at the scan signal input terminal of the outermost pixel PXL of the pixel row, the scan line S is bent.

[0119] The driver further includes an emission driver EDV connected to the pixel PXL, and the emission driver EDV is adjacent to the scan driver SDV. The scan driver SDV may be positioned between the emission driver EDV and the pixel region PXA. Therefore, the emission driver EDV may be disposed further outside (eg, further away from the pixel region PXA) than the scan driver SDV.

[0120] According to an exemplary embodiment of the present disclosure, the emission driver EDV includes an emission stage EST provided in plurality (e.g., a plurality of emission stages EST). The emission control line E connects the output terminal of the emission stage EST to the scan signal input terminal of the outermost pixel PXL of the pixel row. The scanning stage SST is driven as soon as it receives a clock signal. Such an emission stage EST can be implemented with substantially the same circuit.

[0121] The emission driver EDV may have a curved shape corresponding to the corners of the pixel area PXA. In an exemplary embodiment, for example, a virtual line (eg, Figure 3 The dotted line in the figure) can have a curved shape with a predetermined curvature.

[0122] The emission stages EST may be respectively associated with pixel rows of the pixel area PXA, and may supply emission control signals to the pixels PXL arranged in the pixel rows.

[0123] The emission control line E disposed in the pixel area PXA may be parallel to the first direction DR1. The emission control line E in the peripheral area PPA may be parallel to the first direction DR1 or inclined relative to the first direction DR1. The first end of the emission control line E disposed in the peripheral area PPA is connected to the pixel PXL, and the second end of the emission control line E opposite to the first end is connected to the emission stage EST. Because the boundary at the corner of the peripheral area PPA is curved, the emission stage EST is also arranged along the curved angle of the peripheral area PPA. Therefore, the emission control line E in the peripheral area PPA may be bent at a specific position and may have an angle inclined relative to the first direction DR1. Because the position at the output terminal of the emission stage EST is different from the position at the scan signal input terminal of the outermost pixel PXL of the pixel row, the emission control line E is bent.

[0124] Although for ease of illustration, Figure 3 In the example shown in , the scan line S and the emission control line E are connected only to the outermost pixels PXL of the pixel row, but the scan line S is connected to all the pixels PXL included in the pixel row. Likewise, the emission control line E is connected to all the pixels PXL provided in the pixel row.

[0125] Next, the data driver DDV (see Figure 1) may be disposed in a horizontal portion of the additional area ADA. Data lines D associated with the pixel columns may be connected to the pixel columns, respectively. The data lines D are connected to a data driver DDV. Although for ease of illustration, in Figure 3 In the example shown in , the data line D is connected only to the outermost pixel PXL of the pixel column, but the data line D is connected to all pixels PXL included in the pixel column. The pixels PXL in the same column may share the same data line D among the data lines D. The data line D in the pixel area PXA extends along the second direction DR2. The data line D extends in the peripheral area PPA substantially along the second direction DR2. However, the data line D may be bent at a specific position and may extend in a direction inclined relative to the second direction DR2.

[0126] The data lines D may extend such that the distance therebetween decreases in a direction toward the data driver DDV, and a fan-out structure of the data lines D may be formed, for example, the data lines D are extended spaced apart from each other in a direction from the data driver DDV toward the pixels PXL. Figure 3 For example, a first portion of the data line D corresponds to the first initialization voltage supply line VI1, and a distance between end portions of the data line D increases in a direction toward the pixel PXL to define a fan-out structure. Similarly, a second portion of the data line D corresponds to the second initialization voltage supply line VI2, and a distance between end portions of the data line D increases in a direction toward the pixel PXL to define a fan-out structure.

[0127] A plurality of power lines PL (eg, a plurality of power lines PL) provided in association with the pixel columns, respectively, may be connected to the pixel columns. The power lines PL transmit the first power supply voltage ELVDD (see Figure 2 ) is supplied to the pixel PXL. Although for ease of illustration, Figure 2 In the example shown in , the first power line PL1 is connected only to the outermost pixels PXL of the pixel column, but the first power line PL1 is connected to all pixels PXL included in the pixel column. The pixels PXL in the same column may share the same first power line PL1.

[0128] Next, we will describe Figure 3 The pixel PXL is shown in FIG.

[0129] Figure 5 It shows that Figure 3 FIG. 1 is a diagram of an exemplary embodiment of a pixel PXL shown in FIG. 1 . For ease of illustration, Figure 5 A pixel PXL connected to an mth data line Dm and an ith scan line Si is shown.

[0130] refer to Figure 5, the pixel PXL according to an exemplary embodiment of the present disclosure includes an organic light emitting diode OLED, first to seventh transistors T1 to T7 , and a storage capacitor Cst.

[0131] An anode of the organic light emitting diode OLED is connected to the first transistor T1 via the sixth transistor T6, and a cathode of the organic light emitting diode OLED is connected to the second power supply voltage ELVSS. The organic light emitting diode OLED generates light having a predetermined brightness proportional to the amount of current supplied from the first transistor T1.

[0132] The first power voltage ELVDD may be set to a voltage higher than the second power voltage ELVSS so that current may flow to the organic light emitting diode OLED.

[0133] The seventh transistor T7 is connected between the second initialization voltage supply line VI2 and the anode of the organic light emitting diode OLED. The gate electrode of the seventh transistor T7 is connected to the (i+1)th scan line S(i+1). When the scan signal is supplied to the (i+1)th scan line S(i+1), the seventh transistor T7 is turned on, thereby transmitting the voltage of the second initialization voltage supply line VI2 (for example, the second initialization voltage Vint2) to the anode of the organic light emitting diode OLED. The second initialization voltage Vint2 can be set to a voltage lower than the second power supply voltage ELVSS.

[0134] The sixth transistor T6 is connected between the first transistor T1 and the organic light emitting diode OLED. A gate electrode of the sixth transistor T6 is connected to the i-th emission control line Ei. The sixth transistor T6 is turned off when an emission control signal is supplied to the i-th emission control line Ei, and is turned on otherwise.

[0135] The fifth transistor T5 is connected between the first power supply voltage ELVDD and the first transistor T1. A gate electrode of the fifth transistor T5 is connected to the i-th emission control line Ei. The fifth transistor T5 is turned off when an emission control signal is supplied to the i-th emission control line Ei, and is turned on otherwise.

[0136] A first electrode of the first transistor T1 (driving transistor) is connected to the first power supply voltage ELVDD via the fifth transistor T5, and a second electrode of the first transistor T1 is connected to the anode of the organic light emitting diode OLED via the sixth transistor T6. A gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 controls the amount of current flowing from the first power supply voltage ELVDD to the second power supply voltage ELVSS via the organic light emitting diode OLED in proportion to the voltage of the first node N1.

[0137] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. In addition, the gate electrode of the third transistor T3 is connected to the i-th scan line Si. When the scan signal is supplied to the i-th scan line Si, the third transistor T3 is turned on to electrically connect the second electrode of the first transistor T1 with the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 is connected in a diode manner.

[0138] The fourth transistor T4 is connected between the first node N1 and the first initialization voltage supply line VI1. In addition, the gate electrode of the fourth transistor T4 is connected to the (i-1)th scan line S(i-1). When the scan signal is supplied to the (i-1)th scan line S(i-1), the fourth transistor T4 is turned on to supply the voltage of the first initialization voltage supply line VI1 (e.g., the first initialization voltage Vint1) to the first node N1. The first initialization voltage Vint1 can be set to a voltage lower than the voltage of the data signal.

[0139] The second transistor T2 is connected between the mth data line Dm and the first electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 is connected to the i-th scan line Si. When the scan signal is supplied to the i-th scan line Si, the second transistor T2 is turned on to electrically connect the mth data line Dm with the first electrode of the first transistor T1.

[0140] The storage capacitor Cst is connected between the first power supply voltage ELVDD and the first node N1. The storage capacitor Cst stores a voltage equal to the data signal and the threshold voltage of the first transistor T1.

[0141] Figure 6 It shows in detail Figure 3 An enlarged plan view of the pixel PXL. Figure 7 It is along Figure 6 A cross-sectional view taken along line II'. Figure 8 It is along Figure 6 A cross-sectional view taken along line II-II'.

[0142] Figure 6 , Figure 7 and Figure 8 Three scan lines S(i-1), Si and S(i+1), an emission control line Ei, a power line PL, an additional power line PL' and a data line Dj connected to the pixel PXL disposed in the i-th row and the j-th column in the pixel area PXA are shown. Figure 7 and Figure 8, for ease of illustration, the scan line in the (i-1)th row is indicated by the (i-1)th scan line S(i-1), the scan line in the i-th row is indicated by the i-th scan line Si, the scan line in the (i+1)th row is indicated by the (i+1)th scan line S(i+1), the emission control line in the i-th row is indicated by the emission control line Ei, the data line in the j-th column is indicated by the data line Dj, the j-th power line is indicated by the power line PL, and the additional power line is indicated by the additional power line PL'.

[0143] refer to Figures 3 to 6 , Figure 7 and Figure 8 , the display device 1 includes a substrate SUB, lines and pixels PXL.

[0144] The lines supply signals to each pixel PXL, and include scan lines S(i-1), Si, and S(i+1), data lines Dj, emission control lines Ei, power lines PL, additional power lines PL', and first and second initialization voltage lines V1 and V2.

[0145] The scan lines S(i-1), Si and S(i+1) extend along the first direction DR1 and include the (i-1)th scan line S(i-1), the i-th scan line Si and the (i+1)th scan line S(i+1) arranged in this order along the second direction DR2. Scan signals are applied to the scan lines S(i-1), Si and S(i+1). The (i-1)th scan signal is applied to the (i-1)th scan line S(i-1), the i-th scan signal is applied to the i-th scan line Si, and the (i+1)th scan signal is applied to the (i+1)th scan line S(i+1).

[0146] The emission control line Ei extends along the first direction DR1 and is disposed between the i-th scan line Si and the (i+1)-th scan line S(i+1) so as to be spaced apart from the i-th scan line Si and the (i+1)-th scan line S(i+1). An emission control signal is applied to the emission control line Ei.

[0147] The data line Dj extends along the second direction DR2. A data signal is applied to the data line Dj.

[0148] The power line PL extends in the second direction DR2 and is spaced apart from the data line Dj. A first power voltage ELVDD is applied to the power line PL.

[0149] The additional power line PL′ overlaps the power line PL in the thickness direction (eg, the third direction DR3 ) and is connected to the power line PL to apply the same first power voltage ELVDD through the eleventh contact hole CH11 .

[0150] The first initialization voltage line V1 extends along the first direction DR1 and is disposed between the (i+1)th scan line S(i+1) and the (i-1)th scan line S(i-1) of the next pixel row. A first initialization voltage Vint1 is applied to the first initialization voltage line V1.

[0151] The second initialization voltage line V2 extends along the first direction DR1 and is disposed between the (i+1)th scan line S(i+1) and the (i-1)th scan line S(i-1) of the next pixel row. A second initialization voltage Vint2 is applied to the second initialization voltage line V2.

[0152] Each pixel PXL includes first to seventh transistors T1 to T7 , a storage capacitor Cst, and an organic light emitting diode OLED.

[0153] The first transistor T1 includes a first gate electrode GE1, a first active pattern ACT1, a first source electrode SE1, a first drain electrode DE1, and a connection line CNL.

[0154] The first gate electrode GE1 is connected to the third drain electrode DE3 of the third transistor T3 and the fourth drain electrode DE4 of the fourth transistor T4. The connection line CNL connects the first gate electrode GE1 and the third drain electrode DE3 to each other, and connects the first gate electrode GE1 and the fourth drain electrode DE4 to each other. One end of the connection line CNL is connected to the first gate electrode GE1 through the first contact hole CH1, and the other end of the connection line CNL is connected to the third drain electrode DE3 and the fourth drain electrode DE4 through the second contact hole CH2.

[0155] According to an exemplary embodiment of the present disclosure, the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be provided or formed as a semiconductor layer doped with impurities or a semiconductor layer not doped with impurities. The first source electrode SE1 and the first drain electrode DE1 may be provided or formed by a semiconductor layer doped with impurities, and the first active pattern ACT1 may be provided or formed by a semiconductor layer not doped with impurities.

[0156] The first active pattern ACT1 may have a rod shape extending in a predetermined direction, and may have a shape bent several times in the length direction of the extension. When viewed from the top (e.g., a plan view), the first active pattern ACT1 overlaps the first gate electrode GE1. Because the first active pattern ACT1 is provided or formed to be relatively long, the channel region of the first transistor T1 is provided or formed to be relatively long. Therefore, the driving range of the gate voltage applied to the first transistor T1 is widened. Therefore, the gray scale of the light emitted from the organic light emitting diode OLED can be accurately adjusted in subsequent use.

[0157] The first source electrode SE1 is connected to one end of the first active pattern ACT1 and is connected to the second drain electrode DE2 of the second transistor T2 and the fifth drain electrode DE5 of the fifth transistor T5. The first drain electrode DE1 is connected to the other end of the first active pattern ACT1 and is connected to the third source electrode SE3 of the third transistor T3 and the sixth source electrode SE6 of the sixth transistor T6.

[0158] The second transistor T2 includes a second gate electrode GE2 , a second active pattern ACT2 , a second source electrode SE2 , and a second drain electrode DE2 .

[0159] The second gate electrode GE2 is connected to the i-th scan line Si. The second gate electrode GE2 is provided or formed as a part of the i-th scan line Si, or may protrude from the i-th scan line Si. According to an exemplary embodiment of the present disclosure, the second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be provided or formed as a semiconductor layer doped with impurities or a semiconductor layer not doped with impurities. The second source electrode SE2 and the second drain electrode DE2 may be provided or formed by a semiconductor layer doped with impurities, and the second active pattern ACT2 may be provided or formed by a semiconductor layer not doped with impurities. The second active pattern ACT2 corresponds to a portion overlapping with the second gate electrode GE2. One end of the second source electrode SE2 is connected to the second active pattern ACT2, and the other end of the second source electrode SE2 is connected to the data line Dj through the sixth contact hole CH6. One end of the second drain electrode DE2 is connected to the second active pattern ACT2, and the other end of the second drain electrode DE2 is connected to the first source electrode SE1 of the first transistor T1 and the fifth drain electrode DE5 of the fifth transistor T5.

[0160] The third transistor T3 may be implemented as a dual-gate structure to reduce or effectively prevent leakage current. That is, the third transistor T3 may include a transistor T3a and a transistor T3b. The transistor T3a may include a gate electrode GE3a, an active pattern ACT3a, a source electrode SE3a, and a drain electrode DE3a. The transistor T3b may include a gate electrode GE3b, an active pattern ACT3b, a source electrode SE3b, and a drain electrode DE3b. In the following description, the gate electrode GE3a and the gate electrode GE3b are referred to as the third gate electrode GE3, the active pattern ACT3a and the active pattern ACT3b are referred to as the third active pattern ACT3, the source electrode SE3a and the source electrode SE3b are referred to as the third source electrode SE3, and the drain electrode DE3a and the drain electrode DE3b are referred to as the third drain electrode DE3.

[0161] The third gate electrode GE3 is connected to the i-th scan line Si. The third gate electrode GE3 is provided or formed as a part of the i-th scan line Si, or may protrude from the i-th scan line Si. According to an exemplary embodiment of the present disclosure, the third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 may be provided or formed as a semiconductor layer doped with impurities or a semiconductor layer not doped with impurities. The third source electrode SE3 and the third drain electrode DE3 may be provided or formed by a semiconductor layer doped with impurities, and the third active pattern ACT3 may be provided or formed by a semiconductor layer not doped with impurities. The third active pattern ACT3 corresponds to a portion overlapping with the third gate electrode GE3. One end of the third source electrode SE3 is connected to the third active pattern ACT3, and the other end of the third source electrode SE3 is connected to the first drain electrode DE1 of the first transistor T1 and the sixth source electrode SE6 of the sixth transistor T6. One end of the third drain electrode DE3 is connected to the third active pattern ACT3, and the other end of the third drain electrode DE3 is connected to the fourth drain electrode DE4 of the fourth transistor T4. In addition, the third drain electrode DE3 is connected to the first gate electrode GE1 of the first transistor T1 through the connection line CNL, the second contact hole CH2, and the first contact hole CH1.

[0162] The fourth transistor T4 may be implemented as a dual-gate structure to reduce or effectively prevent leakage current. That is, the fourth transistor T4 may include a transistor T4a and a transistor T4b. The transistor T4a may include a gate electrode GE4a, an active pattern ACT4a, a source electrode SE4a, and a drain electrode DE4a. The transistor T4b may include a gate electrode GE4b, an active pattern ACT4b, a source electrode SE4b, and a drain electrode DE4b. In the following description, the gate electrode GE4a and the gate electrode GE4b are referred to as a fourth gate electrode GE4, the active pattern ACT4a and the active pattern ACT4b are referred to as a fourth active pattern ACT4, the source electrode SE4a and the source electrode SE4b are referred to as a fourth source electrode SE4, and the drain electrode DE4a and the drain electrode DE4b are referred to as a fourth drain electrode DE4.

[0163] The fourth gate electrode GE4 is connected to the (i-1)th scan line S(i-1). The fourth gate electrode GE4 is provided or formed as a part of the (i-1)th scan line S(i-1), or may protrude from the (i-1)th scan line S(i-1). The fourth active pattern ACT4, the fourth source electrode SE4, and the fourth drain electrode DE4 are provided or formed by a semiconductor layer doped with impurities or a semiconductor layer not doped with impurities. The fourth source electrode SE4 and the fourth drain electrode DE4 are provided or formed by a semiconductor layer doped with impurities, and the fourth active pattern ACT4 is provided or formed by a semiconductor layer not doped with impurities. The fourth active pattern ACT4 corresponds to a portion overlapping with the fourth gate electrode GE4. One end of the fourth source electrode SE4 is connected to the fourth active pattern ACT4, and the other end of the fourth source electrode SE4 is connected to the first initialization voltage line V1. The source electrode SE4a is connected to the first initialization voltage line V1 through the ninth contact hole CH9. One end of the fourth drain electrode DE4 is connected to the fourth active pattern ACT4, and the other end of the fourth drain electrode DE4 is connected to the third drain electrode DE3 of the third transistor T3. In addition, the fourth drain electrode DE4 is connected to the first gate electrode GE1 of the first transistor T1 through the connection line CNL, the second contact hole CH2 and the first contact hole CH1.

[0164] The fifth transistor T5 includes a fifth gate electrode GE5 , a fifth active pattern ACT5 , a fifth source electrode SE5 , and a fifth drain electrode DE5 .

[0165] The fifth gate electrode GE5 is connected to the emission control line Ei. The fifth gate electrode GE5 is provided or formed as a part of the emission control line Ei, or may protrude from the emission control line Ei. The fifth active pattern ACT5, the fifth source electrode SE5, and the fifth drain electrode DE5 are provided or formed by a semiconductor layer doped with impurities or a semiconductor layer not doped with impurities. The fifth source electrode SE5 and the fifth drain electrode DE5 are provided or formed by a semiconductor layer doped with impurities, and the fifth active pattern ACT5 is provided or formed by a semiconductor layer not doped with impurities. The fifth active pattern ACT5 corresponds to a portion overlapping with the fifth gate electrode GE5. One end of the fifth source electrode SE5 is connected to the fifth active pattern ACT5, and the other end of the fifth source electrode SE5 is connected to the power line PL through the fifth contact hole CH5. One end of the fifth drain electrode DE5 is connected to the fifth active pattern ACT5, and the other end of the fifth drain electrode DE5 is connected to the first source electrode SE1 of the first transistor T1 and the second drain electrode DE2 of the second transistor T2.

[0166] The sixth transistor T6 includes a sixth gate electrode GE6 , a sixth active pattern ACT6 , a sixth source electrode SE6 , and a sixth drain electrode DE6 .

[0167] The sixth gate electrode GE6 is connected to the emission control line Ei. The sixth gate electrode GE6 is provided or formed as a part of the emission control line Ei, or may protrude from the emission control line Ei. The sixth active pattern ACT6, the sixth source electrode SE6, and the sixth drain electrode DE6 are provided or formed by a semiconductor layer doped with impurities or a semiconductor layer not doped with impurities. The sixth source electrode SE6 and the sixth drain electrode DE6 are provided or formed by a semiconductor layer doped with impurities, and the sixth active pattern ACT6 is provided or formed by a semiconductor layer not doped with impurities. The sixth active pattern ACT6 corresponds to a portion overlapping with the sixth gate electrode GE6. One end of the sixth source electrode SE6 is connected to the sixth active pattern ACT6, and the other end of the sixth source electrode SE6 is connected to the first drain electrode DE1 of the first transistor T1 and the third source electrode SE3 of the third transistor T3. One end of the sixth drain electrode DE6 is connected to the sixth active pattern ACT6, and the other end of the sixth drain electrode DE6 is connected to the seventh source electrode SE7 of the seventh transistor T7.

[0168] The seventh transistor T7 includes a seventh gate electrode GE7, a seventh active pattern ACT7, a seventh source electrode SE7, and a seventh drain electrode DE7.

[0169] The seventh gate electrode GE7 is connected to the (i+1)th scan line S(i+1). The seventh gate electrode GE7 is provided or formed as a part of the (i+1)th scan line S(i+1), or may protrude from the (i+1)th scan line S(i+1). The seventh active pattern ACT7, the seventh source electrode SE7, and the seventh drain electrode DE7 are provided or formed by a semiconductor layer doped with impurities or a semiconductor layer not doped with impurities. The seventh source electrode SE7 and the seventh drain electrode DE7 are provided or formed by a semiconductor layer doped with impurities, and the seventh active pattern ACT7 is provided or formed by a semiconductor layer not doped with impurities. The seventh active pattern ACT7 corresponds to a portion overlapping with the seventh gate electrode GE7. One end of the seventh source electrode SE7 is connected to the seventh active pattern ACT7, and the other end of the seventh source electrode SE7 is connected to the sixth drain electrode DE6 of the sixth transistor T6. One end of the seventh drain electrode DE7 is connected to the seventh active pattern ACT7, and the other end of the seventh drain electrode DE7 is connected to the second initialization voltage line V2. The seventh drain electrode DE7 is connected to the second initialization voltage line V2 through the eighth contact hole CH8.

[0170] The storage capacitor Cst includes a lower electrode LE and an upper electrode UE. The lower electrode LE may be provided or formed as a first gate electrode GE1 of the first transistor T1.

[0171] When viewed from the top, the upper electrode UE overlaps the first gate electrode GE1 and covers the lower electrode LE. By increasing the plane area where the upper electrode UE and the lower electrode LE overlap each other, the capacitance of the storage capacitor Cst can be increased. The upper electrode UE may extend along the first direction DR1. According to an exemplary embodiment of the present disclosure, a voltage having the same level as that of the first power supply voltage ELVDD may be applied to the upper electrode UE. The upper electrode UE may have an opening OPN in which a first contact hole CH1 is provided or formed, and the first gate electrode GE1 contacts the connection line CNL here.

[0172] The organic light emitting diode OLED includes an anode AD, a cathode CD, and an emission layer EML disposed between the anode AD and the cathode CD.

[0173] The anode AD is disposed in a pixel region corresponding to each pixel PXL. The anode AD is connected to the seventh source electrode SE7 of the seventh transistor T7 and the sixth drain electrode DE6 of the sixth transistor T6 through the seventh contact hole CH7 and the tenth contact hole CH10. The bridge pattern BRP is disposed between the seventh contact hole CH7 and the tenth contact hole CH10 to connect the sixth drain electrode DE6 and the seventh source electrode SE7 with the anode AD.

[0174] Return to reference Figure 6 , Figure 7 and Figure 8 , the structure of the display device according to the exemplary embodiment of the present disclosure will be described in a stacking order along a thickness direction.

[0175] Initially, active patterns ACT1 to ACT7 (hereinafter, ACT) are disposed on a substrate SUB. The active patterns ACT include first to seventh active patterns ACT1 to ACT7. The first to seventh active patterns ACT1 to ACT7 include or are made of a semiconductor material.

[0176] A buffer layer may be disposed between the substrate SUB and the first to seventh active patterns ACT1 to ACT7 .

[0177] The gate insulating layer GI is disposed on the substrate SUB on which the first to seventh active patterns ACT1 to ACT7 are provided or formed.

[0178] On the gate insulating layer GI, the (i-1)th scan line S(i-1) to the (i+1)th scan line S(i+1), the emission control line Ei, the first initialization voltage line V1, the second initialization voltage line V2, the first gate electrode GE1, and the seventh gate electrode GE7 are provided. The first gate electrode GE1 is used as the lower electrode LE of the storage capacitor Cst. The second gate electrode GE2 and the third gate electrode GE3 may be provided or formed integrally with the i-th scan line Si, the fourth gate electrode GE4 may be provided or formed integrally with the (i-1)th scan line S(i-1), the fifth gate electrode GE5 and the sixth gate electrode GE6 may be provided or formed integrally with the emission control line Ei, and the seventh gate electrode GE7 may be provided or formed integrally with the (i+1)th scan line S(i+1).

[0179] The first insulating layer IL1 is disposed on the substrate SUB on which the (i-1)th scan line S(i-1) and the like are provided or formed.

[0180] The upper electrode UE of the storage capacitor Cst and the initialization power line (not shown) are disposed on the first insulating layer IL1. The upper electrode UE covers the lower electrode LE and forms the storage capacitor Cst together with the lower electrode LE, with the first insulating layer IL1 disposed therebetween.

[0181] The second insulating layer IL2 is disposed on the substrate SUB on which the upper electrode UE and the like are provided or formed.

[0182] The j-th data line Dj, the power line PL, the connection line CNL, and the bridge pattern BRP are disposed on the second insulating layer IL2.

[0183] The jth data line Dj is connected to the second source electrode SE2 through a sixth contact hole CH6 passing through the first insulating layer IL1, the second insulating layer IL2 and the gate insulating layer GI. The power line PL is connected to the upper electrode UE of the storage capacitor Cst through third and fourth contact holes CH3 and CH4 passing through the second insulating layer IL2.

[0184] The power line PL is connected to the fifth source electrode SE5 through a fifth contact hole CH5 passing through the first insulating layer IL1 , the second insulating layer IL2 , and the gate insulating layer GI.

[0185] The connection line CNL is connected to the first gate electrode GE1 through a first contact hole CH1 passing through the first and second insulating layers IL1 and IL2. The connection line CNL may also be connected to the third and fourth drain electrodes DE3 and DE4 through a second contact hole CH2 passing through the gate insulating layer GI, the first and second insulating layers IL1 and IL2.

[0186] The bridge pattern BRP is an intermediate member provided between the sixth drain electrode DE6 and the anode AD to connect the sixth drain electrode DE6 with the anode AD, and is connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through a seventh contact hole CH7 passing through the gate insulating layer GI, the first insulating layer IL1 and the second insulating layer IL2.

[0187] The third insulating layer IL3 is disposed on the substrate SUB on which the j-th data line Dj and the like are provided or formed.

[0188] The additional power line PL' is disposed on the third insulating layer IL3. The additional power line PL' is used to stably supply the first power voltage ELVDD to the power line PL without delay and reduce the resistance applied to the power line PL. The additional power line PL' extends along the second direction DR2 and overlaps the power line PL. The additional power line PL' is connected to the power line PL through an eleventh contact hole CH11 passing through the third insulating layer IL3.

[0189] The passivation layer PSV is disposed on the third insulating layer IL3 where the additional power line PL′ is disposed.

[0190] The anode AD is disposed on the passivation layer PSV. The anode AD is connected to the bridge pattern BRP through the twelfth contact hole CH12 passing through the passivation layer PSV. Since the bridge pattern BRP is connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through the seventh contact hole CH7, the anode AD is finally connected to the sixth drain electrode DE6 and the seventh source electrode SE7.

[0191] On the substrate SUB on which the anode AD and the like are provided or formed, a pixel defining layer PDL is provided to separate pixel areas within each pixel PXL. Within the pixel PXL, the pixel defining layer PDL defines an open area (e.g., a light emitting area or a pixel area) in which light is emitted. The pixel defining layer PDL exposes the upper surface of the anode AD and protrudes from the substrate SUB along the boundary of the pixel PXL.

[0192] The emission layer EML is disposed in a pixel region surrounded by the pixel defining layer PDL in the pixel PXL, and the cathode CD is disposed on the emission layer EML.

[0193] A sealing member SLM covering the cathode CD is provided on the cathode CD.

[0194] Fig. 9 It shows Figure 3 An enlarged plan view of a portion P2 of an exemplary embodiment of the present invention. Fig.10 It is along Fig. 9 A cross-sectional view taken along line III-III'. Fig.11 It is along Fig. 9 A cross-sectional view taken along line IV-IV'. Fig.12 It is along Fig. 9 A cross-sectional view taken along line V-V'. Fig.13 It is along Fig. 9 A cross-sectional view taken along line VI-VI'. Fig.14 It is along Fig. 9 A cross-sectional view taken along line IV-IV'. Fig.15 It is along Fig. 9 A cross-sectional view taken along line V-V'.

[0195] exist Figures 9 to 15 , in order to facilitate the illustration of the relationship between the lines, a scan line connected to a single pixel PXL among a plurality of scan lines and a single emission control line connected to a single pixel PXL among a plurality of emission control lines E are shown as examples, which are indicated by scan line S and emission control line E, respectively. In addition, only a portion of the first initialization voltage line and the second initialization voltage line are depicted. The first initialization voltage source line is referred to as the first initialization voltage source line VI1, the first initialization voltage line is referred to as the first initialization voltage line V1, the second initialization voltage source line is referred to as the second initialization voltage source line VI2, and the second initialization voltage line is referred to as the second initialization voltage line V2. In addition, only a portion of the data line D is shown, and the data line D is shown as "D". Although only a portion of the lines are depicted, scan lines, emission control lines, data lines, first initialization voltage lines, and second initialization voltage lines that are not shown may be further provided in the manner described below.

[0196] In the following, reference will be made to Figures 9 to 15 Describes the connection relationship between lines.

[0197] The emission control line E extends from the pixel area PXA along the first direction DR1, and also extends substantially along the first direction DR1 into the peripheral area PPA. When viewed from the top, the emission control line E is separated from the scan line S by a predetermined distance, and at least a portion of the emission control line E extends parallel to the scan line S. The emission control line E may be bent in a direction inclined relative to the first direction DR1 depending on the position at the corner, and may extend in a direction inclined relative to the first direction DR1. As an example, Fig. 9 The emission control line E is shown to be bent in a direction inclined relative to the first direction DR1. Fig. 9 Describe the first bridge line BR1 that connects the first initialization voltage supply line VI1 to the first initialization voltage line V1, the second bridge line BR2 that connects the first part Ea of the emission control line E and the second part Eb of the emission control line E to each other, and the third bridge line BR3 that connects the first part Sa of the scan line S and the second part Sb of the scan line S to each other.

[0198] The emission control line E is disposed on the substrate SUB in the pixel area PXA. A buffer layer may be disposed between the emission control line E and the substrate SUB. Each emission control line E includes a first portion Ea disposed on the substrate SUB in the peripheral area PPA and extending into the pixel area PXA, a second bridge line BR2 disposed on the second insulating layer IL2, and a second portion Eb disposed on the substrate SUB.

[0199] The second bridge line BR2 is used to connect the first portion Ea of the emission control line E with the second portion Eb of the emission control line E. The second bridge line BR2 is connected to the first portion Ea of the emission control line E through a contact hole CH13a passing through the gate insulating layer GI and the first insulating layer IL1 and the second insulating layer IL2, and is connected to the second portion Eb of the emission control line E through a contact hole CH13b passing through the gate insulating layer GI and the first insulating layer IL1 and the second insulating layer IL2, as shown in Fig.10 The contact hole CH13a and the contact hole CH13b are referred to as thirteenth contact holes.

[0200] The scan line S extends from the pixel area PXA along the first direction DR1 and also extends substantially along the first direction DR1 in the peripheral area PPA. However, the scan line S may be bent in a direction inclined with respect to the first direction DR1 depending on a position at a corner and then extend. Fig. 9 It is shown that the scan line S is bent in a direction inclined with respect to the first direction DR1.

[0201] The scan line S is disposed on the substrate SUB in the pixel area PXA. A buffer layer may be disposed between the scan line S and the substrate SUB. The scan line S may be connected in substantially the same manner as the emission control line E. Specifically, each scan line S includes a first portion Sa disposed on the substrate SUB in the peripheral area PPA, a third bridge line BR3 disposed on the second insulating layer IL2, and a second portion Sb disposed on the gate insulating layer GI.

[0202] The third bridge line BR3 is used to connect the first portion Sa of the scan line S with the second portion Sb of the scan line S. The third bridge line BR3 is connected to the first portion Sa of the scan line S through a contact hole CH14a passing through the gate insulating layer GI and the first insulating layer IL1 and the second insulating layer IL2, and is connected to the second portion Sb of the scan line S through a contact hole CH14b passing through the first insulating layer IL1 and the second insulating layer IL2, as shown in FIG. Fig.11 The contact hole CH14a and the contact hole CH14b are referred to as fourteenth contact holes.

[0203] The first initialization voltage line V1 extends from the pixel area PXA along the first direction DR1, and also extends substantially along the first direction DR1 in the peripheral area PPA. When viewed from the top, the first initialization voltage line V1 is separated from the scan line S by a predetermined distance, and at least a portion of the first initialization voltage line V1 extends parallel to the scan line S. The first initialization voltage line V1 may be bent in a direction inclined relative to the first direction DR1 depending on the position at the corner, and may extend in a direction inclined relative to the first direction DR1. As an example, Fig. 9 It is shown that the first initialization voltage line V1 is bent in a direction inclined with respect to the first direction DR1.

[0204] The first initialization voltage line V1 is disposed on the gate insulating layer GI in the pixel area PXA. The first initialization voltage line V1 may include a first portion V1a disposed on the gate insulating layer GI in the peripheral area PPA, a first bridge line BR1 disposed on the second insulating layer IL2, and a first initialization voltage supply line VI1 disposed on the first insulating layer IL1. The first initialization voltage supply line VI1 may include an output terminal protruding from the first initialization voltage supply line VI1 in a direction inclined relative to the first direction DR1.

[0205] The first bridge line BR1 is used to connect the first portion V1a of the first initialization voltage line V1 to the output terminal of the first initialization voltage supply line VI1. The first bridge line BR1 is connected to the first portion V1a of the first initialization voltage line V1 through a contact hole CH15a passing through the first insulating layer IL1 and the second insulating layer IL2, and is connected to the output terminal of the first initialization voltage supply line VI1 through a contact hole CH15b passing through the second insulating layer IL2, as shown in Fig.12 The contact hole CH15a and the contact hole CH15b are referred to as fifteenth contact holes.

[0206] The second initialization voltage line V2 is disposed on the gate insulating layer GI in the pixel area PXA. The second initialization voltage line V2 may include a first portion V2a disposed on the gate insulating layer GI in the peripheral area PPA, and a second initialization voltage supply line VI2 disposed on the first insulating layer IL1. The second initialization voltage supply line VI2 may include an output terminal protruding from the second initialization voltage supply line VI2 in a direction inclined relative to the first direction DR1.

[0207] The second initialization voltage line V2 is connected to the second initialization voltage supply line VI2 through the sixteenth contact hole CH16 passing through the first insulating layer IL1, as shown in FIG. Fig.13 as shown in .

[0208] The data line D extends from the pixel area PXA along the second direction DR2 and also generally extends into the peripheral area PPA along the second direction DR2. However, the data line D may be bent in a direction inclined with respect to the second direction DR2 depending on the position of the corner and then extend. Fig. 9 It is shown that the data line D is bent in a direction inclined with respect to the second direction DR2 and then extends toward the right side.

[0209] The data line D is disposed on the second insulating layer IL2 in the pixel area PXA. The data line D includes a first data line Da (e.g., a data line portion Da) disposed on the gate insulating layer GI in the peripheral area PPA, and a second data line Db (e.g., a data line portion Db) disposed on the substrate SUB. A buffer layer may be disposed between the second data line Db and the substrate SUB. Both the first data line Da and the second data line Db may be provided in plurality (e.g., a plurality of first data lines Da and a plurality of second data lines Db).

[0210] A portion of the data line D extending from the pixel area PXA is connected to the first data line Da through a seventeenth contact hole CH17 passing through the first insulating layer IL1 and the second insulating layer IL2, as shown in FIG. Fig.14 More than one contact hole may be provided or formed. Another portion of the data line D extending from the pixel area PXA is connected to the second data line Db through an eighteenth contact hole CH18 passing through the gate insulating layer GI and the first and second insulating layers IL1 and IL2, as shown in Fig.15 More than one contact hole may be provided or formed.

[0211] When viewed from the top, the first data lines Da and the second data lines Db may be spaced apart from each other and may be alternately arranged. At least a portion of the first data lines Da and the second data lines Db extend in directions parallel to each other.

[0212] Hereinafter, the structure of the lines in the peripheral area PPA will be described in stacking order.

[0213] The gate insulating layer GI is disposed on the substrate SUB.

[0214] A buffer layer (not shown) may be disposed between the substrate SUB and the gate insulating layer GI.

[0215] On the substrate SUB, a first portion Sa of the scan line S extending from the pixel area PXA, a first portion Ea of the emission control line E, a second portion Eb of the emission control line E, and a second data line Db are provided. The first portion Sa of the scan line S, the first portion Ea of the emission control line E, the second portion Eb of the emission control line E, and the second data line Db may be provided by the same material as the scan line S in the pixel area PXA via the same process. Therefore, the first portion Sa of the scan line S, the first portion Ea of the emission control line E, the second portion Eb of the emission control line E, and the second data line Db may be located in the same layer as the scan line S in the pixel area PXA. With respect to "made of the same material" or "located in the same layer", the elements may be portions of the same layer or a common layer on the substrate SUB.

[0216] A gate insulating layer GI is disposed on the substrate SUB including the first portion Sa of the scan line S, the first portion Ea of the emission control line E, the second portion Eb of the emission control line E, and the second data line Db.

[0217] The first data line Da, the second portion Sb of the scan line S extending from the scan stage SST, the first initialization voltage line V1 and the second initialization voltage line V2 are disposed on the gate insulating layer GI.

[0218] The first insulating layer IL1 is disposed on the gate insulating layer GI to cover the first data line Da, the second portion Sb of the scan line S extending from the scan stage SST, the first initialization voltage line V1, and the second initialization voltage line V2.

[0219] The first initialization voltage supply line VI1 and the second initialization voltage supply line VI2 are not disposed in the same layer as the plurality of first data lines Da and the plurality of second data lines Db, but are disposed so that they overlap the plurality of first data lines Da and the plurality of second data lines Db along the third direction DR3, so that the dead space can be reduced near the corner of the pixel area PXA. Fig. 9 For example, along the rounded corner of the boundary between the pixel area PXA and the peripheral area PPA, the first initialization voltage supply line VI1 and the second initialization voltage supply line VI2 both overlap the first data line Da and the second data line Db along the thickness direction (for example, the third direction DR3). Along the rounded corner, a portion of the length of the first initialization voltage supply line VI1 and the second initialization voltage supply line VI2 corresponds to and overlaps the length of the first data line Da and the second data line Db.

[0220] Specifically, if the first initialization voltage supply line VI1 and the second initialization voltage supply line VI2, the plurality of first data lines Da, and the plurality of second data lines Db are disposed in the same layer within the peripheral area PPA, when viewed from the top, the first data lines Da and the second data lines Db, the first initialization voltage supply line VI1 and the second initialization voltage supply line VI2, the scan driver SDV, and the emission driver EDV are sequentially disposed from the corner of the pixel area PXA and occupy a relatively large plane area together. Therefore, the ineffective space in the display device 1 may increase.

[0221] In contrast, in one or more exemplary embodiments, when the first initialization voltage supply line VI1 and the second initialization voltage supply line VI2 overlap with the plurality of first data lines Da and the plurality of second data lines Db to share a common plane area, when viewed from the top, the first initialization voltage supply line VI1, the second initialization voltage supply line VI2, the scan driver SDV, and the emission driver EDV are sequentially arranged from the corner of the pixel area PXA to define a total plane area except for the plane area of ​​the first data line Da and the second data line Db. Therefore, the dead space in the display device 1 can be reduced.

[0222] The second insulating layer IL2 is disposed on the first insulating layer IL1 to cover the first initialization voltage supply line VI1 and the second initialization voltage supply line VI2.

[0223] The data line D extending from the pixel area PXA and the first, second and third bridge lines BR1, BR2 and BR3 are disposed on the second insulating layer IL2. The third insulating layer IL3 is disposed on the second insulating layer IL2 to cover the data line D extending from the pixel area PXA and the first, second and third bridge lines BR1, BR2 and BR3.

[0224] The passivation layer PSV may be disposed on the third insulating layer IL3, and the sealing member SLM may be disposed on the passivation layer PSV. According to an exemplary embodiment of the present disclosure, various layers may be further disposed between the third insulating layer IL3 and the passivation layer PSV and between the passivation layer PSV and the sealing member SLM. The sealing member SLM may be omitted.

[0225] Hereinafter, other exemplary embodiments of the present disclosure will be described. In the following description, the same or similar elements will be indicated by the same or similar reference numerals, and redundant descriptions will be omitted or briefly described. The description will focus on the differences from the above exemplary embodiments.

[0226] Fig.16 It shows Figure 1 FIG. 1 is an enlarged plan view of another exemplary embodiment of a portion P1 of FIG. 1 , wherein the portion P1 is Fig.16It is marked as part P1_1, which includes the connection relationship between the pixel PXL, the line and the driver. Fig.17 It shows Fig.16 An enlarged plan view of portion P2_1.

[0227] exist Fig.16 and Fig.17 The exemplary embodiment shown in Figure 3 and Fig. 9 The exemplary embodiment shown in FIG. 1 differs in that there is only one initialization voltage supply line instead of two.

[0228] Specifically, according to Fig.16 and Fig.17 In the exemplary embodiment shown in FIG. 1 , the first portion V1a disposed on the gate insulating layer GI in the peripheral area PPA, the first bridge line BR1 disposed on the second insulating layer IL2 , and the first initialization voltage supply line VI1 disposed on the first insulating layer IL1 are removed.

[0229] Although not shown in the drawings, Fig.16 and Fig.17 The exemplary embodiment shown in Figure 5 and Figure 6 Unlike the exemplary embodiment shown in FIG. 1 , the fourth source electrode SE4 of the fourth transistor T4 and the seventh drain electrode DE7 of the seventh transistor T7 may be electrically connected and may be connected to a single initialization voltage supply line VI1_1, while in FIG. Figure 5 and Figure 6 In the exemplary embodiment shown in FIG. 1 , in the pixel PXL, the fourth source electrode SE4 of the fourth transistor T4 is connected to the first initialization voltage supply line VI1 , and the seventh drain electrode DE7 of the seventh transistor T7 is connected to the second initialization voltage supply line VI2 .

[0230] refer to Fig.13 , Fig.16 and Fig.17 The first initialization voltage line V1_1 extends from the pixel area PXA along the first direction DR1 and also extends substantially along the first direction DR1 in the peripheral area PPA. When viewed from the top, the first initialization voltage line V1_1 is separated from the scan line S by a predetermined distance, and at least a portion of the first initialization voltage line V1_1 extends parallel to the scan line S.

[0231] The first initialization voltage line V1_1 is disposed on the gate insulating layer GI in the pixel area PXA. The first initialization voltage line V1_1 may include a first portion V1a_1 disposed on the gate insulating layer GI in the peripheral area PPA, and a first initialization voltage supply line VI1_1 disposed on the first insulating layer IL1. The first initialization voltage supply line VI1_1 may include an output terminal protruding from the first initialization voltage supply line VI1_1 in a direction inclined relative to the first direction DR1.

[0232] Since only one initialization voltage supply line VI1_1 is connected to the pixel PXL, only one initialization voltage line V1_1 is provided or formed along the first direction DR1. Therefore, an ineffective space near the corner of the pixel area PXA may be further reduced.

[0233] When only one initialization voltage line V1_1 is provided or formed, the total plane area occupied by the plurality of lines E, S and V1_1 along the second direction DR2 is reduced compared to the structure in which two initialization voltage lines are provided or formed. Therefore, the scan driver SDV and the emission driver EDV may be substantially disposed on the upper side of the corner of the pixel area PXA.

[0234] That is, because the data line D has a fan-out structure in which the length of the data line D increases along the first direction DR1 as the distance from the lower side of the corner of the pixel area PXA increases, the invalid space can be further reduced because the scan driver SDV and the emission driver EDV are arranged on the upper side of the corner of the pixel area PXA.

Claims

1. A display device, wherein: The display device comprises: Base plate, comprising: A pixel area, including pixels; a peripheral region, adjacent to the pixel region; and a boundary, located between the pixel region and the peripheral region, the boundary including rounded corners; a data driver located in the peripheral area; a data line through which a data signal is supplied from the data driver to the pixel, the data line extending along the rounded corner between the pixel region and the peripheral region; and An initialization voltage supply line, located in the peripheral region and connected to the pixel, faces the data line in a thickness direction and extends along the data line extending along the rounded corner of the boundary between the pixel region and the peripheral region.

2. The display device according to claim 1, wherein: The peripheral area of ​​the substrate includes a terminal area and a portion connecting the terminal area to the pixel area, The terminal region is bendable relative to the rest of the peripheral region, and The bent substrate is provided along the thickness direction with the terminal region overlapping the portion of the peripheral region that connects the terminal region to the pixel region.

3. The display device according to claim 2, wherein: The data driver is located in the terminal region of the peripheral region.

4. The display device according to claim 1, wherein: The data line is provided in plural, including a plurality of data lines having a fan-out structure extending outward in a direction from the data driver to the pixel region.

5. The display device according to claim 4, wherein: The initialization voltage supply line overlaps the plurality of data lines having the fan-out structure.

6. The display device according to claim 1, wherein: The initialization voltage supply line is provided in plurality, including a first initialization voltage supply line and a second initialization voltage supply line located in the peripheral area, and The first initialization voltage supply line and the second initialization voltage supply line are arranged parallel to each other at a constant interval therebetween along the rounded corner of the boundary between the pixel area and the peripheral area.

7. The display device according to claim 1, wherein: The display device further includes a gate insulating layer, a first insulating layer, a second insulating layer and a third insulating layer in order from the substrate, The initialization voltage supply line is provided in plurality, including a first initialization voltage supply line and a second initialization voltage supply line located in the peripheral area.

8. The display device according to claim 7, wherein: The first insulating layer is located between the gate insulating layer and the first initialization voltage supply line, and between the gate insulating layer and the second initialization voltage supply line.

9. The display device according to claim 7, wherein: The display device further includes: a first initialization voltage line connected to the pixel region and extending from the pixel region to the peripheral region, and A first bridge line is located in the peripheral area, the first bridge line connecting the first initialization voltage supply line to the first initialization voltage line.

10. The display device according to claim 9, wherein: The second insulating layer is located between the first bridge line and the first initialization voltage supply line and defines a first contact hole. The first insulating layer and the second insulating layer are located between the first bridge line and the first initialization voltage line and define a second contact hole. The first bridge line is connected to the first initialization voltage supply line at the first contact hole, and The first bridge line is connected to the first initialization voltage line at the second contact hole.

11. The display device according to claim 10, wherein: The second initialization voltage supply line includes an output terminal protruding toward the pixel region.

12. The display device according to claim 11, wherein: The display device further includes: a second initialization voltage line connected to the pixel area and extending from the pixel area to the peripheral area, in, The first insulating layer is located between the output terminal of the second initialization voltage supply line and the second initialization voltage line and defines a third contact hole, and The output terminal of the second initialization voltage supply line is connected to the second initialization voltage line at the third contact hole.

13. The display device according to claim 10, wherein: The data line is provided in plurality, including a first data line and a second data line both located in the peripheral area, and In the peripheral area, The gate insulating layer is located between the first data line and the second data line, and The second data line is located between the gate insulating layer and the substrate.

14. The display device according to claim 13, wherein: In the peripheral area, along the rounded corner of the boundary between the pixel area and the peripheral area, the first data line and the second data line extend parallel to each other.

15. The display device according to claim 14, wherein: The first data line is provided in a plurality, including a plurality of first data lines, and the second data line is provided in a plurality, including a plurality of second data lines, and In the peripheral area, the plurality of first data lines and the plurality of second data lines are alternately arranged.

16. The display device according to claim 1, wherein: The display device further includes a scan driver and an emission driver located in the peripheral area.

17. The display device according to claim 16, wherein: The scan driver is located between the emission driver and the pixel area.

18. The display device according to claim 17, wherein: The initialization voltage source line is located between the scan driver and the pixel area.

19. The display device according to claim 16, wherein: The display device further includes: A first portion of the emission control line is connected to the pixel region and extends from the pixel region to the peripheral region, The second portion of the emission control line is connected to the emission driver, and A second bridge line connects the first portion of the emission control line and the second portion of the emission control line to each other.

20. The display device according to claim 16, wherein: The display device further includes: A first portion of the scan line is connected to the pixel region and extends from the pixel region to the peripheral region, A second portion of the scan lines is connected to the scan driver, and A third bridge line connects the first portion of the scan line and the second portion of the scan line to each other.

21. The display device according to claim 1, wherein: The substrate further includes a rounded corner corresponding to the rounded corner of the boundary between the pixel area and the peripheral area, and The initialization voltage supply line and the data line overlapped by the initialization voltage supply line are both located between the rounded corner of the substrate and the rounded corner of the boundary between the pixel area and the peripheral area.

Images