Display device

Abstract

A display device includes a first transistor including a first channel region, a first gate electrode overlapping the first channel region, and a first electrode connected to a node receiving a driving voltage; a second transistor electrically connected to the first electrode of the first transistor, the second transistor including a second channel region and a second gate electrode overlapping the second channel region and receiving a scan signal; a light emitting element electrically connected to a second electrode of the first transistor; a first conductive line overlapping the first gate electrode and receiving a variable voltage different from the driving voltage with the first channel region in the middle; and a second conductive line overlapping the second gate electrode and receiving the scan signal with the second channel region in the middle.

Description

TECHNICAL FIELD

[0001] Embodiments of the present inventive concept relate to a display apparatus. More particularly, embodiments of the present inventive concept relate to a display apparatus including a plurality of transistors. BACKGROUND

[0002] A display apparatus can include a plurality of pixels to display an image. Each of the pixels can include a plurality of transistors including a driving transistor and a light emitting element electrically connected to the transistors. The driving transistor included in each of the pixels can generate a driving current, and the light emitting element included in each of the pixels can emit light having a luminance corresponding to an amount of the driving current. However, a voltage-current characteristic of the driving transistor during a current period can change according to an operating state of the driving transistor during a previous period. In other words, the driving transistor included in the pixel can have hysteresis.

[0003] When the display apparatus has displayed a black image during the previous period and then displays a white image during a next period, the luminance of the display apparatus during the next period can be lower than expected due to the hysteresis of the driving transistor. This phenomenon can be referred to as step efficiency. Further, when a display area in the display apparatus is driven at different gray levels during the previous period, the display area can emit different luminances for a certain time even if the display area is driven at the same gray level during a subsequent period due to the hysteresis of the driving transistor. This phenomenon can be referred to as temporal image sticking. SUMMARY

[0004] At least one embodiment of the present inventive concept provides a display apparatus having improved step efficiency and / or reduced temporal image sticking.

[0005] A display apparatus according to an exemplary embodiment of the present inventive concept includes a first transistor including a first channel region, a first gate electrode overlapping the first channel region, and a first electrode receiving a driving voltage; a second transistor electrically connected to the first electrode of the first transistor, the second transistor including a second channel region and a second gate electrode overlapping the second channel region and receiving a scan signal; a light emitting element electrically connected to a second electrode of the first transistor; a first conductive line overlapping the first gate electrode and receiving a variable voltage different from the driving voltage; and a second conductive line overlapping the second gate electrode and receiving the scan signal. The first channel region is located between the first conductive line and the first gate electrode. The second channel region is located between the second conductive line and the second gate electrode.

[0006] In an embodiment, the variable voltage is a positive voltage greater than the driving voltage or a negative voltage less than the driving voltage.

[0007] In an embodiment, the display apparatus further includes a third transistor electrically connected to the second electrode of the first transistor, the third transistor including a third channel region and a third gate electrode overlapping the third channel region and receiving a scan signal.

[0008] In an embodiment, the second conductive line overlaps the third gate electrode, and the third channel region is positioned between the second conductive line and the third gate electrode.

[0009] In an embodiment, the display apparatus further includes a scan line receiving the scan signal, wherein each of the second gate electrode and the third gate electrode is a part of the scan line.

[0010] In an embodiment, the first conductive line includes an extension portion extending in a first direction and an overlap portion overlapping the first gate electrode.

[0011] In an embodiment, a width of the overlap portion in a second direction crossing the first direction is greater than a width of the extension portion in the second direction.

[0012] In an embodiment, the second conductive line includes an extension portion extending in a first direction and an overlap portion overlapping the second gate electrode.

[0013] In an embodiment, the overlap portion protrudes from the extension portion in a second direction crossing the first direction.

[0014] In an embodiment, the first conductive line is connected to a variable voltage supply line positioned outside the display area.

[0015] In an embodiment, the second conductive line is connected to a scan signal supply line positioned outside the display area.

[0016] In an embodiment, each of the first transistor and the second transistor is a p-channel metal-oxide-semiconductor (PMOS) transistor.

[0017] A display apparatus according to an exemplary embodiment of the inventive concept includes a substrate; a first conductive layer disposed on the substrate and receiving a variable voltage; a second conductive layer disposed on the substrate, spaced apart from the first conductive layer, and receiving a scan signal; a first transistor including a first active layer disposed on the first conductive layer and a first gate electrode disposed on the first active layer; a second transistor including a second active layer disposed on the second conductive layer and electrically connected to a first end portion of the first active layer, and a second gate electrode disposed on the second active layer and receiving the scan signal; and a light emitting element electrically connected to the first transistor. The first end portion of the first active layer receives a driving voltage different from the variable voltage.

[0018] In an embodiment, the variable voltage is a positive voltage greater than the driving voltage or a negative voltage less than the driving voltage.

[0019] In an embodiment, the display apparatus further includes a third transistor including a third active layer disposed on the second conductive layer and electrically connected to a second end portion of the first active layer, and a third gate electrode disposed on the third active layer and receiving a scan signal.

[0020] In an embodiment, the first conductive layer is connected to a variable voltage supply line located outside the display area.

[0021] In an embodiment, the variable voltage supply line is disposed on the first conductive layer, an insulating layer is located between the variable voltage supply line and the first conductive layer outside the display area, and the first conductive layer contacts the variable voltage supply line through a contact hole formed in the insulating layer.

[0022] In an embodiment, the second conductive layer is connected to a scan signal supply line located outside the display area.

[0023] In an embodiment, the scan signal supply line is disposed on the second conductive layer, an insulating layer is located between the scan signal supply line and the second conductive layer outside the display area, and the second conductive layer contacts the scan signal supply line through a contact hole formed in the insulating layer.

[0024] In an embodiment, each of the first transistor and the second transistor is a p-channel metal-oxide-semiconductor (PMOS) transistor.

[0025] According to an exemplary embodiment of the inventive concept, a display apparatus includes a light emitting element, a driving transistor, and a driving circuit. The driving transistor is to control a current passing through the light emitting element. The driving transistor includes a first terminal connected to a node receiving a driving voltage and a bottom gate terminal connected to a node receiving a variable voltage. The driving circuit is configured to provide the variable voltage, wherein the variable voltage is a positive voltage greater than the driving voltage or a negative voltage less than the driving voltage.

[0026] In an exemplary embodiment, the driving circuit is configured to change a value of the variable voltage to the negative voltage to increase a step efficiency of the display apparatus or to the positive voltage to decrease a number of afterimages perceivable on the display apparatus.

[0027] A display apparatus according to at least one embodiment of the inventive concept can include a first conductive line overlapping the first gate electrode and receiving a variable voltage while a first channel region of the first transistor is in the middle, and a second conductive line overlapping the second gate electrode and receiving a scan signal while a second channel region of the second transistor is in the middle, so that a step efficiency and / or a transient afterimage of the display apparatus can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] The inventive concept will become apparent from the detailed description of exemplary embodiments with reference to the drawings, in which:

[0029] Figure 1 is a plan view showing a display device according to an exemplary embodiment of the present inventive concept;

[0030] Figure 2 is a block diagram showing a display device in Figure 1 ;

[0031] Figure 3 is a circuit diagram showing a pixel of the display device in Figure 2 ;

[0032] Figure 4 is a plan view showing a display area of the display device in Figure 1 ;

[0033] Figure 5 is a plan view showing a first conductive line and a second conductive line in Figure 4 ;

[0034] Figure 6 is a cross-sectional view taken along line I-I' in Figure 4 ;

[0035] Figure 7 is a plan view showing a non-display area of the display device in Figure 1 ;

[0036] Figure 8 is a cross-sectional view taken along lines II-II' and III-III' in Figure 7 ;

[0037] Figure 9 is a graph showing exemplary step efficiency according to a variable voltage received by the first conductive line; and

[0038] Figure 10 is a graph showing a transient image sticking of display devices according to an embodiment example and a comparative example. DETAILED DESCRIPTION

[0039] Hereinafter, a display device according to exemplary embodiments of the present inventive concept will be explained in detail with reference to the accompanying drawings.

[0040] Figure 1 is a plan view showing a display device according to an exemplary embodiment of the present inventive concept;

[0041] Reference is made to Figure 1The display device includes a display area DA and a non-display area NDA. The display area DA can display an image. The display area DA can have a substantially quadrangular shape, but the shape of the display area DA is not limited thereto. The non-display area NDA can be disposed on a periphery of the display area DA. For example, the non-display area NDA can surround the display area DA. The non-display area NDA does not display an image.

[0042] Figure 2 is a block diagram of a display device in Figure 1 according to an exemplary embodiment of the inventive concept.

[0043] Referring to Figure 2 , the display device includes a display unit 10 (e.g., a display panel), a driving circuit unit 20 (e.g., a driving circuit or a voltage generator), a power supply 30, a data driver 40 (e.g., a source driver), and a timing controller 50 (e.g., a timing control circuit).

[0044] The display unit 10 can be disposed in the display area DA. The display unit 10 can include a plurality of pixels PX. The pixels PX can be arranged in a substantially matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. Each of the pixels PX can be connected to a scan line SL, an emission control line ECL, an initialization voltage line IVL, a driving voltage line DVL, a data line DL, a first conductive line CL1, and a second conductive line CL2. Each of the pixels PX can emit light in response to a signal applied through the scan line SL, the emission control line ECL, the initialization voltage line IVL, the driving voltage line DVL, the data line DL, the first conductive line CL1, and the second conductive line CL2.

[0045] The driving circuit unit 20 and the power supply 30 can be disposed in the non-display area NDA. The driving circuit unit 20 can include a scan driver that generates a scan signal and an emission control driver that generates an emission control signal. The driving circuit unit 20 can transmit the scan signal to the pixels PX through the scan line SL and can transmit the emission control signal to the pixels PX through the emission control line ECL. In an embodiment, the driving circuit unit 20 can be disposed at one side of the display unit 10, but the disclosure is not limited thereto. In another embodiment, the scan driver of the driving circuit unit 20 can be disposed at one side of the display unit 10, and the emission control driver of the driving circuit unit 20 can be disposed at the other side of the display unit 10.

[0046] The power supply 30 can generate an initialization voltage, a driving voltage, and a variable voltage. The power supply 30 can transmit the initialization voltage to the pixel PX through an initialization voltage line IVL, can transmit the driving voltage to the pixel PX through a driving voltage line DVL, and can transmit the variable voltage to the pixel PX through a first conductive line CL1. In an embodiment, the power supply 30 can be disposed at one side of the display unit 10 in which the driving circuit unit 20 is disposed, but the present disclosure is not limited thereto. In another embodiment, the power supply 30 can be disposed at the other side of the display unit 10 in which the driving circuit unit 20 is not disposed, or can be disposed at the opposite side of the display unit 10.

[0047] The data driver 40 can generate a data voltage. The data driver 40 can transmit the data voltage to the pixel PX through a data line DL. In an embodiment, the data driver 40 is disposed on a printed circuit board (PCB) connected to the non-display area NDA. However, the present disclosure is not limited thereto. For example, in another embodiment, the data driver 40 can be disposed in the non-display area NDA.

[0048] The timing controller 50 can convert image data IMG supplied from an external device into input image data IDATA, and generate a first control signal CTL1, a second control signal CTL2, and a third control signal CTL3 that control driving of the input image data IDATA. The timing controller 50 can convert the image data IMG supplied from the external device into the input image data IDATA by applying an algorithm configured to correct image quality, such as dynamic capacitance compensation (DCC), to the image data IMG. The timing controller 50 can provide the first control signal CTL1 to the driving circuit unit 20, can provide the second control signal CTL2 to the power supply 30, and can provide the input image data IDATA and the third control signal CTL3 to the data driver 40.

[0049] Figure 3 is a circuit diagram illustrating a pixel PX of a display apparatus in Figure 2 . Figure 3 One of the pixels PX included in each of a plurality of pixel rows can be illustrated.

[0050] Referring to Figure 3 , the pixel PX includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and a light emitting element EE. However, the present embodiment is not limited thereto, and the number of transistors and / or the number of capacitors included in the pixel PX can be variously changed. In an embodiment, the pixel PX can include an organic light emitting diode as the light emitting element EE.

[0051] The first transistor T1 includes a first gate electrode G1, a first source electrode S1, a first drain electrode D1, and a first bottom gate electrode BG1. In an exemplary embodiment, the first transistor T1 is a dual-gate transistor including the first gate electrode G1 and the first bottom gate electrode BG1 serving as gate electrodes. The first gate electrode G1 is connected to the first node N1. The first source electrode S1 is connected to the second node N2, and the first drain electrode D1 is connected to the third node N3. The first bottom gate electrode BG1 receives a variable voltage VV. The first transistor T1 can be a drive transistor for controlling a current passing through the light emitting element EE. In an exemplary embodiment, the power supply 30 supplies the variable voltage VV. In an exemplary embodiment, the power supply 30 is configured to change the variable voltage VV to one of various types of positive voltages and one of various types of negative voltages by taking into account a desired step efficiency and / or a desired number of residual images. In an exemplary embodiment, the timing controller 50 analyzes the image data IMG to determine a result indicating whether a step efficiency needs to be improved and / or a result indicating whether a residual image needs to be improved, the timing controller 50 determines the variable voltage VV according to the results, and transmits a control signal to the power supply 30 to inform the power supply 30 of the determined variable voltage VV to be applied to the first bottom gate electrode BG1.

[0052] The second transistor T2 includes a second gate electrode G2, a second source electrode S2, a second drain electrode D2, and a second bottom gate electrode BG2. In an exemplary embodiment, the second transistor T2 is a dual-gate transistor including the second gate electrode G2 and the second bottom gate electrode BG2 serving as gate electrodes. The second gate electrode G2 receives a first scan signal GW. The first scan signal GW can be a scan signal (or gate signal) for a pixel row including the pixel PX. The second source electrode S2 receives a data voltage DATA, and the second drain electrode D2 is connected to the second node N2. The second bottom gate electrode BG2 receives the first scan signal GW. The second transistor T2 can be a switching transistor for turning on or off the first transistor T1.

[0053] The third transistor T3 includes a third gate electrode G3, a third source electrode S3, a third drain electrode D3, and a third bottom gate electrode BG3. In an exemplary embodiment, the third transistor T3 is a dual-gate transistor including the third gate electrode G3 and the third bottom gate electrode BG3 serving as gate electrodes. The third gate electrode G3 receives the first scan signal GW. The third source electrode S3 is connected to the third node N3, and the third drain electrode D3 is connected to the first node N1. The third bottom gate electrode BG3 receives the first scan signal GW. The third transistor T3 can be a compensation transistor connected between the first drain electrode D1 and the first gate electrode G1 of the first transistor T1 which is a drive transistor.

[0054] The fourth transistor T4 includes a fourth gate electrode G4, a fourth source electrode S4, and a fourth drain electrode D4. The fourth gate electrode G4 receives a second scan signal GI. In an embodiment, the second scan signal GI is a scan signal for a preceding pixel row of pixel rows including the pixel PX. In an exemplary embodiment, the second scan signal GI is the first scan signal GW applied to the pixels in the preceding pixel row. The fourth source electrode S4 receives the initialization voltage VINT, and the fourth drain electrode D4 is connected to the first node N1. The fourth transistor T4 can be an initialization transistor for initializing the first gate electrode Gl of the first transistor Tl that is a drive transistor.

[0055] The fifth transistor T5 includes a fifth gate electrode G5, a fifth source electrode S5, and a fifth drain electrode D5. The fifth gate electrode G5 receives an emission control signal EM. The fifth source electrode S5 can receive a drive voltage VDD, and the fifth drain electrode D5 is connected to the second node N2. In an exemplary embodiment, the drive voltage VDD is a constant voltage.

[0056] The sixth transistor T6 includes a sixth gate electrode G6, a sixth source electrode S6, and a sixth drain electrode D6. The sixth gate electrode G6 receives the emission control signal EM. The sixth source electrode S6 is connected to the third node N3, and the sixth drain electrode D6 is connected to the anode of the light emitting element EE.

[0057] Each of the fifth transistor T5 and the sixth transistor T6 can be an emission control transistor for transmitting the drive voltage VDD to the light emitting element EE by the first transistor Tl that is a drive transistor.

[0058] The seventh transistor T7 includes a seventh gate electrode G7, a seventh source electrode S7, and a seventh drain electrode D7. The seventh gate electrode G7 receives a third scan signal GB. In an embodiment, the third scan signal GB is a scan signal for a succeeding pixel row in the pixel rows including the pixel PX. In an exemplary embodiment, the third scan signal GB is the first scan signal GW applied to the pixels in the succeeding pixel row. The seventh source electrode S7 receives the initialization voltage VINT, and the seventh drain electrode D7 is connected to the anode of the light emitting element EE. The seventh transistor T7 can be an initialization transistor for initializing the anode of the light emitting element EE.

[0059] The first to seventh transistors Tl, T2, T3, T4, T5, T6, and T7 can be transistors of the same type. In an embodiment, each of the first to seventh transistors Tl, T2, T3, T4, T5, T6, and T7 is a p-channel metal oxide semiconductor (PMOS) transistor. However, the present disclosure is not limited thereto. For example, in another embodiment, each of the first to seventh transistors Tl, T2, T3, T4, T5, T6, and T7 is an n-channel metal oxide semiconductor (NMOS) transistor.

[0060] The storage capacitor Cst includes a first electrode connected to the first node N1 and a second electrode receiving the driving voltage VDD.

[0061] The light emitting element EE can include an anode and a cathode. The anode of the light emitting element EE is connected to the sixth drain electrode D6 of the sixth transistor T6 and the seventh drain electrode D7 of the seventh transistor T7, and the cathode of the light emitting element EE receives the common voltage VSS. In an exemplary embodiment, the common voltage VSS is lower than the driving voltage VDD.

[0062] Figure 4 is a plan view showing a display area DA of a display device in Figure 1 , for example, Figure 4 may show Figure 2 a pixel PX in Figure 5 . Figure 4 is a plan view showing a first conductive line CL1 and a second conductive line CL2 in Figure 6 . Figure 4 is a cross-sectional view taken along a line I-I' in .

[0063] Referring to Figure 4 , Figure 5 and Figure 6 , the display device includes a substrate 100, a first conductive line CL1, a second conductive line CL2, an active pattern 110, a first scan line 121, a second scan line 122, an emission control line 123, an initialization voltage line 131, first to seventh transistors T1, T2, T3, T4, T5, T6 and T7, a storage capacitor Cst, a data line 141, a driving voltage line 142, a first connection pattern 143, a second connection pattern 144, a third connection pattern 145, and a light emitting element EE, which are disposed in a display area DA. Figure 2 The scan lines SL shown in

[0064] The substrate 100 can be an insulating substrate including glass, a polymer, or stainless steel. In an embodiment, the substrate 100 can include a first plastic layer, a first barrier layer, a second plastic layer, and a second barrier layer, which are sequentially stacked. For example, each of the first plastic layer and the second plastic layer can include a plastic such as polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyarylate (PAR), polycarbonate (PC), polyetherimide (PEI), or polyethersulfone (PS). Each of the first barrier layer and the second barrier layer can include a silicon compound such as amorphous silicon (a-Si), silicon oxide (SiO x ), or silicon nitride (SiN x ).

[0065] The first conductive line CL1 and the second conductive line CL2 are disposed on the substrate 100. The first conductive line CL1 and the second conductive line CL2 can be spaced apart from each other. The first conductive line CL1 and the second conductive line CL2 can include a metal such as molybdenum (Mo).

[0066] The first conductive line CL1 receives a variable voltage VV. The variable voltage VV can selectively have a positive voltage or a negative voltage. For example, when a first improvement (e.g., reduced transient image sticking) is desired, the first conductive line CL1 can receive a positive voltage, while when a second improvement (e.g., increased step efficiency) is desired, the first conductive line CL1 can receive a negative voltage. In an exemplary embodiment, the positive voltage is higher than a driving voltage VDD. The first conductive line CL1 includes a first extension portion EP1 extending in a first direction DR1 and a first overlap portion OP1 overlapping the first gate electrode G1 of the first transistor T1. In an exemplary embodiment of the inventive concept, a width of the first overlap portion OP1 in a second direction DR2 is greater than a width of the first extension portion EP1 in the second direction DR2.

[0067] The second conductive line CL2 receives a scan signal (e.g., a gate signal). The second conductive line CL2 includes a second extension portion EP2 extending in the first direction DR1 and a second overlap portion OP2 overlapping the second gate electrode G2 of the second transistor T2 and the third gate electrode G3 of the third transistor T3. For example, the second overlap portion OP2 can include a first portion overlapping the second gate electrode G2 and a second portion overlapping the third gate electrode G3. The second overlap portion OP2 can protrude from the second extension portion EP2 in the second direction DR2. Hereinafter, in the disclosure, the first conductive line CL1 is described to have the same meaning as the first conductive layer CL1, and the second conductive line CL2 is described to have the same meaning as the second conductive layer CL2.

[0068] In an embodiment, a first insulating layer IL1 is disposed on the first conductive layer CL1 and the second conductive layer CL2. The first insulating layer IL1 can include an inorganic insulating material such as silicon nitride (SiN x ) or silicon oxide (SiO x ).

[0069] The active pattern 110 is provided on the first insulating layer IL1. The active pattern 110 can be formed of polysilicon or an oxide semiconductor. The oxide semiconductor can include an oxide based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In), and a composite oxide thereof, such as zinc oxide (ZnO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), zinc tin oxide (ZnSnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium zirconium oxide (InZrO), indium zirconium zinc oxide (InZrZnO), indium zirconium tin oxide (InZrSnO), indium zirconium gallium oxide (InZrGaO), indium aluminum oxide (InAlO), indium zinc aluminum oxide (InZnAlO), indium tin aluminum oxide (InSnAlO), indium aluminum gallium oxide (InAlGaO), indium tantalum oxide (InTaO), indium tantalum zinc oxide (InTaZnO), indium tantalum tin oxide (InTaSnO), indium tantalum gallium oxide (InTaGaO), indium germanium oxide (InGeO), indium germanium zinc oxide (InGeZnO), indium germanium tin oxide (InGeSnO), indium germanium gallium oxide (InGeGaO), titanium indium zinc oxide (TiInZnO), and hafnium indium zinc oxide (HfInZnO).

[0070] The second insulating layer IL2 is provided on the active pattern 110. The second insulating layer IL2 can include an inorganic insulating material such as silicon nitride (SiN x ) or silicon oxide (SiO x ).

[0071] In an exemplary embodiment, the first scan line 121, the second scan line 122, and the emission control line 123 are provided on the second insulating layer IL2. The first scan line 121, the second scan line 122, and the emission control line 123 can include a metal such as molybdenum (Mo). The first scan line 121 can extend in the first direction DR1 and receive a scan signal. The second scan line 122 can extend in the first direction DR1. In an exemplary embodiment, the second scan line 122 is spaced apart from the first scan line 121 and receives a preceding scan signal of a preceding pixel row. The emission control line 123 can extend in the first direction DR1. In an exemplary embodiment, the emission control line 123 is spaced apart from the second scan line 122 and receives an emission control signal EM.

[0072] In an exemplary embodiment, a third insulating layer IL3 is provided on the first scan line 121, the second scan line 122, and the emission control line 123. The third insulating layer IL3 can include an inorganic insulating material such as silicon nitride (SiN x ) or silicon oxide (SiOx ) of an inorganic insulating material.

[0073] In an example embodiment, the initialization voltage line 131 is disposed on the third insulating layer IL3. The initialization voltage line 131 can include a metal such as molybdenum (Mo). The initialization voltage line 131 can extend in the first direction DR1.

[0074] The first transistor T1 includes the first active layer A1, the first gate electrode G1, and the first bottom gate electrode BG1. In an example embodiment, the first bottom gate electrode BG1 is wider than the first gate electrode G1. For example, the left side of the first bottom gate electrode BG1 can extend beyond the left side of the first gate electrode G1, and the right side of the first bottom gate electrode BG1 can extend beyond the right side of the first gate electrode G1. The first active layer A1 includes the first source electrode S1, the first drain electrode D1, and the first channel region C1 formed between the first source electrode S1 and the first drain electrode D1. The first active layer A1 is part of the active pattern 110.

[0075] The first source electrode S1 is connected to the second drain electrode D2 of the second transistor T2 and the fifth drain electrode D5 of the fifth transistor T5, and the first drain electrode D1 is connected to the third source electrode S3 of the third transistor T3 and the sixth source electrode S6 of the sixth transistor T6. The first channel region C1 can be doped with N-type impurities or P-type impurities in the channel, and each of the first source electrode S1 and the first drain electrode D1 can be doped with impurities of the opposite type to the impurities doped in the first channel region C1.

[0076] The first gate electrode G1 can be disposed on the first active layer A1. For example, the first gate electrode G1 can overlap the first active layer A1. In an embodiment, the first gate electrode G1 has an island shape. The first gate electrode G1 can be disposed on the same layer as the layers of the first scan line 121, the second scan line 122, and the emission control line 123, and can include the same material as the materials of the first scan line 121, the second scan line 122, and the emission control line 123. For example, the first gate electrode G1 can be disposed on the second insulating layer IL2, and can include a metal such as molybdenum (Mo). In an example embodiment, the first gate electrode G1 overlaps the first channel region C1. In an example embodiment, the first gate electrode G1 and the first channel region C1 are aligned with each other in a plan view. In an example embodiment, the first channel region C1 overlaps the first gate electrode G1, but does not extend beyond the left and right edges of the first gate electrode G1.

[0077] The first bottom gate electrode BG1 can be disposed between the substrate 100 and the first active layer A1. In an exemplary embodiment, the first bottom gate electrode BG1 is a part of the first conductive line CL1. Specifically, the first bottom gate electrode BG1 can be a part of the first conductive line CL1 that overlaps the first channel region C1. The first bottom gate electrode BG1 can overlap the first gate electrode G1 with the first channel region C1 in the middle.

[0078] As described above, the part of the first conductive line CL1 that receives the variable voltage VV selectively having a positive voltage or a negative voltage can form the first bottom gate electrode BG1, so that the step efficiency of the display apparatus can be improved and / or the perception of the transient image sticking on the display apparatus can be reduced or prevented. In an exemplary embodiment of the inventive concept, when the first bottom gate electrode BG1 receives the variable voltage VV having a negative voltage, the on-current of the first transistor T1 increases, thereby improving the step efficiency of the display apparatus. In an exemplary embodiment of the inventive concept, when the first bottom gate electrode BG1 receives the variable voltage VV having a positive voltage, the hysteresis of the first transistor T1 is improved, thereby reducing or preventing the perception of the transient image sticking on the display apparatus due to the hysteresis of the first transistor T1.

[0079] The second transistor T2 includes a second active layer A2, a second gate electrode G2, and a second bottom gate electrode BG2. The second active layer A2 can include a second source electrode S2, a second drain electrode D2, and a second channel region C2 formed between the second source electrode S2 and the second drain electrode D2. The second active layer A2 is a part of the active pattern 110.

[0080] The second drain electrode D2 is connected to the first source electrode S1 of the first transistor T1 and the fifth drain electrode D5 of the fifth transistor T5. The second channel region C2 can be doped with N-type impurities or P-type impurities in the channel, and each of the second source electrode S2 and the second drain electrode D2 can be doped with impurities of an opposite type to the impurities doped in the second channel region C2.

[0081] The second gate electrode G2 can be disposed on the second active layer A2. For example, the second gate electrode G2 can overlap the second active layer A2. In an exemplary embodiment, the second gate electrode G2 is a part of the first scan line 121. The second gate electrode G2 can overlap the second channel region C2.

[0082] The second bottom gate electrode BG2 can be disposed between the substrate 100 and the second active layer A2. In an exemplary embodiment, the second bottom gate electrode BG2 is a part of the second conductive line CL2. Specifically, the second bottom gate electrode BG2 can be a part of the second conductive line CL2 that overlaps the second channel region C2. The second bottom gate electrode BG2 can overlap the second gate electrode G2 with the second channel region C2 in the middle.

[0083] The third transistor T3 includes a third active layer A3, a third gate electrode G3, and a third bottom gate electrode BG3. The third active layer A3 can include a third source electrode S3, a third drain electrode D3, and a third channel region C3 formed between the third source electrode S3 and the third drain electrode D3. In an exemplary embodiment, the third active layer A3 is part of the active pattern 110.

[0084] The third source electrode S3 is connected to the first drain electrode D1 of the first transistor T1 and the sixth source electrode S6 of the sixth transistor T6, and the third drain electrode D3 is connected to the fourth drain electrode D4 of the fourth transistor T4. The third channel region C3 can be doped with N-type impurities or P-type impurities, and each of the third source electrode S3 and the third drain electrode D3 can be doped with impurities of an opposite type to the impurities with which the third channel region C3 is doped.

[0085] The third gate electrode G3 can be disposed on the third active layer A3. For example, the third gate electrode G3 can overlap the third active layer A3. In an exemplary embodiment, the third gate electrode G3 is part of the first scan line 121. The third gate electrode G3 can overlap the third channel region C3.

[0086] The third bottom gate electrode BG3 can be disposed between the substrate 100 and the third active layer A3. In an exemplary embodiment, the third bottom gate electrode BG3 is part of the second conductive line CL2. Specifically, the third bottom gate electrode BG3 can be a portion of the second conductive line CL2 that overlaps the third channel region C3. The third bottom gate electrode BG3 can overlap the third gate electrode G3 with the third channel region C3 in the middle.

[0087] As described above, the portions of the second conductive line CL2 that receive the scan signal can form the second bottom gate electrode BG2 and the third bottom gate electrode BG3, respectively, so that the step efficiency of the display apparatus can be improved. In an embodiment, when the second gate electrode G2 of the second transistor T2 and the second bottom gate electrode BG2 and the third gate electrode G3 of the third transistor T3 and the third bottom gate electrode BG3 receive the scan signal having a negative voltage, the on-current of the second transistor T2 and the on-current of the third transistor T3 increase, thereby improving the step efficiency of the display apparatus.

[0088] The fourth transistor T4 can include a fourth active layer and a fourth gate electrode G4. The fourth active layer can include a fourth source electrode S4, a fourth drain electrode D4, and a fourth channel region C4 formed between the fourth source electrode S4 and the fourth drain electrode D4. In an exemplary embodiment, the fourth active layer is part of the active pattern 110.

[0089] The fourth source electrode S4 is connected to the seventh source electrode S7 of the seventh transistor T7, and the fourth drain electrode D4 is connected to the third drain electrode D3 of the third transistor T3. The fourth channel region C4 can be channel-doped with N-type impurities or P-type impurities, and each of the fourth source electrode S4 and the fourth drain electrode D4 can be doped with impurities of an opposite type from the impurities with which the fourth channel region C4 is doped.

[0090] The fourth gate electrode G4 can be disposed on the fourth active layer. In an exemplary embodiment, the fourth gate electrode G4 is part of the second scan line 122. The fourth gate electrode G4 can overlap the fourth channel region C4.

[0091] The fifth transistor T5 can include a fifth active layer and a fifth gate electrode G5. The fifth active layer can include a fifth source electrode S5, a fifth drain electrode D5, and a fifth channel region C5 formed between the fifth source electrode S5 and the fifth drain electrode D5. In an exemplary embodiment, the fifth active layer is part of the active pattern 110.

[0092] The fifth drain electrode D5 is connected to the first source electrode S1 of the first transistor T1 and the second drain electrode D2 of the second transistor T2. The fifth channel region C5 can be channel-doped with N-type impurities or P-type impurities, and each of the fifth source electrode S5 and the fifth drain electrode D5 can be doped with impurities of an opposite type from the impurities with which the fifth channel region C5 is doped.

[0093] The fifth gate electrode G5 can be disposed on the fifth active layer. In an exemplary embodiment, the fifth gate electrode G5 is part of the emission control line 123. The fifth gate electrode G5 can overlap the fifth channel region C5.

[0094] The sixth transistor T6 can include a sixth active layer and a sixth gate electrode G6. The sixth active layer can include a sixth source electrode S6, a sixth drain electrode D6, and a sixth channel region C6 formed between the sixth source electrode S6 and the sixth drain electrode D6. In an exemplary embodiment, the sixth active layer is part of the active pattern 110.

[0095] The sixth source electrode S6 is connected to the first drain electrode D1 of the first transistor T1 and the third source electrode S3 of the third transistor T3. The sixth channel region C6 can be channel-doped with N-type impurities or P-type impurities, and each of the sixth source electrode S6 and the sixth drain electrode D6 can be doped with impurities of an opposite type from the impurities with which the sixth channel region C6 is doped.

[0096] The sixth gate electrode G6 can be disposed on the sixth active layer. In an exemplary embodiment, the sixth gate electrode G6 is part of the emission control line 123. The sixth gate electrode G6 can overlap the sixth channel region C6.

[0097] The seventh transistor T7 can include a seventh active layer and a seventh gate electrode G7. The seventh active layer can include a seventh source electrode S7, a seventh drain electrode D7, and a seventh channel region C7 formed between the seventh source electrode S7 and the seventh drain electrode D7. In an exemplary embodiment, the seventh active layer is a part of the active pattern 110.

[0098] The seventh source electrode S7 is connected to the fourth source electrode S4 of the fourth transistor T4. The seventh channel region C7 can be doped with N-type impurities or P-type impurities in a channel, and each of the seventh source electrode S7 and the seventh drain electrode D7 can be doped with impurities of an opposite type to the impurities doped in the seventh channel region C7.

[0099] The seventh gate electrode G7 can be disposed on the seventh active layer. In an exemplary embodiment, the seventh gate electrode G7 is a part of the second scan line 122. The seventh gate electrode G7 can overlap the seventh channel region C7.

[0100] The storage capacitor Cst includes a first capacitor electrode 124 and a second capacitor electrode 132. The first capacitor electrode 124 can be the first gate electrode G1. In other words, the first capacitor electrode 124 can serve as an electrode of the storage capacitor Cst as well as a top gate electrode of the first transistor T1.

[0101] The second capacitor electrode 132 can be disposed on the first capacitor electrode 124. In an exemplary embodiment, the second capacitor electrode 132 has an island shape. In an exemplary embodiment, the second capacitor electrode 132 is disposed on the same layer as a layer of the initialization voltage line 131, and can include the same material as a material of the initialization voltage line 131. For example, the second capacitor electrode 132 can be disposed on the third insulating layer IL3, and can include a metal such as molybdenum (Mo). The second capacitor electrode 132 overlaps the first capacitor electrode 124. For example, in a plan view, the second capacitor electrode 132 can overlap the first capacitor electrode 124.

[0102] The fourth insulating layer IL4 can be disposed on the initialization voltage line 131 and the second capacitor electrode 132. The fourth insulating layer IL4 can include an inorganic insulating material such as silicon nitride (SiN x ) or silicon oxide (SiO x ), and / or an organic insulating material such as polyimide (PI).

[0103] The data line 141, the driving voltage line 142, the first connection pattern 143, the second connection pattern 144, and the third connection pattern 145 can be disposed on the fourth insulating layer IL4. The data line 141, the driving voltage line 142, the first connection pattern 143, the second connection pattern 144, and the third connection pattern 145 can include a metal such as aluminum (Al) or titanium (Ti).

[0104] The data line 141 can extend in the second direction DR2. The data line 141 can be connected to the second source electrode S2 of the second transistor T2 through a contact hole.

[0105] The driving voltage line 142 can extend in the second direction DR2. In an exemplary embodiment, the driving voltage line 142 is spaced apart from the data line 141. The driving voltage line 142 can be connected to the fifth source electrode S5 of the fifth transistor T5 through a contact hole, and can be connected to the second capacitor electrode 132 of the storage capacitor Cst through another contact hole.

[0106] In an exemplary embodiment, the first connection pattern 143 is spaced apart from the driving voltage line 142. The first connection pattern 143 can be connected to the first gate electrode G1 of the first transistor T1 through a contact hole, and can be connected to the third drain electrode D3 of the third transistor T3 and the fourth drain electrode D4 of the fourth transistor T4 through another contact hole.

[0107] In an exemplary embodiment, the second connection pattern 144 is spaced apart from the first connection pattern 143. The second connection pattern 144 can be connected to the initialization voltage line 131 through a contact hole, and can be connected to the fourth source electrode S4 of the fourth transistor T4 and the seventh source electrode S7 of the seventh transistor T7 through another contact hole.

[0108] In an exemplary embodiment, the third connection pattern 145 is spaced apart from the second connection pattern 144. The third connection pattern 145 can be connected to the sixth drain electrode D6 of the sixth transistor T6 through a contact hole.

[0109] The fifth insulating layer IL5 can be disposed on the data line 141, the driving voltage line 142, the first connection pattern 143, the second connection pattern 144, and the third connection pattern 145. The fifth insulating layer IL5 can include an organic insulating material such as polyimide (PI).

[0110] The light emitting element EE is disposed on the fifth insulating layer IL5. The light emitting element EE includes a first electrode 151, an emission layer 152, and a second electrode 153. The first electrode 151 can be connected to the third connection pattern 145 through a contact hole. A sixth insulating layer IL6 can be disposed on a peripheral portion of the first electrode 151. The sixth insulating layer IL6 can include an opening that exposes a central portion of the first electrode 151 to define an emission area. The sixth insulating layer IL6 can include an organic insulating material such as polyimide (PI). In an exemplary embodiment, the sixth insulating layer IL6 covers a left edge portion and a right edge portion of the first electrode 151.

[0111] The emission layer 152 is disposed between the first electrode 151 and the second electrode 153. The second electrode 153 is disposed on the emission layer 152. At least one of the first electrode 151 and the second electrode 153 can be one of a light-transmissive electrode, a light-reflective electrode, and a light-semi-transmissive electrode, and light generated from the emission layer 152 can be emitted toward at least one of the first electrode 151 and the second electrode 153.

[0112] A cap layer covering the light emitting element EE can be disposed on the light emitting element EE. An encapsulation layer or an encapsulation substrate can be disposed on the light emitting element EE, with the cap layer in between.

[0113] Figure 7 is a plan view illustrating a non-display area NDA of a display device in Figure 1 , for example. Figure 7 illustrates Figure 1 an area A. Figure 8 is a cross-sectional view taken along lines II-II' and III-III' in Figure 7 .

[0114] Referring to Figure 1 , Figure 7 and Figure 8 , the display device includes a first conductive line CL1, a second conductive line CL2, a first scan line 121, a variable voltage supply line 146, and a scan signal supply line 147 disposed in the non-display area NDA. The first conductive line CL1, the second conductive line CL2, and the first scan line 121 can extend from the display area DA to the non-display area NDA.

[0115] The variable voltage supply line 146 can extend from the power supply 30 in Figure 2 , and can be connected to the first conductive line CL1. Thus, the first conductive line CL1 can be connected to the variable voltage supply line 146 outside the display area DA. In an exemplary embodiment, the variable voltage supply line 146 transmits a variable voltage VV to the first conductive line CL1. The variable voltage supply line 146 can be disposed on the fourth insulating layer IL4. Thus, the variable voltage supply line 146 can be disposed on the first conductive line CL1 outside the display area DA, with insulating layers such as the first through fourth insulating layers IL1, IL2, IL3, and IL4 in between. In an exemplary embodiment, the variable voltage supply line 146 is connected to the first conductive line CL1 by a first contact hole CH1 that passes through the first through fourth insulating layers IL1, IL2, IL3, and IL4. For example, the variable voltage supply line 146 can include a first vertical portion that passes through the first through fourth insulating layers IL1, IL2, IL3, and IL4 to be connected to the first conductive line CL1. In an exemplary embodiment, a first width of the first vertical portion is substantially uniform.

[0116] Scan signal supply line 147 can be supplied from Figure 2 The driving circuit unit 20 extends from the display area DA and can be connected to the second conductive line CL2 and the first scan line 121. Therefore, each of the second conductive line CL2 and the first scan line 121 can be connected to a scan signal supply line 147 outside the display area DA. The scan signal supply line 147 can transmit scan signals to the second conductive line CL2 and the first scan line 121. In an exemplary embodiment, the scan signal includes a gate conduction voltage (e.g., a pulse), which, when applied to the gate terminal of the pixel's transistor, causes the pixel to receive data via a data line connected to the source terminal of the transistor. The scan signal supply line 147 can be disposed on a fourth insulating layer IL4. Therefore, the scan signal supply line 147 can be disposed outside the display area DA, on the second conductive layer CL2, with insulating layers such as the first to fourth insulating layers IL1, IL2, IL3, and IL4 in between; and the scan signal supply line 147 can be disposed outside the display area DA, on the first scan line 121, with insulating layers such as the third insulating layer IL3 and the fourth insulating layer IL4 in between. In an exemplary embodiment, the scan signal supply line 147 is connected to the second conductive line CL2 via a second contact hole CH2 passing through the first to fourth insulating layers IL1, IL2, IL3, and IL4, and can be connected to the first scan line 121 via a third contact hole CH3 passing through the third and fourth insulating layers IL3 and IL4. For example, the variable voltage supply line 147 may include a second vertical portion passing through the first to fourth insulating layers IL1, IL2, IL3, and IL4 to connect to the second conductive line CL2, and a third vertical portion passing through the third and fourth insulating layers IL3 and IL4 to connect to the first scan line 121. In an exemplary embodiment, the second width of the second vertical portion is substantially uniform. In an exemplary embodiment, the widths of the first and second vertical portions are the same. In an exemplary embodiment, the heights of the first and second vertical portions are the same.

[0117] Figure 9 This is a graph illustrating an exemplary step efficiency based on the variable voltage VV received by the first conductive line CL1. Figure 9 In the figure, the horizontal axis shows the voltage difference between the first bottom gate electrode BG1 and the first source electrode S1 of the first transistor T1, and the vertical axis shows the step efficiency, which is the ratio of the brightness of the light emitted from the light-emitting element EE to the brightness corresponding to the data voltage DATA.

[0118] refer to Figure 9As the magnitude of the variable voltage VV decreases, i.e., the difference (Vbs) between the magnitude of the variable voltage VV received by the first conductive line CL1 and the magnitude of the voltage of the first source electrode S1 of the first transistor T1 decreases, the step efficiency of the display apparatus can increase. When the magnitude of the variable voltage VV decreases, the on current of the first transistor T1 increases, and thus, the step efficiency of the display apparatus can be improved.

[0119] Figure 10 FIG. 7 is a graph showing exemplary temporal image sticking of a display apparatus according to an embodiment example and a comparative example. In the embodiment example, the first bottom gate electrode BG1 of the first transistor T1 receives a variable voltage VV having a positive voltage of about 7.5 V. In the comparative example, the first bottom gate electrode BG1 of the first transistor T1 receives a driving voltage VDD having a voltage of about 4.6 V.

[0120] Referring to Figure 10 When the first bottom gate electrode BG1 of the first transistor T1 receives a variable voltage VV having a relatively large voltage (e.g., a voltage greater than the driving voltage VDD), the maintenance time of the temporal image sticking of the display apparatus decreases. In other words, as the magnitude of the variable voltage VV received by the first bottom gate electrode BG1 of the first transistor T1 increases, the maintenance time of the temporal image sticking of the display apparatus decreases. When the first bottom gate electrode BG1 receives a variable voltage VV having a relatively large voltage, the hysteresis of the first transistor T1 can be improved, and thus, the temporal image sticking of the display apparatus due to the hysteresis of the first transistor T1 can be improved.

[0121] In an exemplary embodiment, the variable voltage VV is set to be different (e.g., lower or higher) than the driving voltage VDD. In an exemplary embodiment, the lower variable voltage VV is a negative voltage, and the driving voltage VDD is a positive voltage. In an exemplary embodiment, both the variable voltage VV and the driving voltage VDD are positive voltages, and the variable voltage VV is higher than the driving voltage VDD.

[0122] A display apparatus according to at least one embodiment of the inventive concept can be applied in a computer, a notebook computer, a mobile phone, a smart phone, a smart pad, a portable media player (PMP), a personal digital assistant (PDA), or an MP3 player.

[0123] While the display apparatus according to the exemplary embodiments of the inventive concept has been described with reference to the accompanying drawings, the illustrated embodiments are examples and can be modified and changed by those skilled in the art without departing from the technical spirit described in the present application.

Claims

1. A display device, comprising: The first transistor includes a first channel region, a first gate electrode overlapping the first channel region, and a first electrode for receiving a driving voltage. The second transistor is electrically connected to the first electrode of the first transistor, and the second transistor includes a second channel region and a second gate electrode that overlaps with the second channel region and receives a scan signal. The light-emitting element is electrically connected to the second electrode of the first transistor; A first conductive line overlaps with the first gate electrode, wherein the first channel region is located between the first conductive line and the first gate electrode, and the first conductive line receives a variable voltage different from the driving voltage; as well as A second conductive line overlaps with the second gate electrode, wherein a second channel region is located between the second conductive line and the second gate electrode, and the second conductive line receives the scan signal. The variable voltage is either a negative voltage less than the driving voltage to increase the step efficiency of the display device or a positive voltage greater than the driving voltage to reduce the number of afterimages that can be perceived on the display device.

2. The display device according to claim 1, further comprising: A third transistor is electrically connected to the second electrode of the first transistor, the third transistor including a third channel region and a third gate electrode overlapping the third channel region and receiving the scan signal.

3. The display device according to claim 2, wherein the second conductive line overlaps with the third gate electrode, and the third channel region is located between the second conductive line and the third gate electrode.

4. The display device according to claim 2, further comprising: The scan line that receives the scan signal, Each of the second gate electrode and the third gate electrode is part of the scan line.

5. The display device according to claim 1, wherein the first conductive line includes an extension portion extending along a first direction and an overlapping portion overlapping the first gate electrode.

6. The display device of claim 5, wherein the width of the overlapping portion in a second direction intersecting the first direction is greater than the width of the extending portion in the second direction.

7. The display device of claim 1, wherein the second conductive line includes an extension portion extending along a first direction and an overlapping portion overlapping with the second gate electrode.

8. The display device of claim 7, wherein the overlapping portion protrudes from the extension portion in a second direction intersecting the first direction.

9. The display device according to claim 1, wherein the first conductive line is connected to a variable voltage supply line located outside the display area.

10. The display device according to claim 1, wherein the second conductive line is connected to a scan signal supply line located outside the display area.

11. The display device of claim 1, wherein each of the first transistor and the second transistor is a p-channel metal-oxide-semiconductor transistor.

12. A display device, comprising: substrate; A first conductive layer is disposed on the substrate and receives a variable voltage; A second conductive layer is disposed on the substrate, spaced apart from the first conductive layer, and receives scanning signals; The first transistor includes a first active layer disposed on the first conductive layer and a first gate electrode disposed on the first active layer, wherein a first end of the first active layer receives a driving voltage different from the variable voltage. The second transistor includes a second active layer disposed on the second conductive layer and electrically connected to the first end of the first active layer, and a second gate electrode disposed on the second active layer and receiving the scan signal; as well as The light-emitting element is electrically connected to the first transistor. The variable voltage is either a negative voltage less than the driving voltage to increase the step efficiency of the display device or a positive voltage greater than the driving voltage to reduce the number of afterimages that can be perceived on the display device.

13. The display device according to claim 12, further comprising: The third transistor includes a third active layer disposed on the second conductive layer and electrically connected to the second end of the first active layer, and a third gate electrode disposed on the third active layer and receiving the scan signal.

14. The display device of claim 12, wherein the first conductive layer is connected to a variable voltage supply line located outside the display area.

15. The display device according to claim 14, The variable voltage supply line is disposed on the first conductive layer. An insulating layer is disposed outside the display area, between the variable voltage supply line and the first conductive layer, and The first conductive layer contacts the variable voltage supply line through contact holes formed in the insulating layer.

16. The display device of claim 12, wherein the second conductive layer is connected to a scan signal supply line located outside the display area.

17. The display device according to claim 16, The scan signal supply line is disposed on the second conductive layer. An insulating layer is disposed outside the display area, between the scan signal supply line and the second conductive layer, and The second conductive layer contacts the scan signal supply line through a contact hole formed in the insulating layer.

18. The display device of claim 12, wherein each of the first transistor and the second transistor is a p-channel metal-oxide-semiconductor transistor.

19. A display device, comprising: Light-emitting elements; A driving transistor for controlling the current passing through the light-emitting element, the driving transistor including a first terminal connected to a node receiving a driving voltage and a bottom gate terminal connected to a node receiving a variable voltage; as well as A driving circuit is configured to provide the variable voltage, wherein the variable voltage is a positive voltage greater than the driving voltage or a negative voltage less than the driving voltage. The driving circuit is configured to change the value of the variable voltage to the negative voltage to increase the step efficiency of the display device, or to change it to the positive voltage to reduce the number of afterimages that can be perceived on the display device.

Images