storage device

Abstract

A storage device includes a first nonvolatile memory device, a second nonvolatile memory device, and a data line. The second nonvolatile memory device has a different type from the first nonvolatile memory device. The data line is shared by the first nonvolatile memory device and the second nonvolatile memory device. First data is simultaneously supplied to the first nonvolatile memory device and the second nonvolatile memory device through the data line, the first data is written to the second nonvolatile memory device, and the first data is reprogrammed into the first nonvolatile memory device by reading the first data from the second nonvolatile memory device and supplying the read first data to the first nonvolatile memory device.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0095826, filed on August 7, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a storage device. Background Technology

[0004] Flash memory is a type of non-volatile memory that retains stored data even during power outages. In recent years, storage devices, including embedded multimedia cards (eMMC), universal flash memory (UFS), solid-state drives (SSDs), and memory cards, have become widely used. Storage devices are useful for storing or moving large amounts of data.

[0005] Non-volatile memory devices employing reprogrammable methods store programming data in a buffer memory. This stored data is initially programmed and then reprogrammed. In other words, the buffer memory must hold the programming data until both initial and reprogramming are complete. Therefore, the reprogramming method increases the time the buffer memory is occupied by programming data, thus reducing its utilization. Since buffer memory is typically expensive static random access memory (SRAM), reduced buffer memory utilization decreases the overall price competitiveness of the memory device. Summary of the Invention

[0006] One aspect is to provide a storage device that can improve the utilization of the buffer memory.

[0007] According to one aspect of the embodiments, a storage device is provided, the storage device comprising: a first non-volatile memory device; a second non-volatile memory device having a different type from the first non-volatile memory device; and a data line shared by the first non-volatile memory device and the second non-volatile memory device, wherein first data is simultaneously provided to the first non-volatile memory device and the second non-volatile memory device via the data line, the first data is written to the second non-volatile memory device, and the first data is reprogrammed into the first non-volatile memory device by reading the first data from the second non-volatile memory device and providing the read first data to the first non-volatile memory device.

[0008] According to another aspect of the embodiments, a storage device is provided, the storage device comprising: a NAND flash memory device; a phase change memory device; and a data line shared by the NAND flash memory device and the phase change memory device, wherein first data is simultaneously provided to the NAND flash memory device and the phase change memory device via the data line, and the first data is initially programmed into the NAND flash memory device and simultaneously written to the phase change memory device, wherein the initial programming period of the NAND flash memory device and the writing period of the phase change memory device at least partially overlap.

[0009] According to another aspect of the embodiments, a storage device is provided, the storage device comprising: a first non-volatile memory device; a second non-volatile memory device having a different type from the first non-volatile memory device; a data line shared by the first non-volatile memory device and the second non-volatile memory device; and a buffer memory, wherein first data occupies a first area of ​​the buffer memory, the occupation of the first area by the first data ends after the first data of the buffer memory is simultaneously provided to the first non-volatile memory device and the second non-volatile memory device via the data line, and the first data is written to the second non-volatile memory device while the first data is initially programmed into the first non-volatile memory device.

[0010] According to another aspect of the embodiments, a storage device is provided, the storage device including: a NAND flash memory device, a phase change memory device, a data line shared by the NAND flash memory device and the phase change memory device, and a buffer memory, wherein first data occupies a first area of ​​the buffer memory, and after the first data in the buffer memory is simultaneously provided to the NAND flash memory device and the phase change memory device through the data line, the occupation of the first data in the first area ends, and while the first data is initially programmed into the NAND flash memory device, the first data is written into the phase change memory device, and if it is determined that the verification result is that the initial programming failed, the first data is reprogrammed into the NAND flash memory device by reading the first data stored in the phase change memory device and providing the read first data to the NAND flash memory device.

[0011] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of this disclosure will become clearer to one skilled in the art upon reference to the detailed description of the disclosure provided below. Attached Figure Description

[0012] These and / or other aspects will become clearer and more readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0013] Figure 1 This is a block diagram of a storage device according to an embodiment;

[0014] Figure 2 yes Figure 1 A circuit diagram of the first non-volatile memory cell array of the storage device;

[0015] Figure 3 yes Figure 1 A circuit diagram of the second non-volatile memory cell array of the storage device;

[0016] Figure 4 This illustrates an embodiment. Figures 1 to 3 A flowchart illustrating an example of the operation of a storage device;

[0017] Figure 5 It is used for explanation Figure 4 The flowchart shows the timing diagrams for operations S10 and S20;

[0018] Figure 6 It is used for explanation Figure 4 The flowchart of the operation S30 is a conceptual diagram;

[0019] Figure 7 This is a block diagram of a storage device according to an embodiment;

[0020] Figure 8 It is used for explanation Figure 7 A timing diagram illustrating an example of the operation of a storage device;

[0021] Figure 9 This is a timing diagram used to explain an example of the operation of a storage device according to an embodiment;

[0022] Figure 10 This is a block diagram of a storage device according to an embodiment; and

[0023] Figure 11 This is a block diagram of a storage device according to an embodiment. Detailed Implementation

[0024] In the following description, various embodiments will be described with reference to the accompanying drawings.

[0025] Figure 1 This is a block diagram of a storage device according to an embodiment.

[0026] Reference Figure 1 The storage device includes a first non-volatile memory (NVM) device 100, a second non-volatile memory (NVM) device 200, a controller 300, and a buffer memory 400.

[0027] The first non-volatile memory device 100 can be a primary memory for storing data, and the second non-volatile memory device 200 can be a backup memory for assisting the data storage of the first non-volatile memory device 100. For example, when a program error occurs in the first non-volatile memory device 100, the second non-volatile memory device 200 can be used to restore the backup. Alternatively, the second non-volatile memory device 200 can store data for reprogramming operations of the first non-volatile memory device 100, but the embodiments are not limited to this.

[0028] In some embodiments, the first non-volatile memory device 100 and the second non-volatile memory device 200 may be of different types. Here, the programming time of the first non-volatile memory device 100 may be greater than the writing time of the second non-volatile memory device 200. Additionally, the reading time of the first non-volatile memory device 100 may be greater than the reading time of the second non-volatile memory device 200. For example, in some embodiments, the first non-volatile memory device 100 may be a NAND flash memory device, and the second non-volatile memory device 200 may be a phase-change memory device. Alternatively, in some embodiments, the first non-volatile memory device 100 may be a flash memory device capable of storing multiple bits in a single memory cell (e.g., a third-order cell (TLC) memory device or a fourth-order cell (QLC) memory device), and the second non-volatile memory device 200 may be a flash memory device capable of storing one bit in a single memory cell (e.g., a first-order cell (SLC) memory device). That is, the first non-volatile memory device 100 may have n-order memory cells (where n is a natural number), and the second non-volatile memory device 200 may have m-order memory cells (where m is a natural number), and n > m. The first non-volatile memory device 100 and the second non-volatile memory device 200 are not limited to the above examples.

[0029] For ease of description, in Figure 1 In the diagram, the first non-volatile memory device 100 is shown as including a first non-volatile memory (NVM) cell array 110 having a plurality of first memory cells and a first input / output (I / O) driver 120. Similarly, in Figure 1 In the diagram, the second non-volatile memory device 200 is shown as including a second non-volatile memory (NVM) cell array 210 having a plurality of second memory cells and a second input / output (I / O) driver 220. Specific internal functional blocks may vary depending on the type of the first non-volatile memory device 100 and the type of the second non-volatile memory device 200.

[0030] The buffer memory 400 can be implemented as (but is not limited to) static random access memory (SRAM) or dynamic random access memory (DRAM). The programming / reading time (speed) of the buffer memory 400 can be faster than that of the first non-volatile memory device 100.

[0031] Specifically, in Figure 1 In the storage device according to the embodiment shown, the first non-volatile memory device 100 and the second non-volatile memory device 200 can share the data line 310 with each other. Through the shared data line 310, data DATA1 can be simultaneously provided to both the first non-volatile memory device 100 and the second non-volatile memory device 200. That is, the time required to provide data DATA1 to both the first non-volatile memory device 100 and the second non-volatile memory device 200 can be minimized.

[0032] Furthermore, the second non-volatile memory device 200 can share the interface (not shown) of the first non-volatile memory device 100. Therefore, if the first non-volatile memory device 100 is a NAND flash memory device and the second non-volatile memory device 200 is a phase-change memory device, the commands / addresses / data used to control the NAND flash memory device can also be used to control the phase-change memory device. A method for operating the memory devices using the shared data line 310 and the shared interface will be described in detail later.

[0033] Figure 2 yes Figure 1 A circuit diagram of the first non-volatile memory cell array 110 of the storage device.

[0034] Reference Figure 2 The first non-volatile memory cell array 110 may be a three-dimensional (3D) memory cell array, but the embodiments are not limited to this. The first non-volatile memory cell array 110 may also be a two-dimensional (2D) memory cell array.

[0035] In a 3D memory cell array, the array of memory cells can be monolithically formed on one or more physical levels and may also include circuitry associated with the operation of the memory cells. The term "monolithic" means that each layer of the array is deposited directly on the layer of the next lower level of the array. A 3D memory array may include vertically oriented strings of NAND flash memory such that at least one memory cell is situated above other memory cells. The at least one memory cell may include a charge trapping layer.

[0036] Specifically, unit strings NS11 to NS41 are set in the first line BL. <1> Between the common source pole line CSL. Cell strings NS12 to NS42 are set on the second bit line BL. <2> Between the common-source pole line CSL. Cell strings NS14 to NS44 are set on the fourth bit line BL. <4> Between and the common source pole line CSL.

[0037] The string select transistor SST of each cell string NS is connected to the corresponding bit line BL. The ground select transistor GST of each cell string NS is connected to the common source line CSL. Memory cells MC1 to MC7 are located between the string select transistor SST and the ground select transistor GST of each cell string NS.

[0038] The rows and columns of the unit string NS are defined as follows.

[0039] A series of cells NS connected together to a single bit line form a column. For example, connected to the first bit line BL <1> The unit strings NS11 to NS41 can correspond to the first column. Connected to the second bit line BL. <2> The cell strings NS12 to NS42 can correspond to the second column. Connected to the fourth bit line BL. <4> The unit strings NS14 to NS44 can correspond to the fourth column.

[0040] Unit strings NS connected to a single string select line SSL form a row. For example, connected to the first string select line SSL... <1> The unit strings NS11 to NS14 form the first row. Connect to the second string of select lines SSL. <2> The unit strings NS21 to NS24 form the second row. Connect to the fourth string select line SSL. <4> The unit strings NS41 to NS44 form the fourth row.

[0041] Each cell string NS includes a ground select transistor GST. The ground select transistor GST can be controlled by a ground select line GSL. Alternatively, although not shown in the figures, cell strings corresponding to each row can be controlled by different ground select lines. For example, the ground select transistor GST for each cell string NS11, NS12, and NS14 in the first row can be connected to the first ground select line GSL1. Additionally, the ground select transistor GST for each cell string NS21, NS22, and NS24 in the second row can be connected to the second ground select line GSL2. The ground select transistor GST for each cell string NS41, NS42, and NS44 in the fourth row can be connected to the fourth ground select line GSL4.

[0042] Memory cells corresponding to the same semiconductor layer share word lines (WL). <0> To WL <6> one).

[0043] Strings NS on the same row share a single select line SSL. Strings NS on different rows are connected to different select lines SSL. <1> SSL <2> SSL <4> In the following text, the first string select transistor SST1 is defined as connected to the first string select line SSL. <1> The first string select transistor is SST. The second string select transistor SST2 is defined as connected to the second string select line SSL. <2> The fourth string select transistor SST is defined as connected to the fourth string select line SSL. <4> The string selection transistor SST.

[0044] The common-source pole line CSL is connected to the cell string NS.

[0045] The first non-volatile memory cell array 110 may include multiple memory cell blocks BLKi. A memory block BLKi may be divided into multiple segments, each segment including multiple strings sharing a string select line SSL. That is, the memory block BLKi may be divided into multiple sub-blocks SB, each sub-block SB including multiple cell strings sharing a single string.

[0046] Additionally, alternating programming can be applied in units of sub-blocks (SB), each SB being smaller than a memory block (BLKi). The first select line (SSL) is shared. <1> The unit strings NS11, NS12, and NS14 can be grouped into the first sub-block SB1. The second selection line SSL is shared. <2> The unit strings NS21, NS22, and NS24 can be grouped into the second sub-block SB2. The fourth selection line SSL is shared. <4> The cell strings NS41, NS42, and NS44 can be grouped into the fourth sub-block SB4. Although nine cell strings are grouped into three sub-blocks, the embodiment is not limited to this. Alternatively, unlike the above description, alternating programming can be applied on a memory block BLKi basis, with each memory block BLKi being the basic unit of erasure.

[0047] Figure 3 yes Figure 1 The circuit diagram of the second non-volatile memory cell array 210 of the storage device.

[0048] Reference Figure 3The second non-volatile memory cell array 210 includes multiple word lines WL0 to WLa (where a is a natural number of 1 or greater), multiple bit lines BL0 to BLb (where b is a natural number of 1 or greater), and multiple memory cells MC disposed at the intersections of the word lines WL0 to WLa and the bit lines BL0 to BLb. When the cell array 210 is implemented as a resistive memory, each of the memory cells MC may include a cell transistor and a resistive element. Additionally, the cell transistor and resistive element of each of the memory cells MC may be connected between any of the bit lines BL0 to BLb and the source line SL. Although not explicitly shown, multiple memory cells MC may be connected together to the same source line SL, but the embodiment is not limited to this. The row decoder selects word lines WL0 to WLa to provide signals for turning on or off the cell transistors, and the column decoder selects bit lines BL0 to BLb.

[0049] Resistive elements can be phase-change random access memory (PRAM) using phase-change materials, resistive random access memory (RRAM) using variable resistive materials such as composite metal oxides, or magnetic random access memory (MRAM) using ferromagnetic materials. The material forming the resistive element can have a resistance value that changes according to the magnitude and / or direction of the current or voltage, and can have the non-volatile characteristic of maintaining the resistance value even if the current or voltage is interrupted.

[0050] Now refer to Figures 4 to 6 Detailed description based on Figure 1-3 The operation of the storage device in the illustrated embodiment. Figure 4 This is a flowchart illustrating an example of the operation of a storage device according to an embodiment. Figure 5 It is used for explanation Figure 4 The timing diagram of operations S10 and S20 in the flowchart. Figure 6 It is used for explanation Figure 4 The flowchart shows the concept diagram of operation S30.

[0051] Reference Figure 1 and Figure 4 The first data DATA1 to be programmed into the first non-volatile memory device 100 is stored in the buffer memory 400.

[0052] Then, the first data DATA1 is simultaneously provided to the first non-volatile memory device 100 and the second non-volatile memory device 200 via the shared data line 310 (operation S10).

[0053] Specifically, referring to Figure 5NVM1 indicates the first non-volatile memory device 100, NVM2 indicates the second non-volatile memory device 200, and DQ indicates the data line. CE1 indicates a first chip select signal for selecting the first non-volatile memory device 100, and CE2 indicates a second chip select signal for selecting the second non-volatile memory device 200.

[0054] During the time interval t0 to t1, the first chip select signal CE1 is activated. During this time, the programming command PGM and the first address ADDR1, which indicates the location in the first non-volatile memory device 100, are provided to the first non-volatile memory device 100 via the shared data line DQ.

[0055] During the time interval t1 to t2, the second chip select signal CE2 is activated. During this time, the write command WR and the write address WADDR indicating the location in the second non-volatile memory device 200 are provided to the second non-volatile memory device 200 via the shared data line DQ.

[0056] During the time interval t2 to t3, the first chip select signal CE1 and the second chip select signal CE2 are activated. During this time, the first data DATA1 is provided through the shared data line DQ. Since the data line DQ is shared, the first data DATA1 is simultaneously provided to the first non-volatile memory device 100 and the second non-volatile memory device 200.

[0057] Refer to Figure 1 and Figure 4 The first data DATA1 is initially programmed into the first non-volatile memory device 100 and written to the second non-volatile memory device 200 (operation S20).

[0058] Specifically, referring to Figure 5 During the time interval t3 to t4, the first chip select signal CE1 is activated. The programming confirmation signal CF1 is provided to the first non-volatile memory device 100. Starting from time t4, the first data DATA1 is initially programmed into the first non-volatile memory device 100.

[0059] During the time interval t4 to t5, the second chip select signal CE2 is activated. The write confirmation signal CF2 is provided to the second non-volatile memory device 200. Starting from time t5, the first data DATA1 is written to the second non-volatile memory device 200.

[0060] As described above, the initial programming period tPGM of the first non-volatile memory device 100 and the write period tWR of the second non-volatile memory device 200 can at least partially overlap. As described above, the programming time of the first non-volatile memory device 100 can be longer than the write time of the second non-volatile memory device 200. Therefore, as... Figure 5 As shown, since the initial programming operation of the first non-volatile memory device 100 is started first, the write operation of the second non-volatile memory device 200 can be completed within the initial programming period tPGM of the first non-volatile memory device 100.

[0061] Reference Figure 1 and Figure 4 The first data DATA1 is reprogrammed into the first non-volatile memory device 100 by reading the first data DATA1 from the second non-volatile memory device 200 and providing the first data DATA1 to the first non-volatile memory device 100 (operation S30).

[0062] This situation (i.e., the case where reprogramming is performed using the first data DATA1) can be a case where the verification result indicates that the initial programming of the first data DATA1 into the first non-volatile memory device 100 has failed. The data stored in the second non-volatile memory 220 is used as backup data.

[0063] Specifically, referring to Figure 6 If the verification result indicates that the initial programming operation has failed, the controller 300 can provide a read command / address to the second non-volatile memory device 200 to read the first data DATA1 from the second non-volatile memory device 200. Since, as described above, the read speed of the second non-volatile memory device 200 is faster than that of the first non-volatile memory device 100, the first data DATA1 can be read relatively quickly (see ①). The read first data DATA1 can be temporarily stored in a region (block 401) of the buffer memory 400 (see ②). The controller 300 can retrieve the first data DATA1 from the buffer memory 400 (see ③) and can transfer the first data DATA1 to the first non-volatile memory device 100 (see ④). Therefore, the first data DATA1 can be reprogrammed.

[0064] Here, it is assumed that there is no second non-volatile memory device 200. In this case, the first data DATA1 occupies area 401 of the buffer memory 400 to be reprogrammed into the first non-volatile memory device 100. Then, the first data DATA1 is provided to the first non-volatile memory device 100 and is initially programmed into the first non-volatile memory device 100. During the initial programming operation, the buffer memory 400 cannot release the space occupied by the first data DATA1 (end of the occupation of the first data DATA1). If it is determined that the verification result is that the initial programming operation has failed, the controller 300 retrieves the first data DATA1 from the buffer memory 400 and provides the first data DATA1 to the first non-volatile memory 100 again. Therefore, the first data DATA1 is reprogrammed. If it is determined that the verification result of the reprogramming operation is that the reprogramming operation is successful, the memory 400 can finally release the space occupied by the first data DATA1 (end of the occupation of the first data DATA1). That is to say, the utilization of the buffer memory 400 is very low.

[0065] On the other hand, compared to the above example (where there is no second non-volatile memory device 200), according to Figures 1 to 6 The storage device of the illustrated embodiment operates as follows. First, first data DATA1 occupies area 401 of buffer memory 400. First data DATA1 is simultaneously provided to both the first non-volatile memory device 100 and the second non-volatile memory device 200 via a shared data line 310. After providing first data DATA1, buffer memory 400 releases its occupation of first data DATA1 (ends occupation of first data DATA1). This is because first data DATA1 can be read from the second non-volatile memory device 200, and subsequently, if the verification result indicates that the initial programming operation has failed, first non-volatile memory device 100 can be reprogrammed using first data DATA1. In other words, since buffer memory 400 does not need to be occupied by first data DATA1 until programming of first data DATA1 is complete (successful), the utilization of buffer memory 400 can be increased.

[0066] Figure 7 This is a block diagram of a storage device according to an embodiment. Figure 8 It is used for explanation Figure 7 A timing diagram illustrating an example of the operation of a storage device. For ease of description, the following will primarily describe and refer to... Figures 1 to 6 The differences in the described components and features will be referenced. Figure 7 and Figure 8 Describes the multi-stage programming operations of a storage device.

[0067] First, refer to Figure 7The first non-volatile memory cell array 110 of the first non-volatile memory device 100 may include a plurality of memory cell blocks. For example, in some embodiments, the first non-volatile memory cell array 110 may include odd-numbered memory cell blocks 110a and even-numbered memory cell blocks 110b. The second non-volatile memory device 200 may include memory cell block 210a.

[0068] Multi-stage programming refers to simultaneously programming memory blocks 110a and 110b that are spaced apart from each other. By programming multiple memory blocks 110a and 110b simultaneously, programming time can be reduced. Figure 7 In this process, memory cell blocks 110a with odd numbers and memory cell blocks 110b with even numbers are programmed simultaneously.

[0069] Since the odd-numbered memory blocks 110a and even-numbered memory cell blocks 110b are programmed simultaneously, the programming operation begins after the first data DATA1 for the odd-numbered memory cell blocks 110a and the second data DATA2 for the even-numbered memory cell blocks 110b are provided to the first non-volatile memory device 100.

[0070] Specifically, referring to Figure 8 During the time interval t0 to t1, the first chip select signal CE1 is activated. During this time, the programming command PGM and the first address ADDR1, indicating the location in the first non-volatile memory device 100, are provided via the shared data line DQ.

[0071] During the time interval t1 to t2, the second chip select signal CE2 is activated. During this time, the write command WR and the first write address WADDR1, indicating the location in the second non-volatile memory device 200, are provided via the shared data line DQ.

[0072] During the time interval t2 to t3, the first chip select signal CE1 and the second chip select signal CE2 are activated. During this time, the first data DATA1 is provided via the shared data line DQ. The first data DATA1 may be data to be programmed into the odd-numbered memory cell block 110a.

[0073] During the time interval t3 to t4, the first chip select signal CE1 is activated. During this time, the programming command PGM and the second address ADDR2, indicating the location in the first non-volatile memory device 100, are provided via the shared data line DQ.

[0074] During the time interval t4 to t5, the second chip select signal CE2 is activated. During this time, the write command WR and the second write address WADDR2, indicating the location in the second non-volatile memory device 200, are provided via the shared data line DQ.

[0075] During the time interval t5 to t6, the first chip select signal CE1 and the second chip select signal CE2 are activated. During this time, the second data DATA2 is provided via the shared data line DQ. The second data DATA2 may be data to be programmed into the even-numbered memory cell block 110b.

[0076] During the time interval t6 to t7, the first chip select signal CE1 is activated. The programming confirmation signal CF1 is provided to the first non-volatile memory device 100. Starting from time t7, the first data DATA1 and the second data DATA2 are initially programmed into the first non-volatile memory device 100. The first data DATA1 is programmed into the odd-numbered memory cell block 110a, and the second data DATA2 is programmed into the even-numbered memory cell block 110b.

[0077] During the time interval t7 to t8, the second chip select signal CE2 is activated. The write confirmation signal CF2 is provided to the second non-volatile memory device 200. Starting from time t8, the first data DATA1 and the second data DATA2 are written to the second non-volatile memory device 200.

[0078] The programming period tPGM of the first non-volatile memory device 100 and the writing period tWR of the second non-volatile memory device 200 may overlap with each other at least partially.

[0079] References above Figures 7 to 8 The descriptions differ. In some embodiments, the second data DATA2 can be programmed into the odd-numbered memory cell block 110a, and the first data DATA1 can be programmed into the even-numbered memory cell block 110b.

[0080] As referenced above Figure 7 and Figure 8 As described, in a multi-stage programming operation, data DATA1 and DATA2, respectively for odd-numbered memory cell blocks 110a and even-numbered memory cell blocks 110b, can be provided to the first non-volatile memory device 100. Therefore, the data transfer time (i.e., the time period from t0 to t6) is inevitably longer than that of a reference device. Figures 1 to 6 The description is longer.

[0081] Here, if two or more bits are stored in a single memory cell, the data transfer time increases. If the first non-volatile memory device 100 includes a multi-level cell (MLC), the data transfer time becomes twice the time period t0 to t6. If the first non-volatile memory device 100 includes a three-level cell (TLC), the data transfer time becomes three times the time period t0 to t6. If the first non-volatile memory device 100 includes a four-level cell (QLC), the data transfer time becomes four times the time period t0 to t6.

[0082] Assuming the second memory device 200 is not used as backup memory, the buffer memory (e.g., SRAM) is occupied, increasing data transfer time. Furthermore, the buffer memory remains occupied until programming is complete. Moreover, if two or more bits are stored in a single memory cell, the utilization of the buffer memory is significantly reduced.

[0083] However, Figures 7 to 8 The storage device according to the embodiment shown terminates the data occupation of the buffer memory 400 after transmitting data to the first non-volatile memory device 100 and the second non-volatile memory device 200 via the shared data line 310. The data occupation of the buffer memory 400 can also be released (terminated) before data is written to the second non-volatile memory device 200. Therefore, the utilization of the buffer memory 400 can be increased even if two or more bits are stored in a single memory cell and / or multi-stage operations are performed.

[0084] Figure 9 This is a timing diagram used to explain an example of the operation of a storage device according to an embodiment. For ease of description, the following will primarily describe and utilize... Figures 1 to 8 The differences in the components and features described.

[0085] Reference Figure 9 The following describes, as an example, a NAND flash memory device 100 employing both reprogramming and alternating programming methods. The NAND flash memory device may include TLC or QLC, each storing three or more bits. When three or more bits are stored in a single memory cell, the same data can be programmed two or more times for precise / stable programming. This is the reprogramming method.

[0086] Sequential programming involves programming memory cells connected to the first word line and then programming memory cells connected to the next word line (second word line). Alternating programming, on the other hand, refers to alternately programming some memory cells of the second word line, some memory cells of the previous word line (first word line), and / or some memory cells of the next word line (third word line) in a preset order. That is, memory cells connected to adjacent word lines are programmed alternately.

[0087] Additionally, refer to Figure 9 Each of Channels 0 through 3 refers to an independent data path existing between a cluster (or group) and the controller 300. A data path may include a transmission line through which data and / or commands are transmitted. Each of Ways 0 through 7 may refer to a cluster (or group) of one or more non-volatile memory devices sharing a channel. For example, Ways 0 and 4 share Channel 0. Figure 9 In this context, DMA refers to Data Transfer Time.

[0088] like Figure 9 As shown, the initial programming operation Nth WL PGM1 of the Nth word line, the reprogramming operation (N-1)th WL PGM2 of the (N-1)th word line, the initial programming operation (N+1)th WL PGM1 of the (N+1)th word line, and the reprogramming operation Nth WL PGM2 of the Nth word line are executed in sequence.

[0089] Programming of each word line can be performed, for example, block by block. For instance, if the Nth word line is divided into four sub-blocks, four data transfer operations and four programming operations can be performed. That is, the initial programming operation Nth WL PGM1 for the Nth word line includes the data transfer time 511 corresponding to the first sub-block, the programming time tPGM corresponding to the first sub-block, the data transfer time 512 corresponding to the second sub-block, the programming time of the second sub-block, the data transfer time 513 corresponding to the third sub-block, the programming time of the third sub-block, the data transfer time 514 corresponding to the fourth sub-block, and the programming time of the fourth sub-block. Note that, for ease of explanation, Figure 9 Only the programming time tPGM between data transfer time 511 and data transfer time 512 is shown. That is to say, for example, there is another programming time tPGM between data transfer time 512 and data transfer time 513, etc.

[0090] Similarly, the reprogramming operation (N-1)th WL PGM2 of the (N-1)th word line includes four data transfer operations 515 to 518 and four programming operations (with corresponding programming times).

[0091] The initial programming operation (N+1)th WL PGM1 of the (N+1)th word line includes four data transfer operations 519 to 522 and four programming operations (with corresponding programming times).

[0092] Then, the reprogramming operation Nth WL PGM2 for the Nth word line is executed. In the Nth WLPGM2 reprogramming operation, the data transfer time 523 corresponding to the first sub-block and the programming time tPGM of the first sub-block begin. The data transferred during data transfer times 511 and 523 is the data to be programmed into the same sub-block.

[0093] In short, such as Figure 9 As shown, the time interval tBF1 between the initial programming of the first sub-block of the Nth word line and the reprogramming of the first sub-block of the Nth word line is quite long (see 511 and 523). This is because the programming of the sub-blocks connected to the (N-1)th word line and / or the (N+1)th word line is placed between the initial programming of the first sub-block of the Nth word line and the reprogramming of the first sub-block of the Nth word line.

[0094] Here, it is assumed that the second non-volatile memory device 200 is not used as backup memory, and the data to be programmed into the first sub-block of the Nth word line occupies the buffer memory 400 for a very long period of time tBF1.

[0095] However, in the storage device according to the embodiment, after providing data to the first non-volatile memory device 100 (that is, see 511), the controller 300 releases (ends) the data to be programmed into the first sub-block of the Nth word line from the buffer memory 400. In other words, the data to be programmed into the first sub-block of the Nth word line occupies the buffer memory 400 for only a very short time period tBF2. Therefore, the utilization of the buffer memory 400 can be increased.

[0096] Figure 10 This is a block diagram of a storage device according to an embodiment. For ease of description, the following will mainly describe and utilize... Figures 1 to 9 The differences in the components and features described.

[0097] Reference Figure 10The first non-volatile memory device 111 can be a flash memory device (e.g., a TLC or QLC memory device) capable of storing multiple bits in a single memory cell, and the second non-volatile memory device 112 can be a flash memory device (e.g., an SLC memory device) capable of storing one bit in a single memory cell. That is, the first non-volatile memory device 111 can have n levels of memory cells (where n is a natural number), and the second non-volatile memory device 112 can have m levels of memory cells (where m is a natural number), and n > m. For example, if the first non-volatile memory device 111 is QLC and the second non-volatile memory device 112 is SLC, four bits are stored in one QLC and four SLCs. The controller 300 can generate addresses by taking this into account.

[0098] As shown in the figure, the first non-volatile memory device 111 and the second non-volatile memory device 112 can be incorporated into a single device 101, but the embodiment is not limited to this. The input / output driver 121 can simultaneously program data to the first non-volatile memory device 111 and the second non-volatile memory device 112. Alternatively, in some embodiments, the first non-volatile memory device 111 and the second non-volatile memory device 112 can be physically separated from each other.

[0099] Figure 11 This is a block diagram of a storage device according to an embodiment.

[0100] Reference Figure 11 The storage device 1300 can be used in the data processing system 1000, and the storage device 1300 is connected to the host 1200 and communicates with each other through the interface 1500.

[0101] According to an embodiment, the data processing system 1000 may be implemented as a personal computer (PC), desktop computer, laptop computer, workstation computer, or mobile computing device.

[0102] Mobile computing devices can be implemented as mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital cameras, digital video cameras, portable multimedia players (PMPs), multimedia devices, personal or portable navigation devices (PNDs), handheld game consoles, mobile internet devices (MIDs), wearable devices (or wearable computers), Internet of Things (IoT) devices, Internet of Everything (IoE) devices, or e-books.

[0103] Interface 1500 may be implemented as (but is not limited to) a Serial Advanced Technology Accessory (SATA) interface, a Fast SATA (SATAe) interface, a Serial Small Computer System Interface (SCSI), a Fast Peripheral Component Interconnect (PCIe) interface, a Fast Non-Volatile Memory (NVMe) interface, an Advanced Host Controller Interface (AHCI), a NAND flash memory, or a Multimedia Card (MMC) interface. According to embodiments, interface 1500 may transmit electrical or optical signals.

[0104] The host 1200 can control the data processing operations (e.g., write operations (or programming operations) or read operations) of the storage device 1300 through the interface 1500. For example, the host 1200 can be a host controller.

[0105] According to an embodiment, the host 1200 may be implemented as an integrated circuit (IC), a motherboard, an application processor (AP), a mobile AP, or a system-on-a-chip (SoC).

[0106] The central processing unit (CPU) 1220 and the host interface (I / F) 1230 can exchange commands and / or data with each other through the bus structure 1210.

[0107] The bus architecture 1210 can be implemented as (but is not limited to) Advanced Microcontroller Bus Architecture (AMBA), Advanced High Performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced Extensible Interface (AXI), Advanced System Bus (ASB), or a combination thereof.

[0108] CPU 1220 can generate write requests for controlling write operations on storage device 1300 or read requests for controlling read operations on storage device 1300. A write request may include a write address, and a read request may include a read address. For example, CPU 1220 may include one or more cores. A request may refer to a command.

[0109] Host interface 1230 can change the format of commands and / or data to be transmitted to storage device 1300, and transmit the changed commands and / or data to storage device 1300 via interface 1500. Additionally, host interface 1230 can change the format of responses and / or data received from storage device 1300, and transmit the changed responses and / or data to CPU 1220 via bus structure 1210. According to an embodiment, host interface 1230 may include a transceiver capable of sending and receiving commands and / or data. The structure and operation of host interface 1230 can be suitably implemented for the structure and operation of interface 1500.

[0110] Storage device 1300 may include controller 1310 and non-volatile memory (NVMs) 1400. According to an embodiment, storage device 1300 may also include buffer 1380.

[0111] Storage device 1300 can correspond to the above reference. Figures 1 to 10 The storage device described in the embodiment. The storage device 1300 can store data output from the host 1200 to the non-volatile memory 1400 under the control of the controller 1310.

[0112] Storage device 1300 can be implemented as (but is not limited to) a flash memory-based memory device. For example, storage device 1300 can be implemented as (but is not limited to) a smart card, a secure digital card (SD card), a multimedia card (MMC), an embedded MMC (eMMC), an embedded multi-chip package (eMCP), a page perfect NAND (PPN), universal flash memory (UFS), a universal serial bus (USB) flash drive, a solid-state drive (SSD), or an embedded SSD (eSSD).

[0113] The controller 1310 can control the exchange of commands and / or data between the host 1200 and the non-volatile memory 1400. According to embodiments, the controller 1310 can be implemented as an IC or a SoC. The controller 1310 may include a bus structure 1320, a device interface (I / F) 1330, a processor 1340, internal memory 1350, a memory controller 1360, and a buffer manager 1370.

[0114] The bus structure 1320 can be implemented as (but is not limited to) AMBA, AHB, APB, AXI, ASB or a combination thereof.

[0115] Device interface 1330 can modify the format of responses and / or data to be transmitted to host 1200, and transmit the modified responses and / or data to host 1200 via interface 1500. Additionally, device interface 1330 can receive commands and / or data transmitted from host 1200, modify the format of received commands and / or data, and transmit the modified commands and / or data to processor 1340 and / or buffer manager 1370. According to an embodiment, device interface 1330 may include a transceiver capable of transmitting and receiving signals and / or data. The structure and operation of device interface 1320 can be suitably implemented for the structure and operation of interface 1500.

[0116] Processor 1340 can control device interface 1330, internal memory 1350, memory controller 1360, and buffer manager 1370 via bus structure 1320. Processor 1340 can execute firmware (or computer program) that can control the operation of storage device 1300. According to an embodiment, controller 1310 may include a processor for processing commands and / or data output from host 1200 and a processor for controlling access operations (e.g., write operations, read operations, and / or erase operations) to non-volatile memory 1400.

[0117] Internal memory 1350 may store data for the operation of controller 1310 or data generated by data processing operations (e.g., write operations or read operations) performed by controller 1310. According to embodiments, internal memory 1350 may be implemented as random access memory (RAM), DRAM, SRAM, buffer, buffer memory, cache, or tight-packed memory (TCM).

[0118] Internal memory 1350 may store at least one flash translation layer (FTL) loaded from non-volatile memory 1400. The FTL may instruct firmware for performing address mapping, wear leveling, and / or garbage collection, wherein address mapping is used to map logical addresses output from host 1200 to physical addresses in non-volatile memory 1400.

[0119] The memory controller 1360 can control data processing operations (e.g., write operations, read operations, and / or erase operations) performed on the non-volatile memory 1400 under the control of the processor 1340. For example, when the non-volatile memory 1400 is implemented as flash memory, the memory controller 1360 can function as a flash memory controller. The memory controller 1360 and the non-volatile memory 1400 can exchange control signals and / or data through channels.

[0120] The memory controller 1360 can control garbage collection performed on data blocks included in the non-volatile memory 1400. According to an embodiment, the memory controller 1360 can manage mapping table information about the data blocks to be garbage collected.

[0121] According to an embodiment, the memory controller 1360 may support SATA interface, SATAe interface, SAS, PCIe interface, NVMe interface, AHCI, MMC interface, NAND flash memory interface, or NOR flash memory interface.

[0122] The buffer manager 1370 can write data to or read data from the buffer 1380. According to embodiments, the buffer 1380 can be implemented as RAM, SRAM, or DRAM.

[0123] Buffer 1380 may store a mapping table for logical address-to-physical address translation of non-volatile memory 1400 and a bitmap of mapping table information for each data block included in non-volatile memory 1400. The bitmap may include mapping table numbers and index information for the corresponding data blocks. The mapping table and bitmap may be updated by FTL.

[0124] Buffer 1380 can also be used as a cache, temporarily storing write data to be transferred to non-volatile memory 1400.

[0125] Here, the controller 1310 and the buffer 1380 can correspond to those described above. Figures 1 to 10 The embodiment includes a controller 300 and a buffer memory 400.

[0126] According to an embodiment, when the controller 1310 and the buffer 1380 are implemented as different semiconductor chips, the controller 1310 and the buffer 1380 can be implemented as a package, such as a stacked package (PoP), a multi-chip package (MCP), or a system-on-a-package (SiP).

[0127] The non-volatile memory 1400 can store an operating system (OS), various programs, and various data. Each of the non-volatile memories 1400 may include at least one array of memory cells. Each of the non-volatile memories 1400 may be implemented as a semiconductor chip or a semiconductor package. At least one panel may be arranged (or formed) between the memory controller 1360 and the non-volatile memory 1400. Channels may include transmission lines for transmitting commands and / or data. According to an embodiment, the non-volatile memory 1400 may be implemented as A channels × B paths. Here, A and B may each be a natural number of 1 or greater.

[0128] Here, one or more of the non-volatile memories 1400 can correspond to those referenced above. Figures 1 to 10 The first non-volatile memory device 100 and the second non-volatile memory device 200 of the described embodiments.

[0129] Although exemplary embodiments have been discussed with reference to the accompanying drawings, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the embodiments. Therefore, it should be understood that the above embodiments are illustrative in all respects only and not restrictive, the scope of which is defined by the appended claims.

Claims

1. A storage device, comprising: First non-volatile memory device; The second non-volatile memory device has a different type from the first non-volatile memory device; as well as The data line is shared by the first non-volatile memory device and the second non-volatile memory device. Specifically, the first data is simultaneously provided to both the first non-volatile memory device and the second non-volatile memory device via the data line. Write the first data to the second non-volatile memory device, and The first data is reprogrammed into the first non-volatile memory device by reading the first data from the second non-volatile memory device and providing the read first data to the first non-volatile memory device. Wherein, the first data is initially programmed into the first non-volatile memory device before being reprogrammed into the first non-volatile memory device, wherein the initial programming period of the first non-volatile memory device at least partially overlaps with the write period of the second non-volatile memory device. If the verification result indicates that the initial programming of the first data into the first non-volatile memory device has failed, then the first data is reprogrammed into the first non-volatile memory device.

2. The storage device according to claim 1, further comprising a buffer memory, wherein, The first data occupies a first area of ​​the buffer memory, and the occupation of the first area by the first data ends after the first data is provided to both the first non-volatile memory device and the second non-volatile memory device.

3. The storage device according to claim 2, wherein, The occupation of the first region by the first data ends before the first data is written to the second non-volatile memory device.

4. The storage device according to claim 1, wherein, The first non-volatile memory device is a NAND flash memory device capable of storing three bits or more.

5. The storage device according to claim 1, wherein, During the initial programming and reprogramming processes, the first data is programmed into a memory cell connected to the Nth word line, and Between the initial programming and the reprogramming, programming is also performed on the memory cell connected to the (N+1)th word line or the (N-1)th word line, where N is a natural number greater than 2.

6. The storage device according to claim 1, wherein, In a first time segment, a programming command and a first address are provided to the first non-volatile memory device; in a second time segment different from the first time segment, a write command and a second address are provided to the second non-volatile memory device; and in a third time segment following the first and second time segments, the first data is simultaneously provided to both the first and second non-volatile memory devices.

7. The storage device according to claim 6, wherein, After the third time interval, the first data is initially programmed into the first non-volatile memory device and written to the second non-volatile memory device, and The initial programming period of the first non-volatile memory device and the write period of the second non-volatile memory device overlap at least partially.

8. The storage device according to claim 6, wherein, In a fourth time segment following the third time segment, a programming command and a third address are provided to the first non-volatile memory device. In a fifth time segment different from the fourth time segment, a write command and a fourth address are provided to the second non-volatile memory device. In a sixth time segment following the fourth and fifth time segments, second data is provided to both the first and second non-volatile memory devices simultaneously. The first address corresponds to either an odd-numbered or even-numbered memory block in the first non-volatile memory device, and the third address corresponds to either the odd-numbered or even-numbered memory block in the first non-volatile memory device.

9. The storage device according to claim 8, wherein, After the sixth time segment, the first data is initially programmed into one of the odd-numbered memory blocks or the even-numbered memory blocks in the first non-volatile memory device, the second data is initially programmed into the other of the odd-numbered memory blocks or the even-numbered memory blocks in the first non-volatile memory device, and the first data and the second data are written to the second non-volatile memory device, wherein the initial programming period of the first non-volatile memory device and the writing period of the second non-volatile memory device at least partially overlap.

10. The storage device according to claim 1, wherein, The second non-volatile memory device has a faster read speed than the first non-volatile memory device.

11. The storage device according to claim 1, wherein, The first non-volatile memory device is a NAND flash memory device, and the second non-volatile memory device is a phase-change memory device.

12. The storage device according to claim 1, wherein, The first non-volatile memory device is a NAND flash memory device capable of storing n bits, and the second non-volatile memory device is a NAND flash memory device capable of storing m bits, where n is a natural number of 2 or greater, and m is a natural number less than n.

13. A storage device, comprising: NAND flash memory devices; Phase-change memory devices; as well as The data line is shared by the NAND flash memory device and the phase-change memory device. Specifically, the first data is simultaneously provided to the NAND flash memory device and the phase-change memory device via the data line, and the first data is initially programmed into the NAND flash memory device and simultaneously written into the phase-change memory device. The initial programming period of the NAND flash memory device and the write period of the phase-change memory device at least partially overlap. If the verification result indicates that the initial programming has failed, the first data is reprogrammed into the NAND flash memory device by reading the first data from the phase-change memory device and providing the read first data to the NAND flash memory device.

14. The storage device according to claim 13, wherein, The NAND flash memory device is capable of storing three or more bits, and after initial programming, the first data is reprogrammed into the NAND flash memory device by reading the first data from the phase change memory device and providing the read first data to the NAND flash memory device.

15. The storage device according to claim 14, wherein, During the initial programming and reprogramming processes, the first data is programmed into a memory cell connected to the Nth word line, and Between the initial programming and reprogramming, programming is also performed on the memory cells connected to the (N+1)th word line or the (N-1)th word line, where N is a natural number greater than 2.

16. The storage device according to claim 13, wherein, In a first time segment, programming commands and a first address are provided to the NAND flash memory device. In a second time segment, which is different from the first time segment, write commands and a second address are provided to the phase-change memory device. In a third time segment, which follows the first and second time segments, the first data is provided to both the NAND flash memory device and the phase-change memory device.

17. A storage device, comprising: First non-volatile memory device; The second non-volatile memory device has a different type from the first non-volatile memory device; The data line is shared by the first non-volatile memory device and the second non-volatile memory device; as well as Buffer memory, The first data occupies the first area of ​​the buffer memory. After the first data in the buffer memory is simultaneously provided to the first non-volatile memory device and the second non-volatile memory device through the data line, the occupation of the first area by the first data ends, and... Specifically, while initially programming the first data into the first non-volatile memory device, the first data is also written into the second non-volatile memory device, and... If the verification result indicates that the initial programming has failed, the first data is reprogrammed into the first non-volatile memory device by reading the first data from the second non-volatile memory device and providing the read first data to the first non-volatile memory device.

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