Method of operating a memory controller, storage device and method of operating the same

Abstract

An operating method of a memory controller is provided. The operating method includes receiving first read data and second conversion information, the second conversion information including data obtained by converting second read data based on a linear operation, and the first read data and the second read data including data read from a same memory cell; converting the first read data based on the linear operation to generate first conversion information; performing a logical operation on the first conversion information and the second conversion information to generate operation information; performing an inverse operation of the linear operation on the operation information to generate reliability information; and correcting an error of the first read data based on the first read data and the reliability information.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0098568, filed on August 13, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The methods and apparatus consistent with the embodiments relate to methods of operating a memory controller, storage devices, and methods of operating the same. Background Technology

[0003] Even when power is cut off, flash memory, as a non-volatile memory, can retain the stored data. Recently, storage devices using flash memory, including embedded multimedia cards (eMMC), universal flash storage (UFS), solid-state drives (SSDs), and memory cards, have become widely used. Such storage devices facilitate the storage or movement of large amounts of data.

[0004] If a non-volatile memory device (such as NAND flash memory) is repeatedly programmed and erased, the threshold voltage dispersion may shift due to the degradation of the memory cell characteristics, or adjacent threshold voltage dispersions may overlap. Therefore, the read data may contain several erroneous bits.

[0005] To correct erroneous bits, NAND flash memory devices can use both hard-decision decoding and soft-decision decoding. While hard-decision decoding is more efficient due to its lower resource usage, its error correction capability may be lower than that of soft-decision decoding. On the other hand, although soft-decision decoding has a higher error correction capability than hard-decision decoding, it uses more resources.

[0006] If hard-decision decoding fails, NAND flash memory devices can use soft-decision decoding. However, the drawback of this approach is the increased decoding latency. Summary of the Invention

[0007] One or more embodiments provide a method of operating a memory controller that has high error correction capability while using fewer resources.

[0008] One or more embodiments provide a storage device that has high error correction capabilities while using fewer resources.

[0009] One or more embodiments provide a method of operating a storage device that has high error correction capability while using fewer resources.

[0010] However, the embodiments are not limited to those set forth herein. The above and other embodiments will become more apparent to those skilled in the art from the detailed description given below.

[0011] According to one aspect of the embodiments, an operation method of a memory controller includes: receiving first read data and second conversion information, the second conversion information including data obtained by converting the second read data based on a linear operation, and the first read data and the second read data including data read from the same memory cell; converting the first read data based on a linear operation to generate first conversion information; performing logical operations on the first conversion information and the second conversion information to generate operational information; performing the inverse operation of the linear operation on the operational information to generate reliability information; and correcting errors in the first read data based on the first read data and the reliability information.

[0012] According to another aspect of the embodiments, a method of operating a memory controller includes: receiving first read data and a second corrector, the second corrector including data obtained by transforming the second read data, and the first read data and the second read data including hard-decision read data read from the same memory cell; transforming the first read data to generate a first corrector; performing an XOR or XNOR operation on the first corrector and the second corrector to generate a new corrector; performing the Berlekamp-Masley algorithm and Chien search on the new corrector to generate reliability information; and correcting errors in the first read data based on the first read data and the reliability information.

[0013] According to another aspect of the embodiments, a storage device includes: a memory device configured to read first read data and second read data from the same memory cell, convert the second read data based on a linear operation to generate second conversion information, and output the first read data and second conversion information; and a memory controller configured to receive the first read data and second conversion information, convert the first read data based on a linear operation to generate first conversion information, perform logical operations on the first conversion information and second conversion information to generate operational information, perform the inverse operation of the linear operation on the operational information to generate reliability information, and correct errors in the first read data based on the first read data and the reliability information.

[0014] According to one aspect of the embodiments, a method of operating a storage device including a memory device and a memory controller includes: reading a plurality of memory cells by the memory device to generate first read data; reading a plurality of memory cells by the memory device to generate second read data; dividing the second read data into a plurality of second sub-read data by the memory device; transforming each of the plurality of second sub-read data by the memory device based on a linear operation to generate a plurality of second sub-transformation information; and outputting the first read data and the plurality of second sub-transformation information by the memory device.

[0015] Other features and embodiments may be apparent from the following detailed description, drawings and claims. Attached Figure Description

[0016] The above and other aspects and features will become more apparent from the following detailed description with reference to the accompanying drawings, in which:

[0017] Figure 1 This is a block diagram illustrating a storage device according to some embodiments;

[0018] Figure 2 It is used for explanation Figure 1 An exemplary block diagram of a memory device;

[0019] Figure 3 It is used for explanation Figure 2 An exemplary circuit diagram of a memory cell array;

[0020] Figure 4 This is a diagram illustrating the threshold voltage distribution and hard-decision read operation of a degraded memory cell;

[0021] Figure 5 This is a block diagram illustrating the operation of a memory device in a storage device according to an embodiment;

[0022] Figure 6 This is a block diagram illustrating the operation of a memory controller in a storage device according to an embodiment;

[0023] Figure 7 This is another block diagram illustrating the operation of a memory device in a storage device according to another embodiment;

[0024] Figure 8 This is a diagram used to illustrate an example of a compensator generator;

[0025] Figure 9 This is another block diagram illustrating the operation of a memory controller in a storage device according to another embodiment;

[0026] Figure 10 This is a diagram used to illustrate the relationship between the new corrector and reliability information;

[0027] Figure 11 This is another block diagram illustrating the operation of a memory device in a storage device according to another embodiment;

[0028] Figure 12 This is another block diagram illustrating the operation of a memory controller in a storage device according to another embodiment; and

[0029] Figure 13 This is a perspective view used to illustrate a memory device used in a storage device according to some embodiments. Detailed Implementation

[0030] Various embodiments will be described below with reference to the accompanying drawings. Expressions such as “at least one of…” modify the entire list of elements when following it, without modifying any individual elements. For example, the expression “at least one of a, b, and c” should be understood to include: only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0031] Figure 1 This is a block diagram illustrating a storage device according to some embodiments.

[0032] The storage device according to some embodiments includes a memory device 100 and a memory controller 200.

[0033] Storage devices can be implemented as, but are not limited to, smart cards, secure digital (SD) cards, multimedia cards (MMC), embedded MMC (eMMC), embedded multi-chip package (eMCP), page perfect NAND (PPN), universal flash storage (UFS), USB flash drives, solid-state drives (SSD), or embedded SSDs (eSSD).

[0034] The memory device 100 may be, for example, but not limited to, a device based on non-volatile memory (e.g., flash memory).

[0035] The memory controller 200 typically controls the operation of the memory device 100. The memory controller 200 interprets commands provided from the host and can control the operation of the memory device 100, such as programming, reading, erasing, etc., depending on the interpretation results.

[0036] The memory controller 200 internally includes an error correction code (ECC) circuit 210. The ECC circuit 210 performs an encoding operation on data provided from the host to generate parity bits. The data (including the parity bits) is provided to the memory device 100 and programmed into the memory device 100.

[0037] The ECC circuit 210 also receives data (including parity bits) and additional information read from the memory device 100, performs decoding operations, and performs error correction operations. (See below for further details.) Figures 5 to 12 Detailed description and additional information (see reference) Figure 5 CHDR2, Figure 7 SYD2, etc.

[0038] Figure 2 It is used for explanation Figure 1 An exemplary block diagram of a memory device. Figure 3 It is used for explanation Figure 2 An exemplary circuit diagram of a memory cell array. It will be described based on a NAND flash memory device. Figure 2 and Figure 3 However, the embodiments are not limited to this.

[0039] refer to Figure 2 The memory device 100 includes a memory cell array 110 and an access circuit 112.

[0040] The memory cell array 110 can be a two-dimensional memory cell array or a three-dimensional memory cell array. Reference will be made here. Figure 3 The three-dimensional memory cell array is described exemplarily.

[0041] In this three-dimensional memory cell array, the array of memory cells can be formed monolithically within one or more physical levels and can include circuitry related to the operation of the memory cells. The term "monolithically" means that each layer of the array is directly deposited on top of the layer of each underlying level of the array. The three-dimensional memory cell array may include vertical NAND strings that are vertically oriented such that at least one memory cell is positioned above other memory cells. At least one memory cell may include a charge trapping layer.

[0042] refer to Figure 3 Unit strings NS11 to NS41 are provided in the first line BL. <1> Between the common source line CSL and the second bit line BL. Unit strings NS12 to NS42 are provided on the second bit line BL. <2> Between the common source line CSL and the unit string NS14 to NS44, provided on the fourth bit line BL. <4> Between and the common source line CSL.

[0043] The string select transistor SST of each cell string NS is connected to the corresponding bit line BL. The ground select transistor GST of each cell string NS is connected to the common source line CSL. Memory cells MC1 to MC7 are provided between the string select transistor SST and the ground select transistor GST of each cell string NS.

[0044] The rows and columns of the unit string NS are defined as follows.

[0045] A string of cells NS connected together to a single bit line forms a single column. For example, connected to the first bit line BL <1> The unit strings NS11 to NS41 correspond to the first column. Connected to the second bit line BL. <2> The cell strings NS12 to NS42 correspond to the second column. Connected to the fourth bit line BL. <4> The unit strings NS14 to NS44 correspond to the fourth column.

[0046] Unit strings NS connected to a single string select line SSL form a single row. For example, connected to the first string select line SSL <1> The unit strings NS11 to NS14 form the first row. Connect to the second string of select lines SSL. <2> The unit strings NS21 to NS24 form the second row. Connect to the fourth string select line SSL. <4> The unit strings NS41 to NS44 form the fourth row.

[0047] Each cell string NS includes a ground select transistor GST. The ground select transistor GST can be controlled via a single ground select line GSL. Alternatively, cell strings corresponding to each row can be controlled via different ground select lines. For example, the ground select transistor of each of the cell strings NS11, NS12, and NS14 corresponding to the first row can be connected to the first ground select line GSL1. Furthermore, the ground select transistor of each of the cell strings NS21, NS22, and NS24 corresponding to the second row can be connected to the second ground select line GSL2. The ground select transistor of each of the cell strings NS41, NS42, and NS44 corresponding to the fourth row can be connected to the fourth ground select line GSL4.

[0048] Memory cells corresponding to the same semiconductor layer share a word line WL <0> To WL <6> .

[0049] Strings NS on the same row share the same select line SSL. Strings NS on different rows are connected to different select lines SSL. <1> SSL <2> and SSL <4> In the following text, the first string select transistor SST1 is defined as connected to the first string select line SSL. <1> The first string select transistor is SST. The second string select transistor SST2 is defined as being connected to the second string select line SSL. <2> The fourth string select transistor, SST, is defined as being connected to the fourth string select line, SSL. <4> The string selection transistor SST.

[0050] The common source line CSL is connected to the cell string NS.

[0051] The first memory cell array 110 may include multiple memory cell blocks BLKi. A single memory cell block BLKi may be divided into multiple string units sharing a single string select line SSL. That is, the memory cell block BLKi may be divided into sub-blocks SB that include multiple unit strings sharing a single string.

[0052] Three-dimensional memory cell arrays can be implemented through wafer stacking, chip stacking, or cell stacking.

[0053] Refer again Figure 2 The access circuit 112 may include a voltage generator 140, a row decoder 150, control logic 160, a column decoder 170, a page buffer and a sense amplifier block 120, a Y-gating circuit 130, an I / O block 180, etc.

[0054] Control logic 160 controls the overall operation of access circuitry 112 according to commands (CMD) provided from memory controller 200. For example, control logic 160 can sense memory read status information during a memory read operation and can control the provision of read data to memory controller 200.

[0055] Voltage generator 140 can generate the voltages required for access operations based on control codes generated by control logic 160. Voltage generator 140 generates programming and programming verification voltages required for programming operations, read voltages required for read operations, and erase and erase verification voltages required for erase operations. Additionally, voltage generator 140 provides the voltages required for each operation to line decoder 150.

[0056] Under the control of the control logic 160, the column decoder 170 decodes the column address YADD and provides multiple selection signals to the Y strobe circuit 130.

[0057] Page buffer and sense amplifier block 120 includes multiple page buffers. Each of the multiple page buffers is connected to each of the multiple bit lines.

[0058] Each of the multiple page buffers can operate as a driver under the control of control logic 160 to temporarily store data read from memory cell array 110 during data read operations. Furthermore, each of the multiple page buffers can operate as a detection amplifier under the control of control logic 160, capable of detecting and amplifying the corresponding voltage levels of multiple bit lines during read operations.

[0059] Y-gating circuit 130 can control the transmission of data DATA between page buffer and sense amplifier block 120 and I / O block 180 in response to multiple selection signals provided by column decoder 170.

[0060] I / O block 180 can send data DATA from external input to Y-gating circuit 130, or send data DATA output from Y-gating circuit 130 to memory controller 200 via multiple I / O pins (or data bus).

[0061] Figure 4 This is a diagram illustrating the threshold voltage distribution and hard-decision read operations of degraded memory cells.

[0062] First, a hard-decision read operation refers to a normal data read operation. Specifically, when a read voltage is supplied to the word line of a memory cell, the data stored in the memory cell is read as either 1 or 0, depending on the on / off state of the corresponding memory cell. A soft-decision read operation refers to information formation, where multiple read voltages (i.e., soft-decision read voltages) with a certain voltage difference are applied to the memory cell based on the read voltage used for hard decision (i.e., hard-decision read voltage) to increase the reliability of the hard-decision read data. Hard-decision read operations are also called hard-decision decoding, and soft-decision read operations are also called soft-decision decoding.

[0063] refer to Figure 4 The diagram illustrates two threshold voltage dispersions, LD and RD. Although only two threshold voltage dispersions, LD and RD, are shown based on the case of storing one bit in a memory cell, this is an example and the embodiments are not limited thereto. For example, when storing q bits (here, q is a natural number of 2 or greater) in a memory cell, 2q threshold voltage dispersions can be formed. In other words, in the case of storing two or more bits in a multilevel cell (MLC), three-level cell (TLC), and four-level cell (QLC), four, eight, and sixteen threshold voltage dispersions can be formed, respectively.

[0064] When properly programmed, the two adjacent threshold voltages, LD and RD, are sufficiently separated from each other to allow them to be clearly distinguished by hard-decision read voltages (e.g., VR1).

[0065] However, charge loss can occur, where electrons trapped on the tunnel oxide (or floating gate) are emitted over time. Furthermore, with repeated programming and erasing operations, the tunnel oxide degrades and charge loss may increase further. Charge loss can lower the threshold voltage, and, for example, threshold voltage dispersion may shift to one side. Moreover, programming perturbations, erasing perturbations, back pattern dependency, etc., can increase threshold voltage dispersion. For the above reasons, the characteristics of non-volatile memory cells may degrade. As a result, such as Figure 4 As shown, adjacent threshold voltage dispersions LD and RD can overlap with each other.

[0066] If the threshold voltages LD and RD overlap in this way, errors may be included in the read data when a read is performed using a specific hard-decision read voltage (e.g., VR1).

[0067] The memory cell corresponding to the threshold voltage dispersion LD should be read as 1, and the memory cell corresponding to the threshold voltage dispersion RD should be read as 0. However, if a specific hard-decision read voltage (e.g., VR1) is used to perform the read, the memory cell corresponding to region A may be read as 0 instead of 1, and the memory cell corresponding to region B may be read as 1 instead of 0. That is, an error may occur.

[0068] In the following text, we will use Figures 5 to 12 Describe in detail the methods used for error correction.

[0069] Figure 5 This is a block diagram illustrating the operation of a memory device in a storage device according to an embodiment.

[0070] refer to Figure 5 The memory device 100 may include a linear arithmetic unit 190. The memory device 100 reads the same memory cell twice to generate read data HDR1 and HDR2. The memory device 100 uses a first read voltage (see...). Figure 4 The memory device 100 reads multiple memory cells to generate first read data HDR1. Additionally, the memory device 100 uses a second read voltage (see VR1). Figure 4 VR2) reads multiple memory cells to generate second read data HDR2. Here, the first read voltage VR1 and the second read voltage VR2 may be the same or different. The first read data HDR1 and the second read data HDR2 may be hard-decision read data obtained through a hard-decision read operation. Although Figure 5 An example with only two reads is shown, but the implementation is not limited to this.

[0071] That is, the first read data HDR1 and the second read data HDR2 can be data read at the same read voltage (threshold voltage). Alternatively, the first read data HDR1 and the second read data HDR2 can be data read at preset different threshold voltages. Alternatively, the first read data HDR1 and the second read data HDR2 can be data adaptively set and read at different threshold voltages depending on the state of the NAND flash memory device (e.g., program-erase cycle, time, temperature, etc.).

[0072] Subsequently, the second read data HDR2 is converted into second conversion information CHDR2 by the first linear arithmetic unit 190.

[0073] The first linear arithmetic unit 190 performs a compression operation that reduces the size of the second read data HDR2. For example, the first linear arithmetic unit 190 may perform the compression operation based on linear operations. The first linear arithmetic unit 190 may be configured, for example, using only XOR or only XNOR.

[0074] Here, if the first linear arithmetic unit 190 is represented by the function F, then CHDR2 = F(HDR2) is established.

[0075] The size of the first read data HDR1 is N bits (where N is a natural number of 2 or greater), and the size of the second read data HDR2 is also N bits. Each N-bit read data (HDR1, HDR2) includes n bits of data (where n is a natural number) corresponding to the above data and w bits of parity bits (where w is a natural number less than n). The size of the second conversion information CHDR2 converted by the first linear arithmetic unit 190 is M bits (where M is a natural number less than N). For example, the size of the second conversion information CHDR2 can be 10% or less of the size of the second read data HDR2. More specifically, if the second read data HDR2 is 256 bits, then the second conversion information CHDR2 can be 25 bits.

[0076] The memory device 100 outputs the first read data HDR1 and the second conversion information CHDR2 to the memory controller 200.

[0077] Figure 5 The operation of the memory device 100 can be summarized as generating / outputting HDR1+CHDR2 (=HDR1+F(HDR2)).

[0078] Figure 6This is a block diagram illustrating the operation of a memory controller in a storage device according to an embodiment. For example, the memory controller 200 may include a second linear arithmetic unit 290, an arithmetic unit 292, an inverse linear arithmetic unit 294, and a decoder 298 (e.g., a low-density parity-check (LDPC) decoder).

[0079] refer to Figure 6 The memory controller 200 receives first read data HDR1 and second conversion information CHDR2 from the memory device 100.

[0080] Subsequently, the first read data HDR1 is converted into first conversion information CHDR1 using the second linear arithmetic unit 290. Here, the first linear arithmetic unit used to generate the second conversion information CHDR2 (see...) Figure 5 The first linear operator (190) and the second linear operator (290) used to generate the first conversion information CHDR1 are of the same type. The second linear operator (290) performs a compression operation that reduces the size of the first read data HDR1, but performs the compression operation based on linear operations. The second linear operator (290) can be configured, for example, only by XOR or only by XNOR. If the second linear operator (290) is represented by a function F, then CHDR1 = F(HDR1) is established.

[0081] Therefore, the size of the first read data HDR1 is N bits (where N is a natural number of 2 or greater), and the size of the first conversion information CHDR1 converted by the second linear arithmetic unit 290 is M bits (where M is a natural number less than N). For example, the size of the first conversion information CHDR1 can be 10% or less of the size of the first read data HDR1. If the first read data HDR1 is 256 bits, then the first conversion information CHDR1 can be 25 bits.

[0082] Arithmetic unit 292 performs logical operations on the first transformation information CHDR1 and the second transformation information CHDR2 to generate the operation information CXDR1. The logical operation may include an XOR operation or an XNOR operation. For example, the action of arithmetic unit 292 can be summarized as CXDR1 = CHDR1 + CHDR2 = F(HDR1) + F(HDR2) (where + represents modulo 2 addition, i.e., the logical operation XOR). As mentioned above, the first linear arithmetic unit 190 and the second linear arithmetic unit 290 are of the same type and perform linear operations. Therefore, F(HDR1) + F(HDR2) = F(HDR1 + HDR2) is established. This is because F(A) + F(B) = F(A + B) is established for the linear operation function F.

[0083] Subsequently, the inverse linear arithmetic unit 294 converts the computation information CXDR1 into reliability information WRB. The reliability information WRB indicates the location of errors in the first read data HDR1. The inverse linear arithmetic unit 294 performs the inverse operations of the linear arithmetic units 190 and 290 described above. That is, the operation of the inverse linear arithmetic unit 294 can be summarized as: WRB = F -1 (CXDR1)=F -1 (CHDR1 + CHDR2) = F -1 (F(HDR1+HDR2)) = HDR1+HDR2. As a result, the reliability information WRB becomes HDR1+HDR2. The reliability information WRB is an N-bit string with the same size as the first read data HDR1 and the second read data HDR2.

[0084] The decoder 298 performs actions to correct errors in the first read data HDR1 based on the first read data HDR1 and the reliability information WRB.

[0085] For example, the first read data HDR1 is 1111111, and the second read data HDR2 is 1111110. Because the first read data HDR1 and the second read data HDR2 are different even though they were read from the same memory cell, it can be known that there is an error in either the first read data HDR1 or the second read data HDR2. Since the calculated reliability information WRB is an XOR operation of the first read data HDR1 and the second read data HDR2, the calculated reliability information WRB is 000001. Because the last bit in the reliability information WRB is 1, the decoder 298 can know that the last bit of the first read data HDR1 is different from the last bit of the second read data.

[0086] The memory controller 200 can check whether error correction of the first read data HDR1 can be performed based on the operation information CXDR1. When the operation information CXDR1 is a preset specific value, the memory controller 200 can determine that error correction is impossible.

[0087] If the memory controller 200 determines that error correction is impossible, it ignores the generated reliability information WRB and processes the first read data HDR1 according to a preset method. The preset method is, for example, not correcting the first read data HDR1 under the assumption that there are no errors in the first read data HDR1 (i.e., error-free case). Alternatively, the preset method is to correct the first read data HDR1 under the assumption that errors have occurred in all bits of the first read data HDR1 (i.e., all-error case). Alternatively, if the memory controller 200 determines that error correction is impossible after more than a preset number of references, the number of bits in the first transition information CHDR1 and the second transition information CHDR2 can be increased. This is because if the number of bits in the first transition information CHDR1 and the second transition information CHDR2 increases, the number of error bits can be increased.

[0088] refer to Figure 5 and Figure 6 The memory device 100 outputs first read data HDR1 and second conversion information CHDR2 (i.e., compressed data of the second read data HDR2). If the memory device 100 outputs the second read data HDR2 without compression, both the first read data HDR1 and the second read data HDR2 need to be output. Therefore, it takes twice as long as it does when only the first read data HDR1 is output. However, in the memory device according to some embodiments, the second conversion information CHDR2 is compressed to approximately 1 / 10 of the second read data HDR2. Therefore, outputting the first read data HDR1 and the second conversion information CHDR2 takes approximately 1.1 times longer than outputting only the first read data HDR1.

[0089] If the memory device 100 generates and outputs XOR operation information (i.e., HDR1 + HDR2) of the first read data HDR1 and the second read data HDR2, the miniaturization / integration of the memory device 100 is hindered because the XOR operator needs to be formed within the memory device 100. Furthermore, if the first / second read data HDR1 and HDR2 are N bits, the XOR operation information is also N bits. Therefore, outputting both the first read data HDR1 and the XOR operation information takes twice as long as outputting only the first read data HDR1.

[0090] In a storage device according to some embodiments, the memory device 100 outputs only the first read data HDR1 and the second conversion information CHDR2, and for this purpose, only the first linear arithmetic unit 190 (e.g., a compressor) can be formed in the memory device 100. For example, although the first linear arithmetic unit 190 can be mounted in the page buffer and the sense amplifier block (see... Figure 2In (120), but the embodiments are not limited thereto. Therefore, there is no obstacle to the miniaturization / integration of the memory device 100. Furthermore, since the output compressed data (i.e., the second conversion information CHDR2), the data transfer time is not significantly increased.

[0091] Furthermore, the reliability information WRB is generated by the memory controller 200, not the memory device 100. That is, the memory controller 200 includes an arithmetic unit 292 (e.g., XOR operation) and an inverse linear arithmetic unit 294, and generates the reliability information WRB. Because the memory controller 200 has more space than the memory device 100, such an additional module can be installed.

[0092] Linear arithmetic units 190 and 290 perform linear operations, enabling the generation of reliability information WRB in memory controller 200. This is because F(HDR1) + F(HDR2) becomes identical to F(HDR1 + HDR2), where F(HDR1) + F(HDR2) is the value obtained by XORing CHDR2 (= F(HDR2)) generated by memory device 100 and CHDR1 (= F(HDR1)) generated by memory controller 200. This is because F(A) + F(B) = F(A + B) is established only for linear arithmetic functions F. If F is not a linear arithmetic function, then F... -1 (CHDR1+CHDR2) only becomes F -1 (F(HDR1)+F(HDR2)). Since F is a linear operation function, we can obtain F. -1 (CHDR1 + CHDR2) = F -1 (F(HDR1)+F(HDR2))=F -1 (F(HDR1+HDR2))=HDR1+HDR2.

[0093] As shown in Table 1 below, the effects of the storage device according to some embodiments are summarized. In the case of hard-decision decoding, although the number of reads is one and the data output time is short, the error correction capability is poor. In the case of soft-decision decoding, although the error correction capability is good, the number of reads is at least three, and the data output time is at least twice that of hard-decision decoding. As described above, the storage device according to some embodiments has good error correction capability, and the number of reads and the data output time are shorter than those of soft-decision decoding.

[0094] [Table 1]

[0095]

[0096] In the following text, reference will be made to Figures 7 to 10An embodiment related to BCH decoding is described. Specifically, a syndrome former is used as an example of a first linear arithmetic unit 190 and a second linear arithmetic unit 290.

[0097] Figure 7 This is another block diagram illustrating the operation of a memory device in a storage device according to another embodiment. Figure 8 This is a diagram used to illustrate an example of the corrector generator 190a. Figure 9 This is another block diagram illustrating the operation of a memory controller in a storage device according to another embodiment. Figure 10 This is a diagram used to illustrate the relationship between the new corrector and reliability information. For ease of explanation, the main descriptions and references will be provided. Figure 5 and Figure 6 The descriptions are different.

[0098] exist Figures 7 to 10 The BCH decoding used can correct 100% of errors below a certain number, depending on the number of parity bits. Specifically, when the data size (i.e., the field size) is 2... m When the parity bit count is -1, if the number of parity bits is equal to or greater than m×t (where m and t are natural numbers), the maximum number of errors that can be corrected with 100% accuracy is t. That is, the values ​​of parameters m and t indicate whether error correction can be performed during BCH decoding. Extended BCH decoding is an extension of BCH decoding. When the data size is 2... m When the number of parity bits is equal to or greater than m×t+1, the maximum number of errors that can be 100% corrected is t. In the case of BCH extended decoding, in 256 (=2 8 If the parity bit in the data is 25 bits (=8×3+1) bits, then all three errors can be completely corrected. In the following text, BCH decoding also includes BCH extended decoding.

[0099] BCH decoding involves three steps: the comparator operation, the Berlekamp Massey (BM) algorithm, and the Chien Search.

[0100] refer to Figure 7 The memory device 100 includes a corrector formor 190a. The memory device 100 reads the same memory cell twice to generate read data HDR1 and HDR2. The first read data HDR1 and the second read data HDR2 can be hard-decision read data obtained through a hard-decision read operation.

[0101] The second read data HDR2 is converted into a second corrector SYD2 by the first corrector formulator 190a. Subsequently, the memory device 100 outputs the first read data HDR1 and the second corrector SYD2 to the memory controller 200. If the first corrector formulator 190a is represented by a function S, then SYD2 = S(HDR2) is obtained, and the memory device 100 generates / outputs HDR1 + SYD2 ( = HDR1 + S(HDR2)).

[0102] The first corrector generator 190a multiplies the second read data HDR2 by the parity check matrix to generate the second corrector SYD2. As described above, the second read data HDR2 is a codeword and includes n data bits and w parity bits. If the second read data HDR2 is multiplied by the parity check matrix, a w-bit second corrector SYD2 is generated. That is, the size of the second corrector SYD2 can be the same as the size of the parity bits, but is not limited to this.

[0103] The first corrector generator 190a corresponds to the linear arithmetic unit (see...). Figure 5 (190), and can be configured solely by linear operations XOR or XNOR.

[0104] refer to Figure 8 The first corrector generator 190a can be configured using only an XOR operation. The first corrector generator 190a will convert 256 (= 2 8 The second read data HDR2 of 100 bits is converted into a second corrector SYD2 of 25 bits (=8×3+1). For example, as shown in [Table 2], the first corrector generator 190a can be represented by an XOR operation on some input values.

[0105] [Table 2]

[0106] Output value Relationship with input value (XOR operation) s0_0 d0_0+d0_230+d0_232+d0_234…d0_255 s0_1 d0_1+d0_230+d0_233…+d0_254+ … … s0_24 d0_24+d0_231+d0_233+d0_252

[0107] refer to Figure 9 The memory controller 200 includes a corrector former 290a, an arithmetic unit 292a, a BCH decoder 294, and a decoder 298 (e.g., an LDPC decoder). The memory controller 200 receives first read data HDR1 and a second corrector SYD2 from the memory device 100.

[0108] Next, the first read data HDR1 is transformed using the second corrector formor 290a to generate the first corrector SYD1. A linear arithmetic unit is used to generate the second corrector SYD2 (see [link to linear arithmetic unit]). Figure 7 The second corrector generator 290a, used to generate the first corrector SYD1, is of the same type as 190a. If the second corrector generator 290a is represented by a function S, then SYD1 = S(HDR1) is established.

[0109] Subsequently, arithmetic unit 292a performs logical operations (e.g., XOR or XNOR operations) on the first corrector SYD1 and the second corrector SYD2 to generate a new corrector CXDR2. That is, CXDR2 = SYD1 + SYD2 = S(HDR1) + S(HDR2). Furthermore, because corrector formulators 190a and 290a perform linear operations, S(HDR1) + S(HDR2) = S(HDR1 + HDR2) is established. In the example above, because the first corrector SYD1 and the second corrector SYD2 are 25 bits and the logical operation is a logical XOR operation, CXDR2 is also 25 bits.

[0110] Subsequently, the inverse operator 294a runs the BM algorithm and Chien search, transforms the new corrector CXDR2, and generates the reliability information WRB. The BM algorithm and Chien search correspond to the inverse operation of the corrector unit in BCH decoding. That is, the actions of the BM algorithm and Chien search can be summarized as: WRB = S -1 (CXDR2)=S -1 (SYD1+SYD2)=S -1 (S(HDR1+HDR2)=HDR1+HDR2. As a result, the reliability information WRB is HDR1+HDR2. The reliability information WRB is 256 bits and has the same size as the first read data HDR1 and the second read data HDR2.)

[0111] The decoder 298 performs actions to correct errors in the first read data HDR1 based on the first read data HDR1 and the reliability information WRB.

[0112] The following will describe and reference Figures 7 to 9 Examples related to the description are provided below. The following is an example of BCH decoding with parameters m=3 and t=1.

[0113] Assume the first read data HDR1 and the second read data HDR2 are 7 (=2) 3 -1) A 7-bit codeword. In a 7-bit codeword, 4 bits are data and 3 bits (=3×1) are parity bits. That is, the first read data HDR1 and the second read data HDR2 are 1×7 vectors.

[0114] Each of the first calibrator 190a and the second calibrator 290a is a 7×3 matrix.

[0115] The first corrector SYD1 is obtained by multiplying the first read data HDR1 by the first corrector formor 190a. The second corrector SYD2 is obtained by multiplying the second read data HDR2 by the second corrector formor 290a. Therefore, the first corrector SYD1 and the second corrector SYD2 are 1×3 vectors.

[0116] Since the new corrector CXDR2 is the result of the operation of the first corrector SYD1 and the second corrector SYD2, it is a 1×3 vector.

[0117] When the BM algorithm and Chien search are run for the new corrector CXDR2, the reliability information WRB of the 1×7 vector is generated again.

[0118] As mentioned above, when m=3 and t=1, that is, if the data size is 7 (=2) 3 -1) bits and the number of parity bits is 3 (=3×1) bits, so that when there is an error in the data, the error can be corrected 100%. This is because, as in Figure 10 As outlined in the document, the new corrector CXDR2 and the reliability information WRB are matched one-to-one.

[0119] For example, when the new corrector CXDR2 is 000, the reliability information WRB is 0000000, which means that the first read data HDR1 and the second read data HDR2 are exactly the same. That is, there are no error bits in the first read data HDR1.

[0120] When the new corrector CXDR2 is 001, the reliability information WRB is 0000001, which means that the last bit of the first read data HDR1 is different from the last bit of the second read data HDR2. Therefore, the decoder 298 can correct the last bit of the first read data HDR1.

[0121] Similarly, when the new corrector CXDR2 is 111, the reliability information WRB is 1000000, which means that the first bit of the first read data HDR1 is different from the first bit of the second read data HDR2. Therefore, the decoder 298 can correct the first bit of the first read data HDR1.

[0122] If the first 7-bit read data HDR1 has two or more bits of error, error correction is not possible. A parameter transformation (m or t) is required to correct the error.

[0123] Specifically, the memory controller 200 can check whether error correction of the first read data HDR1 is possible based on the new corrector CXDR2.

[0124] If the memory controller 200 determines that error correction is impossible, it ignores the generated reliability information WRB and can process the first read data HDR1 according to a preset method. The preset method is, for example, not correcting the first read data HDR1 under the assumption that there are no errors in it. Alternatively, the preset method is correcting the first read data HDR1 under the assumption that errors have occurred in all bits of it.

[0125] Alternatively, if the memory controller 200 determines that error correction is impossible after exceeding a preset number of references, the parameter (m or t) can be switched. That is, the parameter (m or t) can be switched in the direction of increasing the number of bits in the first corrector SYD1 and the second corrector SYD2. As mentioned above, since the number of bits in the first corrector SYD1 and the second corrector SYD2 is the same as the parity bits, it can be represented by m×t. Therefore, by changing the parameter (m or t), the number of bits in the first corrector SYD1 and the second corrector SYD2 can be increased.

[0126] Figure 11 This is another block diagram illustrating the operation of a memory device in a storage device according to another embodiment. Figure 12 This is another block diagram illustrating the operation of a memory controller in a storage device according to another embodiment. For ease of explanation, the description will primarily focus on usage. Figures 5 to 10 The differences in the explanations.

[0127] The first / second read data HDR1 and HDR2, which need to be compressed (converted), do not require ECC circuitry in the storage device (see [link]). Figure 1 The format matching used in 210). That is, the ECC circuit 210 of the NAND flash memory-based storage device receives inputs of very long (i.e., very large) data and corrects errors. Therefore, no matter how simple the linear arithmetic unit (or corrector formor) is, it may be difficult to achieve the same results in the memory device 100 (i.e., the page buffer and sense amplifier (see 210)). Figure 2 Implemented in 120).

[0128] refer to Figure 11 The same memory cell is read to generate first read data HDR1 and second read data HDR2. Here, the memory cell can be, but is not limited to, a NAND flash memory cell. As shown, the memory device 100 may include a plurality of first corrector formors 190a1 to 190ak.

[0129] The second read data HDR2 is divided into multiple second sub-read data HDR20 to HDR2k. For example, each of the second sub-read data HDR20 to HDR2k can be 256 bits.

[0130] Each of the multiple second sub-read data HDR20 to HDR2k can be converted / generated into multiple second sub-correctors SYD20 to SYD2k using multiple first corrector formulators 190a1 to 190ak. For example, each of the second sub-correctors SYD20 to SYD2k can be 25 bits. As mentioned above, the size of each second sub-corrector SYD20 to SYD2k can be approximately 10% of the size of the corresponding second sub-read data HDR20 to HDR2k. In the case of BCH decoding, the number of errors that can be corrected can be determined depending on the parameter values ​​(i.e., the values ​​of m and t). For example, in the case of BCH extended decoding, if in 256 (= 2 8 With 25 (8 × 3 + 1) parity bits in 256-bit data, three errors can be completely corrected. Typically, the probability of an error in a NAND flash memory device is between 0.1% and 1%. In the case of 256-bit data, approximately three or fewer errors occur. Therefore, if 25 parity bits are present in 256-bit data, most errors can be corrected.

[0131] The memory device 100 outputs the first read data HDR1 and a plurality of second sub-correctors SYD20 to SYD2k to the memory controller 200.

[0132] refer to Figure 12 The memory controller 200 can receive first read data HDR1 and multiple second sub-correctors SYD20 to SYD2k.

[0133] Subsequently, the first read data HDR1 was divided into multiple first sub-read data HDR10 to HDR1k.

[0134] Subsequently, each of the multiple first sub-read data HDR10 to HDR1k is transformed using multiple second corrector generators 290a1 to 290ak to generate multiple first sub-correctors SYD10 to SYD1k.

[0135] Subsequently, multiple arithmetic units 292a1 to 292ak are used to perform logical operations (e.g., XOR operations) on multiple corresponding first sub-correctors SYD10 to SYD1k and second sub-correctors SYD20 to SYD2k to generate multiple new sub-correctors CXDR21 to CXDR2k.

[0136] Subsequently, each of the multiple sub-correctors CXDR21 to CXDR2k is transformed by multiple inverse operators 294al to 294ak to generate multiple sub-reliability information WRB0 to WRBk. Each of the multiple sub-reliability information WRB0 to WRBk can be the result of an XOR operation on the corresponding first sub-read data HDR10 to HDR1k and second sub-read data HDR20 to HDR2k.

[0137] Subsequently, decoder 298 can correct errors in the first read data HDR1 based on multiple first sub-read data HDR10 to HDR1k and multiple sub-reliability information WRB0 to WRBk.

[0138] For reference Figure 11 and Figure 12 As described, the memory controller 200 performs the partitioning of first read data HDR1 into a plurality of first sub-read data HDR10 to HDR1k. However, the embodiments are not limited thereto. That is, the memory device 100 may partition the first read data HDR1 into a plurality of first sub-read data HDR10 to HDR1k, and the plurality of second sub-correctors SYD20 to SYD2k corresponding to the plurality of first sub-read data HDR10 to HDR1k may also be output together.

[0139] Furthermore, despite Figure 11 and Figure 12 The first corrector generators 190a1 to 190ak, the first sub-correctors SYD10 to SYD1k, the second corrector generators 290a1 to 290ak, the second sub-correctors SYD20 to SYD2k, and the sub-new correctors CXDR21 to CXDR2k are described, but these can be described by changing them to the first linear arithmetic unit, the first sub-transformation information, the second linear arithmetic unit, the second sub-transformation information, and the sub-operation information, respectively.

[0140] Figure 13 This is a perspective view used to illustrate a memory device 100 used in a storage device according to some embodiments.

[0141] refer to Figure 13 A direction substantially perpendicular to the upper surface of the base 11 is defined as the first direction, and two directions intersecting each other and parallel to the upper surface of the base are defined as the second direction and the third direction, respectively. For example, the second direction and the third direction may intersect each other substantially perpendicularly.

[0142] The memory device 100 includes a peripheral circuit region PCR in which peripheral circuitry is formed, a memory cell region MCR in which an array of memory cells is formed, and an I / O pad PAD.

[0143] The peripheral circuit region PCR may include a semiconductor substrate 11, peripheral circuitry formed on the upper surface of the semiconductor substrate 11, and a lower insulating film 12 covering the peripheral circuitry. The memory cell region MCR may include a base layer 13 formed on the upper surface of the lower insulating film 12, a memory cell array formed on the upper surface of the base layer 13, and an upper insulating film 14 covering the memory cell array. I / O pads PAD are formed on the lower surface 11 of the semiconductor substrate. The I / O pads PAD may be formed to overlap a portion of the memory cell array (i.e., a portion of the memory cell region MCR) in the vertical direction. As described later, the I / O pads PAD may be formed to cover the through-silicon vias formed in the peripheral circuit region PCR.

[0144] The memory device 100 employs a Cell on Peripheral (COP) structure, wherein peripheral circuitry is formed on a semiconductor substrate 11, and an array of memory cells is stacked on the peripheral circuitry. Therefore, the size of the memory device 100 can be reduced.

[0145] In some embodiments, a linear arithmetic unit needs to be additionally formed in the memory device 100 (see [link]). Figure 5 190), syndrome former ( Figure 7 190a, and Figure 11 (e.g., 190a1 to 190ak). If the memory device 100 adopts a COP structure, then due to the increase in the memory cell region MCR in the peripheral circuit region PCR, there is sufficient space to form the aforementioned linear arithmetic unit and corrector generator.

[0146] According to an exemplary embodiment, such as Figure 1 , Figure 2 , Figures 5-9 , Figure 11 and Figure 12At least one of the controllers, circuits, generators, decoders, buffers, control logic, arithmetic units, corrector generators, blocks, components, elements, modules, or units shown as blocks can be embodied in various numbers of hardware, software, and / or firmware structures that perform the functions described above. For example, at least one of these circuits, generators, decoders, buffers, control logic, arithmetic units, corrector generators, blocks, components, elements, modules, or units can use a direct circuit structure, such as a memory, processor, logic circuit, lookup table, etc., that can operate the corresponding function under the control of one or more microprocessors or other control devices. Moreover, at least one of these components, elements, modules, or units can be embodied in a portion of a module, program, or code containing one or more operable instructions for performing a specified logical function, and operated by one or more microprocessors or other control devices. Furthermore, at least one of these components, elements, modules, or units can further include, or be implemented therein, a processor, microprocessor, etc., such as a central processing unit (CPU) that performs the corresponding function. Two or more of these components, elements, modules, or units can be combined into a single component, element, module, or unit that performs all the operations or functions of the combined two or more components, elements, modules, or units. Furthermore, at least a portion of the functionality of at least one of these components, elements, modules, or units can be performed by another of these components, elements, modules, or units. Additionally, although a bus is not shown in the above block diagrams, communication between components, elements, modules, or units can be performed via a bus. The functional aspects of the above exemplary embodiments can be implemented using algorithms running on one or more processors. Furthermore, the components, elements, modules, or units represented by blocks or processing steps can employ any number of related techniques for electronic configuration, signal processing and / or control, data processing, etc.

[0147] In closing this detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without departing substantially from the principles.

Claims

1. A method of operating a memory device including a memory device and a memory controller, comprising: receiving, by the memory controller, first read data and second syndrome information from the memory device, the second syndrome information including data obtained by converting second read data based on a linear operation, and the first read data and the second read data including data read from a same memory cell of the memory device; converting, by the memory controller, the first read data based on a linear operation to generate first syndrome information; performing, by the memory controller, a logical operation on the first syndrome information and the second syndrome information to generate operation information; performing, by the memory controller, an inverse operation of the linear operation on the operation information to generate reliability information; and correcting, by the memory controller, an error of the first read data based on the first read data and the reliability information. the first read data includes N bits, and the first syndrome information includes M bits, 2. The operating method of a storage device according to claim 1, wherein, wherein the second read data includes N bits, and the second syndrome information includes M bits, wherein N is a natural number of 2 or more, and wherein M is a natural number smaller than N. M is equal to or smaller than 10% of N.

3. The operating method of a storage device according to claim 2, wherein, the first read data and the second read data are hard decision read data.

4. The operating method of a storage device according to claim 1, wherein, identifying, by the memory controller, whether to perform error correction of the first read data according to the reliability information based on the operation information, 5. The operating method of a storage device according to claim 1, further comprising: wherein correcting the error of the first read data includes processing, by the memory controller, the first read data based on identifying not to perform the error correction according to the reliability information; processing, by the memory controller, the first read data based on the reliability information based on identifying to perform the error correction according to the reliability information. the linear operation includes only XOR or only XNOR.

6. The operating method of a storage device according to claim 1, wherein, the linear operation is performed by a syndrome former.

7. The operating method of a storage device according to claim 1, wherein, the inverse operation includes performing a Berlekamp Massey algorithm and performing a Chien search.

8. The operating method of a storage device according to claim 7, wherein, the memory cell is a NAND flash memory cell, and 9. The operating method of a storage device according to claim 1, wherein, the first read data includes 256 bits, and the first syndrome information includes 25 bits. the logical operation includes an XOR operation or an XNOR operation.

10. The operating method of a storage device according to claim 1, wherein, the first read data and the second read data are read from the same memory cell with a same threshold voltage.

11. The operating method of a storage device according to claim 1, wherein, the first read data and the second read data are read from the same memory cell with different threshold voltages.

12. The operating method of a storage device according to claim 1, wherein, 13. A method of operating a memory controller, comprising: receiving first read data and second syndrome, the second syndrome including data obtained by converting second read data, and the first read data and the second read data including hard decision read data read from a same memory cell; converting the first read data to generate first syndrome; performing an XOR or XNOR operation on the first syndrome and the second syndrome to generate a new syndrome; performing a Berlekamp Massey algorithm and a Chien search on the new syndrome to generate reliability information; and ​ correcting errors of the first read data based on the first read data and the reliability information.

14. The method of operating a memory controller of claim 13, wherein, a first compression size of the first syndromer is equal to or less than 10% of a first size of the first read data, and wherein a second compression size of the second syndromer is equal to or less than 10% of a second size of the second read data.

15. The method of operating a memory controller of claim 13, further comprising: identifying whether to perform error correction of the first read data based on the new syndromer, wherein correcting errors of the first read data comprises, based on identifying not to perform error correction, ignoring the reliability information and processing the first read data according to a preset manner.

16. The method of operating a memory controller of claim 15, further comprising: in response to identifying not to perform error correction according to a preset reference number, increasing a bit number of the first syndromer and the second syndromer.

17. A storage device, comprising: a memory device configured to read first read data and second read data from a same memory cell, convert the second read data based on a linear operation to generate second conversion information, and output the first read data and the second conversion information; and a memory controller configured to receive the first read data and the second conversion information, convert the first read data based on a linear operation to generate first conversion information, perform a logical operation on the first conversion information and the second conversion information to generate operation information, perform an inverse operation of the linear operation on the operation information to generate reliability information, and correct errors of the first read data based on the first read data and the reliability information.

18. The storage device of claim 17, wherein, the memory device has a cell-on-periphery (COP) structure.

19. The storage device of claim 17, wherein, the first read data comprises N bits, and the first conversion information comprises M bits, wherein the second read data comprises N bits, and the second conversion information comprises M bits, wherein N is a natural number of 2 or more, and wherein M is a natural number less than N.

Images