Integrated multi-path power amplifier with interdigital transistors

Abstract

A multipath amplifier (e.g., a Dougherty amplifier) ​​includes: a first amplifier input, a second amplifier input, and an amplifier output, the first amplifier input, the second amplifier input, and the amplifier output being integrally formed with a semiconductor die; and at least two amplifier units positioned adjacent to each other between the amplifier input and the amplifier output. Each amplifier unit includes a first transistor and a second transistor integrally formed with the semiconductor die, wherein the first transistor and the second transistor each include a transistor input and a transistor output. The first transistor input is coupled to the first amplifier input, and the second transistor input is coupled to the second amplifier input. A combination node is coupled to the second transistor output and to the amplifier output, and a first phase-shifting element is electrically connected between the first transistor output and the combination node.

Description

Technical Field

[0001] The embodiments of the subject matter described herein generally relate to power amplifiers having multiple sub-amplifiers, and more specifically to Dougherty power amplifiers having a carrier amplifier and a peaking amplifier as well as an output combination circuit. Background Technology

[0002] For many years, the Dougherty power amplifier has been one of the most popular amplifiers for cellular infrastructure applications. A bidirectional Dougherty amplifier comprises two sub-amplifiers (i.e., a carrier amplifier and a peaking amplifier) ​​connected in parallel between the amplifier input and output. During operation, the input radio frequency (RF) signal is split into a carrier signal and a peaking signal, and a 90-degree phase difference is applied between the carrier and peaking signals before amplification by the carrier and peaking amplifiers. On the output side, one of the amplified carrier or peaking signals is then transmitted through an n×90-degree transmission line (n = 1, 2, ...), while the other amplified carrier or peaking signal is transmitted through an (n-1)×90-degree transmission line, and then the amplified signals are combined together by a signal combiner. This enables active load pulling of the carrier and peaking amplifiers.

[0003] In some typical Dougherty amplifier configurations, the carrier amplifier and peaking amplifier are implemented on two separate semiconductor dies (i.e., one die for the carrier amplifier and another for the peaking amplifier), which are mounted on a package substrate or printed circuit board (PCB). For example, each of the carrier amplifier and peaking amplifier can be implemented using multi-finger field-effect transistors, and within each die, the amplified signal generated by each transistor finger is combined at an output bonding pad. Wire bonding arrays are typically used to transfer the amplified carrier signal and peaking signal from the output bonding pad to output leads or to conductive structures on the package substrate or PCB. In a 90-0 Dougherty amplifier configuration, the amplified carrier signal or amplified peaking signal is conducted through a conductor (e.g., a transmission line) with an electrical length of 90 degrees (e.g., a quarter-wavelength transmission line) before signal combination. Similarly, in a 90-180 Dougherty amplifier configuration, before the combined signals, the amplified carrier signal or the amplified peaked signal is conducted through a transmission line with an electrical length of 90 degrees, and another of the amplified carrier signal or the amplified peaked signal is conducted through a conductor (e.g., a transmission line) with an electrical length of 180 degrees (e.g., a half-wavelength transmission line).

[0004] The number of transistor fingers used in each of the carrier amplifier and peaking amplifier is proportional to the desired output power level. Therefore, more transistor fingers are used for higher power amplifiers, which necessitates the use of relatively long output bonding pads to interconnect the transistor finger outputs in such amplifiers. Unfortunately, at higher frequencies (e.g., in the gigahertz (GHz) range), the distribution characteristics of the output bonding pads used to combine numerous transistor fingers can lead to significant and undesirable signal power losses. More specifically, as the wavelength of the amplified RF signal approaches the physical size of the transistor block, relatively large phase differences can arise between the signals at the edge fingers of each amplifier in the amplifier. Large phase differences can lead to significant signal power losses, which in turn can translate into relatively poor power gain efficiency at the circuit level. Therefore, there is a need for more energy-efficient Dougherty amplifier designs capable of supporting amplification at high frequencies with relatively low losses. Summary of the Invention

[0005] According to one aspect of the present invention, a multipath amplifier is provided, comprising:

[0006] Semiconductor die;

[0007] A first amplifier input terminal, a second amplifier input terminal, and an amplifier output terminal are integrally formed with the semiconductor die; and

[0008] At least two amplifier units are positioned between the amplifier input and the amplifier output, wherein the at least two amplifier units are positioned adjacent to each other, and each of the at least two amplifier units comprises:

[0009] A first transistor is integrally formed with the semiconductor die, wherein the first transistor has a first transistor input and a first transistor output, wherein the first transistor input is coupled to the input of the first amplifier;

[0010] The second transistor is integrally formed with the semiconductor die, wherein the second transistor has a second transistor input and a second transistor output, wherein the second transistor input is coupled to the input of the second amplifier;

[0011] A combination node, the combination node being coupled to the output of the second transistor and coupled to the output of the amplifier; and

[0012] A first phase shift element is electrically connected between the output of the first transistor and the combined node.

[0013] According to one or more embodiments, the first phase-shifting element includes:

[0014] A first inductor, wherein a first end of the first inductor is coupled to the output of the first transistor, and a second end of the first inductor is coupled to the combined node.

[0015] According to one or more embodiments, the first inductor is a spiral inductor integrally formed with the semiconductor die.

[0016] According to one or more embodiments, the first inductor is a discrete inductor coupled to the top surface of the semiconductor die.

[0017] According to one or more embodiments, the inductance value of the first inductor is in the range of 0.1 nanohenries to 20 nanohenries.

[0018] According to one or more embodiments, the first transistor is a first field-effect transistor including a first drain region, a first source region, and a first gate terminal, wherein a first drain-source capacitance exists between the first drain region and the first source region, the first gate terminal is coupled to the input of the first transistor, and the first drain region is coupled to the output of the first transistor.

[0019] The second transistor is a second field-effect transistor including a second drain region, a second source region, and a second gate terminal, wherein a second drain-source capacitance exists between the second drain region and the second source region, the second gate terminal is coupled to the input of the second transistor, and the second drain region is coupled to the output of the second transistor.

[0020] The first drain-source capacitor, the second drain-source capacitor, and the first inductor cause a 90-degree phase delay, which is imparted to the radio frequency signal transmitted between the first drain region and the combined node.

[0021] According to one or more embodiments, the first transistor is a first field-effect transistor including first transistor fingers, the first transistor fingers including an elongated first drain region, an elongated first source region, and an elongated first gate terminal, wherein the first gate terminal is coupled to the first transistor input, and the first drain region is coupled to the first transistor output; and

[0022] The second transistor is a second field-effect transistor including a second transistor finger, the second transistor finger including an elongated second drain region, an elongated second source region and an elongated second gate terminal, wherein the second gate terminal is coupled to the input of the second transistor and the second drain region is coupled to the output of the second transistor.

[0023] According to one or more embodiments, the first length of the first transistor finger is shorter than the second length of the second transistor finger.

[0024] According to one or more embodiments, the first transistor finger and the second transistor finger have input ends aligned along a first line perpendicular to the first length of the first transistor finger and the second length of the second transistor finger, the second transistor finger has an output end aligned along a second line perpendicular to the first length of the first transistor finger and the second length of the second transistor finger, and the first phase shift element is positioned between the output end of the first transistor finger and the second line.

[0025] According to one or more embodiments, the first length of the first transistor finger is substantially equal to the second length of the second transistor finger.

[0026] According to one or more embodiments, the first transistor finger and the second transistor finger are directly adjacent to each other.

[0027] According to one or more embodiments, the multipath amplifier is a Dougherty power amplifier, the first transistor finger is a carrier finger, and the second transistor finger is a peaking finger.

[0028] According to one or more embodiments, the multipath amplifier is a Dougherty power amplifier, the first transistor finger is a peaking finger, and the second transistor finger is a carrier finger.

[0029] According to one or more embodiments, each amplifier unit is an asymmetric amplifier unit.

[0030] According to one or more embodiments, each amplifier unit is a symmetrical amplifier unit.

[0031] According to one or more embodiments, the at least two amplifier units include two to fifty amplifier units.

[0032] According to one or more embodiments, each amplifier unit further includes:

[0033] A third transistor, integrally formed with the semiconductor die, wherein the third transistor has a third transistor input and a third transistor output, wherein the third transistor input is coupled to the input of a third amplifier; and

[0034] A second phase-shifting element is electrically connected between the output of the third transistor and a node located between the output of the first transistor and the first phase-shifting element.

[0035] According to one or more embodiments, it further includes:

[0036] One or more electromagnetic isolation features are located between the first transistor and the second transistor.

[0037] According to one or more embodiments, it further includes:

[0038] One or more electromagnetic isolation features are located between adjacent amplifier units in the at least two amplifier units.

[0039] According to a second aspect of the present invention, an amplifier is provided, comprising:

[0040] Semiconductor die;

[0041] A first input signal manifold is located on the input side of the semiconductor die and is integrally formed with the semiconductor die.

[0042] The second input signal manifold is located at the input side of the semiconductor die and is integrally formed with the semiconductor die;

[0043] An output signal manifold, the output signal manifold being positioned on the output side of the semiconductor die and integrally formed with the semiconductor die; and

[0044] At least two amplifier units are positioned between the input side and the output side of the semiconductor die, wherein the at least two amplifier units are positioned adjacent to each other, and each of the at least two amplifier units includes:

[0045] A first transistor, which is integrally formed with the semiconductor die, wherein the first transistor has a first transistor input and a first transistor output, wherein the first transistor input is coupled to the input of a first amplifier;

[0046] A second transistor is integrally formed with the semiconductor die, wherein the second transistor has a second transistor input and a second transistor output, wherein the second transistor input is coupled to the input of a second amplifier;

[0047] A combination node, said combination node being coupled to the output of the second transistor and coupled to the output of the amplifier; and

[0048] A phase-shifting element is electrically connected between the output of the first transistor and the combined node.

[0049] According to one or more embodiments, the amplifier is a Dougherty power amplifier, the first transistor is a carrier amplifier or a peaking amplifier, and the second transistor is the other of the carrier amplifier or the peaking amplifier.

[0050] According to one or more embodiments, the first transistor is a first elongated field-effect transistor finger; the second transistor is a second elongated field-effect transistor finger; and the phase-shifting element is an inductor. Attached Figure Description

[0051] A more complete understanding of the subject matter can be derived by referring to the detailed embodiments and claims when considered in conjunction with the following figures, wherein similar reference numerals refer to similar elements throughout the figures.

[0052] Figure 1 This is a simplified schematic diagram of a Doherty power amplifier according to an example embodiment;

[0053] Figure 2 This is a schematic diagram of a Dougherty power amplifier with an interdigitated carrier subamplifier and a peaking subamplifier according to an example embodiment;

[0054] Figure 3 This is a top view of an asymmetric power amplifier integrated circuit (IC) having multiple asymmetric Dougherty cells, interdigitated carrier fingers, and interdigitated peaking fingers according to an example embodiment;

[0055] Figure 4 According to an example embodiment Figure 3 A side view of the cross section along line 4-4 of the Doherty element;

[0056] Figure 5 According to an example embodiment Figure 3 A side view of the cross section along line 5-5 of the Doherty element;

[0057] Figure 6 This is a top view of an asymmetric Dougherty unit according to another example embodiment;

[0058] Figure 7 This is a top view of an asymmetric Dougherty unit according to yet another example embodiment;

[0059] Figure 8 This is a top view of an asymmetric Dougherty unit according to another example embodiment;

[0060] Figure 9 This is a top view of a symmetrical Dougherty unit according to an example embodiment;

[0061] Figure 10 This is a top view of a symmetrical Dougherty unit according to another example embodiment;

[0062] Figure 11 This is a top view of a symmetrical Dougherty unit according to yet another example embodiment;

[0063] Figure 12 This is a top view of a three-way Dougherty unit according to another example embodiment;

[0064] Figure 13 This is a top view of an asymmetric power amplifier IC with a top source contact according to an example embodiment;

[0065] Figure 14 This is a top view of a Dougherty amplifier device packaged in a high-power package according to an example embodiment;

[0066] Figure 15 This is a top view of a packaged Dougherty amplifier device coupled to a printed circuit board substrate according to an example embodiment; and

[0067] Figure 16 This is a flowchart of a method for manufacturing a Dougherty power amplifier IC and a packaged Dougherty amplifier device according to an example embodiment. Detailed Implementation

[0068] Embodiments of the subject matter of this invention include a multipath amplifier (i.e., an amplifier having multiple amplifiers amplifying signals in parallel), the multipath amplifier having integrated and interdigitated first and second power transistor fingers, an integrated phase shifter, and an integrated signal combiner coupled to the outputs of the first and second power transistor fingers. In some embodiments, the multipath amplifier may be a Dougherty power amplifier. More specifically, some embodiments described below correspond to a Dougherty power amplifier with a “non-inverting” load network configuration (also referred to as a “non-inverting” Dougherty amplifier). Based on the description herein, those skilled in the art will understand that the embodiments described below can also be implemented in a Dougherty power amplifier with an “inverting” load network configuration (also referred to as an “inverting” Dougherty amplifier). Additionally, some embodiments of the Dougherty amplifier IC described and illustrated below correspond to a bidirectional Dougherty amplifier including a carrier amplifier and a peaking amplifier (each composed of multiple parallel-coupled transistor fingers). As will be explained in more detail later, other embodiments may include an “N-directional” Dougherty power amplifier, where N > 2, and where the number of peaking amplifiers is equal to N-1. Additionally, the embodiments described below can be implemented in multipath amplifiers other than Dougherty power amplifiers. Therefore, the scope of the subject matter of this invention is not limited to bidirectional non-inverting Dougherty power amplifiers, but is broad enough to cover inverting Dougherty power amplifiers, N-directional Dougherty amplifiers (where N > 2), and other types of multipath amplifiers.

[0069] As used herein and as will be described in detail later, a transistor “finger” (also referred to as a “sub-amplifier”) comprises an elongated (i.e., length significantly greater than width) transistor structure having multiple parallel-aligned doped semiconductor regions and contact regions. In some embodiments, the multipath amplifier may be a Dougherty power amplifier having multiple integrated, interdigitated pairs or groups of carrier power transistor fingers (also referred to as “carrier fingers” or “carrier sub-amplifiers”) and peaking power transistor fingers (also referred to as “peaking fingers” or “peaking sub-amplifiers”) and an integrated phase shifter (e.g., an inductor) located between the output of each carrier transistor or peaking transistor and the output combiner, all carrier finger outputs and peaking finger outputs being coupled to the output combiner.

[0070] In various embodiments, carrier fingers and peaking fingers, phase shifters, and output combiners are integrally and / or integrally formed with or within a single integrated circuit (IC) die (or semiconductor die). As used herein, the terms "integral" or "integratedly formed" mean integrated with or within a single semiconductor die. When a component is referred to herein as being "integratedly formed" with an IC or semiconductor die, this means that the component structure forms part of the die itself (e.g., the component is produced during the die manufacturing process and is physically positioned between the top and bottom surfaces of the die). For example, simply refer to... Figure 3 Transistor fingers 336 and 356, as well as inductor 380, are considered to be "integrated" with die 301. In contrast, when a component is described as being "integrated" with an IC or semiconductor die, this means that the component structure is "integrated" with the die, or that the component is attached to the die (e.g., mounted to the surface of the die). For example, simply refer to... Figure 6 As used in this document, inductor 680 is considered to be “integrated” with die 601 because terminals 682, 684 of inductor 680 are physically and electrically attached to bonding pads 683, 685 exposed on the surface of die 601.

[0071] As indicated above, embodiments of the Dougherty amplifier include an integrated or integrally formed output combiner coupled to the outputs of multiple carrier fingers and peaking fingers. In a non-inverting Dougherty amplifier embodiment, the output combiner is tightly electrically coupled to the output of the peaking finger (e.g., the intrinsic drain terminal), where "tightly electrically coupled" as used herein means directly connected or electrically coupled through one or more conductive features (e.g., one or more integrated conductive traces and / or one or more vias) forming a conductive path with negligible total resistance (e.g., less than about 100 milliohms) and no passive or active electrical components (e.g., discrete or integrated resistors, inductors, capacitors, or transistors). In an inverting Dougherty amplifier embodiment, the output combiner is tightly electrically coupled to the output of the carrier finger (e.g., the intrinsic drain terminal).

[0072] Because the output combiner can be implemented very close to one or more intrinsic drains of the peaked fingers, a 90-0 Dougherty amplifier can be implemented, wherein an approximately 90-degree phase shift is implemented between the drain regions of the carrier fingers and the drain regions of the peaked fingers, and no substantial phase shift is implemented between the drain regions of the peaked fingers and the output combiner. According to one embodiment, a 90-degree phase difference between the carrier finger output and the peaked finger output is provided by a circuit system having a CLC (capacitor-inductor-capacitor) topology. The CLC topology includes drain-source capacitors for the carrier and peaked fingers and a tightly controlled series inductor (e.g., ...) implemented between each carrier finger output and the output combiner. Figure 3 , 6 The inductors 380, 680, 780, 781, 880, 980, 1080, 1081, 1180, 1181, 1380, and 1381 are listed in sections 7-11 and 13. More specifically, the CLC topology is essentially a pi network with a first parallel capacitor (carrier finger drain-source capacitor), a second parallel capacitor (peaked finger drain-source capacitor), and an inductor coupled between the carrier drain terminal and the peaked drain terminal. In other words, the drain-source capacitors of the carrier fingers, the drain-source capacitors of the peaked fingers, and the inductor's inductance cause a 90-degree phase delay that is imparted to the RF signal transmitted between the drain region of the carrier fingers and the output combiner (or combination node).

[0073] The basic structure of the Dougherty power amplifier will now be described to enhance understanding of the rest of the instruction manual. Figure 1 This is a simplified schematic diagram of a bidirectional non-inverting Dougherty power amplifier 100 according to an example embodiment. The Dougherty amplifier 100 includes an input node 102, an output node 104, a power divider 110 (or distributor), a carrier amplification path 130, a peaking amplification path 150, an input phase shifter 182, an output phase shifter 180, and a combination node 170. A load 106 can be coupled to the combination node 170 (e.g., via an impedance transformer 190 and the output node 104) to receive an amplified RF signal from the amplifier 100.

[0074] The Dougherty power amplifier 100 is considered a "bidirectional" Dougherty power amplifier, comprising a carrier amplifier 136 and one or more peaking amplifiers 156. The carrier amplifier 136 provides amplification along a carrier amplification path 130, and the peaking amplifier 156 provides amplification along a peaking amplification path 150. In other embodiments, more than one peaking amplifier may be implemented in parallel with the first peaking amplifier 156 to produce an N-directional Dougherty power amplifier, where N > 2.

[0075] While the dimensions of the carrier amplifier 136 and the peaking amplifier 156 can be equal (e.g., a 1:1 peaking size ratio in a symmetrical Dougherty configuration), their dimensions can also be unequal (e.g., in various asymmetrical Dougherty configurations). In a symmetrical bidirectional Dougherty amplifier configuration, the size of the peaking power amplifier 156 is approximately the same as that of the carrier power amplifier 136, where "size" refers to the total transistor perimeter and / or current carrying capacity. Conversely, in an asymmetrical bidirectional Dougherty amplifier configuration, the size of the peaking power amplifier 156 is typically several times larger than that of the carrier power amplifier 136. For example, the size of the peaking power amplifier 156 can be twice the size of the carrier power amplifier 136, such that the current carrying capacity of the peaking power amplifier 156 is twice that of the carrier power amplifier 136. Asymmetrical carrier amplifier to peaking amplifier size ratios other than 1:2 can also be implemented.

[0076] Power divider 110 is configured to distribute the power of the input RF signal received at input node 102 into a carrier portion and a peaking portion of the input signal. The carrier input RF signal is provided to carrier amplification path 130 at power divider output 114, and the peaking input RF signal is provided to peaking amplification path 150 at power divider output 116. During low-power mode operation, where only carrier amplifier 136 supplies current to load 106, power divider 110 supplies input signal power only to carrier amplification path 130. During full-power mode operation, where both carrier amplifier 136 and peaking amplifier 156 supply current to load 106, power divider 110 distributes input signal power between amplification paths 130 and 150.

[0077] Power divider 110 can distribute the power of the input RF signal equally or unequally. For example, when the Dougherty amplifier 100 has an asymmetric Dougherty amplifier configuration where the size of the peaking amplifier 156 is approximately twice the size of the carrier amplifier 136 (i.e., the Dougherty amplifier 100 has an asymmetric configuration with a carrier-to-peaking size ratio of 1:2), power divider 110 can distribute power such that approximately one-third of the input signal power is provided to the carrier amplification path 130 and approximately two-thirds of the input signal power is provided to the peaking amplification path 150. In other words, with a carrier-to-peaking size ratio of 1:2, the size of the peaking amplifier 156 is approximately twice the size of the carrier amplifier 136, and power divider 110 is configured to produce a peaked input signal with a power approximately twice that of the carrier input signal power.

[0078] Alternatively, in a symmetrical Dougherty amplifier configuration (i.e., a carrier to peaking ratio of approximately 1:1), the power divider 110 can distribute power such that approximately half of the input signal power is provided to the carrier amplification path 130 at the power divider output 114, and approximately half of the input signal power is provided to the peaking amplification path 150 at the power divider output 116.

[0079] Essentially, power divider 110 distributes the input RF signal supplied at input node 102 and amplifies the distributed signal along carrier amplification path 130 and peaking amplification path 150, respectively. The amplified signals are then combined in phase at combining node 170. Importantly, the phase coherence between carrier amplification path 130 and peaking amplification path 150 is maintained across the band of interest (or operating band) to ensure that the amplified carrier signal and peaked signal arrive in phase at combining node 170, and thus ensure proper Dougherty amplifier operation. Figure 1 In the depicted Dougherty amplifier configuration (i.e., a non-inverted Dougherty configuration), an input phase shifter 182 is coupled between the power divider output 116 and the peaking amplifier 156. According to one embodiment, the input phase shifter 182 applies an approximately 90-degree phase delay to the peaked input signal before it is provided to the peaking amplifier 156. For example, the input phase shifter 182 may comprise a quarter-wavelength transmission line, a lumped element delay circuit, or another suitable type of delay element or circuit with an electrical length of approximately 90 degrees.

[0080] According to one embodiment, carrier amplifier 136 and peaking amplifier 156 are each single-stage amplifiers (i.e., amplifiers with a single amplification stage). In other embodiments, carrier amplifier 136 is a two-stage amplifier comprising a relatively low-power preamplifier (not shown) and a relatively high-power final stage amplifier (not shown) connected in a cascaded (or series) arrangement between the input and output of the carrier amplifier. In the cascaded carrier amplifier arrangement, the output of the preamplifier is electrically coupled to the input of the final stage amplifier. Similarly, peaking amplifier 156 may comprise a two-stage amplifier comprising a relatively low-power preamplifier (not shown) and a relatively high-power final stage amplifier (not shown) connected in a cascaded arrangement between the input and output of the peaking amplifier. In the cascaded peaking amplifier arrangement, the output of the preamplifier is electrically coupled to the input of the final stage amplifier. In other embodiments, each of carrier amplifier 136 and peaking amplifier 156 may comprise more than two cascaded coupled amplification stages. Input impedance matching networks 134, 154 (IMN) may be implemented at the input of each amplifier 136, 156. In each case, matching networks 134 and 154 can increase the circuit impedance in ascending order of the load impedance.

[0081] During operation of the Dougherty amplifier 100, the carrier amplifier 136 is biased to operate in Class AB mode or deep Class AB mode, and the peaking amplifier 156 is typically biased to operate in Class C mode. In some configurations, the peaking amplifier 156 may be biased to operate in Class B or deep Class B mode. For example, in one embodiment, one or more gate bias circuits (e.g., Figure 2 The bias circuits 220 and 222 are used to perform gate biasing of the carrier amplifier 136 and the peaking amplifier 156. When the power of the input signal at node 102 is below the turn-on threshold level of the peaking amplifier 156, amplifier 100 operates in a low-power mode, in which the carrier amplifier 136 is the only amplifier supplying current to the load 106. When the power of the input signal exceeds the threshold level of the peaking amplifier 156, amplifier 100 operates in a high-power mode, in which both the carrier amplifier 136 and the peaking amplifier 156 supply current to the load 106. In this mode, the peaking amplifier 156 provides active load modulation at the combined node 170, thereby allowing the current of the carrier amplifier 136 to continue to increase linearly.

[0082] The Dougherty amplifier 100 has a “non-inverting” load network configuration. In the non-inverting configuration, the input circuitry is configured such that the input signal supplied to the peaking amplifier 156 is delayed by 90 degrees relative to the input signal supplied to the carrier amplifier 136 at the center operating frequency fo of the amplifier 100. As described above, to ensure that the carrier input RF signal and the peaked input RF signal arrive at the carrier amplifier 136 and the peaking amplifier 156 with an approximately 90-degree phase difference, which is essential for proper Dougherty amplifier operation, the input phase shifter 182 applies an approximately 90-degree phase delay to the peaked input signal before it is supplied to the peaking amplifier 156.

[0083] To compensate for the 90-degree phase delay difference between the carrier amplification path 130 and the peaking amplification path 150 at the inputs of amplifiers 136 and 156 (i.e., to ensure that the amplified signal arrives in phase at the combination node 170), the output phase shifter 180 is configured to apply an approximately 90-degree phase delay to the signal between the output of the carrier amplifier 136 and the combination node 170. (The last sentence appears to be incomplete and possibly refers to a different topic.) Figure 2-13 In more detail, the output phase shifter 180 may include one or more inductive components (e.g., ...) coupled between the output of the carrier amplifier 136 and the combination node 170. Figure 2-13 Inductors 380 and 680). For example, such as combining Figure 2-13 In more detail, the output phase shifter 180 may include a combination of an integrated spiral inductor, a discrete inductor, a leaded joint, and an integrated transmission line.

[0084] Alternative embodiments of the Dougherty amplifier may have an “inverting” load network configuration. In this configuration, the amplifier is configured such that the input phase shifter delays the input signal supplied to the carrier amplifier 136 by approximately 90 degrees relative to the input signal supplied to the peaking amplifier 156 at the operating center frequency f0 of the amplifier 100, and the output phase shifter is configured to apply approximately 90-degree phase delay to the signal between the output of the peaking amplifier 156 and the combination node, without applying a significant delay to the signal between the output of the carrier amplifier 136 and the combination node.

[0085] The Dougherty amplifier 100 is "integrated," as the terminology used herein, because at least the carrier amplifier 136, peaking amplifier 156, phase shifter 180, and combination node 170 are integrated with or within a single IC die, as indicated by dashed box 101 (e.g., Figure 3 , 5 -13 die 301, 501, 601, 701, 801, 901, 1001, 1101, 1201, 1301). This die may be referred to herein as an "integrated Dougherty amplifier die". According to one embodiment, all or part of the input impedance matching networks 134, 154 may also be integrated with the same IC die 101 (e.g., Figure 3 , 5 Dies 301, 501, 601, 701, 801, 901, 1001, 1101, 1201, and 1301 (-13) are integrated or integrated within the same IC die 101. Additionally, the distributor 110 may be integrated with or within the same IC die 101. Alternatively, all or part of the distributor 110 and / or input impedance matching networks 134 and 154 may be implemented in one or more components different from the IC die including the carrier amplifier 136 and the peaking amplifier 156.

[0086] As mentioned above, each of the carrier amplifier 136 and the peaking amplifier 156 includes a plurality of transistor “fingers”. Essentially, each finger of the amplifier acts as a small sub-amplifier. The transistor fingers (or sub-amplifiers) for the carrier amplifier 136 (referred to herein as “carrier fingers”) are connected in parallel between the carrier amplifier input and the combination node 170, and the transistor fingers (or sub-amplifiers) for the peaking amplifier 156 (referred to herein as “peaking fingers”) are connected in parallel between the peaking amplifier input and the combination node. According to one embodiment, a phase delay element (corresponding to phase shifter 180) is coupled between the output (e.g., intrinsic drain) of each carrier finger and the combination node. According to another embodiment, the carrier fingers and peaking fingers are arranged in a cross-finger configuration (or interleaved) to form a plurality of “Dougherty amplifier units” that amplify the input RF signal in parallel. Figure 2 The circuit diagram illustrates this unique amplifier structure.

[0087] More specifically, Figure 2 This is a schematic diagram of a Dougherty power amplifier 200 having an interdigitated carrier subamplifier and a peaking subamplifier (or fingers) according to an example embodiment. The Dougherty amplifier 200 includes an input node 202 (e.g., Figure 1 Input node 101), output node 204 (e.g., Figure 1 Output node 104), power divider 210 (e.g., Figure 1 The power divider 110), carrier bias circuit 220, peaking bias circuit 222, first phase shifter 282 (e.g., phase shifter 182 of FIG1), carrier input signal manifold 230, peaking input signal manifold 250, output signal combiner manifold 270, and a plurality of "Dougherty units" 240, 241, 242, 243, 244, 245, 246, 247 coupled in parallel between the carrier input signal manifold 230 and the peaking input signal manifold 250 and the output signal combiner manifold 270. Although Figure 2 Eight Dougherty units 240-247 are shown in parallel coupling, but other embodiments of the Dougherty amplifier 200 may include more or fewer Dougherty units 240-247 (e.g., two to fifty units).

[0088] Power divider 210 is coupled between input node 202 and carrier input signal manifold 230 and peaking input signal manifold 250. Power divider 210 is configured to distribute the power of the input RF signal received at input node 202 into a carrier portion and a peaking portion of the input signal, which are generated at the carrier signal output and peaking signal output of power divider 210, respectively.

[0089] A first phase shifter 282 is coupled between the peaked signal output of the power divider 210 and the peaked input signal manifold 250. According to one embodiment, the first phase shifter 282 applies an approximately 90-degree phase delay to the peaked input signal before it is provided to the peaked input signal manifold 250. For example, the first phase shifter 282 may include a quarter-wavelength transmission line, a lumped element delay circuit, or another suitable type of delay element or circuit with an electrical length of approximately 90 degrees. The first phase shifter 282 serves to impart a 90-degree phase difference between the carrier input signal and the peaked input signal upon arrival at the carrier input signal manifold 230 and the peaked input signal manifold 250, respectively. In other embodiments, the power divider 210 may impart a 90-degree phase difference between the carrier input signal and the peaked input signal, or other circuitry may be used to impart a 90-degree phase difference.

[0090] Multiple Dougherty units 240-247 are coupled in parallel between the carrier input signal manifold 230 and the peaking input signal manifold 250 and the output signal combiner manifold 270. Referring to the enlarged Dougherty unit 240, each Dougherty unit 240 includes parallel carrier amplification paths and peaking amplification paths (e.g., Figure 1 The carrier path includes a carrier input 232, a carrier sub-amplifier 236, a second phase shifter 280, and a carrier output 272. Similarly, the peaking path includes a peaking input 252, a peaking sub-amplifier 256, and a peaking output 274. The carrier input 232 for all Dougherty units 240-247 is electrically coupled to the carrier input signal manifold 230, and the peaking input 252 for all Dougherty units 240-247 is electrically coupled to the peaking input signal manifold 250. The carrier output 272 and peaking output 274 for all Dougherty units 240-247 are electrically coupled to the output signal combiner manifold 270, which acts as a combining node for all RF signals amplified by the carrier path and peaking path of the Dougherty units 240-247 (e.g., Figure 1 (Combined node 170).

[0091] If combined Figure 3-13 In more detail, each carrier sub-amplifier 236 and peaking sub-amplifier 256 can be implemented, for example, using one or more transistor fingers, wherein each transistor finger corresponds to a field-effect transistor (FET) having a control terminal (or gate terminal) and a first current conduction terminal and a second current conduction terminal (or drain and source terminals). Therefore, in Figure 2In the diagram, each carrier sub-amplifier 236 and peaking sub-amplifier 256 is depicted as a three-terminal FET. The FET 237 for the carrier sub-amplifier 236 has a control terminal (e.g., gate terminal) coupled to the carrier input signal manifold 230 via the carrier input terminal 232, a first current conduction terminal (e.g., drain terminal) coupled to the output signal combiner manifold 270 via the phase shifter 280 and the carrier output terminal 272, and a second current conduction terminal (e.g., source terminal) coupled to a ground voltage reference. Similarly, the FET 257 for the peaking sub-amplifier 256 has a control terminal (e.g., gate terminal) coupled to the peaking input signal manifold 250 via the peaking input terminal 252, a first current conduction terminal (e.g., drain terminal) coupled to the output signal combiner manifold 270 via the peaking output terminal 274, and a second current conduction terminal (e.g., source terminal) coupled to a ground voltage reference.

[0092] Phase shifter 280 in the carrier path is configured to impart a predetermined phase delay to the amplified RF signal received from a first current conduction terminal (e.g., drain terminal) of FET 237 for carrier subamplifier 236. According to one embodiment, the predetermined phase delay may be about 90 degrees or less to impart a total phase delay between the first current conduction terminal (or more specifically, the intrinsic drain of FET 237) and the output signal combiner manifold 270.

[0093] On the input side of each Dougherty unit 240-247, the carrier input terminal 232 of each Dougherty unit 240-247 is electrically coupled to the carrier input signal manifold 230, and the peaking input terminal 252 of each Dougherty unit 240-247 is electrically coupled to the peaking input signal manifold 250. On the output side of each Dougherty unit 240-247, the output terminals 272 and 274 of each Dougherty unit 240-247 are electrically coupled to the output signal combiner manifold 270.

[0094] Each of the carrier input signal manifold 230, the peaking input signal manifold 250, and the output signal combiner manifold 270 may include an elongated conductive structure (e.g., one or more patterned wires or traces) spanning the width of the Dougherty cells 240-247. Therefore, the carrier input signal manifold 230 is physically configured to facilitate electrical connection of all carrier input terminals 232 of all Dougherty cells 240-247 to the carrier input signal manifold 230. Similarly, the peaking input signal manifold 250 is physically configured to facilitate electrical connection of all peaking input terminals 263 of all Dougherty cells 240-247 to the peaking input signal manifold 250. The carrier input signal manifold 230 and the peaking input signal manifold 250 are electrically isolated from each other, and therefore also electrically isolated from each other when the carrier input signal and the peaking input signal arrive at the Dougherty cells 240-247. On the output side, the output signal combiner manifold 270 is physically configured to facilitate electrical connection of all output terminals 272, 274 of all Dougherty units 240-247 to the output signal combiner manifold 270. Therefore, the output signal combiner manifold 270 is configured to combine all amplified signals from the carrier paths and peaking paths of all Dougherty units 240-247.

[0095] The carrier amplifier of the Dougherty amplifier 200 (e.g., Figure 1 The carrier amplifier 136) consists of multiple parallel-coupled carrier sub-amplifiers 236 from all the Dougherty units 240-247, and the peaking amplifier of the Dougherty amplifier 200 (e.g., Figure 1 The peaking amplifier 156) consists of multiple parallel-coupled peaking sub-amplifiers 236 from all the Dougherty units 240-247. For example... Figure 2As shown, carrier sub-amplifier 236 and peaking sub-amplifier 256 are arranged in a cross-finger (or interleaved) pattern across multiple units 240-247. In other words, in one embodiment, starting from Dougherty unit 240 and proceeding towards Dougherty unit 247, carrier sub-amplifier 236 and peaking sub-amplifier 256 are physically arranged in a strictly alternating manner (e.g., carrier sub-amplifier, peaking sub-amplifier, carrier sub-amplifier, peaking sub-amplifier, etc.). In other embodiments, carrier sub-amplifier 236 and peaking sub-amplifier 256 may be interleaved, but not in a strictly alternating manner. For example, starting from Dougherty unit 240 and proceeding towards Dougherty unit 247, carrier sub-amplifier 236 and peaking sub-amplifier 256 may be physically arranged such that there is a carrier sub-amplifier 236, then two peaking sub-amplifiers 256, then two carrier sub-amplifiers 236, etc. Other cross-finger arrangements may also be used. In any case, the carrier subamplifier 236 and the peaking subamplifier 256 are positioned adjacent to each other across the width of the device.

[0096] During operation of the Dougherty power amplifier 200, carrier bias circuit 220 provides a first DC bias voltage (from first bias voltage input 221) to carrier input signal manifold 230 to bias the carrier sub-amplifier 236 of each Dougherty unit 240-247 to operate in Class AB mode or deep Class AB mode. Similarly, peaking bias circuit 222 provides a second DC bias voltage (from second bias voltage input 223) to peaking input signal manifold 250 to bias the peaking sub-amplifier 256 of each Dougherty unit 240-247 to operate in Class B or deep Class B mode. Each of the bias circuits 220, 222 includes a circuit system (e.g., a quarter-wavelength transmission line) that presents a high impedance to RF signal energy to suppress RF signal energy from being transmitted to bias voltage inputs 221, 223.

[0097] An input RF signal is received at input node 202, and power divider 210 divides the input RF signal into a carrier input RF signal and a peaked input RF signal, which are transmitted at the carrier signal output and peaked signal output of power divider 210, respectively. A first phase shifter 282 delays the peaked input signal by approximately 90 degrees, such that when the carrier input signal and the peaked input signal arrive at carrier input signal manifold 230 and peaked input signal manifold 250, respectively, they are approximately 90 degrees out of phase. Carrier input signal manifold 230 transmits the carrier input signal to the carrier input terminal 232 of each Dougherty unit 240-247, and peaked input signal manifold 250 transmits the peaked input signal to the peaked input terminal 252 of each Dougherty unit 240-247. Each Dougherty unit 240-247 amplifies the received carrier input signal and peaked input signal, and generates an amplified carrier RF signal and a peaked RF signal at the carrier output terminal 272 and peaked output terminal 274, respectively. The amplified carrier RF signal and peaked RF signal from each Dougherty unit 240-247 are received at the output signal combiner manifold 270 and combined by the output signal combiner manifold 270, generating a combined output RF signal at the output node 204.

[0098] Now we will combine Figure 3-5 An embodiment of the physical implementation of an integrated circuit (IC) embodying a carrier input signal manifold 230 and a peaking input signal manifold 250, multiple Dougherty cells 240-247, and an output signal combiner manifold 270 is discussed. More specifically, Figure 3 This is a top view of an asymmetric Dougherty power amplifier IC 300 (“Dougherty IC”) having a plurality of asymmetric Dougherty units 340-347 and interdigitated carrier fingers 336 and interdigitated peaking fingers 356 according to an example embodiment. Figure 3 The enlarged Dougherty unit 347 is shown to illustrate the various features of the invention more clearly. For enhanced understanding, it should be noted that an example embodiment is relevant. Figure 4 and 5 (these are respectively) Figure 3 (The cross-sectional side views of Doherty unit 347 along lines 4-4 and 5-5 are viewed together.) Figure 3 .

[0099] exist Figure 3-5In one embodiment, the components of the Dougherty IC 300 are integrally formed (i.e., the components form part of die 301 and are physically positioned between the top surface 401 and the bottom surface 402 of die 301). In other embodiments, some components of the assembly may be integrated with the IC (e.g., attached to the die, rather than integrally formed with the die). As used herein, the terms "integrated circuit die" and "IC die" mean a single, distinct semiconductor die (or semiconductor substrate) in which one or more circuit components (e.g., transistors, passive devices, etc.) are integrally formed and / or directly physically connected to create an integral structure.

[0100] In one embodiment, the Dougherty IC 300 is an integral semiconductor device. More specifically, the components of the IC 300 form part of a single semiconductor die 301. The die 301 includes a substrate semiconductor substrate 410 and a stacked structure 412, the stacked structure 412 including a plurality of dielectric and patterned conductive layers and structures on and above the top surface of the substrate semiconductor substrate 410. The top surface of the stacked structure 412 defines a top surface 401 of the die 301. According to one embodiment, a conductive layer 428 is formed on the bottom surface of the substrate semiconductor substrate 410 to define a bottom surface 402 of the die 301.

[0101] The conductive layer 428 also serves as a ground reference node for the die 301. As used herein, "ground reference node" means a conductive feature integrally formed with the semiconductor die 301, and said conductive feature is configured to be electrically coupled to an external conductive feature, which in turn can be electrically coupled to a ground reference voltage. Therefore, although Figure 4-5 Not shown in the diagram, but when the Dougherty IC300 is finally packaged, the conductive layer 428 can be physically and electrically coupled to the package substrate (e.g., ...). Figure 14 The grounding node of the flange 1420. In other embodiments, the "grounding reference node" may be an integrally formed conductive feature of the die 301 other than the conductive layer 428 (e.g., the grounding reference node may be a bonding pad, one or more ends of one or more conductive vias, or other integrally formed conductive features).

[0102] In one particular example embodiment, the substrate semiconductor substrate 410 is a high-resistivity silicon substrate (e.g., a silicon substrate with a bulk resistivity in the range of about 500 ohm-cm (cm) to about 100,000 ohm-cm or greater). Alternatively, the substrate semiconductor substrate 410 may be a semi-insulating gallium arsenide (GaAs) substrate (e.g., a bulk resistivity up to 10 ohm-cm). 8The substrate can be a GaAs substrate (ohm-cm) or another suitable high-resistivity substrate. The advantage of using a high-resistivity substrate is that it allows for relatively low losses in various on-die circuit systems compared to amplifier ICs that do not utilize a high-resistivity substrate. In other alternative embodiments, the substrate semiconductor 410 can be any of a variety of variations of a silicon substrate, a silicon-germanium substrate, a gallium nitride (GaN) substrate, another type of III-V semiconductor substrate, or some other type of semiconductor substrate.

[0103] The stacked structure 412 may include, for example, multiple alternating dielectric and patterned conductive layers and other conductive structures (e.g., conductive polysilicon structures). Within the stacked structure 412, portions of the different patterned conductive layers and conductive structures are electrically coupled to conductive vias. Additionally, conductive through-substrate vias (TSVs) (e.g., TSV 464) may provide a conductive path between the top and bottom surfaces of the substrate semiconductor substrate 410. The TSVs may be lined with or without a dielectric material to insulate them from the substrate semiconductor substrate 410.

[0104] The circuit system implemented in the Doherty IC 300 corresponds to Figure 2 This is a partial schematic of the Dougherty amplifier 200. More specifically, the Dougherty IC 300 includes a carrier input signal manifold 330 (e.g., Figure 2 The carrier manifold 230), peaking input signal manifold 350 (e.g., Figure 2 Peaking manifold 250), output signal combiner manifold 370 (e.g., peaking manifold 250), output signal combiner manifold 370 Figure 2 The output manifold 270) and multiple Dougherty units 340, 341, 342, 343, 344, 345, 346, 347 (e.g., Figure 2 The Dougherty units 240-247). The carrier input signal manifold 330 and the peaking input signal manifold 350 are located on the "input side" of IC 300 (i.e., the first side of Dougherty units 340-347), and the output signal combiner manifold 370 is located on the "output side" of IC 300 (i.e., the second opposite side of Dougherty units 340-347). Although Figure 3 Eight Dougherty units 340-347 are shown in parallel coupling, but other embodiments of the Dougherty IC 300 may include more or fewer Dougherty units 340-347.

[0105] The carrier input signal manifold 330 and the peaking input signal manifold 350 are electrically isolated from each other on the input side of the Doughnut units 340-347, such that each manifold 330, 350 can receive input signals independently of each other (i.e., the carrier input signal manifold 330 receives the carrier input signal, and the peaking input signal manifold 350 receives the peaking input signal). Each of the carrier input signal manifold 330, the peaking input signal manifold 350, and the output signal combiner manifold 370 may include an elongated conductive feature, at least a portion of which is exposed at the top surface 401 of the die 301. For example, each of the manifolds 330, 350, 370 may be an elongated conductive bonding pad or conductive solder area. In the illustrated embodiment, the length of each manifold 330, 350, 370 ( Figure 3 The vertical dimension in the middle is approximately equal to the combined width of the Dougherty unit 340-347. Figure 3 (Vertical dimensions in the diagram). In alternative embodiments, some or all of manifolds 330, 350, and 370 may be shorter or longer than the combined width of Dougherty units 340-370. In embodiments where manifolds 330, 350, and 370 are bonding pads, manifolds 330, 350, and 370 may be configured to attach one or more lead bonding arrays (e.g., ...). Figure 14 The lead wires are connected to 1432, 1452, and 1472.

[0106] Multiple Dougherty units 340-347 are coupled in parallel between the carrier input signal manifold 330, the peaking input signal manifold 350, and the output signal combiner manifold 370. The Dougherty units 340-347 are arranged side-by-side and directly adjacent to each other, where "adjacent" means adjacent and "directly adjacent" means adjacent without any isolation structure between them (e.g., Figure 4 There are no significant electrical or non-electrical components or structures outside the shallow or deep trench isolation structure 467. In some embodiments, the distance between adjacent Dougherty cells 340-347 is less than the width of the transistor fingers.

[0107] refer to Figure 3 The bottom enlarged Dougherty cells 347, each Dougherty cell 340-347 including parallel carrier transistor fingers 336 and peaking transistor fingers 356, and phase shifting elements 380 (e.g., corresponding to...). Figure 2 The carrier sub-amplifier 236 and peaking sub-amplifier 256, and phase shifter 280). The carrier input 332 of each Dougherty unit 340-347 is electrically coupled to the carrier input signal manifold 330, the peaking input 352 of each Dougherty unit 340-347 is electrically coupled to the peaking input signal manifold 350, and the outputs (e.g., the drain terminals) of both the carrier finger 336 and the peaking finger 356 are electrically coupled to the output signal combiner manifold 370.

[0108] like Figure 4 and 5 Most clearly depicted, each transistor finger 336, 356 corresponds to a small FET, which includes a gate terminal 337, 357 (or control terminal); a drain terminal 338, 358 (or first current-carrying terminal); and a source terminal (or second current-carrying terminal) 462, 463. For example, each transistor finger 336, 356 may be a metal-oxide-semiconductor FET (MOSFET), a laterally diffused MOSFET (LDMOS FET), an enhancement-mode or depletion-mode high electron mobility transistor (HEMT), or another type of FET. According to various embodiments, each of the transistor fingers 336, 356 may be implemented, for example, using: a silicon-based FET; a silicon-germanium (SiGe)-based FET; or a III-V FET (e.g., HEMT), such as a gallium nitride (GaN) FET (or another type of III-V transistor, including gallium arsenide (GaAs) FET, gallium phosphide (GaP) FET, indium phosphide (InP) FET, or indium antimonide (InSb) FET). In one specific embodiment, each transistor finger 336, 356 is a laterally diffused metal-oxide-semiconductor (LDMOS) FET finger comprising one or more active regions disposed between the source and drain terminals.

[0109] Each transistor finger 336, 356 has an elongated active region, wherein the length of the finger or gate (i.e., the dimension extending along the axis between the input signal manifold 330, 350 and the output signal manifold 370) is significantly greater than the width of the finger or gate (i.e., the dimension extending along an axis perpendicular to the length). For example, the finger / gate length can be in the range of about 50 micrometers to about 1200 micrometers, and the finger / gate width can be in the range of about 0.1 micrometers to about 0.4 micrometers. In other embodiments, the finger length and width can be less than or greater than the ranges given above. Each active region includes a plurality of elongated, parallel-aligned drain regions 438, 458 and source regions 460, 461, wherein each drain region 438, 458 and each source region 460, 461 is a doped semiconductor region formed in the substrate semiconductor substrate 410. Variable conductive channels 437, 457 (and drain drift regions in some embodiments) exist between adjacent source regions 460, 461 and drain regions 438, 458.

[0110] Conductive (e.g., polysilicon or metal) gate terminals 337, 357 are formed in a stacked structure 412 above the top surface of the substrate semiconductor substrate 410. Each gate terminal 337, 357 extends over and along the length of the channel regions 437, 457. Each gate terminal 337, 357 is electrically coupled at multiple points along its length (e.g., through conductive vias and patterned conductive layers in the stacked structure 412) to elongated conductive gate structures and "channels" 439, 459, which are in turn electrically coupled to a carrier input signal manifold 330 via a carrier input 332. Similarly, conductive (e.g., polysilicon) drain terminals 338, 358 are formed in the stacked structure 412 above the top surface of the substrate semiconductor substrate. Each drain terminal 338, 358 extends above and along the length of the drain regions 438, 458. Finally, source regions 460, 461 are electrically coupled to conductive (e.g., polysilicon or metal) source contacts 462, 463, which in turn are coupled to conductive TSVs (e.g., TSVs) extending through the substrate semiconductor substrate (e.g., substrate 410) to connect with a conductive layer (e.g., layer 428) on the bottom surface of the substrate semiconductor substrate. Figure 4 (TSV 464). In some embodiments, the source contacts 462, 463 between adjacent fingers 336, 356 can be replaced by a single source contact and one or more TSVs (i.e., shared electrical connection to the conductive layer 428 can be implemented between the source contacts 462, 463 of adjacent fingers 336, 356 within the cell). In either case, the voltage applied to the gate terminals 337, 357 during operation modulates the conductivity of the variable conductive channels 437, 457, thus enabling current to flow between the source and drain regions (or ultimately between the conductive layer 428 and each drain terminal 338, 358).

[0111] Electromagnetic isolation features can be integrally formed in die 301 to reduce or substantially eliminate electromagnetic coupling between carrier fingers 336 and peaked fingers 356 and / or between adjacent Dougherty cells 340-347 during operation. For example, additional conductive features 465, 466 can be formed in the stacked structure 412 to provide electromagnetic shielding between carrier fingers 336 and peaked fingers 356 and / or between adjacent Dougherty cells 340-347. According to one embodiment, the additional conductive features 465, 466 may include additional conductive vias and conductive traces coupled to source contacts 462, 463 and extending upward or into the top surface 401 of die 301. In some embodiments, the height of the additional conductive features 456, 466 may be substantially equal to or greater than the height of gate channels 439, 459. During operation, the electromagnetic energy from collisions with other conductive features 465, 466 can be shunt to ground via source contacts 462, 463. Alternatively, to reduce or substantially eliminate electromagnetic coupling between carrier fingers 336 and peaked fingers 356 across the substrate semiconductor substrate 410, electromagnetic isolation features may include shallow trench isolation (STI) and / or deep trench isolation (DTI) structures 467 formed in the substrate semiconductor substrate 410 between and / or adjacent to Dougherty cells 340-347. The STI or DTI structure 467 may include, for example, elongated trenches filled with dielectric material and / or elongated doped regions with high electrical isolation characteristics.

[0112] exist Figure 3-5 In the illustrated embodiment, in each transistor finger 336, 356, source regions 460, 461 are located on both sides of a single drain region 438, 458, and channels 437, 457 and associated gate structures 337, 357 are also located on both sides of each drain region 438, 458. Therefore, each transistor finger 336, 356 is substantially symmetrical about the central drain region 438, 458. During operation, current is drawn into each drain region 438, 458 from the two source regions 460, 461 located on either side of each drain region 438, 458 (and through the channel regions 437, 457). In other embodiments, each transistor finger 336, 356 may include only a single source region and a single drain region or may be otherwise configured.

[0113] The gate terminal 337 of each carrier finger 336 is coupled to the carrier input signal manifold 330 via the carrier input terminal 332 and a conductor (e.g., a transmission line). Similarly, the gate terminal 357 of each peaking finger 356 is coupled to the peaking input signal manifold 350 via the peaking input terminal 352 and a conductor (e.g., a transmission line).

[0114] The drain terminal 358 of each peaking finger 356 is tightly electrically coupled to the output signal combiner manifold 370 (e.g., directly connected). Conversely, the drain terminal 338 of each carrier finger 336 is connected via a phase shift element 380 (e.g., Figure 2 The phase shifter 280 is coupled to the output signal combiner manifold 370. More specifically, the first end or end 382 of the phase shifter 380 is coupled to the drain end 338 of the carrier finger 336, and the second end or end 384 of the phase shifter 380 is coupled to the output signal combiner manifold 370 (e.g., via a conductor, such as a transmission line).

[0115] Phase shift element 380 is configured to impart a predetermined phase delay to the amplified RF signal generated at the drain terminal 338 of carrier finger 336. According to one embodiment, the predetermined phase delay imparted by phase shift element 380 may be about 90 degrees or less to impart a total phase delay of about 90 degrees between the drain terminal 338 of carrier finger and the output signal combiner manifold 370.

[0116] According to one embodiment, and as Figure 3 and 5 As most clearly shown, the phase shift element 380 can be implemented using a spiral inductor, which is integrally formed in die 301 using patterned portions of one or more conductive layers of a stacked structure 412. In other embodiments, and referring to... Figure 6The Dougherty unit 600 may include a phase-shifting element in the form of a chip inductor 680 (i.e., an inductor embodied in a discrete component), which is electrically and physically coupled to the top surface of a die 601 (i.e., the chip inductor 680 is integrated with the die 601). More specifically, a first end 682 of the chip inductor 680 may be connected (e.g., soldered or bonded with conductive adhesive) to a first bonding pad 683 exposed at the top surface of the die and electrically connected to the drain end 338 of the carrier finger 336. A second end 684 of the chip inductor 680 may be connected (e.g., soldered or bonded with conductive adhesive) to a second bonding pad 685 exposed at the top surface of the die and electrically connected to an output signal combiner manifold 370 (e.g., via a conductor, such as a transmission line). In other embodiments, the chip inductor 680 may be replaced by one or more wire connections, wherein a first end is connected to a first bonding pad 683 and a second end is connected to a second bonding pad 685. According to one embodiment, the inductance value of the phase-shifting element (e.g., an inductor) is in the range of about 0.1 nanohenries to about 20 nanohenries, although the inductance value may also be smaller or larger. Figure 6 Only one Dougherty unit 600 is shown, but multiple instances of Dougherty units 600 (e.g., two to fifty units 600) can be implemented side-by-side on die 601 (as shown in the image). Figure 3 The Dougherty unit 340-347), wherein the second bonding pad 685 and the drain end 358 of each peaked finger 356 are coupled to a single output signal combiner manifold 370.

[0117] like Figure 3As shown, carrier fingers 336 and peaked fingers 356 are directly adjacent to each other in each Dougherty unit 340-347. Alternating arrangements of transistor fingers are generated along the width of the output signal combiner manifold 370 (i.e., carrier fingers of unit 340 are directly adjacent to peaked fingers of unit 340, peaked fingers of unit 340 are directly adjacent to carrier fingers of unit 341, carrier fingers of unit 341 are directly adjacent to peaked fingers of unit 341, peaked fingers of unit 341 are directly adjacent to carrier fingers of unit 342, carrier fingers of unit 342 are directly adjacent to peaked fingers of unit 342, etc.). In other embodiments, adjacent units 340-347 may be “flipped” relative to each other, such that the alternating arrangement of carrier fingers and peaked fingers can have the same finger type (i.e., carrier fingers or peaked fingers) directly adjacent to each other from one unit 340-347 to the next unit. In other words, this will result in different alternating arrangements of transistor fingers (i.e., the carrier fingers of cell 340 are directly adjacent to the peaked fingers of cell 340, the peaked fingers of cell 340 are directly adjacent to the peaked fingers of cell 341, the peaked fingers of cell 341 are directly adjacent to the carrier fingers of cell 341, the carrier fingers of cell 341 are directly adjacent to the carrier fingers of cell 342, the carrier fingers of cell 342 are directly adjacent to the peaked fingers of cell 342, etc.).

[0118] Each of the Dougherty units 340-347 is an asymmetric Dougherty unit because the size (or periphery) of the carrier finger 336 differs from that of the peaking finger 356. More specifically, in Figure 3 In the illustrated embodiment, the length 339 of the carrier finger 336 is approximately half the length 359 of the peaking finger 356 (or conversely, the length 359 of the peaking finger 356 is approximately twice the length 339 of the carrier finger 336). Therefore, the periphery (and current-carrying capacity) of the carrier finger 336 is approximately half the periphery (and current-carrying capacity) of the peaking finger 356 (or conversely, the periphery of the peaking finger 356 is approximately twice the periphery of the carrier finger 336). Thus, the carrier to peaking amplifier size ratio of each of the Dougherty units 340-347 is approximately 1:2, and the carrier to peaking ratio of the entire Dougherty IC 300 is also approximately 1:2. In other embodiments, a larger or smaller asymmetry ratio can be implemented by adjusting the relative lengths of the carrier finger 336 and the peaking finger 356.

[0119] Each of the Dougherty units 340-347 has a relatively compact arrangement. More specifically, and as... Figure 3As shown, the carrier finger 336 and the peaking finger 356 have input ends aligned along a first line 390 perpendicular to the length 339 of the carrier finger 336 and the length 359 of the peaking finger 356. The peaking finger 359 has an output end aligned along a second line 391 perpendicular to the length 339 of the carrier finger 336 and the length 359 of the peaking finger 356. A phase shift element 380 is positioned between the output end of the carrier finger 336 and the second line 391.

[0120] In other embodiments, asymmetric Dougherty units can be implemented by including multiple carrier fingers and peaking fingers in each Dougherty unit. For example, Figure 7 This is a top view of an asymmetric Dougherty cell 700 according to another example embodiment. The Dougherty cell 700 includes two carrier transistor fingers 735, 736 integrally formed with a die 701; two peaking transistor fingers 755, 756; and two phase shifting elements 780, 781.

[0121] On the input side of the Dougherty unit 700, the gate terminals (directly adjacent to each other) of the carrier fingers 735, 736 are coupled to the carrier input terminal 732, which in turn is coupled to the carrier input signal manifold (e.g., Figure 3 (manifold 330). Similarly, the gate ends (directly adjacent to each other) of the peaking fingers 755, 756 are coupled to the peaking input 752, which in turn is coupled to the peaking input signal manifold (e.g., Figure 3 The drain terminals of each peaking finger 755, 756 are tightly electrically coupled to the output signal combiner manifold 770 (e.g., manifold 350). Figure 3 The manifold 370). Conversely, the drain terminals of each carrier finger 735, 736 are connected via phase shift elements 780, 781 (e.g., Figure 2 The phase shifter 280) is coupled to the output signal combiner manifold 770 (e.g., Figure 3 The phase shift element 780 (manifold 370) is coupled to the drain terminal of the carrier finger 735. More specifically, a first end or terminal of the phase shift element 780 is coupled to the drain terminal of the carrier finger 735, and a second end or terminal of the phase shift element 780 is coupled to the output signal combiner manifold 770. Similarly, a first end or terminal of the phase shift element 781 is coupled to the drain terminal of the carrier finger 736, and a second end or terminal of the phase shift element 781 is coupled to the output signal combiner manifold 770. In the illustrated embodiment, each phase shift element 780, 781 includes an integrally formed helical inductor. In other embodiments, the phase shift elements 780, 781 may be chip inductors (e.g., chip inductors). Figure 6 The chip inductor 680 or lead bonding can be used instead.

[0122] Each phase shift element 780, 781 is configured to impart a predetermined phase delay to the amplified RF signal generated at one of the drain terminals of the carrier fingers 735, 736. According to one embodiment, the predetermined phase delay imparted by each phase shift element 780, 781 may be about 90 degrees or less, to impart a total phase delay of about 90 degrees between the drain terminal of each carrier finger and the output signal combiner manifold 770.

[0123] With Doherty Unit 347 ( Figure 3 Similarly, the length 739 and periphery of the carrier fingers 735, 736 differ from the length 759 and periphery of the peaked fingers 755, 756. Again, the total periphery of the peaked fingers 755, 756 (i.e., the sum of the peripheries of fingers 755, 756) is approximately twice the total periphery of the carrier fingers 735, 736 (i.e., the sum of the peripheries of fingers 735, 736). Therefore, the carrier to peaked amplifier size ratio of the Dougherty unit 700 is approximately 1:2. In other embodiments, a larger or smaller asymmetry ratio can be implemented by adjusting the relative lengths of the carrier fingers 735, 736 and the peaked fingers 755, 756. Additionally, larger or smaller asymmetry ratios (e.g., 1:3, 1:4, 1:1.5, etc.) can be implemented by including different numbers of carrier fingers and peaking fingers (e.g., other embodiments may include more or fewer than two carrier fingers 735, 736 and / or more or fewer than two peaking fingers 755, 756).

[0124] For a brief reference again Figure 3 Each of the Dougherty units 340-347 can be replaced by an instance Dougherty unit 700 to produce a Dougherty IC comprising a plurality of Dougherty units 700 electrically connected in parallel between a carrier input signal manifold 330 and a peaking input signal manifold 350 and an output signal combiner manifold 370. More specifically, the carrier input 732 of each instance of the Dougherty unit 700 is electrically coupled to the carrier input signal manifold 330, the peaking input 752 of each instance of the Dougherty unit 700 is electrically coupled to the peaking input signal manifold 350, and the output (e.g., the drain terminal) of each of the carrier fingers 735, 736 and the peaking fingers 755, 756 is electrically coupled to the output signal combiner manifold 370. In other words, although Figure 7 Only one Dougherty unit 700 is shown, but multiple instances of Dougherty units 700 (e.g., two to fifty units 700) can be implemented side-by-side on die 701 (as shown in the image). Figure 3 The Dougher units 340-347) are coupled to the drain terminals of phase shifters 780, 781 and each peaking unit 755, 756 to a single output signal combiner manifold 770.

[0125] In other embodiments, asymmetric Dougherty units can be implemented by including different numbers of carrier fingers and peaking fingers of equal length in each Dougherty unit. For example, Figure 8 This is a top view of an asymmetric Dougherty cell 800 according to another example embodiment. The Dougherty cell 800 includes a carrier transistor finger 836, two peaking transistor fingers 855 and 856, and a phase shifting element 880.

[0126] On the input side of the Dougherty unit 800, the gate terminal of the carrier finger 836 is coupled to the carrier input terminal 832, which in turn is coupled to the carrier input signal manifold (e.g., Figure 3 The manifold 330). Similarly, the gate ends of both peaking fingers 855 and 856 are coupled to the peaking input 852, which in turn is coupled to the peaking input signal manifold (e.g., Figure 3 The drain terminals of each peaking finger 855, 856 are tightly electrically coupled to the output signal combiner manifold 870 (e.g., manifold 350). Figure 3 The manifold 370). Conversely, the drain terminal of the carrier finger 836 passes through the phase shift element 880 (e.g., Figure 2 The phase shifter 280) is coupled to the output signal combiner manifold 870 (e.g., Figure 3 The phase shift element 880 (manifold 370) is more specifically coupled to the drain terminal of the carrier finger 836, and a second end of the phase shift element 880 is coupled to the output signal combiner manifold 870 (e.g., via a conductor, such as a transmission line). In the illustrated embodiment, the phase shift element 880 includes an integrally formed helical inductor. In other embodiments, the phase shift element 880 may be a chip inductor (e.g., Figure 6 The chip inductor 680 or lead bonding can be used instead.

[0127] Furthermore, the phase shift element 880 is configured to impart a predetermined phase delay to the amplified RF signal generated at the drain terminal of the carrier finger 836. According to one embodiment, the predetermined phase delay imparted by the phase shift element 880 may be about 90 degrees or less, to impart a total phase delay of about 90 degrees between the drain terminal of the carrier finger and the output signal combiner manifold 870.

[0128] With Doherty Unit 347 ( Figure 3In comparison, the length 859 and perimeter of each of the carrier finger 836 and the peaking fingers 855, 856 are substantially equal (i.e., differing from each other by about 5%). However, because one carrier finger 836 and two peaking fingers 855, 856 are implemented, the total perimeter of the peaking fingers 855, 856 is approximately twice the perimeter of the carrier finger 836. Therefore, the carrier to peaking amplifier size ratio of the Dougherty unit 800 is approximately 1:2. In other embodiments, a larger or smaller asymmetry ratio can be implemented by adjusting the number of carrier fingers 836 and peaking fingers 855, 856. Typically, a Dougherty unit can have n carrier fingers (n≥1) and m peaking fingers (m≥1), all with equal lengths (perimeters), and an asymmetry ratio can be achieved as long as n≠m. Of course, when n = m, as long as the length (and periphery) of the carrier finger and the peaking finger are equal, the Dougherty cell will be a symmetric Dougherty cell.

[0129] although Figure 8 Only one Dougherty unit 800 is shown, but multiple instances of Dougherty units 800 (e.g., two to fifty units 800) can be implemented side-by-side on die 801 (as shown in the image). Figure 3 The Dougherty units 340-347), wherein the drain terminals of each phase shifter 880 and each peaking unit 855, 856 are coupled to a single output signal combiner manifold 870.

[0130] As indicated above, in various embodiments, a Dougherty cell may have n carrier fingers (n≥1) and m peaked fingers (m≥1) of equal or unequal length (perimeter). Furthermore, although the embodiments discussed above include asymmetric Dougherty cells, other embodiments may include symmetric Dougherty cells. In a symmetric Dougherty cell, the total perimeter of one or more carrier fingers in the cell is substantially equal to the total perimeter of one or more peaked fingers in the cell.

[0131] For example, Figure 9 This is a top view of a symmetrical Dougherty cell 900 according to an example embodiment. The Dougherty cell 900 includes a carrier transistor finger 936, a peaking transistor finger 956, and a phase shifting element 980.

[0132] On the input side of the Dougherty unit 900, the gate terminal of the carrier finger 936 is coupled to the carrier input terminal 932, which in turn is coupled to the carrier input signal manifold (e.g., Figure 3 (manifold 330). Similarly, the gate end of the peaking finger 956 is coupled to the peaking input 952, which in turn is coupled to the peaking input signal manifold (e.g., Figure 3The drain terminal of the peaking finger 956 is tightly electrically coupled to the output signal combiner manifold 970 (e.g., manifold 350). Figure 3 The manifold 370). Conversely, the drain terminal of the carrier finger 936 passes through the phase shift element 980 (e.g., Figure 2 The phase shifter 280) is coupled to the output signal combiner manifold 970 (e.g., Figure 3 The phase shift element 980 (manifold 370) is more specifically coupled to the drain terminal of the carrier finger 936, and a second end of the phase shift element 980 is coupled to the output signal combiner manifold 970 (e.g., via a conductor, such as a transmission line). In the illustrated embodiment, the phase shift element 980 includes an integrally formed helical inductor. In other embodiments, the phase shift element 980 may be a chip inductor (e.g., Figure 6 The chip inductor 680 or lead bonding can be used instead.

[0133] Furthermore, the phase shift element 980 is configured to impart a predetermined phase delay to the amplified RF signal generated at the drain terminal of the carrier finger 936. According to one embodiment, the predetermined phase delay imparted by the phase shift element 980 may be about 90 degrees or less, to impart a total phase delay of about 90 degrees between the drain terminal of the carrier finger and the output signal combiner manifold 970.

[0134] With Doherty Unit 800 ( Figure 8 Similarly, the length 959 and periphery of each of the carrier finger 936 and peaking finger 956 are substantially equal (i.e., differing from each other by about 5%). Furthermore, because one carrier finger 936 and one peaking finger 956 are implemented, the periphery of the peaking finger 956 is approximately equal to the periphery of the carrier finger 936. Therefore, the carrier to peaking amplifier size ratio of the Dougherty unit 900 is approximately 1:1, and the Dougherty unit 900 is symmetrical.

[0135] although Figure 9 Only one Dougherty unit 900 is shown; multiple instances of Dougherty units 900 (e.g., two to fifty units 900) can be implemented side-by-side on die 901 (as shown in the diagram). Figure 3 The drain terminals of each phase shifter 980 and each peaking unit 956 are coupled to a single output signal combiner manifold 970.

[0136] exist Figure 9 In one embodiment, the symmetric Dougherty unit 900 includes a single carrier finger 936 and a single peaking finger 956, wherein the carrier finger 936 and the peaking finger 956 are of equal length. In other embodiments, the symmetric Dougherty unit may include multiple carrier fingers and peaking fingers of equal length. For example, Figure 10 This is a top view of a symmetrical Dougherty cell 1000 according to another example embodiment, the symmetrical Dougherty cell 1000 including an equal number of carrier fingers 1035, 1036 and peaking fingers 1055, 1056 of equal length. More specifically, the Dougherty cell 1000 includes two carrier transistor fingers 1035, 1036; two peaking transistor fingers 1055, 1056; and two phase shifting elements 1080, 1081.

[0137] On the input side of the Dougherty unit 1000, the gate terminal of each carrier finger 1035, 1036 is coupled to the carrier input terminal 1032, which in turn is coupled to the carrier input signal manifold (e.g., Figure 3 (manifold 330). Similarly, the gate end of each peaking finger 1055, 1056 is coupled to the peaking input 1052, which in turn is coupled to the peaking input signal manifold (e.g., Figure 3 The drain terminals of each peaked finger 1055, 1056 are tightly electrically coupled to the output signal combiner manifold 1070 (e.g., manifold 350). Figure 3 (manifold 370). Conversely, the drain terminals of each carrier finger 1035, 1036 are connected via phase shift elements 1080, 1081 (e.g., phase shifter 280, ...). Figure 2 Coupled to the output signal combiner manifold 1070 (e.g., Figure 3 The manifold 370). More specifically, a first end or terminal of each phase shift element 1080, 1081 is coupled to the drain terminal of the carrier fingers 1035, 1036, and a second end or terminal of each phase shift element 1080, 1081 is coupled to the output signal combiner manifold 1070 (e.g., via a conductor, such as a transmission line). In the illustrated embodiment, each phase shift element 1080, 1081 includes an integrally formed helical inductor. In other embodiments, the phase shift elements 1080, 1081 may be chip inductors (e.g., Figure 6 The chip inductor 680 or lead bonding can be used instead.

[0138] Furthermore, each phase shift element 1080, 1081 is configured to impart a predetermined phase delay to the amplified RF signal generated at the drain terminal of each carrier finger 1035, 1036. According to one embodiment, the predetermined phase delay imparted by each phase shift element 1080, 1081 may be about 90 degrees or less, to impart a total phase delay of about 90 degrees between the drain terminal of each carrier finger and the output signal combiner manifold 1070.

[0139] With Doherty Unit 800, 900 ( Figure 8 , 9Similarly, the length 1059 and perimeter of each of the carrier fingers 1035, 1036 and the peaking fingers 1055, 1056 are substantially equal (i.e., differing from each other by about 5%). Furthermore, because equal numbers of carrier fingers 1035, 1036 and peaking fingers 1055, 1056 are implemented, the total perimeter of the peaking fingers 1055, 1056 is approximately equal to the total perimeter of the carrier fingers 1035, 1036. Therefore, the carrier to peaking amplifier size ratio of the Dougherty unit 1000 is approximately 1:1, and the Dougherty unit 1000 is symmetrical.

[0140] Although the Dougherty unit 1000 includes two carrier fingers 1035, 1036 and two peaked fingers 1055, 1056, in other embodiments, more than two carrier fingers of equal length and more than two peaked fingers can be implemented in a symmetrical unit. For example, a Dougherty unit can have n carrier fingers (n≥1) and m peaked fingers (m≥1), all of which have equal lengths (peripherals), and a symmetrical Dougherty unit can be implemented as long as n = m.

[0141] Furthermore, despite Figure 10 Only one Dougherty unit 1000 is shown, but multiple instances of Dougherty units 1000 (e.g., two to fifty units 1000) can be implemented side-by-side on die 1001 (as shown in the image). Figure 3 The Dougher units 340-347) are coupled to the drain terminals of phase shifters 1080, 1081 and each peaking unit 1055, 1056 to a single output signal combiner manifold 1070.

[0142] Figure 9 and 10 Embodiments of the symmetric Dougherty units 900 and 1000 are implemented using carrier fingers 936, 1035, 1036 and peaking fingers 956, 1055, 1056 of equal length. In other embodiments, the symmetric Dougherty units can be implemented using carrier fingers and peaking fingers of different lengths. For example, Figure 11 This is a top view of a symmetrical Dougherty cell 1100 according to yet another example embodiment, the symmetrical Dougherty cell 1100 including unequal numbers of carrier fingers 1135, 1136 and peaking fingers 1156 of different lengths. More specifically, the Dougherty cell 1100 includes two carrier transistor fingers 1135, 1136; one peaking transistor finger 1156 and two phase shifting elements 1180, 1181.

[0143] On the input side of the Dougherty unit 1100, the gate of each carrier finger 1135, 1136 is coupled to the carrier input terminal 1132, which in turn is coupled to the carrier input signal manifold (e.g., Figure 3 (manifold 330). Similarly, the gate end of the peaking finger 1156 is coupled to the peaking input 1152, which in turn is coupled to the peaking input signal manifold (e.g., Figure 3 The drain terminal of the peaking finger 1156 is tightly electrically coupled to the output signal combiner manifold 1170 (e.g., manifold 350). Figure 3 The manifold 370). Conversely, the drain terminals of each carrier finger 1135, 1136 are connected via phase shift elements 1180, 1181 (e.g., Figure 2 The phase shifter 280) is coupled to the output signal combiner manifold 1170 (e.g., Figure 3 The manifold 370). More specifically, a first end or terminal of each phase shift element 1180, 1181 is coupled to the drain terminal of the carrier fingers 1135, 1136, and a second end or terminal of each phase shift element 1180, 1181 is coupled to the output signal combiner manifold 1170 (e.g., via a conductor, such as a transmission line). In the illustrated embodiment, each phase shift element 1180, 1181 includes an integrally formed helical inductor. In other embodiments, the phase shift elements 1180, 1181 may be chip inductors (e.g., Figure 6 The chip inductor 680 or lead bonding can be used instead.

[0144] Furthermore, each phase shift element 1180, 1181 is configured to impart a predetermined phase delay to the amplified RF signal generated at the drain terminal of each carrier finger 1135, 1136. According to one embodiment, the predetermined phase delay imparted by each phase shift element 1180, 1181 may be about 90 degrees or less, to impart a total phase delay of about 90 degrees between the drain terminal of each carrier finger and the output signal combiner manifold 1170.

[0145] With Doherty Unit 300, 700 ( Figure 3 , 6 7) Similarly, the length 1139 of carrier fingers 1135 and 1136 is not equal to the length 1159 of peaked finger 1156. More specifically, in Figure 11In the illustrated embodiment, the length 1139 of the carrier fingers 1135, 1136 is approximately half the length 1159 of the peaking finger 1156 (or conversely, the length 1159 of the peaking finger 1156 is approximately twice the length 1139 of the carrier fingers 1135, 1136). However, because two carrier fingers 1135, 1136 and one peaking finger 1156 are implemented, the periphery of the peaking finger 1156 is approximately equal to the total periphery of the carrier fingers 1135, 1136. Therefore, the carrier-to-peaking amplifier size ratio of the Dougherty unit 1100 is approximately 1:1, and the Dougherty unit 1100 is symmetrical.

[0146] Although the Dougherty unit 1000 includes two carrier fingers 1135, 1136 and one peaking finger 1156, in other embodiments, more than two carrier fingers and / or more than one peaking finger may be implemented in a symmetrical unit having carrier fingers and peaking fingers of unequal length.

[0147] In addition, although Figure 11 Only one Dougherty unit 1100 is shown, but multiple instances of Dougherty unit 1100 (e.g., two to fifty units 1100) can be implemented side-by-side on die 1101 (as shown in the image). Figure 3 The Dougherty units 340-347), wherein the drain terminals of phase shifters 1180, 1181 and peaking unit 1156 are coupled to a single output signal combiner manifold 1170.

[0148] Figure 2-11 Each of the Dougherty amplifier ICs and Dougherty units shown and described above corresponds to a bidirectional Dougherty amplifier or bidirectional Dougherty unit, which includes a carrier amplifier (consisting of one or more carrier fingers) and a peaking amplifier (consisting of one or more peaking fingers) respectively coupled between the carrier input and the peaking input and a combination structure (e.g., an output signal combination manifold). Other embodiments may include an "N-directional" Dougherty power amplifier, where N > 2, and includes one carrier amplifier and N-1 peaking amplifiers.

[0149] For example, Figure 12 This is a top view of a three-way Dougherty unit 1200 according to another example embodiment. Essentially, the three-way Dougherty unit 1200 includes a carrier sub-amplifier (in the form of carrier fingers 1236) and two peaking sub-amplifiers (in the form of peaking fingers 1255, 1256).

[0150] On the input side of the three-way Dougherty unit 1200, the gate of the carrier finger 1236 is coupled to the carrier input 1232, which in turn is coupled to the carrier input signal manifold (not shown). The gate of the first peaking finger 1255 is coupled to the first peaking input 1252, which in turn is coupled to the first peaking input signal manifold (not shown). Finally, the gate of the second peaking finger 1256 is coupled to the second peaking input 1253, which in turn is coupled to the second peaking input signal manifold (not shown). Each of the carrier input signal manifold, the first peaking input signal manifold, and the second peaking input signal manifold (not shown) is electrically isolated from each other on the input side of die 1201, and each input signal manifold receives power from a three-way signal distributor (e.g., Figure 2 An embodiment of the distributor 210, wherein the distributor 210 distributes the signal energy of the input RF signal into three parts (receiving a portion of the signal energy of the input RF signal).

[0151] On the output side of the Dougherty unit 1200, the drain terminal of peaking finger 1256 is tightly electrically coupled to the output signal combiner manifold 1270, and the drain terminal of peaking finger 1255 is coupled to the output signal combiner manifold 1270 via phase shift element 1281. More specifically, a first end or terminal of phase shift element 1281 is coupled to the drain terminal of peaking finger 1255, and a second end or terminal of phase shift element 1281 is coupled to the output signal combiner manifold 1270 (e.g., via a conductor, such as a transmission line). The drain terminal of carrier finger 1236 is electrically coupled to node 1270 located between the drain terminal of peaking finger 1255 and phase shift element 1281 via phase shift element 1280.

[0152] According to one embodiment, node 1270 acts as a first combining node, where signal energy from carrier finger 1236 and peaking finger 1255 is combined. After phase-shifting the combined signal energy from carrier finger 1236 and peaking finger 1255 by phase-shifting element 1281, output signal combiner manifold 1270 acts as a second combining node, where signal energy from peaking finger 1256 is combined with the phase-shifted, combined signal energy from carrier finger 1236 and peaking finger 1255.

[0153] In the illustrated embodiment, each phase shift element 1280, 1281 includes an integrally formed spiral inductor. In other embodiments, the phase shift elements 1280, 1281 may be chip inductors (e.g., Figure 6The chip inductor 680 or wire bonding is used instead. Again, each phase shift element 1280, 1281 is configured to impart a predetermined phase delay to the RF signal transmitted through the phase shift elements 1280, 1281. According to one embodiment, the predetermined phase delay imparted by each phase shift element 1280, 1281 may be about 90 degrees or less.

[0154] although Figure 12 Only one Dougherty unit 1200 is shown, but multiple instances of Dougherty units 1200 (e.g., two to fifty units 1200) can be implemented side-by-side on die 1201 (as shown in the image). Figure 3 The Dougher unit 340-347), wherein the drain terminals of the phase shifter 1281 and the peaking unit 1256 are coupled to a single output signal combiner manifold 1270.

[0155] Combination Figure 1-12 The various embodiments described in detail correspond to a "non-inverting" Dougherty amplifier, wherein the output of the carrier amplifier (or each carrier finger) is combined with the combination node (e.g., Figure 3 and 6 -11 output signal combiner manifolds 370, 770, 870, 970, 1070, 1170) implement an approximately 90-degree phase delay, and no significant phase delay is implemented between the output of the peaking amplifier (or each peaking finger) and the combination node. In other embodiments, the subject matter of the invention may be included within an "inverting" Dougherty amplifier, wherein an approximately 90-degree phase delay is implemented between the output of the peaking amplifier (or each peaking finger) and the combination node, and no significant phase delay is implemented between the output of the carrier amplifier (or each carrier finger) and the combination node. Alternatively, the subject matter of the invention may be implemented in multipath amplifiers other than Dougherty power amplifiers. Therefore, and specifically in the claims, "first amplifier" may mean a carrier amplifier, a peaking amplifier, or another type of amplifier, and "second amplifier" may mean a peaking amplifier, a carrier amplifier, or yet another type of amplifier. Similarly, references to "first amplifier finger" or "first sub-amplifier" can be applied to carrier finger or sub-amplifier, peaking finger or sub-amplifier or another type of amplifier finger or sub-amplifier, and references to "second amplifier finger" or "second sub-amplifier" can be applied to peaking finger or sub-amplifier, carrier finger or sub-amplifier or yet another type of amplifier finger or sub-amplifier.

[0156] Other modifications can also be implemented. For example, such as... Figure 4 and 5 The most clearly shown are the source regions of the carrier fingers and peaking fingers (e.g., Figure 4 , 5The source regions 460 and 461 can be coupled to a physically located portion of the amplifier die (e.g., Figure 3-12 The bottom surface (e.g., any one of the dies 301, 601, 701, 801, 901, 1001, 1101, 1201) Figure 4 , 5 The ground reference node at surface 402) (e.g., Figure 4 , 5 The conductive layer 428). As previously described, in such embodiments, a ground reference node located at the bottom can be coupled to the package substrate (e.g., the conductive layer 428). Figure 14 The ground node of the flange 1420. In an alternative embodiment, the source regions of the carrier fingers and peaking fingers may be coupled to one or more ground reference nodes exposed on the top surface of the die. In such embodiments, one or more ground reference nodes located on top may be coupled to the system ground via wire bonding, or the die may be flip-chip mounted to the package substrate (i.e., mounted with the top surface of the die in contact with the top surface of the package substrate).

[0157] For example, Figure 13 This is a top view of a power amplifier IC 1300 with a top source contact 1328 according to an example embodiment. Power amplifier IC 1300 and power amplifier IC 300 ( Figure 3 They are essentially similar, as the power amplifier IC 1300 includes multiple Dougherty amplifier units 1340, 1341, 1342, 1343, 1344, 1345, 1346, and 1347 electrically coupled between the carrier input signal manifold 1330 and the peaking input signal manifold 1350 and the output signal combiner manifold 1370. Although Figure 13 The Dougherty amplifier units 1340-1347 in the middle seem to be related to Figure 3-5 The Dougherty amplifier units 340-347 in the above are substantially similar, but the Dougherty amplifier units 1340-1347 can be used in many other previously described Dougherty amplifier unit embodiments (e.g., Figure 7-12 The units 700, 800, 900, 1000, 1100, and 1200 are used instead.

[0158] A significant difference between the power amplifier IC 1300 and the previously described embodiments is that the source region of each of the transistor fingers in the IC 1300 (e.g., Figure 4 , 5 The source regions 460 and 461 are electrically coupled to the top source contact 1328, rather than to the ground reference node located on the bottom surface of the die (e.g., Figure 4 , 5The conductive layer 428). According to one embodiment, the top source contact 1328 includes conductive bonding pads exposed on the top surface of the die 1301, and the top source contact 1328 is via a die stack structure (e.g., Figure 4 , 5 The patterned conductive layer and conductive via in the stacked structure 412) are electrically coupled to the source region.

[0159] According to one embodiment, the top source contact 1328 can be configured to physically and electrically connect (e.g., solder or conductively bond) to a corresponding conductive pad on the top surface of a system substrate (e.g., a PCB). Alternatively, the top source contact 1328 can be configured to attach wire bonds. Although Figure 13 Two top source contacts 1328 are shown positioned on either side of the Dougherty cells 1340-1347, but in other embodiments, more or fewer source contacts 1328 may be implemented and / or the source contacts 1328 may be positioned at other locations on the top surface of the die.

[0160] As indicated above, the power amplifier ICs, more specifically amplifier chips 301, 601, 701, 801, 901, 1001, 1101, 1201, and 1301 ( Figure 3-13 Any of these can be packaged and / or integrated into a larger electrical system in various ways. For example, the amplifier die described above can be packaged in a molded or cavity power device package. Alternatively, the amplifier die described above can be packaged in a surface-mount package, such as a leadless package (e.g., a dual-plane leadless (DFN) package or a quad-plane leadless (QFN) package). In other embodiments, the amplifier die described above can be directly mounted to the surface of a module or PCB substrate.

[0161] For example, Figure 14 This is a top view of a Dougherty amplifier device 1400 according to an example embodiment, the Dougherty amplifier device 1400 including a Dougherty amplifier die 1401 packaged in a high-power discrete device package 1404 (e.g., Figure 3-13 The die is any one of 301, 601, 701, 801, 901, 1001, 1101, 1201, or 1301. Package 1404 includes a carrier input signal lead 1430, a peaked input signal lead 1450, and an output signal lead 1470. In some embodiments, package 1404 may further include one or more additional bias voltages or other leads. Input signal leads 1430 and 1450 are located on the input side of package 1404, and output lead 1470 is located on the output side of package 1404.

[0162] According to one embodiment, package 1404 includes a package substrate, such as a conductive flange 1420, to which a Dougherty amplifier die 1401 (e.g., using conductive epoxy, solder, brazing, sintering, or other conductive connection methods) is physically and electrically connected (to the conductive flange 1420). Finally, package 1404 includes non-conductive structural features or materials, such as molding compound and / or other insulating materials, which hold leads 1430, 1450, 1470 and flange 1420 in a fixed orientation relative to each other.

[0163] Conductive connections such as conductive lead connections 1432, 1452 electrically connect the input signal manifold on die 1401 to the conductive leads 1430, 1450 on the input side of package 1404. For example, one or more first lead connections 1432 can electrically connect the carrier signal lead 1430 to the corresponding carrier input signal manifold (e.g., Figure 3 The first bonding pad of the manifold 330 is provided, and the carrier signal lead 1430 can be used to transmit the input carrier signal to the carrier fingers on the die 1401. Similarly, one or more second lead connections 1452 can electrically connect the peaking signal lead 1450 to the manifold corresponding to the peaking input signal (e.g., Figure 3 The second bonding pad of the manifold 350 is provided, and the peaking signal lead 1450 can be used to transmit the input peaking signal to the peaking fingers on the die 1401. On the output side, one or more third lead bonds 1472 can electrically connect the output signal lead 1470 to the corresponding output signal manifold (e.g., ...). Figure 3 The third bonding pad of the manifold 370, and the output signal lead 1470 can be used to transmit the amplified output signal generated by the die 1401.

[0164] In some embodiments, leads 1430, 1450, 1470 and flange 1420 may form portions of a lead frame. To complete the encapsulation during device manufacturing, after the attachment of die 1401 and the interconnection of lead joints between the leads and die 1401, the inner ends of die 1401, leads 1430, 1450, 1470, lead joints, and the upper and side surfaces of flange 1420 may be sealed with a non-conductive (e.g., plastic) molding material 1440. Figure 14 Only a portion is shown to avoid obscuring the internal components of device 1400. Molding material 1440 defines the perimeter of device 1400, from which leads 1430, 1450, and 1470 protrude, and the molding material 1440 also defines the top surface of device 1400. The bottom surface of device 1400 is partially defined by the molding material 1440 and by the bottom surface portion of flange 1420. Therefore, when properly coupled to a system substrate (e.g., ...), Figure 15When using PCB 1510, flange 1420 can serve (e.g., via...) Figure 4 The bottom conductive layer 428) transmits the ground reference to the die 1401 and can also act as a heat sink for the device 1400.

[0165] In similar but different embodiments, having Figure 14 The leads 1430, 1450, and 1470 shown in the configuration can be replaced by solder pads of a leadless package. The flange 1420 and the solder pads can be re-formed into a lead frame, the die 1401 and the leads are attached to the lead frame, and the assembly can be sealed again with a non-conductive molding compound to form a leadless surface mount device (e.g., a DFN or QFN device).

[0166] In other embodiments, the package 1404 may be a cavity package. In this embodiment, the flange 1420 may have a larger perimeter, which is equal to or approximately equal to the perimeter of the device 1400. A non-conductive insulator (e.g., ceramic, plastic, or another material) with a frame shape may be attached to the top surface of the flange, leads 1430, 1450, 1470 may be placed above the non-conductive insulator, attached to lead engagements, and a cap (not shown) may be placed above the frame opening to enclose the internal components of the device 1400 within the cavity.

[0167] although Figure 14 A Dougherty amplifier device 1400 is shown, comprising a single Dougherty amplifier die 1401 and corresponding leads. However, other embodiments of the Dougherty amplifier device may include multiple Dougherty amplifier dies placed side-by-side (e.g., multiple instances of die 1401), with corresponding sets of leads associated with each die. Using such a device, output RF signals from multiple Dougherty amplifier dies can be combined, for example, using a 3-dB coupler or other means (e.g., on a PCB to which the Dougherty amplifier device is coupled). Additionally, other embodiments of the Dougherty amplifier device may include a signal distributor (e.g., corresponding to...) located within the device package. Figure 2 Distributor 210) and / or phase shifter (e.g., Figure 2 Phase shifter 282).

[0168] Ultimately, the Dougherty amplifier unit 1400 is integrated into larger electrical systems (e.g., power transmitter arrays in cellular base stations). For example, as... Figure 15 As shown, the Dougherty amplifier device 1520 can be coupled to a system substrate such as a single-layer or multi-layer PCB 1501 to enable the Dougherty amplifier device 1520 (e.g., Figure 14The device 1400 is incorporated into the amplifier system 1500. In one embodiment, the Dougherty amplifier device 1520 includes a carrier signal input lead 1530 and a peaking signal input lead 1550 (e.g., Figure 14 Leads 1430, 1450) and output signal lead 1570 (e.g., Figure 14 Lead 1470), said lead is configured to connect the conductive features of PCB 1501 with a die enclosed within device 1420 (e.g., Figure 14 The bias voltage and RF signal are transmitted between the die 1401.

[0169] In one embodiment, PCB 1501 may be a single-layer or multi-layer PCB, and multiple components are coupled to PCB 1501. According to one embodiment, a conductive coin 1502 (or other feature) is embedded within PCB 1501, and the top and bottom surfaces of the conductive coin 1502 are exposed at the top and bottom surfaces of PCB 1501, respectively. Dougherty amplifier device 1520 (e.g., Figure 14 The device 1400 is connected to the conductive coin 1502. More specifically, the bottom surface of the Dougherty amplifier device 1520 (e.g., Figure 14 The bottom of the flange 1420 can be physically and electrically connected to the top surface of the conductive coin 1502. The conductive coin 1502 can then be electrically connected to the system ground, and the bottom surface of the coin 1502 can be physically connected to the system heat sink. Therefore, the conductive coin 1502 can serve as a ground reference and heat sink for the amplifier system 1500.

[0170] In a typical configuration, the amplifier system 1500 includes an input RF connector 1503 and an output RF connector 1504 coupled to a PCB 1501. The input RF connector 1503 and the output RF connector 1504 are respectively configured to receive an input RF signal from an RF signal source and generate an amplified output RF signal for transmission to a load (e.g., ...). Figure 1 The load 106 may be a cellular antenna coupled to the connector 1504.

[0171] PCB 1501 includes multiple conductive paths 1505, 1506, 1507, and 1572 electrically coupled between input RF connector 1503 and output RF connector 1504 and Dougher amplifier device 1520. Additional conductive paths (unnumbered) may be used to transfer DC gate and drain bias voltages from bias voltage connectors 1580, 1581, and 1582 to device 1520. For example, conductive paths and features on PCB 1501 may be formed by patterned portions of the top conductive layer, bottom conductive layer, and / or one or more internal conductive layers (if included) of PCB 1501.

[0172] In the illustrated embodiment, a first conductive path 1505 electrically connects an input RF connector 1503 to an input of a signal distributor 1510, which is configured to distribute the input RF signal transmitted via path 1505 into a first RF signal and a second RF signal (e.g., corresponding to a carrier input RF signal and a peaked input RF signal). The first and second RF signals are generated at two outputs of the signal distributor 1510, and are transmitted via a second conductive path 1506 and a third conductive path 1507 to a first RF input lead 1530 and a second RF input lead 1550 of a Dougherty amplifier device 1520, respectively. According to one embodiment, the signal distributor 1510 generates the first and second RF signals such that they have a phase difference of approximately 90 degrees. In other embodiments, the phase difference may be imparted by a circuitry different from that of the signal distributor 1510.

[0173] The Dougherty amplifier device 1520 in the illustrated embodiment corresponds to one that does not include an integrated signal distributor (e.g., Figure 2 The signal distributor 1510 is a device for distributing the input RF signal into a first RF signal and a second RF signal (e.g., a carrier RF signal and a peaked RF signal). In an alternative embodiment, the Dougherty amplifier device 1520 may include an integrated signal distributor (e.g., a signal distributor 210). Figure 2 In the case of the distributor 210), the signal distributor 1510 can be excluded from the system 1500, and the input RF connector 1503 can be directly connected to a single input lead through a single conductive path.

[0174] As discussed in detail above, the Dougherty amplifier die within the Dougherty amplifier device 1520 amplifies one or more input RF signals to output at lead 1570 (e.g., Figure 14 An amplified output RF signal is generated at lead 1470. An additional conductive path 1572 on PCB 1501 electrically connects the output RF signal lead 1570 of the Dougherty amplifier device 1520 to the output RF connector 1504. Therefore, during operation of system 1500, the amplified RF signal generated by the Dougherty amplifier device 1520 is transmitted to the output RF connector 1504 via conductive path 1572.

[0175] although Figure 15 The system shown depicts a Dougherty amplifier device 1520 mounted on PCB 1501, but in other embodiments, the Dougherty die (e.g., Figure 3-13The dies 301, 601, 701, 801, 901, 1001, 1101, 1201, and 1301 can be directly mounted to a PCB to form a compact Dougherty amplifier module. For example, such a module may include a multilayer PCB; conductive bonding pads or bottom-side solder areas configured to transmit RF input and output signals; and Dougherty dies (e.g., ...) mounted to the surface of the PCB. Figure 3-13 The module may include: any one of the dies 301, 601, 701, 801, 901, 1001, 1101, 1201, and 1301; an embedded heatsink (e.g., a copper coin or thermal via in a PCB) mounted above the Dougherty die; a surface-mount or lumped element signal distributor having an RF input and two outputs (carrier output and peaking output); conductive paths (e.g., printed traces formed by a patterned conductive layer of the PCB) between the RF input and the signal distributor, between the signal distributor and the Dougherty die (e.g., one path for the carrier signal and one path for the peaking signal), and between the Dougherty die and the output signal solder pads or bonding pads; and an input-side phase shifter (approximately 90 degrees) along one of the conductive paths between the distributor and the Dougherty die. The module may also include a bias voltage circuit or path (to receive a bias voltage from an external circuit system).

[0176] Figure 16 This refers to the manufacture of a Dougherty power amplifier die according to an example embodiment (e.g., Figure 3-13 301, 601, 701, 801, 901, 1001, 1101, 1201, 1301); packaged Dougherty amplifier devices (e.g., Figure 14 The device 1400) and the Dougherty amplifier system (e.g., Figure 15 A flowchart of a method for system 1500. The method can be implemented in block 1602 by forming an amplifier die (e.g., Figure 3-13 Starting with 301, 601, 701, 801, 901, 1001, 1101, 1201, 1301), the amplifier die includes an integrated carrier amplifier and a peaking amplifier, the carrier amplifier and the peaking amplifier including interdigitated carrier amplifier fingers and peaking amplifier fingers, as described in detail above.

[0177] In box 1604, the Dougherty amplifier die can then be packaged. As previously mentioned, the Dougherty amplifier die can be packaged in a molded or cavity package. Alternatively, the Dougherty amplifier die can be attached as a bare die to a system substrate (e.g., a module or PCB substrate). When packaged in a molded package (e.g., Figure 14When packaged in a cavity package (1404), the Dougherty amplifier die can be connected to the conductive flange of the lead frame, wire bonding can be coupled between the input and output leads of the lead frame and the appropriate bonding pads of the Dougherty amplifier die, and the flange, leads, and Dougherty amplifier die can be sealed in molding material. When packaged in a cavity package, the insulator frame can be attached to the top surface of the conductive flange, the Dougherty amplifier die can be connected to the top surface of the flange in the frame opening, the input and output leads can be connected to the top surface of the insulator frame, wire bonding can be coupled between the input and output leads and the appropriate bonding pads of the Dougherty amplifier die, and a cap can be applied over the flange, insulator frame, leads, wire bonding, and Dougherty amplifier die to enclose the Dougherty amplifier die in the cavity.

[0178] In box 1606, the amplifier system can be configured by using a Dougherty amplifier device (e.g., Figure 14 The device 1400 (or in some embodiments, a bare die) is attached to a PCB (e.g., Figure 15 The system substrate (such as PCB 1501) is used for this purpose. More specifically, the bottom surface of the Dougherty amplifier device can be connected to a conductive coin (e.g., Figure 15 Coin 1502) to provide a ground reference and heat sink for the device, and the input and output leads of the device can be connected to the corresponding conductive paths of the system substrate (e.g., Figure 15 Paths 1505-1507, 1572).

[0179] According to one embodiment, additional components (e.g., Figure 15 The distributor 1510 can be coupled to the system substrate (e.g., Figure 15 The amplifier system is then completed using PCB 1501. The method can then be terminated.

[0180] One embodiment of a multipath amplifier includes: a semiconductor die; a first amplifier input, a second amplifier input, and an amplifier output, the first amplifier input, the second amplifier input, and the amplifier output being integrally formed with the semiconductor die; and at least two amplifier units positioned between the amplifier input and the amplifier output. The at least two amplifier units are positioned adjacent to each other. Each of the at least two amplifier units includes a first transistor and a second transistor integrally formed with the semiconductor die. The first transistor has a first transistor input and a first transistor output, wherein the first transistor input is coupled to the first amplifier input. The second transistor has a second transistor input and a second transistor output, wherein the second transistor input is coupled to the second amplifier input. Each amplifier unit further includes a combination node coupled to the second transistor output and coupled to the amplifier output, and a first phase-shifting element is electrically connected between the first transistor output and the combination node.

[0181] Another embodiment of the amplifier includes a semiconductor die; a first input signal manifold located at the input side of the semiconductor die and integrally formed with the semiconductor die; a second input signal manifold located at the input side of the semiconductor die and integrally formed with the semiconductor die; an output signal manifold located at the output side of the semiconductor die and integrally formed with the semiconductor die; and at least two amplifier units located between the input side and the output side of the semiconductor die. The at least two amplifier units are positioned adjacent to each other. Each of the at least two amplifier units includes a first transistor integrally formed with the semiconductor die, a second transistor integrally formed with the semiconductor die, a combination node, and a phase shifting element. The first transistor has a first transistor input and a first transistor output, wherein the first transistor input is coupled to the first amplifier input. The second transistor has a second transistor input and a second transistor output, wherein the second transistor input is coupled to the second amplifier input. The combination node is coupled to the second transistor output and coupled to the amplifier output. The phase-shifting element is electrically connected between the output of the first transistor and the combined node.

[0182] According to another embodiment, the amplifier is a Dougherty power amplifier, the first transistor is a carrier amplifier or a peaking amplifier, and the second transistor is the other of the carrier amplifier or the peaking amplifier. According to yet another embodiment, the first transistor is a first elongated field-effect transistor finger, the second transistor is a second elongated field-effect transistor finger, and the phase-shifting element is an inductor.

[0183] The connecting lines shown in the various figures included herein are intended to illustrate exemplary functional relationships and / or physical couplings between various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in embodiments of this subject matter. Furthermore, certain terms may be used herein for reference only and are therefore not intended to be limiting, and the terms “first,” “second,” and other such numerical terms relating to structures do not imply a sequence or order unless the context clearly indicates otherwise.

[0184] As used herein, "node" means any internal or external reference point, connection point, junction, signal line, conductive element, etc., where a given signal, logic level, voltage, data pattern, current, or quantity exists. Furthermore, two or more nodes can be implemented by a single physical element (and even if received or output at a common node, two or more signals can be multiplexed, modulated, or otherwise distinguished).

[0185] The foregoing description refers to elements, nodes, or features that are “connected” or “coupled” together. As used herein, unless otherwise explicitly stated, “connected” means that one element is directly and not necessarily mechanically engaged to (or directly connected to) another element. Similarly, unless otherwise explicitly stated, “coupled” means that one element is directly or indirectly and not necessarily mechanically engaged to (or directly or indirectly connected to) another element via electrical or other means. Therefore, although the schematic diagrams shown in the accompanying drawings depict an exemplary arrangement of elements, additional intermediate elements, devices, features, or components may be present in embodiments of the subjects depicted.

[0186] As used herein, the terms “exemplary” and “example” mean “serving as an example, instance, or illustration.” Any embodiment described herein as exemplary or illustrative is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, it is not intended to be bound by any express or implied theory presented in prior art, background technology, or specific embodiments.

[0187] While at least one exemplary embodiment has been presented in the foregoing detailed descriptions, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed descriptions will provide those skilled in the art with a convenient roadmap for implementing one or more of the described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, including known and foreseeable equivalents at the time of filing this patent application.

Claims

1. A multipath amplifier, characterized in that, include: Semiconductor die; A first input signal manifold is located at the input side of the semiconductor die and is integrally formed with the semiconductor die, wherein the first input signal manifold is coupled to the input terminal of a first amplifier; A second input signal manifold is located at the input side of the semiconductor die and is integrally formed with the semiconductor die, wherein the second input signal manifold is coupled to the input terminal of the second amplifier; An output signal manifold, the output signal manifold being positioned at the output side of the semiconductor die and integrally formed with the semiconductor die, wherein the output signal manifold is coupled to the amplifier output terminal; and At least two amplifier units are positioned between the input side and the output side of the semiconductor die, wherein the at least two amplifier units are positioned adjacent to each other, and each of the at least two amplifier units includes: A first transistor is integrally formed with the semiconductor die, wherein the first transistor has a first transistor input and a first transistor output, wherein the first transistor input is coupled to the input of the first amplifier; A second transistor is integrally formed with the semiconductor die, wherein the second transistor has a second transistor input and a second transistor output, wherein the second transistor input is coupled to the input of the second amplifier; A combination node, the combination node being coupled to the output of the second transistor and coupled to the output of the amplifier; and A first phase shift element is electrically connected between the output of the first transistor and the combined node.

2. The multipath amplifier according to claim 1, characterized in that, The first phase-shifting element includes: A first inductor, wherein a first end of the first inductor is coupled to the output of the first transistor, and a second end of the first inductor is coupled to the combined node.

3. The multipath amplifier according to claim 2, characterized in that, The first inductor is a spiral inductor integrally formed with the semiconductor die.

4. The multipath amplifier according to claim 2, characterized in that, The first inductor is a discrete inductor coupled to the top surface of the semiconductor die.

5. The multipath amplifier according to claim 2, characterized in that, The inductance value of the first inductor is in the range of 0.1 nanohenries to 20 nanohenries.

6. The multipath amplifier according to claim 2, characterized in that: The first transistor is a first field-effect transistor including a first drain region, a first source region and a first gate terminal, wherein a first drain-source capacitance exists between the first drain region and the first source region, the first gate terminal is coupled to the input of the first transistor, and the first drain region is coupled to the output of the first transistor; The second transistor is a second field-effect transistor including a second drain region, a second source region, and a second gate terminal, wherein a second drain-source capacitance exists between the second drain region and the second source region, the second gate terminal is coupled to the input of the second transistor, and the second drain region is coupled to the output of the second transistor. The first drain-source capacitor, the second drain-source capacitor, and the first inductor cause a 90-degree phase delay, which is imparted to the radio frequency signal transmitted between the first drain region and the combined node.

7. The multipath amplifier according to claim 1, characterized in that: The first transistor is a first field-effect transistor including a first transistor finger, the first transistor finger including an elongated first drain region, an elongated first source region and an elongated first gate terminal, wherein the first gate terminal is coupled to the first transistor input and the first drain region is coupled to the first transistor output. and The second transistor is a second field-effect transistor including a second transistor finger, the second transistor finger including an elongated second drain region, an elongated second source region and an elongated second gate terminal, wherein the second gate terminal is coupled to the input of the second transistor and the second drain region is coupled to the output of the second transistor.

8. The multipath amplifier according to claim 7, characterized in that, The first length of the first transistor finger is shorter than the second length of the second transistor finger.

9. The multipath amplifier according to claim 8, characterized in that, The first transistor finger and the second transistor finger have input ends aligned along a first line perpendicular to the first length of the first transistor finger and the second length of the second transistor finger. The second transistor finger has an output end aligned along a second line perpendicular to the first length of the first transistor finger and the second length of the second transistor finger. The first phase shift element is positioned between the output end of the first transistor finger and the second line.

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