Multi-level coding in the field of battery management systems

Abstract

A battery management system includes a first battery cell controller, a second battery cell controller each monitoring a plurality of battery cells, and an electrically isolated transmission line providing a point-to-point signal transmission path between the first battery cell controller and the second battery cell controller. At least one of the first battery cell controller or the second battery cell controller includes at least one encoding / decoding circuit that encodes data in accordance with a multi-level encoding technique for transmission along the signal transmission path as a serial data stream, including modulating the serial data stream on at least three discrete signal levels at a predetermined and fixed data pulse frequency, encoding a plurality of data nibbles of the serial data stream into a data packet, the data packet including a plurality of symbols structured and arranged to have at least four consecutive chips per symbol, wherein the at least four consecutive chips per symbol of the data packet include a DC balance line code in each of the symbols.

Description

Technical Field

[0001] This disclosure generally relates to battery management systems for electric vehicles, and more specifically, to encoding and decoding techniques for the physical layer of data transmission in battery management systems to which communication protocols can be applied. Background Technology

[0002] In battery management systems (BMS) applications, electronic systems have been developed to monitor the arrangement of lithium-ion battery cells, etc. These systems store and output the energy required by various vehicle electronics (also known as automotive electronic control units) to operate the electric vehicle, for example, by controlling the charging and discharging functions of the battery cells. A BMS typically includes one or more battery cell controllers mounted in series, each configured and arranged to control several battery cells. The battery cell controllers communicate with a microcontroller unit (MCU), which provides the system's intelligence to control and monitor the state of the battery cells, such as their normal operating condition, and can prevent attempted operation of faulty battery cells.

[0003] As the amount of data that needs to be transmitted between different automotive electronic control units in a vehicle continues to grow, reliable and high-speed data transmission is required between battery cell controllers that manage battery cells. Summary of the Invention

[0004] The appended claims define aspects of this disclosure.

[0005] In a first aspect, a battery management system is provided, comprising: a first battery cell controller; a second battery cell controller, the first and second battery cell controllers each monitoring a plurality of battery cells; and an electrically isolated transmission line providing a point-to-point signal transmission path between the first and second battery cell controllers, wherein at least one of the first or second battery cell controllers includes at least one encoding / decoding circuitry that encodes data according to a multilevel encoding technique for transmission as a serial data stream along the signal transmission path, including modulating the serial data stream at at least three discrete signal levels at a predetermined and fixed data pulse frequency, encoding a plurality of data nibbles of the serial data stream into data packets, the data packets including a plurality of symbols, the plurality of symbols being constructed and arranged such that each symbol has at least four consecutive chips, wherein each symbol of the data packet includes a DC balanced line code in each of the symbols.

[0006] In one or more embodiments, the battery management system may further include: a microcontroller unit that outputs the data to at least one of the first or second battery cell controllers and manages the serial data stream, including generating commands and outputting the commands to the encoding / decoding circuit to control the conversion between the at least three discrete signal levels.

[0007] In one or more embodiments, the battery management system may further include: a driver circuit between the microcontroller unit and the transmission line, the driver circuit reading a plurality of sequential bits from the MCU and translating the plurality of sequential bits into a multi-bit word to output as pulse bit data to the transmission line.

[0008] In one or more embodiments, the transmission line may include: a first transformer isolation circuit coupled to the first battery cell controller; a second transformer isolation circuit coupled to the second battery cell controller; and a twisted-pair cable extending between the first and second transformer isolation circuits.

[0009] In one or more embodiments, the battery management system may further include logic circuitry, which includes the at least one encoding / decoding circuit and a logic device that translates each symbol into a multi-bit word to be output as the serial data stream to one of the first or second transformer isolation circuits.

[0010] In one or more embodiments, the at least four consecutive chips per symbol may include four consecutive transmissions per symbol.

[0011] In one or more embodiments, the first or second battery cell controller may include an adaptive multilevel transceiver, the adaptive multilevel transceiver including a transmission circuit, a receiving circuit, and logic circuitry including registers, the logic circuitry processing configuration bits controlling at least one of the transmission circuit or the receiving circuitry to change from a first number of signal levels of the multilevel encoding technique to a second number of signal levels of the multilevel encoding technique to adapt to the determined integrity of the transmission line.

[0012] In one or more embodiments, the first number of signal levels may be three signal levels, and the second number of signal levels may be five signal levels.

[0013] In one or more embodiments, the at least one encoding / decoding circuit can transmit each of the symbols, each of the symbols being transmitted via the four consecutive chips.

[0014] In one or more embodiments, the at least one encoding / decoding circuit can encode the three-bit word of the data packet in two cycles.

[0015] In one or more embodiments, the three-bit word can be encoded with four chips per symbol.

[0016] In one or more embodiments, the plurality of symbols may include eight symbols, and for each of the eight symbols, the at least one encoding / decoding circuit may encode a three-digit word in two cycles.

[0017] In one or more embodiments, the data packet does not include reserved bits and includes the same number of consecutive transmissions having -1 and +1 levels or -2 and +2 levels, and the sum of chips corresponding to the same number of consecutive transmissions must be null.

[0018] In one or more embodiments, the at least one encoding / decoding circuit may include: a first-in-first-out (FIFO) memory that reads a predetermined number of sequential bits from the serial data stream and translates the predetermined number of sequential bits into a multi-bit word; and an encoder / decoder that translates the multi-bit word into a symbol comprising pulse-coded symbols comprising the at least four consecutive chips per symbol.

[0019] In a second aspect, a semiconductor device is provided, comprising: a bidirectional transceiver; and logic circuitry configured and arranged to encode data to output from the bidirectional transceiver along a signal transmission path as a serial data stream modulated at at least three discrete signal levels at a predetermined and fixed data pulse frequency, the logic circuitry encoding a plurality of data nibbles of the serial data stream into data packets, the data packets comprising at least three symbols, the at least three symbols being configured and arranged such that each symbol has at least four consecutive chips, each chip employing one of the three discrete signal levels; wherein the at least three symbols are encoded into a subset of a maximum number of possible combinations of the at least three discrete signal levels, and wherein the circuitry discards any of the maximum number of possible combinations.

[0020] In one or more embodiments, the logic circuit may include the at least one encoding / decoding circuit and a logic device that translates each symbol into a multi-bit word to be output as the serial data stream to the transformer isolation circuit.

[0021] In one or more embodiments, the at least one encoding / decoding circuit may include: a first-in-first-out (FIFO) memory that reads a predetermined number of sequential bits from the serial data stream and translates the predetermined number of sequential bits into a multi-bit word; and an encoder / decoder that translates the multi-bit word into a symbol comprising pulse-coded symbols comprising the at least four consecutive chips per symbol.

[0022] In one or more embodiments, the semiconductor device may further include an adaptive multilevel transceiver, the adaptive multilevel transceiver including transmission circuitry, reception circuitry, and logic circuitry including registers, the logic circuitry processing configuration bits that control at least one of the transmission circuitry or the reception circuitry to change from a first number of signal levels of the multilevel encoding technique to a second number of signal levels of the multilevel encoding technique to adapt to the determined integrity of the signal transmission path.

[0023] In a third aspect, a method for encoding data bits onto a transmission bus is provided, comprising: configuring a battery cell controller to output a serial data stream to an electrically isolated transmission line; modulating the serial data stream at at least three discrete signal levels at a predetermined and fixed data pulse frequency; encoding a plurality of data nibbles of the serial data stream into data packets, the data packets comprising at least three symbols, the at least three symbols being constructed and arranged such that each symbol has at least four consecutive chips; and discarding combinations of the at least three discrete signal levels to provide a DC balanced line code within each of the symbols.

[0024] In one or more embodiments, the method may further include: reading a predetermined number of sequential bits of the serial data stream and translating the predetermined number of sequential bits into a multi-bit word; and translating the multi-bit word into a symbol comprising a pulse-coded symbol comprising the at least four consecutive chips per symbol. Attached Figure Description

[0025] The invention is illustrated by way of example and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. The elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0026] Figure 1 This is a block diagram of a battery management system according to an exemplary embodiment of the present disclosure.

[0027] Figure 2 It includes those used for Figure 1 A schematic diagram of the physical layer interface between two battery cell controllers in the electrically isolated bus communication of the battery management system.

[0028] Figure 3This is a block diagram of the detailed physical layer interface of a battery cell controller according to an exemplary embodiment of this disclosure.

[0029] Figure 4 This is a flowchart illustrating a three-level encoding method performed by a battery management system according to an exemplary embodiment of this disclosure.

[0030] Figure 5 This is an illustrative example of a three-symbol data packet encoded with three signal levels according to an exemplary embodiment of this disclosure.

[0031] Figure 6 It is a data encoding table for three-digit words according to an example embodiment of this disclosure.

[0032] Figure 7 This is a graphical view of the simulation results of the three-level differential voltage at the receiver input of the transceiver of the battery cell controller according to an exemplary embodiment of this disclosure.

[0033] Figure 8 This is an illustrative example of a two-symbol data packet corresponding to sixteen chips or data bits and encoded with three signal levels, according to an exemplary embodiment of this disclosure.

[0034] Figure 9 This is an illustrative example of the code for a data encoding table according to an exemplary embodiment of this disclosure.

[0035] Figure 10 This is a flowchart illustrating a multilevel encoding method for a battery management system according to an exemplary embodiment of the present disclosure.

[0036] Figure 11 This is an illustrative example of a three-symbol data packet encoded with five signal levels according to an exemplary embodiment of this disclosure.

[0037] Figure 12 This is a data encoding table based on an example embodiment of this disclosure.

[0038] Figure 13 This is a graphical view of the simulation results of the five-level differential voltage at the receiver input of the transceiver of the battery cell controller according to an exemplary embodiment of this disclosure.

[0039] Figure 14 This is a schematic diagram of a battery cell controller with two adaptive multilevel transceivers according to an exemplary embodiment of this disclosure.

[0040] Figure 15 yes Figure 14 The circuit diagram of the adaptive multilevel transmission circuit.

[0041] Figure 16 This is a receiver decoding data table according to an example embodiment of this disclosure. Detailed Implementation

[0042] In short, embodiments of the present invention concept include multilevel data encoding techniques for communication protocols used in battery management system applications, which exchange data between a physical layer interface communicating with upstream battery cell controller electronics and another physical layer interface communicating with downstream battery cell controller electronics and / or between a battery cell controller and a microcontroller unit (MCU). Compared to conventional battery management systems, the features of the present invention concept provide increased data communication speeds to accommodate the growing data transfer demands between electronic components in electric and hybrid vehicles. In some embodiments, the innovative multilevel data encoding techniques include adaptive multilevel data encoding techniques and corresponding physical layers supporting the data encoding techniques. Furthermore, data encoding techniques are included when using electrically isolated buses comprising magnetically and electrically coupled transformers to accommodate point-to-point differential transmission lines. In some embodiments, the data encoding techniques include three (3) signal level decoding techniques, wherein a data nibble is encoded into multiple symbols, which in turn encode information into multiple bits (specifically, three-bit or eight-bit words). In other embodiments, the data encoding techniques include five (5) signal level decoding techniques, wherein a data nibble is encoded into multiple symbols, which in turn encode information into five bits. In some embodiments, a system is provided to increase the communication data speed in an electronic circuit by expanding the number of chips in a symbol from 4 to 8 or more. In some embodiments, a system is provided to increase the communication data speed by increasing the number of signal encoding levels from 3 to 5 or more.

[0043] Figure 1 This is a schematic diagram illustrating an embodiment in which the inventive concept can be practiced.

[0044] like Figure 1 As shown, the battery management system includes a first battery cell controller 102, a second battery cell controller 104, and / or a dedicated hardware processor such as a microcontroller unit (MCU) that provides intelligence to the system, such as managing and controlling multiple battery cell controllers. Although two battery cell controllers are shown, according to some embodiments, the battery management system includes more than two battery cell controllers configured to communicate serially with each other, i.e., also connected in a daisy-chain configuration to one or more battery cell controllers (n). The battery management system is not limited to... Figure 1 The aforementioned elements, and may include, except for Figure 1 Components, features, and functions other than those shown.

[0045] The battery management system is configured and arranged to perform synchronous battery voltage / current measurements, coulomb counting, battery temperature measurements, and integrated battery balancing, verification of measurement integrity, and / or other functions related to vehicle battery monitoring, and to maximize vehicle battery life, such as sensing physical quantities of the lithium-ion battery, monitoring battery functions to verify the integrity of battery measurements, etc. Each of the first battery cell controller 102 and the second battery cell controller 104 can monitor a battery pack comprising multiple battery cells, such as 6 to 18 cells, but not limited thereto. In doing so, data communication is established between the first battery cell controller 102, the second battery cell controller 104, and the microcontroller unit (MCU) 106. An electrically isolated transmission line or bus 110 may extend between the first battery cell controller 102 and the second battery cell controller 104, and / or between at least one of the battery cell controllers 102, 104, and the MCU 106 to provide point-to-point differential communication between these various circuits. In some embodiments, the battery cell controllers 102 and 104 are co-located in the same module, circuit board, housing, etc. In some embodiments, at least one of the battery cell controllers 102, 104 and MCU 106 is located in the same module, circuit board, housing, etc.

[0046] In some embodiments, the battery management system includes driver circuitry having a Serial Peripheral Interface (SPI) / Transformer-isolated (TPL) transceiver 105 between the MCU 106 and two other battery cell controllers 102 in a daisy-chain configuration. The SPI / TPL transceiver 105 is configured and arranged to receive data from the MCU 106 via a Serial Peripheral Interface 112, connect the MCU 106 to a high-speed isolated communication network including electrically isolated transmission lines 110, and convert data to be output to the battery cell controllers 102 via the transmission lines 110. The SPI / TPL transceiver 105 (also referred to as driver circuitry) includes a physical layer transceiver configured and arranged to connect a microcontroller, such as the MCU 106, to the high-speed isolated communication network including the transmission lines 110.

[0047] like Figure 2As shown, transmission line 110 uses transformer isolation circuitry 204 between upstream bidirectional transceiver 212 of battery cell controller 102 in transmitter mode and downstream bidirectional transceiver 222 of battery cell controller 104 in receiver mode to provide high-speed point-to-point differential isolation communication. Data communication is exchanged between battery cell controller 102 and battery cell controller 104, as indicated by the arrows. Because the communication is bidirectional, upstream transceiver 212 of battery cell controller 104 can operate in receiver mode and transmit data via logic circuitry 221 to downstream transceiver 222 of battery cell controller 104, which operates in transmitter mode. Data is output from battery cell controller 104 to battery cell controller 102 via transmission line 110 in the opposite direction of the arrows, and transceiver 212 of battery cell controller 102 switches to its receiver mode. As data propagates from one battery cell controller to another via a daisy chain through the downstream and upstream transceivers of each battery cell controller, the integrity of the data signal is not lost, and transmission is ensured by unattenuated messages. The twisted-pair cable 202 of the transmission line ensures the connection between the two battery cell controllers located on different boards in the vehicle. Transformer circuit 204A allows DC isolation between the twisted-pair cable 202 and battery cell controller 102, while transformer circuit 204B allows DC isolation between the twisted-pair cable 202 and battery cell controller 104. This provides electrical protection for the battery cell controllers 102 and 104 against any transient voltages or improper electrical connections present on the twisted-pair cable 202.

[0048] Figures 1 to 3 The communication shown conforms to a communication protocol that forms a physical layer between the physical interfaces of battery cell controllers 102, 104 and MCU 106, respectively. The physical layer of the communication protocol stack may include a physical signaling sublayer, wherein encoding, transmission, decoding and electrical isolation functions are performed between battery cell controllers 102, 104 and / or between battery cell controllers 102 and / or 104 and MCU 106 to disrupt ground loops and prevent improper flow of direct current (DC) in the daisy chain, and to ensure proper discharge of the transformer of bus 110 without DC offset.

[0049] Figure 3 This is a block diagram of the logic circuit of the battery cell controller, for example... Figure 2 The shown battery cell controller 102 includes logic circuitry 211 and transceivers 212 and 222. Although the battery cell controller 102 is shown and described as a data transmission device, similar logic circuitry 221 and transceivers 212 and 222 of the battery cell controller 104 can also be used as a receiving device.

[0050] The bus driver transceivers 212, 222 and the encoder / decoder circuit 266 may include components similar to the SPI / TPL transceiver 105 between the MCU 106 and the battery cell controller 102.

[0051] like Figure 3 As shown, in some embodiments, logic circuits 211 and 221 may each include, but are not limited to, a battery cell controller (BCC) logic device 250 and at least one encoder / decoder circuit 266. As illustrated, one encoder / decoder circuit 266 may communicate with the transceiver's transmit driver 212, while the other encoder / decoder circuit 266 may communicate with the transceiver's receive driver 222. The BCC logic device 250 provides global control logic functions for the battery cell controller, such as battery cell equalization, current chain measurement, and voltage cell measurement.

[0052] Each encoding / decoding circuit 266 may include, but is not limited to, a first-in-first-out (FIFO) memory 252 and an encoder / decoder 254. Figure 1 The bidirectional transceivers 212, 222 of the illustrated SPI / TPL transceiver 105 and / or battery cell controllers 102, 104 may include encoder / decoder circuitry 266, and therefore may include bit memory 152 and encoder / decoder circuitry 154. Bit memory device 252, such as a first-in-first-out (FIFO) memory, can read a plurality of sequential bits received from MCU 106 and translate the plurality of sequential bits into a multi-bit word. Encoder / decoder 254 translates the word into a multi-level pulse-coded symbol comprising four or more consecutive transmissions or chips. In some embodiments, encoder / decoder 254 stores and / or otherwise processes, for example, in... Figure 9 Alternatively, the data in the encoder / decoder table in 12. In response, the encoder / decoder 254 outputs a binary level corresponding to the symbol transmission on the high and low inputs of the analog interface of the transceiver 212.

[0053] The following provides an example of the operation of a battery management system, including data exchange between an MCU 106 and battery cell controllers 102 and / or 104. An SPI / TPL transceiver 105 receives a plurality of bits 1, 0, 0, 1, 1 sequentially output from the MCU 106 via a serial peripheral interface 112. The SPI / TPL transceiver 105 includes a transformer driver for the transceiver physical layer, which is configured and arranged to connect a microcontroller, such as the MCU 106, to a high-speed isolated communication network including a transmission line 110. In doing so, data bits are directly converted into pulse bit information by the SPI / TPL transceiver 105 and transmitted to the transmission line 110. In this example, the SPI / TPL transceiver 105 reads five sequential bits received from the MCU 106 and translates these five sequential bits into a 5-bit word (10011). The SPI / TPL transceiver 105 then translates the five-bit word (10011) into a multi-level pulse-coded symbol comprising four consecutive transmissions, or into a symbol configured to handle five different levels (e.g., 0, 1, 2, -1, -2) (see [link to SPI]). Figure 6 The chip (Table 500) is used. In response, binary levels corresponding to symbol transmissions (e.g., high, low) of the analog interface of the SPI / TPL transceiver 105 are generated. The analog interface outputs analog signals by activating or deactivating pull-up and / or pull-down circuits at each analog output. The resulting pull-up and pull-down paths allow the generated current to flow through transmission line 110 into the bus termination resistor.

[0054] The following provides another example of the operation of the battery management system, which includes data exchange between BCC 102 and BCC 104 via transmission line 110: BCC 102 (or 104) receives analog signals via transmission line 110. The analog interface of the receiving transceiver 222 uses pull-up / pull-down voltage circuits, etc., to convert signals (e.g., high: 0, 1, 0, 1; low: 0, 0, 2, 0) so that the decoding circuit 266 can translate the output of the analog interface of the transceiver 222 into a multilevel pulse-coded symbol comprising four consecutive transmissions or chips (e.g., 0, 1, -2, -1), which is then output to the battery cell controller (BCC) logic device 250, which translates the symbol into a five-bit word (10011).

[0055] As described herein, the embodiments are not limited to the processing of five signal levels. For example, Figure 4 It is shown by Figures 1 to 3 The flowchart of the three-level encoding method 300 executed by the battery management system.

[0056] During the operation, in box 302, will Figures 1 to 3The battery management system shown is constructed and arranged for three-level encoding, which involves, for example, using three different signal levels (e.g., -1, 0, +1), such as voltage, current, or amplitude levels, depending on the level transitions, transmitting and receiving binary numbers, such as 1 or 0 bits corresponding to data packets or other data units. For example, the encoding circuitry of the battery management system encodes logic (1) or (0) bits corresponding to the voltage level transitions between the different signal levels. In other embodiments, the encoding / decoding circuitry 266 of the battery management system performs the relevant encoding functions when exchanging signal information with bus 110.

[0057] In some embodiments, the battery management system includes a three-level encoding circuit for an SPI / TPL transceiver 105 between the MCU 106 and the battery cell controller 102, for generating signal levels corresponding to successive chips and providing symbols for arranging data for output to the isolation transmission line 110. In some embodiments, the three-level encoding circuit is part of the battery cell controllers 102, 104, and / or other battery cells.

[0058] In block 304, multiple data units, such as nibbles, are generated. In some embodiments, the data nibbles of a data unit are three-bit words embedded in a symbol. Data nibbles are generated from five signal levels (-1, 0, 1) to be encoded into three symbols, such as a three-symbol data packet comprising 9 bits of data. The pulse-coded symbols are then encoded into signal levels to form a set of three-bit words, such as each symbol corresponding to one three-bit word.

[0059] In box 306, four consecutive transmissions are generated for each symbol, referred to as the 1st to 4th "chips". Each chip uses one of three discrete levels for encoding positive, negative, and zero signal pulses, respectively. Figure 5 As shown. In some embodiments, the data pulse is a single-cycle pulse wave based on a phase indicator logic 1 or 0 value.

[0060] In some embodiments, as shown in block 308, each symbol encodes 3 bits of information. The data encoding table may include combinations of signal levels or values ​​that are identified, translated, or otherwise established according to predetermined computer standards, protocols, guidelines, etc. In block 310, the data encoding table is constructed and arranged such that undesirable combinations lacking DC balanced codes are discarded, for example, as illustrated herein by way of example.

[0061] As mentioned above, Figures 1 to 3 The system shown can be constructed and configured for use with other decoding techniques. Figure 4 Method 300 describes one such technique, but is not limited thereto. For example, in Figure 5As shown in Figure 350, other embodiments may include a three-level decoding technique applied to a three-symbol data packet comprising nine (9) data bits, wherein each symbol encodes information for a three (3)-bit word. The communication protocol defines the number of data bits in each message, which is related to the number of symbols per message. For example... Figure 5 As shown, each symbol transmitted via four (4) chips encodes three (3) bits of information in two (2) cycles at a fixed data pulse frequency, for a total of 12 chips or 9 data bits. In contrast, conventional encoding techniques transmit one (1) bit in two (2) cycles. Therefore, reference Figure 10 The described embodiments provide speed improvements of at least three times compared to conventional encoding techniques of this type. For example, a 4.0 MHz frequency used by the physical layer of a communication protocol can produce a data communication speed of 6.0 Mbps. Therefore, if the circuit is configured for a specific fixed frequency, such as 4.0 MHz, no hardware modifications are required, and no modifications are needed to the design circuitry that produces the fixed frequency. Other configurations can similarly apply, for example, a three-level decoding method, where a data nibble is encoded into a symbol formed by three consecutive transmissions, where each symbol encodes four bits of information or content in 1.5 cycles. Regardless of the configuration, the embodiments do not permit DC-balanced code operation, which uses a transformer and / or capacitive isolation bus 110 to provide relevant parameters to the physical layer of the data protocol, to perform the data encoding techniques according to the guidelines of this data encoding technique.

[0062] In some embodiments, there may be four consecutive three-level chips (i.e., 3). 4 The system has 81 (81) combinations. As previously mentioned, information about these combinations can be stored in the registers of the control logic of the battery cell controller, which can discard various combinations of four consecutive multilevel chips to avoid saturation of the isolation transformer and perform DC balancing linecode operation within each of the three symbols. In doing so, the system conforms to a set of predetermined criteria for discarding undesirable combinations, for example, establishing a criterion for discarding all combinations containing the same value (1, 0, -1), thus ensuring that any response packet has at least one transition in each symbol. Another criterion can be established to discard all combinations containing a chip at the value (-1) but without an adjacent chip at the value (-1). These last two features allow the system to prevent saturation of the isolation transformer 204 and perform DC balancing linecode operation within each symbol.

[0063] After discarding undesirable combinations, eight remaining possible combinations can be executed to allow for... Figure 6 The data decoding table 360 ​​shows the encoding of multi-bit pairs of information.

[0064] Figure 7Graphical view 370 shows the output of transmitter TX 212 of n-level battery cell controller 102 according to an example embodiment of the present disclosure. Figure 10 The differential voltage seen at the input of the receiver RX of the transceiver 222 of the n+1 stage battery cell controller 104 after the encoded data is shown. The numbers shown in graphical view 1200 are... Figure 6 This corresponds to Table 360. Data encoding Table 360 ​​is a three-word representation of the four chips for each symbol. A message can be formed from several consecutive symbols, where Y is the number of symbols and 3*Y represents the number of data bits to be transmitted. At the end of consecutive symbols within a message, no reserved bits are needed to perform DC balanced line coding because each message contains the same number of chips with -1 and +1 levels due to the undesirable combination of consecutive levels discarded from the symbols.

[0065] In some embodiments, encoder / decoder circuitry 266 contains combinational or other codes for accessing register tables stored at encoding circuitry or other components in the system to perform four, eight, or more consecutive transmissions, thereby increasing data communication speed. In some embodiments, registers of the control logic of battery cell controllers 102, 104 may include one or more data bits configured to discard all of 6561 possible combinations of eight consecutive three-level chips according to one or more criteria described herein. After discarding such combinations, 256 combinations may be retained for operation.

[0066] Refer again Figure 8 Examples of two-symbol data packets corresponding to 16 chips or 16 data bits are shown in some embodiments. Figure 9 Data decoding table 480 shows eight consecutive chips or a set of eight-bit words over a given symbol. More specifically, table 480 shows 32 of the first 256 codes. Information about these combinations can be stored in a storage device such as an encoding table memory, or in a register in the control logic of the battery cell controllers 102, 104. Signals ensure that any response packet has at least one transition and follows a set of predetermined criteria (e.g., the above regarding...). Figure 9 The criteria described in Table 480 are used to discard combinations, such as combinations with the same value, to avoid saturation of the isolation transformer of bus 110, and DC balancing is performed for each symbol. In some embodiments, each symbol can encode eight-bit words of information into four cycles at a fixed frequency (e.g., 4 MHz), resulting in a data communication speed of 8 Mbps. Related encoding techniques can be performed on multi-bit words ranging from 2 to 8 bits or more in one or more cycles at a fixed frequency.

[0067] Figure 10 This is a flowchart illustrating a multilevel encoding method 500 for a battery management system according to some embodiments. Some or all of the method steps in the flowchart can be generated based on the above multilevel encoding architecture. In some embodiments, some or all of method 500 is executed by hardware circuitry of one or two battery cell controllers 102, 104 and / or MCU 106. For example, Figures 1 to 3 The coded logic circuit 211 and transceiver 212 of the battery cell controller 102 and the coded logic circuit 221 and transceiver 222 of the battery cell controller 104 may perform some or all of the methods in 500.

[0068] During the operation, in box 502, for example... Figures 1 to 3 The circuitry of the battery management system shown is constructed and arranged for multi-level encoding, for example, using five different signal levels (e.g., -2, -1, 0, +1, +2), such as voltage, current, or amplitude levels, depending on the level transitions, to transmit and receive binary numbers, such as 1 or 0 bits corresponding to data packets or other data units. For example, the battery management system's encoding / decoding circuitry 266 encodes logic (1) or (0) bits corresponding to the voltage level transitions between different signal levels. In other embodiments, the battery management system's encoding / decoding circuitry 266 performs relevant encoding functions when exchanging signal information with bus 110.

[0069] In some embodiments, the battery management system includes a multilevel encoding circuit for an SPI / TPL transceiver 105 between the MCU 106 and the battery cell controller 102, for generating signal levels corresponding to consecutive chips and providing symbols for arranging data for output to the isolation transmission line 110. In some embodiments, the multilevel encoding circuit is part of the battery cell controllers 102, 104, and / or other battery cells.

[0070] In block 504, multiple data units, such as nibbles, are generated. In some embodiments, the data nibbles of a data unit are five-bit words embedded in a symbol. Data nibbles are generated from five signal levels (-2, -1, 0, 1, 2) to be encoded into three symbols. The pulse-coded symbols are then encoded into signal levels to form a set of five-bit words.

[0071] In box 506, as Figure 11 As shown in Figure 450, four consecutive transmissions are generated for each symbol (1 to 3), referred to as the 1st to 4th "chips". Each chip uses one of five discrete levels for encoding positive, negative, and zero signal pulses, respectively. The data pulse is a single-cycle pulse wave based on a phase-indicating logic 1 or 0 value.

[0072] In some embodiments, as shown in box 508, each symbol encodes 5 bits of information. See, for example, [link to example]. Figure 12 , Figure 12 A data encoding table 580 is shown, comprising five bits per symbol in four chips. The data encoding table 580 includes combinations of signal levels or values ​​that are identified, translated, or otherwise established according to predetermined computer standards, protocols, guidelines, etc.

[0073] Refer again Figure 11 In Figure 450, a three-symbol data packet corresponds to twelve (12) chips or fifteen (15) data bits. The communication protocol defines the number of data bits in each message, which is related to the number of symbols per message. Referring again to block 308, in some embodiments, each symbol transmitted via four (4) chips encodes five (5) bits of information in two (2) cycles at a fixed data pulse frequency. In contrast, conventional encoding techniques transmit one (1) bit in two (2) cycles, which provides the present invention concept with a data communication speed that is five times faster than such conventional encoding techniques. For example, a 4.0 MHz frequency provided by MCU 106 and used by the physical layer of the communication protocol can produce a data communication speed of 10 Mbps (i.e., 4.0 MHz × two cycles / symbol × 5 bits). Therefore, if the circuit is configured for a specific fixed frequency, such as 4.0 MHz, the circuit does not require hardware modification, and Figures 1 to 4 and Figures 10 to 14 The embodiments of the described data encoding techniques can be applied to improve data communication speed without modifying the analog interface design circuit systems 212 and 222.

[0074] As shown in box 510, and again refer to Figure 12 Table 580, as shown, is a data encoding table constructed and arranged such that unwanted combinations that do not conform to predetermined criteria are discarded. The following is a set of criteria for discarding various combinations of four consecutive multilevel chips.

[0075] In some embodiments, there are 625 possible combinations of four consecutive five-level chips (see...). Figure 11 In this process, combinations containing the same value (2, 1, 0, -1, -2) are discarded, thus ensuring that any response packet has at least one transition in each symbol. Therefore, for example, when the system transmits "1" as +1 volt and "0" as -1 volt, low (DC) signal components are avoided, ensuring that the total number of "0" and "1" bits is approximately equal over certain intervals, thereby providing a DC balanced signal.

[0076] In some embodiments, of the 625 possible combinations of four consecutive five-level chips, all combinations without a DC balanced code are discarded. This corresponds to discarding all combinations when the sum of the levels of the four chips is not equal to zero. For example, Figure 11 The symbol (1) shown can be DC balanced, i.e., the sum of the four signal levels (2 + (-1) + (-1) + 0) = 0. This criterion allows the device to avoid saturation of the isolation transformers 204A, 204B (typically 204), or to ensure charge neutrality between the AC coupling capacitors in embodiments where capacitive isolation is part of transmission line 110. Therefore, the transmission configuration using capacitive and / or transformer isolation performs DC balanced decoding against the physical layer of the communication protocol stack.

[0077] After applying the above criteria, 60 combinations out of 625 possible combinations can be used. In some embodiments, 32 combinations are selected for a five-bit word with a current consumption parameter smaller than a predetermined threshold. For example, for drivers 212 and 222, signal levels of 2 and -2 consume more current than levels of +1 and -1, while for drivers 212 and 222, a signal level of 0 consumes no current. The remaining 28 combinations can be used for communication protocols, such as fields including message start, message end, security, etc.

[0078] like Figure 13 As shown in example graphical view 600, the transmitter TX of transceiver 211, which is daisy-chained to another battery cell controller 102, receives a differential voltage determined at the input of the receiver RX of transceiver 222 of battery cell controller 104. In this example, the first battery cell controller 102 is in a first stage (n), where n is an integer. After transmission in stage n, the voltage is received at the input of the receiver RX of transceiver 222 in stage n+1. Figure 13 The differential voltages are shown. In this example, the voltage thresholds of comparators RX1, RX2, RX3, and RX4 can be set to -1.5V for level -2, -800mV for level -1, +800mV for level +1, and 1.5V for level +2, but are not limited to these.

[0079] As mentioned above, Figure 12 Table 580 shows a data encoding table 580 for a five-bit word in four chips per symbol. A message can be formed from several consecutive symbols, where Y is the number of symbols and 5*Y represents the number of data bits to be transmitted. At the end of consecutive symbols within a message, no reserved bits are needed to perform DC-balanced line coding, because each symbol is DC-balanced, and the four signal levels add up to 0. Through the DC-balanced line coding performed within the symbol itself, the data encoding is suitable for physical layers using transformer-isolated and / or capacitively isolated layers. Any additional chips in its configuration must be null.

[0080] In some embodiments, the signal combination processor can process 390,626 (5) signals per symbol, consisting of eight consecutive transmissions or chips, or eight consecutive five-level chips. 8 There are 12,000 possible combinations. In these embodiments, by applying the aforementioned criteria associated with the criterion that the four transmission chips can be equally applied, all combinations can be discarded, and in doing so, the remaining 12,000+ combinations can allow information to be encoded in three-bit words. The 4.0 MHz frequency used by the physical layer of the communication protocol can produce a data communication speed of 13 Mbps, where each of the eight symbols can encode three-bit information into four cycles at a fixed frequency. In some embodiments, for each of the eight symbols, the encoding / decoding circuitry herein encodes the three-bit word in two cycles.

[0081] Figure 14 This is a schematic diagram of a battery cell controller 602 having two adaptive multilevel transceivers 612A, 612B (typically 612) according to an exemplary embodiment of this disclosure. The battery cell controller 602 also includes logic circuitry 611, which may be similar to... Figures 1 to 3 The logic circuits 211 or 221 are shown. Therefore, for the sake of brevity, such repetitive details of logic circuit 611 will not be described again.

[0082] In some embodiments, the control logic of the battery cell controller 602 may include configuration bits (also referred to as select bits) in the hardware registers of the logic circuit 611 or other storage circuits of the controller 602. These configuration bits allow a change from a five-level configuration (-2, -1, 0, +1, +2) to a three-level configuration (-1, 0, 1). Changing from a five-level configuration (-2, -1, 0, +1, +2) to a three-level configuration (-1, 0, 1) may result in a decrease in communication speed, but provides the advantage of improved robustness of data communication exchanged via transmission line 110. For example, if transmission line 100 is not perfectly matched, signal bounce may occur in this line, which may be seen at the receivers of controllers 102, 104, especially for transmission line 110 with a particularly long twisted-pair cable 202. In this example, this bounce may cause a +1 level to be interpreted as a +2 level due to line integrity. In such cases, the configuration will be set to three-level decoding for communication robustness or integrity.

[0083] like Figure 15As shown, when the previously described five-level encoding technique is enabled in response to a five-level configuration bit, the transmission circuit 614 of the battery cell controller 602 and a plurality of electronic switches 622 (e.g., transistors, etc.) connected in series with resistors 624 allow activation of various signal levels 1 and 2 of interest. If one resistor 624 is connected to pull-up switch 622 and to ground of pull-down switch, the differential voltage at analog outputs TXP-TXN is twice as large as in the configuration of two resistors 624 connected in parallel. The plurality of switches in the transmission circuit 614 can open or close in response to various signals S1 to S8 to activate the levels of interest, for example, switching between a five-level configuration (-2, -1, 0, 1, 2) and a three-level configuration (-1, 0, 1). For example, to transmit a +1 level, switches S1, S3, S4, and S6 are closed, and all other switches are open. To transmit a +2 level, switches S1, S3, S4, S5, S6, and S8 are closed, and all other switches are open. To transmit a 0 level, switches S1 through S8 are all open. To transmit a -1 level, switches S1, S2, S4, and S7 are closed, and all other switches are open. To transmit a -2 level, switches S1, S2, S4, S5, S7, and S8 are closed, and all other switches are open.

[0084] Refer again Figure 14 The receiving circuit 615 of the transceiver 612 may include four comparators configured to detect various levels (+2, +1, 0, -1, -2) for different thresholds. Figure 16 This is receiver decoding data sheet 670, which shows... Figure 14 The translation between the thresholds of the various receiver comparators (RX1 to RX4) and the logic received values ​​corresponding to each level (+2, +1, 0, -1, +2).

[0085] As will be understood, the disclosed embodiments include at least the following. In one embodiment, a battery management system includes: a first battery cell controller; a second battery cell controller (104), each of the first and second battery cell controllers monitoring a plurality of battery cells; and an electrically isolated transmission line providing a point-to-point signal transmission path between the first and second battery cell controllers. At least one of the first or second battery cell controllers includes: at least one encoding / decoding circuit that encodes data according to a multi-level encoding technique for transmission as a serial data stream along the signal transmission path, including modulating the serial data stream at at least three discrete signal levels with a predetermined and fixed data pulse frequency, and encoding a plurality of data nibbles of the serial data stream into data packets. Each symbol of the data packet includes at least four consecutive chips comprising a DC balanced line code within each of the symbols.

[0086] Alternative embodiments of the battery management system include one or any combination of the following features.

[0087] The battery management system includes: a microcontroller unit that outputs data to at least one of a first or second battery cell controller and manages a serial data stream, including generating commands and outputting the commands to an encoding / decoding circuit to control the conversion between at least three discrete signal levels; and a driver circuit between the microcontroller unit and a transmission line that converts a serial peripheral interface output from the microcontroller unit into pulse bit data for output to the transmission line.

[0088] The battery management system further includes a driver circuit between the microcontroller unit and the transmission line, which reads multiple sequential bits from the MCU and converts the multiple sequential bits into a multi-bit word for output as pulse bit data to the transmission line.

[0089] The transmission line includes a first transformer isolation circuit coupled to a first battery cell controller; a second transformer isolation circuit coupled to a second battery cell controller; and a twisted-pair cable extending between the first and second transformer isolation circuits.

[0090] The transmission line includes a first transformer isolation circuit coupled to a first battery cell controller; a second transformer isolation circuit coupled to a second battery cell controller; and a twisted-pair cable extending between the first and second transformer isolation circuits.

[0091] The battery management system further includes logic circuitry, which includes at least one encoding / decoding circuit and a logic device that translates each symbol into a multi-bit word for output as a serial data stream to one of the first or second transformer isolation circuits.

[0092] Each symbol has at least four consecutive chips corresponding to four transmissions.

[0093] The first or second battery cell controller includes an adaptive multilevel transceiver, which includes a transmission circuit, a receiving circuit, and logic circuitry including registers. The logic circuitry processes configuration bits of at least one of the transmission or receiving circuitry to change from a first number of signal levels of multilevel coding to a second number of signal levels of multilevel coding to accommodate the determined integrity of the transmission line.

[0094] The first number of signal levels is three signal levels, and the second number of signal levels is five signal levels.

[0095] At least one encoding / decoding circuit transmits each of the symbols transmitted via four consecutive chips and encodes the information of a five-bit word over two cycles of a fixed data pulse frequency.

[0096] At least one encoding / decoding circuit encodes three bits of the data packet in two cycles.

[0097] The three-digit word is encoded using four chips per symbol.

[0098] The multiple symbols include eight symbols, and for each of the eight symbols, at least one encoding / decoding circuit encodes a three-bit word in two cycles.

[0099] The data packet does not include reserved bits and includes the same number of consecutive transmissions with -1 and +1 levels or -2 and +2 levels, and the sum of the chips corresponding to the same number of consecutive transmissions must be null.

[0100] At least one encoding / decoding circuit includes: a first-in-first-out (FIFO) memory that reads a predetermined number of sequential bits from a serial data stream and translates the predetermined number of sequential bits into a multi-bit word; and an encoder / decoder that translates the multi-bit word into a pulse-coded symbol comprising at least four consecutive chips per symbol.

[0101] In another embodiment, a method for encoding data bits onto a bus includes: configuring a battery cell controller to output a serial data stream to an electrically isolated transmission line; modulating the serial data stream at at least three discrete signal levels at a predetermined and fixed data pulse frequency; encoding a plurality of data nibbles of the serial data stream into data packets, the data packets comprising at least three symbols, the at least three symbols being constructed and arranged such that each symbol has at least four consecutive chips; and discarding combinations of at least three discrete signal levels to provide a DC balanced line code within each of the symbols.

[0102] Alternative embodiments of the method include one or any combination of the following features.

[0103] The logic circuit includes at least one encoding / decoding circuit and a logic device that translates each symbol into a multi-bit word for output as a serial data stream to a transformer-isolated circuit.

[0104] At least one encoding / decoding circuit includes: a first-in-first-out (FIFO) memory that reads a predetermined number of sequential bits from a serial data stream and translates the predetermined number of sequential bits into a multi-bit word; and an encoder / decoder that translates the multi-bit word into a pulse-coded symbol comprising at least four consecutive chips per symbol.

[0105] The semiconductor device further includes an adaptive multilevel transceiver (612A, 612B), which includes a transmission circuit, a receiving circuit, and logic circuitry including a register. The logic circuitry processes configuration bits of at least one of the transmission or receiving circuitry to change from a first number of signal levels of a multilevel encoding technique to a second number of signal levels of a multilevel encoding technique to adapt to the determined integrity of the signal transmission path.

[0106] In another embodiment, a method for encoding data bits onto a transmission bus includes: configuring a battery cell controller to output a serial data stream to an electrically isolated transmission line; modulating the serial data stream at at least three discrete signal levels at a predetermined and fixed data pulse frequency; encoding a plurality of data nibbles of the serial data stream into data packets, the data packets comprising at least three symbols, the at least three symbols being constructed and arranged such that each symbol has at least four consecutive chips; and discarding combinations of at least three discrete signal levels to provide a DC balanced line code within each of the symbols.

[0107] Alternative embodiments of the method include one or any combination of the following features.

[0108] The method further includes reading a predetermined number of sequential bits from a serial data stream and translating the predetermined number of sequential bits into a multi-bit word; and translating the multi-bit word into a pulse-coded symbol comprising at least four consecutive chips per symbol.

[0109] A battery management system includes: a first battery cell controller; a second battery cell controller, each monitoring a plurality of battery cells; and an electrically isolated transmission line providing a point-to-point signal transmission path between the first and second battery cell controllers. At least one of the first or second battery cell controllers includes at least one encoding / decoding circuit that encodes data using a multi-level encoding technique for transmission as a serial data stream along the signal transmission path. This includes modulating the serial data stream at at least three discrete signal levels with a predetermined and fixed data pulse frequency, encoding a plurality of data nibbles of the serial data stream into data packets, each data packet comprising a plurality of symbols constructed and arranged such that each symbol has at least four consecutive chips, wherein each symbol of the data packet comprises at least four consecutive chips including a DC balanced line code in each of the symbols.

[0110] Although the invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. Therefore, this specification and drawings should be considered illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the invention. Any benefits, advantages, or solutions to problems described herein with reference to specific embodiments are not intended to be construed as key, essential, or necessary features or elements of any or all claims.

[0111] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the temporal or other priority order of these elements.

Claims

1. A battery management system, characterized by, comprising: a first battery unit controller; a second battery unit controller, each of the first and second battery unit controllers monitoring a plurality of battery cells; and an electrically isolated transmission line providing a point-to-point signal transmission path between the first and second battery unit controllers, wherein at least one of the first or second battery unit controllers comprises: at least one encoding / decoding circuit encoding data in a multi-level encoding technique for transmission along the signal transmission path as a serial data stream, including modulating the serial data stream on at least three discrete signal levels at a predetermined and fixed data pulse frequency, encoding a plurality of data nibbles of the serial data stream into a data packet, the data packet comprising a plurality of symbols structured and arranged with at least four consecutive chips per symbol, wherein the at least four consecutive chips per symbol of the data packet comprises a DC balance line code in each of the symbols.

2. The battery management system of claim 1, wherein, further comprising: a microcontroller unit outputting the data to the at least one of the first or second battery unit controllers and managing the serial data stream, including generating and outputting commands to the encoding / decoding circuit to control transitions between the at least three discrete signal levels.

3. The battery management system of claim 2, wherein, further comprising: a driver circuit between the microcontroller unit and the transmission line, the driver circuit reading a plurality of sequential bits from the MCU and translating the plurality of sequential bits into a multi-bit word for output as pulse bit data and output to the transmission line.

4. The battery management system of any preceding claim, wherein, the transmission line comprising: a first transformer isolation circuit coupled to the first battery unit controller; a second transformer isolation circuit coupled to the second battery unit controller; and a twisted pair cable extending between the first and second transformer isolation circuits.

5. The battery management system of claim 4, wherein, further comprising a logic circuit including the at least one encoding / decoding circuit and a logic device translating each symbol into a multi-bit word for output as the serial data stream to one of the first or second transformer isolation circuits.

6. The battery management system of any one of claims 1-3, wherein, the at least four consecutive chips per symbol comprises four consecutive transmissions per symbol.

7. The battery management system of any one of claims 1-3, wherein, the first or second battery unit controller comprises an adaptive multi-level transceiver including a transmission circuit, a receiving circuit, and a logic circuit including a register, the logic circuit processing configuration bits to control at least one of the transmission circuit or the receiving circuit to vary from a first number of signal levels of the multi-level encoding technique to a second number of signal levels of the multi-level encoding technique to accommodate a determined integrity of the transmission line.

8. The battery management system of claim 7, wherein, the first number of signal levels is three signal levels and the second number of signal levels is five signal levels.

9. A semiconductor device, characterized by comprising: comprising: a bi-directional transceiver; and and a logic circuit constructed and arranged to encode data for output from the bidirectional transceiver along a signal transmission path as a serial data stream modulated at a predetermined and fixed data pulse frequency on at least three discrete signal levels, the logic circuit encoding a plurality of data nibbles of the serial data stream into data packets, the data packets comprising at least three symbols constructed and arranged to have at least four consecutive chips per symbol, each chip taking one of the three discrete signal levels; wherein the at least three symbols are encoded into a subset of the maximum number of possible combinations of the at least three discrete signal levels, and wherein the circuit discards any combination of the maximum number of possible combinations.

10. A method of encoding data bits onto a transmission bus, characterized by, comprising: configuring a battery unit controller to output a serial data stream to an electrically isolated transmission line; modulating the serial data stream at a predetermined and fixed data pulse frequency on at least three discrete signal levels; and encoding a plurality of data nibbles of the serial data stream into data packets, the data packets comprising at least three symbols constructed and arranged to have at least four consecutive chips per symbol; and discarding combinations of the at least three discrete signal levels to provide a DC balanced line code within each of the symbols.

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