Semiconductor device and method for forming the same

Abstract

The present invention provides a semiconductor device and a method for forming the same. The method comprises: providing a substrate, forming a dielectric layer on the substrate; etching the dielectric layer, forming a through hole in the dielectric layer, and exposing the surface of the substrate; performing surface treatment on the dielectric layer on the side wall of the through hole; and filling the through hole with a metal layer. Before filling the through hole with a metal layer, the present invention performs surface treatment on the dielectric layer on the side wall of the through hole, thereby improving the adhesion between the subsequently filled metal layer and the dielectric layer on the side wall of the through hole, and achieving good forming quality between the metal layer and the through hole, thereby improving the performance and yield of the formed semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving towards higher component density and higher integration. As the most basic semiconductor device, the device is currently being widely used. However, the control ability of traditional planar devices for channel current has weakened, resulting in short channel effects and leakage current, which ultimately affects the electrical performance of semiconductor devices.

[0003] During the manufacturing process of semiconductor devices, it is necessary to form vias in a dielectric layer and fill the vias with metal layers to achieve connections between transistors and the metal layers. However, the current via formation process suffers from poor adhesion between the filled metal layer and the vias, resulting in poor forming quality between the metal layer and the vias. This can cause damage to the devices underneath the vias during the metal filling process.

[0004] How to fill the through-hole with a high-quality metal layer to ensure that the formed semiconductor device has good performance is a problem that urgently needs to be solved. Summary of the Invention

[0005] The problem solved by the present invention is to provide a semiconductor device and a method for forming the same, so that the formed metal layer and the through hole have good forming quality, ensuring that the formed semiconductor device has good performance and yield.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, forming a dielectric layer on the substrate; etching the dielectric layer, forming a through hole in the dielectric layer, exposing the surface of the substrate; performing surface treatment on the dielectric layer on the side wall of the through hole; and filling the through hole with a metal layer.

[0007] Optionally, the surface treatment method is a plasma surface treatment method or an ion doping method.

[0008] Optionally, the type of surface treatment is surface ruthenium treatment, surface tungsten treatment, surface cobalt treatment, or surface titanium treatment.

[0009] Optionally, the material of the metal layer is the same as the type of the surface treatment.

[0010] Optionally, a conductive plug is provided on the substrate, and the through hole exposes a surface of the conductive plug.

[0011] Optionally, the method further includes forming an etch stop layer on the substrate before forming the dielectric layer.

[0012] Optionally, before the through hole is fully filled with the metal layer, the etch stop layer is etched until the surface of the conductive plug is exposed.

[0013] Optionally, the material of the dielectric layer is nitrogen-undoped silicide or nitrogen-doped silicide.

[0014] Optionally, when the material of the dielectric layer is silicide not doped with nitrogen, before performing surface treatment on the dielectric layer on the sidewall of the through hole, the method further includes: performing nitridation surface treatment on the dielectric layer on the sidewall of the through hole.

[0015] Optionally, the dielectric layer is formed by chemical vapor deposition, atomic layer vapor deposition, or physical vapor deposition.

[0016] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0017] Before filling the through-hole with a metal layer, the dielectric layer on the through-hole sidewall is surface treated to improve the adhesion between the subsequently filled metal layer and the dielectric layer on the through-hole sidewall, so that the metal layer and the through-hole have better forming quality, thereby improving the performance and yield of the formed semiconductor device. This is because after the dielectric layer on the through-hole sidewall is surface treated, the material properties of the dielectric layer on the through-hole sidewall are less different from the properties of the material of the filled metal layer. In this way, when the metal layer is filled in the through-hole, the metal layer and the dielectric layer on the through-hole sidewall are easily combined and the adhesion is improved, thereby improving the forming quality between the filled metal layer and the dielectric layer on the through-hole sidewall, so that the performance and yield of the formed semiconductor device are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figures 1 to 5 is a structural schematic diagram of a semiconductor device forming process in one embodiment;

[0019] Figures 6 to 11 It is a structural schematic diagram of a semiconductor device forming process in one embodiment of the present invention. DETAILED DESCRIPTION

[0020] During the formation of semiconductor devices, it is necessary to fill a metal layer in the through-hole to achieve electrical connection between the transistor and the metal layer. However, after the metal layer is filled in the through-hole, when the filled metal layer is planarized, due to the weak adhesion between the filled metal layer and the dielectric layer on the sidewall of the through-hole, the metal layer and the dielectric layer on the sidewall of the through-hole are peeled off due to the action of external force during planarization, thereby forming holes or gaps between the metal layer and the sidewall of the through-hole. In this way, the chemical liquid used for planarization or the impurities generated can reach the surface of the transistor along the holes or gaps, thereby damaging the transistor, reducing the performance and yield of the formed semiconductor device, and limiting the use of the semiconductor device. For the specific formation process, please refer to Figures 1 to 5 .

[0021] First reference Figure 1 , providing a substrate 1, on which an interlayer dielectric layer 2 is formed, a contact hole 3 is formed in the interlayer dielectric layer 2, and a first metal layer 31 is filled in the contact hole 3.

[0022] refer to Figure 2 , forming an etch stop layer 4 on the interlayer dielectric layer 2 and the first metal layer 31 , and forming a dielectric layer 5 on the etch stop layer 4 .

[0023] refer to Figure 3 , patterning the dielectric layer 5 and the etch stop layer 4 until the surface of the first metal layer 31 is exposed, forming a through hole 6.

[0024] refer to Figure 4 , a second metal layer 61 is filled in the through hole 6 .

[0025] refer to Figure 5 , planarize the second metal layer 61 until the top surface of the second metal layer 61 is flush with the top surface of the dielectric layer 5 .

[0026] The inventors have found that the semiconductor device formed by this method has poor stability in performance and is prone to failure, which limits the use of the semiconductor device. This is because the material properties of the second metal layer 61 formed are quite different from those of the dielectric layer 5. The second metal layer 61 formed in this way is not easy to adhere to the dielectric layer 5, and the adhesion between the second metal layer 61 and the dielectric layer 5 is small, resulting in poor forming quality between the second metal layer 61 and the dielectric layer 5. When the second metal layer 61 is flattened, it is easy for the second metal layer 61 to peel off from the dielectric layer 5, causing chemical liquid or impurities in the flattening process to flow along the gaps or holes to the surface of the first metal layer 31, thereby damaging the first metal layer 31 and causing the formed semiconductor device to have poor performance.

[0027] The inventors have discovered that before filling the through-hole with a metal layer, the dielectric layer on the side wall of the through-hole is surface treated so that the surface of the treated dielectric layer has material properties similar to those of the metal layer. In this way, when filling the through-hole with a metal layer, due to the small difference in material properties between the metal layer and the dielectric layer, the surfaces of the metal layer and the dielectric layer are easily bonded together, thereby ensuring that the metal layer and the dielectric layer have better forming quality, ensuring that in the subsequent process of flattening the metal layer, no peeling occurs between the metal layer and the dielectric layer, thereby improving the performance and yield of the formed semiconductor device.

[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] Figures 6 to 11 It is a structural schematic diagram of a semiconductor device forming process in one embodiment of the present invention.

[0030] First reference Figure 6 , providing a substrate 100 , and forming a dielectric layer 200 on the substrate 100 .

[0031] In this embodiment, the base 100 includes a substrate 110 and an interlayer dielectric layer 120 located on the substrate 110 .

[0032] In this embodiment, the substrate 110 includes storage devices and logic devices (not shown in the figure) located on the substrate 110 .

[0033] In this embodiment, a contact hole is formed in the interlayer dielectric layer 120 , and the contact hole is filled with a first metal layer 121 to form a conductive plug.

[0034] In this embodiment, before forming the dielectric layer 200 , an etch stop layer 130 is formed on the substrate 100 .

[0035] In other embodiments, the etch stop layer 130 may not be formed before forming the dielectric layer 200 .

[0036] In this embodiment, the material of the etch stop layer 130 is tungsten nitride, aluminum nitride, or silicon nitride.

[0037] In this embodiment, the purpose of forming the etch stop layer 130 before forming the dielectric layer 200 is to utilize the protective effect of the etch stop layer 130 on the underlying substrate 110, the interlayer dielectric layer 120 and the first metal layer 121 (conductive plug), so as to prevent the substrate 110, the interlayer dielectric layer 120 and the first metal layer 121 (conductive plug) from being damaged in subsequent processes, thereby improving the quality of the formed semiconductor device.

[0038] In this embodiment, the material of the dielectric layer 200 is a nitrogen-undoped silicide, including silicon oxide or silicon carbide, etc.; in other embodiments, the material of the dielectric layer 200 can also be a nitrogen-doped silicide, and the material of the dielectric layer 200 is silicon nitride, silicon boron nitride, silicon carbon nitride or silicon nitride oxide, etc.

[0039] In this embodiment, the material of the dielectric layer 200 is silicon oxide; in other embodiments, the material of the dielectric layer 200 may also be silicon carbide or the like.

[0040] In this embodiment, the dielectric layer 200 is formed on the substrate 100 by chemical vapor deposition. The process parameters of the chemical vapor deposition process include the following: the gases used include oxygen, ammonia (NH3), and N(SiH3)3 gas, the flow rate of oxygen is 20 sccm to 10,000 sccm, the flow rate of ammonia (NH3) gas is 20 sccm to 10,000 sccm, the flow rate of N(SiH3)3 gas is 20 sccm to 10,000 sccm, the chamber pressure is 0.01 to 10 Torr, and the temperature is 30°C to 90°C.

[0041] refer to Figure 7 , etching the dielectric layer 200 to form a through hole 210 in the dielectric layer 200 , exposing the surface of the etch stop layer 130 .

[0042] In this embodiment, a dry etching process is used to form the through hole 210. The parameters of the dry etching process include: the gases used include CF4 and CH3F, the flow rate of CF4 is 20sccm~200sccm, the flow rate of CH3F is 20sccm~50sccm, the source RF power is 200W~500W, and the chamber pressure is 1torr~10torr.

[0043] In other embodiments, wet etching may be used to form the through hole 210 .

[0044] refer to Figure 8 , performing a nitridation surface treatment on the dielectric layer 200 on the sidewall of the through hole 210.

[0045] The arrows in the figure represent the implanted ions.

[0046] In this embodiment, since the material of the dielectric layer 200 is silicon oxide, which is a silicide material not doped with nitrogen, the dielectric layer 200 on the side wall of the through hole 210 is subjected to nitridation surface treatment before surface treatment is performed on the dielectric layer 200 on the side wall of the through hole 210.

[0047] In other embodiments, the material of the dielectric layer 200 is nitrogen-doped silicide, such as silicon nitride, and does not require nitridation surface treatment.

[0048] In this embodiment, the nitridation surface treatment method is a plasma surface treatment method; in other embodiments, the nitridation surface treatment method may also be an ion doping method.

[0049] In this embodiment, the process parameters of the nitridation surface treatment include using ammonia (NH 3 ) as a reaction gas, wherein the gas flow rate of the ammonia (NH 3 ) is 500 to 20,000 sccm; the power is 100 to 2,000 watts; and the chamber pressure is 2 to 100 mTorr.

[0050] In this embodiment, the reason for performing nitridation surface treatment before surface treatment is, on the one hand, to enhance the density of the surface of the dielectric layer 200 on the side wall of the through hole 210 and improve the barrier effect; on the other hand, after the surface of the dielectric layer 200 on the side wall of the through hole 210 is nitrided, the dielectric layer 200 contains silicon nitride, and the formed silicon nitride can be used as a transition layer between different material properties, so that when the dielectric layer 200 is surface treated, better surface treatment quality can be obtained, thereby obtaining a higher quality semiconductor device.

[0051] refer to Figure 9 , performing surface treatment on the dielectric layer 200 on the sidewall of the through hole 210.

[0052] The arrows in the figure represent the implanted ions.

[0053] In this embodiment, the surface treatment method is a plasma surface treatment method; in other embodiments, the surface treatment method may also be an ion doping method.

[0054] In this embodiment, the type of surface treatment is surface tungsten (W) treatment; in other embodiments, the type of surface treatment is surface ruthenium (Ru) treatment, surface cobalt (Co) treatment, or surface titanium (Ti) treatment.

[0055] In this embodiment, the type of surface treatment refers to the dielectric layer 200 on the side wall of the through hole 210 being subjected to surface ruthenium treatment, surface tungsten treatment, surface cobalt treatment, or surface titanium treatment, so that the dielectric layer 200 on the side wall of the through hole 210 has material properties similar to or the same as those of metal ruthenium, metal tungsten, metal cobalt, or metal titanium. In this way, when the metal layer is subsequently filled, the material properties of the dielectric layer 200 are little different from those of the metal layer.

[0056] In this embodiment, the process parameters for surface tungsten treatment include: the gases used include WF6 and hydrogen, wherein the gas flow rate of WF6 is 10-1000 sccm and the gas flow rate of hydrogen is 50-20000 sccm; the reaction temperature is 200-400°C; and the chamber pressure is 5-100 mTorr.

[0057] In this embodiment, after the dielectric layer 200 on the sidewall of the through hole 210 is subjected to surface tungsten treatment, the surface of the dielectric layer 200 has material properties similar to or the same as metal tungsten (W), preparing for the subsequent filling of the W metal layer in the through hole.

[0058] refer to Figure 10 The etch stop layer 130 is etched along the sidewall of the through hole 210 until the surface of the conductive plug 121 (first metal layer) is exposed.

[0059] In this embodiment, the etch stop layer 130 is etched until the surface of the conductive plug 121 (first metal layer) is exposed, in order to achieve electrical connection between the transistor and the metal layer after subsequent metal filling.

[0060] refer to Figure 11 , the through hole 210 is fully filled with a metal layer 300 , and the formed metal layer 300 is planarized until the top surface of the metal layer 300 is flush with the top surface of the dielectric layer 200 .

[0061] The material of the metal layer 300 is the same as the type of the surface treatment.

[0062] In this embodiment, the material of the metal layer 300 is the same as the type of the surface treatment, which means that the material properties of the surface of the dielectric layer 200 on the side wall of the through hole 210 after surface ruthenium treatment, surface tungsten treatment, surface cobalt treatment or surface titanium treatment are the same as or similar to the properties of the material of the metal layer 300.

[0063] In this embodiment, the material of the metal layer 300 is tungsten (W); in other embodiments, the material of the metal layer 300 may also be Ru, cobalt (Co), or titanium (Ti).

[0064] In this embodiment, the metal layer 300 is formed by a selective growth method; in other embodiments, the metal layer 300 can also be formed by a chemical vapor deposition method (CVD), an atomic layer vapor deposition method (ALD), or a physical vapor deposition method (PVD).

[0065] In this embodiment, the parameters for forming the metal layer 300 by the selective growth method include: the reaction gas includes WF6 gas and H2, wherein the gas flow rate of the WF6 gas is 50~1000sccm, and the gas flow rate of the H2 is 500~20000sccm; the reaction temperature is 100~400℃; and the chamber pressure is 2~100 Torr.

[0066] In this embodiment, the metal layer 300 is formed by a selective growth method because, on the one hand, the metal layer 300 formed by the selective growth method grows gradually upward from the bottom of the through hole 210, and the formed metal layer 300 has good density; on the other hand, since the dielectric layer 200 on the side wall of the through hole 210 has undergone precursor treatment, the surface has a large number of polar bonds or charges, and the surface of the metal layer 300 also has a large number of polar bonds or charges, so that the metal layer 300 and the dielectric layer 200 can attract each other, so that the metal layer 300 can easily grow at the bottom and side wall of the through hole 210, thereby forming a high-quality metal layer 300.

[0067] In this embodiment, the precursor treatment is a process of treating various surfaces before forming the metal layer 300 .

[0068] In this embodiment, since the dielectric layer 200 on the side wall of the through hole 210 is surface treated before filling the metal layer 300, the surface of the treated dielectric layer 200 has the same material properties as the filled metal layer 300. Since the material properties of the surface of the dielectric layer 200 are slightly different from the material surface properties of the filled metal layer 300, when filling the metal layer 300, the surface of the metal layer 300 and the surface of the dielectric layer 200 are easily adhered together, and the metal layer 300 and the dielectric layer 200 have good formation quality. In this way, when planarizing the metal layer 300, it is not easy for the metal layer 300 and the dielectric layer 200 to peel off, thereby improving the quality and yield of the formed semiconductor device.

[0069] In this embodiment, after the metal layer 300 is formed and before the metal layer 300 is planarized, the filled metal layer 300 is annealed at a temperature of 400 to 450°C. The purpose is to facilitate the formation of an amorphous phase of WN / WN-Si / WSi between the filled metal layer 300 and the side wall of the through hole 210 as a bonding layer, so as to better bond the metal layer 300 to the side wall of the through hole 210, improve the adhesion between the metal layer 300 and the dielectric layer 200 on the side wall of the through hole 210, avoid the peeling phenomenon between the dielectric layer 200 and the metal layer 300 during the planarization of the metal layer 300, and improve the performance and yield of the formed semiconductor device.

[0070] Correspondingly, using the above method, the present invention also provides a semiconductor device, including: a base 100, composed of a substrate 110 and an interlayer dielectric layer 120, wherein the interlayer dielectric layer 120 is located on the substrate 110; a conductive plug composed of a first metal layer 121, and the first metal layer 121 is located in the interlayer dielectric layer 120; an etch stop layer 130, located on the interlayer dielectric layer 120; a dielectric layer 200, located on the etch stop layer 130; a through hole 210, located in the dielectric layer 200, and the bottom of which exposes the surface of the conductive plug 121 (first metal layer); a metal layer 300, filling the through hole 210 and located on the conductive plug 121 (first metal layer).

[0071] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that: include: providing a substrate, and forming a dielectric layer on the substrate; Etching the dielectric layer to form a through hole in the dielectric layer to expose the substrate surface; performing surface treatment on the dielectric layer on the sidewall of the through hole; The through hole is filled with a metal layer, and the metal layer and the sidewall of the through hole form an amorphous phase of WN / WN-Si / WSi as a bonding layer.

2. The forming method according to claim 1, wherein: The surface treatment method is a plasma surface treatment method or an ion doping method.

3. The forming method according to claim 1, wherein: The surface treatment type is surface ruthenium treatment, surface tungsten treatment, surface cobalt treatment or surface titanium treatment.

4. The forming method according to claim 3, wherein: The material of the metal layer is the same as the type of the surface treatment.

5. The forming method according to claim 1, wherein: A conductive plug is provided on the substrate, and the through hole exposes a surface of the conductive plug.

6. The forming method according to claim 5, wherein: The method further includes forming an etch stop layer on the substrate before forming the dielectric layer.

7. The forming method according to claim 6, wherein: Before the through hole is fully filled with the metal layer, the etch stop layer is etched until the surface of the conductive plug is exposed.

8. The forming method according to claim 1, wherein: The dielectric layer is made of nitrogen-undoped silicide or nitrogen-doped silicide.

9. The forming method according to claim 8, wherein: When the material of the dielectric layer is silicide not doped with nitrogen, before performing surface treatment on the dielectric layer on the sidewall of the through hole, the method further includes: performing nitridation surface treatment on the dielectric layer on the sidewall of the through hole.

10. The forming method according to claim 1, wherein: The dielectric layer is formed by chemical vapor deposition, atomic layer vapor deposition, or physical vapor deposition.

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