Semiconductor device and method of forming the same

Abstract

One aspect of the present application provides a method of forming a semiconductor device, including: forming a first dummy gate and a second dummy gate over a fin, the fin protruding above a substrate; replacing the first dummy gate and the second dummy gate with a first metal gate and a second metal gate, respectively; forming a dielectric cut pattern between the first metal gate and the second metal gate, the dielectric cut pattern extending further from the substrate than the first metal gate and the second metal gate; forming a patterned mask layer over the first metal gate, the second metal gate, and the dielectric cut pattern, an opening in the patterned mask layer exposing a portion of the first metal gate, a portion of the second metal gate, and a portion of the dielectric cut pattern below the opening; filling the opening with a first conductive material; and recessing the first conductive material below an upper surface of the dielectric cut pattern. Another aspect of the present application provides a semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly, to semiconductor devices and methods of forming the same. Background Art

[0002] Due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. In most cases, this improvement in integration density has come from successive reductions in the minimum feature size, which allows more components to be integrated into a given area.

[0003] Fin field-effect transistor (FinFET) devices are becoming prevalent in integrated circuits. A FinFET device has a three-dimensional structure that includes semiconductor fins protruding from a substrate. A gate structure configured to control the flow of charge carriers in a conductive channel of the FinFET device surrounds the semiconductor fins. For example, in a triple-gate FinFET device, the gate structure surrounds three sides of the semiconductor fin, and thus a conductive channel is formed on three sides of the semiconductor fin. Summary of the Invention

[0004] Embodiments of the present application provide a method of forming a semiconductor device, including: forming a first dummy gate and a second dummy gate over a fin protruding above a substrate; replacing the first dummy gate and the second dummy gate with a first metal gate and a second metal gate, respectively; forming a dielectric cut pattern between the first metal gate and the second metal gate, the dielectric cut pattern extending further from the substrate than the first metal gate and the second metal gate; forming a patterned mask layer over the first metal gate, the second metal gate, and the dielectric cut pattern, an opening in the patterned mask layer exposing a portion of the first metal gate, a portion of the second metal gate, and a portion of the dielectric cut pattern below the opening; filling the opening with a first conductive material; and recessing the first conductive material below an upper surface of the dielectric cut pattern remote from the substrate.

[0005] Embodiments of the present application also provide a method of forming a semiconductor device, including: forming a first dummy gate and a second dummy gate above a first fin, the first fin protruding above a substrate; forming an interlayer dielectric layer around the first dummy gate and the second dummy gate; replacing the first dummy gate and the second dummy gate with a first metal gate and a second metal gate respectively; forming a first opening in the interlayer dielectric layer between the first metal gate and the second metal gate, wherein the first opening is spaced apart from the first fin; filling the first opening with one or more dielectric materials to form a cutting pattern; removing the interlayer dielectric layer after forming the cutting pattern, wherein removing the interlayer dielectric layer forms a groove between the first metal gate and the second metal gate; and filling the groove with a first conductive material, wherein the cutting pattern separates the first conductive material into a first portion and a second portion.

[0006] Embodiments of the present application also provide a semiconductor device, including: a fin located above a substrate; a first metal gate and a second metal gate, the first metal gate located above the fin, the second metal gate located above the fin; a first dielectric cutting pattern located between the first metal gate and the second metal gate, wherein the first dielectric cutting pattern is spaced apart from the fin, and wherein the first dielectric cutting pattern extends further from the substrate than a first gate electrode of the first metal gate and a second gate electrode of the second metal gate; a dielectric layer located above the first gate electrode and the second gate electrode and in contact with the first gate electrode and the second gate electrode, wherein an upper surface of the dielectric layer is flush with a first upper surface of the first dielectric cutting pattern; and a first contact plug and a second contact plug, the first contact plug and the second contact plug located above the first gate electrode and the second gate electrode respectively and connected to the first gate electrode and the second gate electrode respectively, wherein the first contact plug and the second contact plug extend through the dielectric layer and contact opposite sidewalls of the first dielectric cutting pattern.

[0007] Embodiments of the present application provide fin field effect transistor devices and methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0009] Figure 1 is a perspective view of a fin field effect transistor (FinFET) according to some embodiments;

[0010] Figures 2 - 7 、 Figures 8A - 8C 、 Figure 9 、 Figures 10A - 10C 、Figures 11A - 11C , Figure 12A - Figure 12C , Figures 13A - 13C , Figures 14A - 14C , Figures 15A - 15C , Figures 16A - 16C , Figures 17A - 17C , and Figures 18A - 18C show various views (e.g., cross - sectional views, plan views) of a FinFET device at various stages of manufacture according to an embodiment;

[0011] Figure 19A and Figure 19B shows a cross - sectional view of a FinFET device according to an embodiment;

[0012] Figure 20A and Figure 20B shows a cross - sectional view of a FinFET device according to an embodiment;

[0013] Figure 21A and Figure 21B shows a cross - sectional view of a FinFET device according to an embodiment;

[0014] Figure 22A and Figure 22B shows a cross - sectional view of a FinFET device according to an embodiment;

[0015] Figure 23A and Figure 23B shows a cross - sectional view of a FinFET device according to an embodiment;

[0016] Figure 24A and Figure 24B shows a cross - sectional view of a FinFET device according to an embodiment;

[0017] Figure 25A and Figure 25B shows a cross - sectional view of a FinFET device according to an embodiment;

[0018] Figure 26A and Figure 26B shows a cross - sectional view of a FinFET device according to an embodiment;

[0019] Figure 27A and Figure 27B shows a cross - sectional view of a FinFET device according to an embodiment;

[0020] Figure 28A and Figure 28B shows a cross - sectional view of a FinFET device according to an embodiment;

[0021] Figure 29A and Figure 29BShows a cross-sectional view of a FinFET device according to one embodiment;

[0022] Figure 30A and Figure 30B Shows a cross-sectional view of a FinFET device according to one embodiment;

[0023] Figure 31A and Figure 31B Shows a cross-sectional view of a FinFET device according to one embodiment;

[0024] Figure 32A and Figure 32B Shows a cross-sectional view of a FinFET device according to one embodiment;

[0025] Figure 33A and Figure 33B Shows a cross-sectional view of a FinFET device according to one embodiment;

[0026] Figure 34A and Figure 34B Shows a cross-sectional view of a FinFET device according to one embodiment;

[0027] Figure 35 Shows a flowchart of a method of manufacturing a semiconductor device according to some embodiments. Detailed Description

[0028] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact.

[0029] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to easily describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientations shown in the figures, spatially relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Throughout the specification herein, unless otherwise stated, the same or similar reference numerals in different figures represent the same or similar elements formed of the same or similar (some) materials by the same or similar forming methods.

[0030] Embodiments of the present invention are discussed in the context of forming semiconductor devices, particularly in the context of forming fin field-effect transistor (FinFET) devices. In some embodiments, a first metal gate and a second metal gate are formed over a plurality of fins in a back-gate process. A dielectric cut pattern is formed between the first metal gate and the second metal gate, and the dielectric cut pattern is spaced apart from the fins. Next, an interlayer dielectric (ILD) layer around the first metal gate and the second metal gate is removed, and a first conductive material is formed between the first metal gate and the second metal gate. The dielectric cut pattern separates the first conductive material into a first portion and a second portion. Next, a patterned mask layer is formed over the first metal gate, the second metal gate, the dielectric cut pattern, and the first conductive material. Openings in the patterned mask layer expose a portion of the first metal gate, a portion of the second metal gate, and a portion of the dielectric cut pattern. Next, the openings are filled with a second conductive material, and the second conductive material is recessed such that an upper surface of the second conductive material is closer to the substrate than an upper surface of the dielectric cut pattern. Thus, the dielectric cut pattern separates the second conductive material into a first gate contact and a second gate contact in a self-aligned manner.

[0031] Figure 1 An example of a FinFET 30 is shown in a perspective view. The FinFET 30 includes a substrate 50 that includes fins 64. The substrate 50 includes isolation regions 62 formed thereon, and the fins 64 protrude above and between adjacent isolation regions 62. A gate dielectric 66 is along sidewalls of the fins 64 and above a top surface of the fins 64, and a gate electrode 68 is located above the gate dielectric 66. Source / drain regions 80 are located in the fins on opposite sides of the gate dielectric 66 and the gate electrode 68. Figure 1 Reference cross-sections used in the subsequent figures are also shown. Cross-section B-B extends along a longitudinal axis of the gate electrode 68 of the FinFET 30. Cross-section A-A is perpendicular to cross-section B-B and along a longitudinal axis of the fins 64 and in a direction of current flow between, for example, source / drain regions 80. Cross-section C-C is parallel to cross-section A-A and is located outside the fins 64. Cross-section D-D is parallel to cross-section B-B and is located outside the gate electrode 68, for example, through the source / drain regions 80. Cross-section A-A, cross-section B-B, cross-section C-C, and cross-section D-D are also shown Figure 9 in a plan view. For clarity, the subsequent figures refer to these reference cross-sections.

[0032] Figures 2 - 7 、 Figures 8A - 8C 、 Figure 9 、 Figures 10A - 10C 、 Figures 11A - 11C 、Figure 12A - Figure 12C 、 Figures 13A - 13C 、 Figures 14A - 14C 、 Figures 15A - 15C 、 Figures 16A - 16C 、 Figures 17A - 17C 、 and Figures 18A - 18C illustrate various views (e.g., cross-sectional views, plan views) of a FinFET device 100 at various stages of fabrication. Except for a plurality of fins and a plurality of gate structures, the FinFET device 100 is similar to Figure 1 the FinFET 30 in Figures 2 - 5 illustrates a cross-sectional view of the FinFET device 100 along cross-section B-B, Figure 6 and Figure 7 illustrates a cross-sectional view of the FinFET device 100 along cross-section A-A. Figure 8A 、 Figure 8B and 8C respectively illustrate cross-sectional views of the FinFET device 100 along cross-section A-A, cross-section B-B, and cross-section C-C. Figure 9 is a plan view of the FinFET device 100. Figures 10A - 18C illustrates cross-sectional views of the FinFET device 100 along different cross-sections at various stages of fabrication, wherein the drawings with the same numbers (e.g., Figure 10A 、 Figure 10B 、 and Figure 10C ) illustrate cross-sectional views of the FinFET device 100 at the same processing stage. In particular, Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 and 18A illustrate top views of the FinFET device 100, Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 FIG. 14B, Figure 15B 、 Figure 16B 、 Figure 17B 、 and 18B illustrate cross-sectional views of the FinFET device 100 along cross-section C-C of the corresponding top views, Figure 10C 、 Figure 11C 、 Figure 12C 、 Figure 13C 、 Figure 14C 、 Figure 15C 、 Figure 16C 、 Figure 17C, and FIGS. 18C show cross-sectional views of the FinFET device 100 along cross-section D-D of the corresponding top views. Note that, for clarity, some of the figures may show only a part of the FinFET device 100, and not all features of the FinFET device 100 are shown in the figures.

[0033] Figure 2 A cross-sectional view of the substrate 50 is shown. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates can also be used, such as a multi-layer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0034] Reference Figure 3 , using, for example, lithography and etching techniques, the substrate 50 shown in Figure 2 is patterned. For example, above the substrate 50, a mask layer such as a pad oxide layer 52 and an overlying pad nitride layer 56 are formed. The pad oxide layer 52 can be a thin film including silicon oxide formed, for example, using a thermal oxidation process. The pad oxide layer 52 can serve as an adhesion layer between the substrate 50 and the overlying pad nitride layer 56, and can serve as an etch stop layer for etching the pad nitride layer 56. In some embodiments, the pad nitride layer 56 is formed of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc., or combinations thereof, and as an example, can be formed using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0035] The mask layer can be patterned using lithography techniques. Generally, lithography techniques utilize a photoresist material (not shown), which is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps such as etching. In this example, the photoresist material is used to pattern the pad oxide layer 52 and the pad nitride layer 56 to form a patterned mask 58, as shown in Figure 3 .

[0036] Subsequently, a patterned mask 58 is used to pattern the exposed portion of the substrate 50 to form trenches 61, thereby defining semiconductor fins 64 (also referred to as fins 64) between adjacent trenches 61 as shown in Figure 3 . In some embodiments, the trenches in the substrate 50 are etched, such as by using reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof, to form the semiconductor fins 64. The etching can be anisotropic. In some embodiments, the trenches 61 can be strips (when viewed from the top) that are parallel to each other and closely spaced relative to each other. In some embodiments, the trenches 61 can be continuous and surround the semiconductor fins 64. After forming the semiconductor fins 64, the patterned mask 58 can be removed by etching or any suitable method.

[0037] Figure 4 The formation of an insulating material between adjacent semiconductor fins 64 is shown to form an isolation region 62. The insulating material can be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and can be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it to another material, such as an oxide), etc., or a combination thereof. Other insulating materials and / or other forming processes can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by the FCVD process. Once the insulating material is formed, an annealing process can be implemented. A planarization process such as chemical mechanical polishing (CMP) can remove any excess insulating material (and, if present, the patterned mask 58), and form a coplanar top surface of the isolation region 62 and the top surface of the semiconductor fins 64.

[0038] In some embodiments, the isolation region 62 includes a liner, such as a liner oxide (not shown), at the interface between the isolation region 62 and the substrate 50 / semiconductor fins 64. In some embodiments, the liner oxide is formed to reduce crystal defects at the interface between the substrate 50 / semiconductor fins 64 and the isolation region 62. The liner oxide (e.g., silicon oxide) can be a thermal oxide formed by thermal oxidation of the surface layer of the substrate 50 / semiconductor fins 64, but other suitable methods can also be used to form the liner oxide.

[0039] Next, the isolation region 62 is recessed to form a shallow trench isolation (STI) region. The isolation region 62 is recessed such that the upper portion of the semiconductor fin 64 protrudes above the top surface of the isolation region 62. The top surface of the isolation region 62 may have a flat surface (as shown), a raised surface, a recessed surface (e.g., a depression), or a combination thereof. By appropriate etching, the top surface of the isolation region 62 can be formed into a flat, raised, and / or recessed surface. An acceptable etching process can be used, such as an etching process selective to the material of the isolation region 62, to recess the isolation region 62. For example, a process using dilute hydrofluoric acid (dHF) for chemical oxide removal can be used.

[0040] Figures 2 to 4 An embodiment of forming the fin 64 is shown, but the fin can be formed by various different processes. In one example, a dielectric layer can be formed above the top surface of the substrate; trenches can be etched through the dielectric layer; a homoepitaxial structure can be grown epitaxially in the trenches; and the dielectric layer can be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form a fin. In another example, a heteroepitaxial structure can be used for the fin. For example, a semiconductor fin can be recessed, and a material different from the semiconductor fin can be grown epitaxially in its place.

[0041] In a further example, a dielectric layer can be formed on the top surface of the substrate; trenches can be etched through the dielectric layer; a heteroepitaxial structure can be grown epitaxially in the trenches using a material different from the substrate; and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form a fin.

[0042] In some embodiments of growing a homoepitaxial structure or a heteroepitaxial structure epitaxially, the material grown during growth can be doped in-situ, which can avoid prior and subsequent implantations, although in-situ and implantation doping can be used together. Additionally, it may be advantageous to grow epitaxially a material in the NMOS region that is different from the material in the PMOS region. In various embodiments, the fin can include silicon germanium (Si x Ge 1-x , where x can be between about 0 and 1), silicon carbide, pure or substantially pure germanium, group III-V compound semiconductors, group II-VI compound semiconductors, etc. For example, available materials for forming group III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.

[0043] Figure 5 The formation of a dummy gate structure 75 above the semiconductor fin 64 is shown. In some embodiments, the dummy gate structure 75 includes a gate dielectric 66 and a gate electrode 68.Figure 5 Also shown is a mask 70 over the dummy gate structure 75. The dummy gate structure 75 can be formed by patterning a mask layer, a gate layer, and a gate dielectric layer, where the mask layer, the gate layer, and the gate dielectric layer respectively include the same materials as the mask 70, the gate electrode 68, and the gate dielectric 66. To form the dummy gate structure 75, a gate dielectric layer is formed over the semiconductor fin 64 and the isolation region 62. The gate dielectric layer can be, for example, silicon oxide, silicon nitride, a multi-layer thereof, etc., and can be deposited or thermally grown according to acceptable techniques. The method of forming the gate dielectric layer can include molecular beam deposition (MBD), atomic layer deposition (ALD), plasma enhanced CVD (PECVD), etc.

[0044] A gate layer is formed over the gate dielectric layer, and a mask layer is formed over the gate layer. The gate layer can be deposited over the gate dielectric layer and then planarized, for example, by a CMP process. The mask layer can be deposited over the gate layer. The gate layer can be formed of, for example, polysilicon, but other materials can also be used. The mask layer can be formed of, for example, silicon nitride, etc.

[0045] After forming the gate dielectric layer, the gate layer, and the mask layer, the mask layer can be patterned using acceptable lithography and etching techniques to form the mask 70. Then, through appropriate etching techniques, the pattern of the mask 70 can be transferred to the gate layer and the gate dielectric layer to form the gate electrode 68 and the gate dielectric 66, respectively. The gate electrode 68 and the gate dielectric 66 cover the corresponding channel regions of the semiconductor fin 64. The gate electrode 68 can also have a length direction that is substantially perpendicular to the length direction of the corresponding semiconductor fin 64. Although Figure 5 a cross-sectional view shows one dummy gate structure 75, more than one dummy gate structure 75 can be formed on the semiconductor fin 64. For example, Figure 9 the plan view in shows multiple metal gates 97 (which replace the dummy gate structure in subsequent processing) over the semiconductor fin 64.

[0046] Figures 6 - 8A A cross-sectional view of a further process of the FinFET device 100 along the cross-section A-A (along the longitudinal axis of the fin) is shown. As Figure 6 shown, a lightly doped drain (LDD) region 65 is formed in the fin 64. The LDD region 65 can be formed by an implantation process. The implantation process can implant N-type or P-type impurities into the fin 64 to form the LDD region 65. In some embodiments, the LDD region 65 abuts the channel region of the FinFET device 100. A portion of the LDD region 65 can extend under the gate electrode 68 and into the channel region of the FinFET device 100. Figure 6A non-limiting example of the LDD region 65 is shown. Other configurations, shapes, and formation methods of the LDD region 65 are also possible and are fully intended to be included within the scope of the present invention. For example, the LDD region 65 can be formed after the formation of the gate spacers 87.

[0047] Still referring to Figure 6 , after the formation of the LDD region 65, gate spacers 87 are formed on the gate structure. In Figure 6 's example, gate spacers 87 are formed on the opposite sidewalls of the gate electrode 68 and on the opposite sidewalls of the gate dielectric 66. The gate spacers 87 can be formed of nitrides such as silicon nitride, silicon oxynitride, silicon carbonitride, etc., or a combination thereof, and can be formed using, for example, thermal oxidation, CVD, or other suitable deposition processes. The gate spacers 87 can also extend above the upper surface of the semiconductor fin 64 and the upper surface of the isolation region 62.

[0048] As Figure 6 shown, the shape and formation method of the gate spacers 87 are only non-limiting examples, and other shapes and formation methods are also possible. For example, the gate spacers 87 can include a first gate spacer (not shown) and a second gate spacer (not shown). The first gate spacer can be formed on the opposite sidewalls of the dummy gate structure 75. The second gate spacer can be formed on the first gate spacer, and the first gate spacer is disposed between the corresponding dummy gate structure 75 and the corresponding second gate spacer. In a cross-sectional view, the first gate spacer can have an L shape. As another example, the gate spacers 87 can be formed after the formation of the epitaxial source / drain regions 80 (refer to Figure 7 ). In some embodiments, before the epitaxial process of the epitaxial source / drain regions 80 shown in Figure 7 , a dummy gate spacer is formed on a first gate spacer (not shown), and after the formation of the epitaxial source / drain regions 80, the dummy gate spacer is removed and replaced with a second gate spacer. All of these embodiments are fully intended to be included within the scope of the present invention.

[0049] Next, as Figure 7 shown, the source / drain regions 80 are formed. The source / drain regions 80 are formed by etching the fin 64 to form a groove and epitaxially growing a material in the groove using a suitable method such as metalorganic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), etc., or a combination thereof.

[0050] As Figure 7As shown, the epitaxial source / drain regions 80 may include surfaces that protrude from corresponding surfaces of the fins 64 (e.g., protrude above non-recessed portions of the fins 64), and may include facets. The source / drain regions 80 of adjacent fins 64 may be merged to form a continuous epitaxial source / drain region 80. In some embodiments, the source / drain regions 80 of adjacent fins 64 are not merged together and remain separate source / drain regions 80. In some example embodiments, the resulting FinFET is an n-type FinFET, and the source / drain regions 80 include silicon carbide (SiC), silicon phosphide (SiP), phosphorous-doped silicon carbide (SiCP), etc. In some alternative example embodiments, the resulting FinFET is a p-type FinFET, and the source / drain regions 80 include SiGe and p-type impurities such as boron or indium.

[0051] The epitaxial source / drain regions 80 may be doped with dopants to form the source / drain regions 80, followed by an annealing process. The implantation process may include forming and patterning a mask, such as photoresist, to cover regions of the FinFET that need to be protected from the implantation process. The source / drain regions 80 may have an impurity (e.g., dopant) concentration in the range of about 1E19 cm -3 to about 1E21 cm -3 . In some embodiments, the epitaxial source / drain regions may be doped in-situ during growth.

[0052] Next, as Figure 8A shown, a first interlayer dielectric (ILD) 90 is formed over the structure shown in Figure 7 , and a post-gate process (sometimes referred to as a replacement gate process) is implemented. In the post-gate process, the gate electrode 68 and the gate dielectric 66 (refer to Figure 7 ) are considered to be dummy structures, which are removed and replaced with an active gate electrode and an active gate dielectric. The active gate electrode and the active gate dielectric may be collectively referred to as a replacement gate or a metal gate.

[0053] In some embodiments, the first ILD 90 is formed of a dielectric material such as silicon oxide (SiO), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., and may be deposited by any suitable method such as CVD, PECVD, or FCVD. A planarization process such as a CMP process may be implemented to remove the mask 70 and planarize the top surface of the first ILD 90, such that after the CMP process, the top surface of the first ILD 90 is flush with the top surface of the gate electrode 68 (refer to Figure 7 ). Thus, after the CMP process, in some embodiments, the top surface of the gate electrode 68 is exposed.

[0054] According to some embodiments, in some etching steps, the gate electrode 68 and the gate dielectric 66 directly under the gate electrode 68 are removed to form a groove (not shown). Each groove exposes the channel region of the corresponding fin 64. Each channel region may be disposed between adjacent pairs of epitaxial source / drain regions 80. During the removal of the dummy gate, when etching the dummy gate electrode 68, the dummy gate dielectric 66 may be used as an etch stop layer. Then, after removing the dummy gate electrode 68, the dummy gate dielectric 66 may be removed.

[0055] Next, a metal gate 97 is formed in the groove by sequentially forming a gate dielectric layer 96, a barrier layer 94, and a gate electrode 98 in each groove. As Figure 8A shown, the gate dielectric layer 96 is conformally deposited in the groove. The barrier layer 94 is conformally formed over the gate dielectric layer 96, and the gate electrode 98 fills the groove. Although not shown, a work function layer may be formed, for example, between the gate dielectric layer 96 and the barrier layer 94.

[0056] According to some embodiments, the gate dielectric layer 96 includes silicon oxide, silicon nitride, or a multi-layer thereof. In other embodiments, the gate dielectric layer 96 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 96 may have a k value greater than about 7.0 and may include metal oxides, or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The method of forming the gate dielectric layer 96 may include MBD, ALD, PECVD, etc.

[0057] A work function layer may be conformally formed over the gate dielectric layer 96. The work function layer includes any suitable material for the work function layer. Exemplary p-type work function metals that may be included in the metal gate 97 include TiN, TaN, Ru, Mo, Al, WN, ZrSi 2 、MoSi 2 、TaSi 2 、NiSi 2 、WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals that may be included in the metal gate 97 include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function value is associated with the material composition of the work function layer. Therefore, the material of the first work function layer may be selected to adjust its work function value so as to achieve the target threshold voltage Vt in the device to be formed in the corresponding region. The (some) work function layer may be deposited by CVD, physical vapor deposition (PVD), and / or other suitable processes.

[0058] Next, a barrier layer 94 is conformally formed over the gate dielectric layer 96 and, if present, over the work function layer. The barrier layer 94 may include a conductive material such as titanium nitride, but other materials such as tantalum nitride, titanium, tantalum, etc. may alternatively be used. The barrier layer 94 may be formed using a CVD process such as PECVD. However, other alternative processes such as sputtering, or MOCVD, ALD may alternatively be used.

[0059] Next, a gate electrode 98 is formed over the barrier layer 94. The gate electrode 98 may be made of a metal-containing material such as Cu, Al, W, etc., their combinations, or their multi-layers, and may be formed by methods such as electroplating, electroless plating, PVD, CVD, or other suitable methods. A planarization process such as CMP may be implemented to remove the excess portions of the materials of the gate dielectric layer 96, the work function layer, the barrier layer 94, and the gate electrode 98 that are above the top surface of the first ILD 90. The remaining portions of the materials of the resulting gate electrode 98, barrier layer 94, work function layer, and gate dielectric layer 96 then form the metal gate 97 of the FinFET device 100. In Figure 8A an example, three metal gates 97 are shown. However, it is readily understood by those skilled in the art that more or fewer than three metal gates 97 may be used to form the FinFET device 100.

[0060] Figure 8B and Figure 8C show Figure 8A the FinFET device 100, but along cross-sections B-B and C-C, respectively. Figure 8B show the fin 64 and the metal gate 97 above the fin 64. Figure 8C show the metal gate 97 above the gate spacer 87 and the STI 62. Note that in Figure 8C the cross-section, the fin 64 is not visible.

[0061] Now referring to Figure 9 , a plan view of the FinFET device 100 after the processing steps of Figures 8A - 8C is shown. For simplicity, not all features of the FinFET device 100 are shown. For example, the gate spacer 87, the isolation region 62, and the source / drain regions 80 are not shown in Figure 9 .

[0062] As Figure 9As shown, a metal gate 97 (e.g., 97A / 97B / 97C / 97D / 97E / 97F) spans across a semiconductor fin 64 (e.g., 64A / 64B). In subsequent processing, a plurality of cut patterns 106 are formed between the metal gates 97 (or adjacent to the metal gates 97) (refer to, for example Figure 14A - Figure 14C ). The cut patterns 106 will be used to cut (e.g., separate) a conductive material (refer to 111 in Figures 16A - 16C ) into separate portions, thereby defining electrical connections between different source / drain regions. The cut patterns 106 will also be used to separate a conductive material (refer to 121 in Figures 18A - 18C ) into separate portions, thereby forming gate contact plugs in a self-aligned manner. Details are discussed below.

[0063] Now referring to Figures 10A - 10C , Figure 10A shows a top view of the FinFET device 100. The fin 64 is shown in dashed lines in Figure 10A . The position of the metal gate 97 (corresponding to the position of the dielectric layer 103) is not shown in Figure 10A , but is shown in Figure 14A , Figure 15A , Figure 16A , and Figure 18A . Figure 10B shows a cross-sectional view of the FinFET device 100 along the cross-section C-C, Figure 10C shows a cross-sectional view of the FinFET device 100 along the cross-section D-D. The positions of the cross-section C-C and the cross-section D-D relative to the metal gate 97 are as shown in Figure 14A . Note that, for simplicity, the details of the metal gate 97 (e.g., the gate electrode 98, the barrier layer 94, and the gate dielectric layer 96) are not shown in Figure 10B and the subsequent figures.

[0064] As shown in Figures 10A - 10C , for example, through an anisotropic etching process, the metal gate 97 is recessed below the upper surface of the gate spacer 87. As a result, grooves are created between the gate spacers 87 due to the recess of the metal gate 97. The top of the gate spacer 87 can also be removed through an anisotropic etching process, as shown in Figure 10BAs shown below. Next, a dielectric layer 103 is formed to fill the grooves between the gate spacers 87. The dielectric layer 103 may include suitable dielectric materials such as SiC, LaO, AlO, AlON, ZrO, HfO, SiN, Si, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, SiO, etc., and may be formed by suitable formation methods such as CVD, PVD, etc., or a combination thereof. The dielectric layer 103 may be formed in a self-aligned manner, and the sidewalls of the dielectric layer 103 may be aligned with the sidewalls of the gate spacers 87, respectively. A planarization process such as CMP may be implemented to planarize the upper surface of the dielectric layer 103.

[0065] After the dielectric layer 103 is formed, a dielectric layer 92 is formed above the first ILD 90 and above the dielectric layer 103, which may be the same as or similar to the first ILD 90. After that, a hard mask layer 101 (e.g., an oxide or nitride layer) is formed above the dielectric layer 92. In an exemplary embodiment, both the first ILD 90 and the dielectric layer 92 are formed of an oxide (e.g., silicon oxide). Therefore, hereinafter, the first ILD 90 and the dielectric layer 92 may be collectively referred to as the oxide 90 / 92.

[0066] Figure 10C A cross-sectional view of the FinFET device 100 along the cross-section D-D is shown. Figure 10C The fins 64 protruding above the substrate 50 and the STI 62 are shown. Figure 10C The first ILD 90, the dielectric layer 92, and the hard mask layer 101 are also shown.

[0067] Next, in Figures 11A - 11C , an opening 102 is formed in the hard mask layer 101 to pattern the hard mask layer 101. The opening 102 is formed at a position between the metal gates 97 and is spaced apart from the fins 64. Suitable methods such as photolithography and etching may be used to form the opening 102. Once the opening 102 is formed, the patterned hard mask layer 101 serves as an etch mask to pattern the dielectric layer 92 and the first ILD 90 using an etching process such as an isotropic etching process. The etching process removes portions of the dielectric layer 92 and portions of the first ILD 90. As Figure 11B and 11C shown, the opening 102 extends into the first ILD 90 and has slanted sidewalls. For example, the width of the opening 102 may decrease as the opening 102 extends toward the substrate 50. After the etching process, a portion of the STI 62 below the opening 102 may be exposed. In Figure 11B the example, the sidewalls of the dielectric layer 103 and the sidewalls of the gate spacers 87 are exposed through the opening 102.

[0068] Next, in Figures 12A - 12C Figures 12A - 12C , a dielectric material 105 is formed to partially fill the opening 102. In some embodiments, the dielectric material 105 includes SiC, LaO, AlO, AlON, ZrO, HfO, SiN, Si, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, etc., and is formed by a suitable formation method such as CVD, PVD, etc., or a combination thereof.

[0069] Next, in Figures 13A - 13C Figures 13A - 13C , a dielectric material 107 different (e.g., having a different composition) from the dielectric material 105 is formed over the dielectric material 105 to fill the remaining portion of the opening 102. The dielectric material 107 is different (e.g., having a different composition) from the dielectric layer 103 to provide etch selectivity in subsequent processing. In some embodiments, the dielectric material 107 includes SiC, LaO, AlO, AlON, ZrO, HfO, SiN, Si, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfS, etc., and is formed by a suitable formation method such as CVD, PVD, etc., or a combination thereof. The dielectric material 107 can be formed over the upper surface of the hard mask layer 101. In some embodiments, a planarization process such as CMP is performed to remove the excess portion of the dielectric material 107 from the upper surface of the hard mask layer 101. In other embodiments, the planarization process is omitted, and in subsequent processing, the hard mask layer 101 is used to remove the portion of the dielectric material 107 over the upper surface of the hard mask layer 101.

[0070] Next, in Figures 14A - 14C Figures 14A - 14C , the hard mask layer 101 and the portion of the dielectric material 107 (if any) over the hard mask layer 101 are removed. Additionally, the first ILD 90 and the dielectric layer 92 are also removed, and the fin 64 is exposed. The removal of the hard mask layer 101, the portion of the dielectric material 107, the first ILD 90, and the dielectric layer 92 is performed by one or more suitable etching processes such as a CMP process, a dry etching process (e.g., a plasma process), a wet etching process, etc., or a combination thereof. For example, a CMP process can be first performed to remove the hard mask layer 101 and the portion of the dielectric material 107 over the hard mask layer 101. Next, an etching process (e.g., dry etching or wet etching) using an etchant selective (e.g., having a higher etching rate) to the materials of the first ILD 90 and the dielectric layer 92 can be performed to remove the first ILD 90 and the dielectric layer 92.

[0071] In Figures 14A - 14C the example of, each metal gate 97 is located directly below a corresponding portion of the dielectric layer 103. Thus, in Figure 14A the top view of, each metal gate 97 with a corresponding gate spacer 87 has the same boundary as the corresponding portion of the dielectric layer 103. As a result, in the top view (e.g., Figure 14A , Figure 15A , Figure 16A , and Figure 18A ), the position of the dielectric layer 103 corresponds to the position of the metal gate 97. Thus, Figure 14A shows that above the fin 64 shown, each metal gate 97 extends continuously.

[0072] After removing the dielectric layer 92 and the first ILD 90, an opening 104 (e.g., trench) is formed between adjacent metal gates 97. The opening 104 exposes the sidewall of the gate spacer 87 facing away from the corresponding metal gate 97, and exposes the sidewall of the dielectric layer 103. The fin 64 is also exposed. In the following discussion, the dielectric material 105 and the overlying dielectric material 107 located in the same opening 102 (refer to Figures 12A - 12C ) are collectively referred to as the cut pattern 106, or the dielectric cut pattern 106. For example, Figure 14A shows eight cut patterns 106.

[0073] Figure 14C shows the tapered sidewall of the cut pattern 106, which is formed in some embodiments due to the tapered sidewall of the opening 102 (refer to Figure 12B and Figure 12C ). Figure 14C It also shows the remaining portion of the oxide 90 / 92 along the tapered sidewall of the cut pattern 106.

[0074] Next, in Figures 15A - 15C , a liner 109 is formed along the sidewall of the Figures 14A - 14C structure shown. The liner 109 can be formed by forming a conformal liner layer (e.g., dielectric layer) above the structure shown in Figures 14A - 14C , and then anisotropically etching to remove the horizontal portion of the liner layer. In some embodiments, the liner 109 is formed of a dielectric material such as SiC, LaO, AlO, AlON, ZrO, HfO, SiN, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, SiO, etc. In other embodiments, the liner 109 is omitted.

[0075] Next, in Figures 16A - 16C , in the opening 104 (e.g., trench, refer toFigure 15A - Figure 15C ) A conductive material 111, such as Cu, W, Al, Co, etc., or a combination thereof, is formed therein. Although not shown, a barrier layer may be conformally formed along the sidewalls and bottom of the opening 104 before forming the conductive material 111. The barrier layer may include TiN, TaN, Ti, Ta, etc., and may be formed using processes such as PECVD, sputtering, MOCVD, ALD, etc. Next, a planarization process such as CMP is implemented to achieve a coplanar upper surface between the conductive material 111 and the dielectric materials 103 / 107. Note that the planarization process may remove at least the upper portion of the dielectric material 107. After the planarization process, the height T1 of the dielectric material 105 is between about 2 nm and about 100 nm, and the height T2 of the dielectric material 107 is between about 0 nm and about 100 nm. The upper surface 106U of the cut pattern 106 is higher (farther from the substrate 50) than the upper surface of the metal gate 97. The thickness T4 of the pad 109 is between about 0 nm and about 20 nm. Note that the cut pattern 106 separates the conductive material 111 into separate parts (e.g., discrete, non - continuous parts). These separated parts define different electrical connections between source / drain regions disposed above different fins 64. For example, by defining different positions of the cut pattern 106, different electrical connections of the source / drain regions can be achieved.

[0076] As the feature size continues to shrink in advanced processing nodes, forming the cut pattern 106 becomes increasingly challenging. To understand the advantages of the present disclosure, consider a reference method in which the cut pattern is formed by simply patterning the first ILD 90 and the dielectric layer 92 using a patterned hard mask layer 101' (not shown), where the patterned hard mask layer 101' is Figure 12A complementary to the patterned hard mask layer 101. In other words, the patterned hard mask layer 101' includes small, separate rectangular pieces (e.g., eight pieces) disposed at the positions of the openings 102 in Figure 12A However, during the patterning process used to form the cut pattern, these small, separate rectangular pieces of the patterned hard mask layer 101' may flake off, thus preventing the correct cut pattern from being formed under the patterned hard mask layer 101', which may cause a short circuit in the circuits of different parts of the conductive material 111 in subsequent processing.

[0077] In contrast, the currently disclosed method avoids the peeling problem of the method for reference. Therefore, the cutting pattern 106 can be correctly formed. The size and material of the cutting pattern 106 ensure that the cutting pattern 106 is strong enough to withstand subsequent processing. For example, compared with the method for reference in which the first ILD 90 and the dielectric layer 92 are patterned by using the patterned hard mask layer 101' to form the cutting pattern as discussed above, the cutting pattern 106 disclosed in the present invention is thicker. Therefore, it can better withstand subsequent processing (such as etching), thereby reducing or avoiding the peeling problem. In addition, some of the materials of the cutting pattern 106 in the present invention have better physical properties than the materials of the oxides 90 / 92 (such as silicon oxide). For example, some of the materials of the cutting pattern 106 can be denser, less porous, and / or more resistant to etching (such as having a slower etching rate). As Figures 14A - 14C shown, during the etching process for removing the first ILD 90 and the dielectric layer 92, the better physical properties help prevent damage to the cutting pattern 106, thus avoiding the short-circuit problem discussed above. In addition, the better physical properties of the materials of the cutting pattern 106 improve the time-dependent dielectric breakdown (TDDB) performance between adjacent source / drain regions.

[0078] Next, in Figures 17A - 17C , the conductive material 111 is etched back (e.g., recessed), and a dielectric layer 119 is formed over the (recessed) conductive material 111. In some embodiments, the dielectric layer 119 is the same as the dielectric material 105 and the dielectric layer 103 (e.g., having the same composition), and the dielectric material 107 is different from the dielectric material 105 and the dielectric layer 103 (e.g., having a different composition). In some embodiments, the dielectric layer 119 includes SiC, LaO, AlO, AlON, ZrO, HfO, SiN, Si, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, SiO, etc., and is formed by a suitable formation method such as CVD, PVD, etc., or a combination thereof. A planarization process can be implemented after forming the dielectric layer 119 such that the upper surface of the dielectric layer 119 is flush with the upper surface of the dielectric layer 103.

[0079] Next, an etch stop layer 117 is formed over the cutting pattern 106, the dielectric layer 119, and the metal gate 97, and a mask layer 115 is formed over the etch stop layer 117. The etch stop layer 117 can include suitable materials such as silicon nitride, silicon carbide, silicon carbonitride, etc., and can be formed by PVD, CVD, sputtering, etc. The mask layer 115 can be, for example, an oxide and can be formed by any suitable method.

[0080] Next, openings 118 are formed in the mask layer 115, for example, using photolithography and etching techniques. The openings 118 may extend through the etch stop layer 117. Next, an anisotropic etching process is performed using the patterned mask layer 115 as an etch mask to remove portions of the dielectric layer 103 such that the cut pattern 106 and the metal gate 97 directly below the openings 118 are exposed. Note that due to the etch selectivity between the dielectric material 107 and the dielectric layer 103, the etching process removes the dielectric layer 103 with substantially no erosion of the dielectric material 107. In Figure 17B the example of, a remaining portion of the dielectric layer 103 remains at the sidewalls of the openings 118 between the gate spacers 87 and the etch stop layer 117.

[0081] Note that on opposite sides of the cut pattern 106, the openings 118 expose the cut pattern 106 and the metal gate 97. The upper surface of the cut pattern 106 is higher (e.g., farther from the substrate 50) than the upper surface of the metal gate 97. In Figures 17A - 17C the example of, the cut pattern 106 includes two different dielectric materials, for example, an upper layer formed of the dielectric material 107 and a lower layer formed of the dielectric material 105. The layered structure of the cut pattern 106 provides flexibility in the selection of dielectric materials. For example, during the formation of the openings 118, the dielectric material 107 can be selected to provide etch selectivity between the dielectric material 107 and the dielectric layer 103, and the dielectric material 105 can be selected to provide better TDDB performance between adjacent source / drain regions. However, the double-layer structure of the cut pattern 106 may require more processing steps and may be more costly to form than a single-layer cut pattern 106 (refer to, for example, Figures 27A - 27B 106 in) where the cut pattern 106 is formed of a single dielectric material. However, compared to the double-layer cut pattern 106, the selection of dielectric materials for the single-layer cut pattern 106 may be more restricted because the dielectric material of the single-layer cut pattern 106 has to provide both good TDDB performance (e.g., between adjacent source / drain regions) and etch selectivity above the dielectric layer 103.

[0082] Next, in Figures 18A - 18C a conductive material 121 (e.g., Cu, W, Al, Co, etc.) is formed in the openings 118. The conductive material 121 fills the openings 118 and may be formed above the upper surface of the mask layer 115. Next, the mask layer 115, the etch stop layer 117, and the excess portions of the conductive material 121 disposed above the upper surface of the cut pattern 106 are removed, for example, by a CMP process, dry etching, wet etching, a combination thereof, etc. As Figure 18BAs shown, a coplanar upper surface is achieved between the dielectric material 107, the conductive material 121, the dielectric layer 119, and the dielectric layer 103. Note that the cut pattern 106 separates the conductive material 121 into two separate gate contacts 121 (also referred to as gate contact plugs), each gate contact 121 being connected to a corresponding underlying metal gate 97.

[0083] Note that the width of the opening 118 (refer to Figures 17A - 17C ) is greater than the width of each gate contact 121, and the gate contacts 121 are formed in a self-aligned manner using the cut pattern 106. This illustrates another advantage of the present invention. As the feature size continues to decrease in advanced processing nodes, the resolution of conventional lithography may not be sufficient to form a separate opening for each gate contact 121. The disclosed method allows for the formation of a larger opening (e.g., 118) using conventional lithography and the separation of the filled metal in the opening 118 by using the cut pattern 106 to form smaller gate contacts (e.g., 121) in a self-aligned manner. This helps to reduce the manufacturing cost (e.g., less stringent requirements for lithography tools) and can also increase the yield (e.g., self-aligned gate contacts are easier to form and are less likely to have problems associated with filling high aspect ratio openings).

[0084] In some embodiments, the thickness T3 of the dielectric layer 119 is between about 0 nm and about 50 nm. In some embodiments, the width T6 of the remaining portion of the dielectric layer 103 at the sidewalls of the gate contacts 121 is between about 0 nm and about 30 nm. The thickness T7 of the dielectric layer 103 above the metal gate 97 measured along the middle of the dielectric layer 103 can be between about 1 nm and about 80 nm. The thickness T8 of the dielectric layer 103 measured at the corners of the dielectric layer 103 (e.g., directly above the gate spacer 87) can be between about 0 nm and about 60 nm. The thickness T9 of the remaining oxide 90 / 92 along the sidewalls of the cut pattern 106 can be between about 0 nm and about 30 nm.

[0085] Additional processing can be implemented to complete the fabrication of the FinFET device 100, such as forming additional dielectric layers and forming source / drain contacts. The details are not discussed here.

[0086] Variations and modifications to the disclosed embodiments are possible and are fully intended to be included within the scope of the present invention. For example, the cut pattern 106 can be formed through a single dielectric material (e.g., 105) instead of through two different dielectric materials (e.g., 105 and 107). As another example, the dielectric layer 119 above the conductive material 111 can be omitted. As yet another example, the liner 109 can be omitted. As an additional example, the opening 102 used to form (refer to Figures 11A - 11C) The etching process can leave some residual oxides 90 / 92 at the bottom of the opening 102, such that the residual oxides 90 / 92 are retained between the cutting pattern 106 and the substrate 50. These variations can be combined to form different embodiments, some of which will be discussed below.

[0087] Figures 19A - 34B Various alternative embodiments are shown, where figures having the same number but different letters (e.g., 19A and Figure 19B ) represent the same embodiment but along different cross-sections. For example, Figure 19A shows a cross-sectional view of a FinFET device along the cross-section C-C, while Figure 19B shows a cross-sectional view of a FinFET device along the cross-section D-D.

[0088] Now refer to Figure 19A and Figure 19B , Figure 19A and Figure 19B show cross-sectional views of FinFET devices similar to the FinFET device 100 in Figure 18A -FIG. 18C but without the pad 109. Note that the oxides 90 / 92 on the tapered sidewalls of the cutting pattern 106 along in Figure 18C are not shown in the example of Figure 19B . This is because in the processing steps shown in Figures 16A - 16C , a pre-cleaning process (e.g., an etching process) can be implemented before forming the conductive material 111. If the pad 109 is not formed, the pre-cleaning process may consume the oxides 90 / 92. In embodiments where the pad 109 is formed (refer to, for example, Figure 18C ), the pad 109 protects the oxides 90 / 92 from the pre-cleaning process, and thus the oxides 90 / 92 are retained in the formed device.

[0089] Figure 20A and 20B show similar to Figures 19A - 19BCross-sectional view of a FinFET device in [[ ]] with a residual oxide 90 / 92 below the cutting pattern 106. In some embodiments, the thickness T5 of the oxide 90 / 92 below the cutting pattern 106 is between about 0 nm and about 60 nm. In some embodiments, due to the tapered sidewalls of the cutting pattern 106, the distance between the sidewalls of the cutting pattern 106 and the gate spacer 87 decreases as the cutting pattern 106 extends away from the substrate 50. For example, the distance D2 between the sidewalls of the cutting pattern 106 and the corresponding gate spacer 87 measured at the lower surface of the dielectric material 105 can be between about 0 nm and about 30 nm; the distance D1 between the sidewalls of the cutting pattern 106 and the corresponding gate spacer 87 measured at the lower surface of the dielectric material 107 can be between about 0 nm and about 20 nm. The angle α measured between the sidewalls of the cutting pattern 106 (e.g., the sidewalls of the dielectric material 105 or the dielectric material 107) and the upper surface of the substrate 50 can be between about 65 degrees and 95 degrees.

[0090] Figure 21A and Figure 21B shows a cross-sectional view of a FinFET device similar to [[ ]] but with a different shape for the dielectric layer 103. In particular, the dielectric layer 103 shown in FIG. 21A has a T-shaped cross-section, with an upper part and a lower part, and a substantially right angle between the lower surface of the upper part and the sidewalls of the lower part. In contrast, Figures 18A - 18C the dielectric layer 103 shown in [[ ]] has smooth curved sidewalls connecting the upper and lower parts of the dielectric layer 103. Figure 18B shown in [[ ]]

[0091] Figure 22A and Figure 22B shows a cross-sectional view of a FinFET device similar to [[ ]] but with a residual oxide 90 / 92 below and around the cutting pattern 106. Figures 18A - 18C

[0092] Figure 23A and Figure 23B shows a cross-sectional view of a FinFET device similar to [[ ]] but without the pad 109 and without the dielectric layer 119. Figures 18A - 18C

[0093] Figure 24A and Figure 24B shows a cross-sectional view of a FinFET device similar to [[ ]] Figure 23A and Figure 23B but with a residual oxide 90 / 92 below the cutting pattern 106.

[0094] Figure 25A and Figure 25B shows a cross-sectional view of a FinFET device similar to the FinFET device 100 in Figures 18A - 18C but without the dielectric layer 119.

[0095] Figure 26A and Figure 26B shows a cross-sectional view of a FinFET device similar to the FinFET device in Figure 25A and Figure 25B but with residual oxides 90 / 92 under the cut pattern 106.

[0096] Figure 27A and Figure 27B shows a cross-sectional view of a FinFET device similar to the FinFET device 100 in Figures 18A - 18C but without the liner 109 and without the dielectric material 107. In other words, the cut pattern 106 is formed of a single material (e.g., 105). In an embodiment where the cut pattern 106 is formed only of the dielectric material 105 (instead of 105 and 107), the dielectric material 105 is different (e.g., has a different composition) from the dielectric layer 103 to provide etch selectivity in the process of forming the gate contact 121.

[0097] Figure 28A and Figure 28B shows a cross-sectional view of a FinFET device similar to the FinFET device in Figure 27A and Figure 27B but with residual oxides 90 / 92 under the cut pattern 106.

[0098] Figure 29A and Figure 29B shows a cross-sectional view of a FinFET device similar to the FinFET device in Figure 27A and Figure 27B but with the liner 109.

[0099] Figure 30A and Figure 30B shows a cross-sectional view of a FinFET device similar to the FinFET device in Figure 29A and Figure 29B but with residual oxides 90 / 92 under the cut pattern 106.

[0100] Figure 31A and Figure 31B shows a cross-sectional view of a FinFET device similar to the FinFET device in Figure 27A and Figure 27B but without the dielectric layer 119.

[0101] Figure 32A and Figure 32B shows a cross-sectional view of a FinFET device similar to that in Figure 31A and Figure 31B but having a residual oxide 90 / 92 under the cut pattern 106.

[0102] Figure 33A and Figure 33B shows a cross-sectional view of a FinFET device similar to that in Figure 27A and Figure 27B but having a liner 109 and no dielectric layer 119.

[0103] Figure 34A and Figure 34B shows a cross-sectional view of a FinFET device similar to that in Figure 33A and Figure 33B but having a residual oxide 90 / 92 under the cut pattern 106.

[0104] Figure 35 shows a flowchart of a method for manufacturing a semiconductor device according to some embodiments. It should be understood that Figure 35 the exemplary method shown in Figure 35 is merely an example of many possible exemplary methods. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. For example, various steps as shown in

[0105] can be added, removed, replaced, rearranged, and repeated. Figure 35 Referring to

[0106] Embodiments can achieve advantages. The method of the present disclosure avoids or reduces the problem of peeling of the hard mask layer 101 during the formation of the cut pattern 106, thereby avoiding the formation of an incorrect cut pattern 106 and an electrical short circuit occurring between source / drain regions designed to be separated. Due to the improved physical properties of the material of the cut pattern 106, the TDDB performance between adjacent source / drain regions of the device is improved. Additionally, the cut pattern 106 allows for the formation of gate contact plugs in a self-aligned manner, which allows the use of a lithography tool with a lower resolution to form gate contact plugs with a tight pitch. As a result, the production cost is reduced and the yield is increased.

[0107] In one embodiment, a method includes: forming a first dummy gate and a second dummy gate over a fin, the fin protruding above a substrate; replacing the first dummy gate and the second dummy gate with a first metal gate and a second metal gate, respectively; forming a dielectric cut pattern between the first metal gate and the second metal gate, the dielectric cut pattern extending further from the substrate than the first metal gate and the second metal gate; forming a patterned mask layer over the first metal gate, the second metal gate, and the dielectric cut pattern, an opening in the patterned mask layer exposing a portion of the first metal gate, a portion of the second metal gate, and a portion of the dielectric cut pattern below the opening; filling the opening with a first conductive material; and recessing the first conductive material below an upper surface of the dielectric cut pattern remote from the substrate. In one embodiment, replacing the first dummy gate and the second dummy gate includes: forming a dielectric layer around the first dummy gate and the second dummy gate; removing the first dummy gate and the second dummy gate to form a first groove and a second groove in the dielectric layer, respectively; and filling the first groove and the second groove with one or more conductive materials to form the first metal gate and the second metal gate. In one embodiment, forming the dielectric cut pattern includes: forming an opening in a dielectric layer between the first metal gate and the second metal gate, the opening located between the first metal gate and the second metal gate; filling the opening in the dielectric layer with one or more dielectric materials. In one embodiment, the opening in the dielectric layer extends through the dielectric layer. In one embodiment, a bottom of the opening in the dielectric layer is formed between an upper surface of the dielectric layer facing away from the substrate and a lower surface of the dielectric layer facing the substrate, wherein, after forming the dielectric cut pattern, a portion of the dielectric layer is located between the dielectric cut pattern and the substrate. In one embodiment, filling the opening in the dielectric layer includes: forming a first dielectric material in a bottom of the opening in the dielectric layer; forming a second dielectric material different from the first dielectric material in an upper portion of the opening in the dielectric layer. In one embodiment, the method further includes: replacing upper portions of the first metal gate and the second metal gate with a third dielectric material before forming the dielectric cut pattern. In one embodiment, the second dielectric material is different from the third dielectric material. In one embodiment, the dielectric cut pattern is formed at a first location between the first metal gate and the second metal gate, wherein the method further includes forming a second conductive material at a second location adjacent to the first location, the second location being between the first metal gate and the second metal gate. In one embodiment, the method further includes: forming a liner layer along sidewalls of the dielectric cut pattern, along sidewalls of the first metal gate, and along sidewalls of the second metal gate before forming the second conductive material. In one embodiment, the method further includes: replacing an upper portion of the second conductive material with a dielectric material after forming the second conductive material. In one embodiment, an upper surface of the dielectric material remote from the substrate is flush with an upper surface of the dielectric cut pattern.

[0108] In one embodiment, a method includes: forming a first dummy gate and a second dummy gate over a first fin, the first fin protruding above a substrate; forming an interlayer dielectric (ILD) layer around the first dummy gate and the second dummy gate; replacing the first dummy gate and the second dummy gate with a first metal gate and a second metal gate, respectively; forming a first opening in the ILD layer between the first metal gate and the second metal gate, wherein the first opening is spaced apart from the first fin; filling the first opening with one or more dielectric materials to form a cut pattern; removing the ILD layer after forming the cut pattern, wherein removing the ILD layer forms a groove between the first metal gate and the second metal gate; and filling the groove with a first conductive material, wherein the cut pattern separates the first conductive material into a first portion and a second portion. In one embodiment, the method further includes: forming a patterned mask layer over the first metal gate, the second metal gate, the cut pattern, and the first conductive material, wherein a second opening in the patterned mask layer exposes the first metal gate and the second metal gate; filling the second opening with a second conductive material; and removing an upper portion of the second conductive material such that the cut pattern extends further from the substrate than the second conductive material, thereby separating the second conductive material into a first contact plug and a second contact plug. In one embodiment, the method further includes, before forming the first opening: recessing the first metal gate to form a first groove between first gate spacers of the first metal gate; recessing the second metal gate to form a second groove between second gate spacers of the second metal gate; and filling the first groove and the second groove with a first dielectric material. In one embodiment, filling the first opening includes: forming a second dielectric material in the first opening to partially fill the first opening; and forming a third dielectric material in the first opening and over the second dielectric material, wherein the composition of the third dielectric material is different from the composition of the second dielectric material and the composition of the first dielectric material. In one embodiment, the depth of the first opening in the ILD layer is less than the thickness of the ILD layer, wherein removing the ILD layer removes a first portion of the ILD layer around the cut pattern, and a second portion of the ILD layer between the cut pattern and the substrate remains after removing the ILD layer.

[0109] In one embodiment, a semiconductor device includes: a fin located above a substrate; a first metal gate and a second metal gate located above the fin; a first dielectric cut pattern located between the first metal gate and the second metal gate, wherein the first dielectric cut pattern is spaced apart from the fin, and wherein the first dielectric cut pattern extends further from the substrate than a first gate electrode of the first metal gate and a second gate electrode of the second metal gate; a dielectric layer located above and in contact with the first gate electrode and the second gate electrode, wherein an upper surface of the dielectric layer is flush with a first upper surface of the first dielectric cut pattern; and a first contact plug and a second contact plug located above the first gate electrode and the second gate electrode, respectively, and connected to the first gate electrode and the second gate electrode, respectively, wherein the first contact plug and the second contact plug extend through the dielectric layer and contact opposite sidewalls of the first dielectric cut pattern. In one embodiment, the semiconductor device further includes: a second dielectric cut pattern located between the first metal gate and the second metal gate, wherein the second dielectric cut pattern is spaced apart from the fin and includes a second upper surface flush with the first upper surface of the first dielectric cut pattern; and a conductive material located between the first metal gate and the second metal gate, wherein the conductive material extends continuously from the first dielectric cut pattern to the second dielectric cut pattern. In one embodiment, a third upper surface of the conductive material is flush with the first upper surface of the first dielectric cut pattern or closer to the substrate than the first upper surface of the first dielectric cut pattern.

[0110] The features of several embodiments are outlined above so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and / or achieving the same or similar advantages. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor device, comprising: forming a first dummy gate and a second dummy gate over a fin, the fin protruding above a substrate; forming a dielectric layer around the first dummy gate and the second dummy gate, replacing the first dummy gate and the second dummy gate with a first metal gate and a second metal gate respectively, a third dielectric material being on the first metal gate and the second metal gate, the first metal gate and the second metal gate being lower than a top surface of the dielectric layer; forming a dielectric cut pattern between the first metal gate and the second metal gate, the dielectric cut pattern extending higher upward from the substrate than the first metal gate and the second metal gate; forming a patterned mask layer over the first metal gate, the second metal gate, and the dielectric cut pattern, an opening in the patterned mask layer exposing a portion of the first metal gate, a portion of the second metal gate, and a portion of the dielectric cut pattern below the opening; filling the opening with a first conductive material; and recessing the first conductive material below an upper surface of the dielectric cut pattern remote from the substrate, wherein the recessing separates the first conductive material filled in the opening into a first contact plug over the first metal gate and a second contact plug over the second metal gate.

2. The method according to claim 1, wherein replacing the first dummy gate and the second dummy gate comprises: removing the first dummy gate and the second dummy gate to form a first groove and a second groove in the dielectric layer respectively; and filling the first groove and the second groove with one or more conductive materials to form the first metal gate and the second metal gate.

3. The method according to claim 1, wherein forming the dielectric cut pattern comprises: forming an opening in the dielectric layer around the first metal gate and the second metal gate, the opening being between the first metal gate and the second metal gate; and filling the opening in the dielectric layer with one or more dielectric materials.

4. The method according to claim 3, wherein the opening in the dielectric layer extends through the dielectric layer.

5. The method according to claim 3, wherein a bottom of the opening in the dielectric layer is formed between an upper surface of the dielectric layer facing away from the substrate and a lower surface of the dielectric layer facing the substrate, wherein after forming the dielectric cut pattern, a portion of the dielectric layer is between the dielectric cut pattern and the substrate.

6. The method according to claim 3, wherein filling the opening in the dielectric layer comprises: forming a first dielectric material in a bottom of the opening in the dielectric layer; and forming a second dielectric material different from the first dielectric material in an upper portion of the opening in the dielectric layer.

7. The method according to claim 6, further comprising: Before forming the dielectric cut pattern, replace the upper portions of the first metal gate and the second metal gate with the third dielectric material.

8. The method according to claim 7, wherein, the second dielectric material is different from the third dielectric material.

9. The method according to claim 1, wherein, the dielectric cut pattern is formed at a first position between the first metal gate and the second metal gate, and the method further includes forming a second conductive material in a second position adjacent to the first position, the second position being between the first metal gate and the second metal gate.

10. The method according to claim 9, further comprising: Before forming the second conductive material, form a liner layer along the sidewalls of the dielectric cut pattern, along the sidewalls of the first metal gate, and along the sidewalls of the second metal gate.

11. The method according to claim 9, further comprising: After forming the second conductive material, replace the upper portion of the second conductive material with a dielectric material.

12. The method according to claim 11, wherein, the upper surface of the dielectric material away from the substrate is flush with the upper surface of the dielectric cut pattern.

13. A method of forming a semiconductor device, comprising: Form a first dummy gate and a second dummy gate above a first fin, the first fin protruding above a substrate; Form an interlayer dielectric layer around the first dummy gate and the second dummy gate; Replace the first dummy gate and the second dummy gate with a first metal gate and a second metal gate respectively; Form a first opening in the interlayer dielectric layer between the first metal gate and the second metal gate, wherein the first opening is spaced apart from the first fin; Fill the first opening with one or more dielectric materials to form a cut pattern; After forming the cut pattern, remove the interlayer dielectric layer, wherein removing the interlayer dielectric layer forms a groove between the first metal gate and the second metal gate; and Fill the groove with a first conductive material, wherein the cut pattern separates the first conductive material into a first portion and a second portion; Form a patterned mask layer above the first metal gate, the second metal gate, the cut pattern, and the first conductive material, wherein a second opening in the patterned mask layer exposes the first metal gate and the second metal gate; Fill the second opening with a second conductive material; and Remove the upper portion of the second conductive material such that the cut pattern extends higher upward from the substrate than the second conductive material, thereby separating the second conductive material filled in the second opening into a first contact plug and a second contact plug.

14. The method according to claim 13, wherein, the width of the second opening is greater than the widths of the first contact plug and the second contact plug.

15. The method according to claim 13, further comprising, before forming the first opening: Recess the first metal gate to form a first groove between first gate spacers of the first metal gate; Recess the second metal gate to form a second groove between second gate spacers of the second metal gate; and Fill the first groove and the second groove with a first dielectric material.

16. The method according to claim 15, wherein, Filling the first opening includes: Forming a second dielectric material in the first opening to partially fill the first opening; and Forming a third dielectric material in the first opening and above the second dielectric material, wherein the composition of the third dielectric material is different from the composition of the second dielectric material and the composition of the first dielectric material.

17. The method according to claim 13, wherein, The depth of the first opening in the interlayer dielectric layer is less than the thickness of the interlayer dielectric layer, wherein removing the interlayer dielectric layer removes a first portion of the interlayer dielectric layer around the cutting pattern, and a second portion of the interlayer dielectric layer located between the cutting pattern and the substrate remains after removing the interlayer dielectric layer.

18. A semiconductor device, comprising: A fin located above a substrate; A first metal gate and a second metal gate, the first metal gate located above the fin, the second metal gate located above the fin; A first dielectric cutting pattern located between the first metal gate and the second metal gate, wherein the first dielectric cutting pattern is spaced apart from the fin, and wherein the first dielectric cutting pattern extends higher upward from the substrate than a first gate electrode of the first metal gate and a second gate electrode of the second metal gate; A third dielectric layer located above and in contact with the first gate electrode and the second gate electrode, wherein an upper surface of the third dielectric layer is flush with a first upper surface of the first dielectric cutting pattern; and A first contact plug and a second contact plug, the first contact plug and the second contact plug located above the first gate electrode and the second gate electrode respectively, and connected to the first gate electrode and the second gate electrode respectively, wherein the first contact plug and the second contact plug extend through the third dielectric layer and contact opposite sidewalls of the first dielectric cutting pattern, wherein a lowest bottom surface of the first contact plug and the second contact plug is spaced apart from the substrate and in direct contact with the first metal gate and the second metal gate respectively, wherein the first dielectric cutting pattern includes a first dielectric layer and a second dielectric layer located on a top surface of the first dielectric layer, the material of the second dielectric layer being different from the material of the first dielectric layer and the material of the third dielectric layer, and the material of the first dielectric layer being the same as the material of the third dielectric layer.

19. The semiconductor device according to claim 18, further comprising: A second dielectric cut pattern, the second dielectric cut pattern being located between the first metal gate and the second metal gate, wherein the second dielectric cut pattern is spaced apart from the fin and includes a second upper surface flush with the first upper surface of the first dielectric cut pattern; and A conductive material, the conductive material being located between the first metal gate and the second metal gate, wherein the conductive material extends continuously from the first dielectric cut pattern to the second dielectric cut pattern.

20. The semiconductor device according to claim 19, wherein, a third upper surface of the conductive material is flush with the first upper surface of the first dielectric cut pattern or closer to the substrate than the first upper surface of the first dielectric cut pattern.

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