Polycrystalline Silicon Resistor Structure and Fabrication Method Thereof

Abstract

The present disclosure is a polysilicon resistor structure and a method of fabricating the same. A method of forming a polysilicon resistor having a high dielectric constant dielectric and a polysilicon gate electrode includes depositing a resistor stack on a substrate, and the substrate includes a first isolation region and a second isolation region separated from each other. The method further includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region, and forming a gate structure between the first isolation region and the second isolation region, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure, and forming source / drain regions in the substrate adjacent to the gate structure. In addition, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure and a method of forming the same, and more particularly to a polysilicon resistor structure and a method of forming the same. Background Art

[0002] The operation of integrated circuits (ICs) requires the combination of active components (e.g., transistors) and passive components (e.g., resistors, inductors, and capacitors), and the active and passive components can be formed on the same substrate. Resistors in ICs are mainly used to control the current flowing through other components of the IC. For example, a resistor can be used to distribute a supply voltage into smaller increments. Summary of the Invention

[0003] According to an aspect of an embodiment of the present disclosure, a semiconductor structure includes a semiconductor substrate having a first isolation region and a second isolation region formed therein and separated therefrom, wherein the first isolation region is wider than the second isolation region. The semiconductor substrate further includes a resistor structure disposed on the first isolation region, wherein the resistor structure includes a dielectric layer, a nitride layer, and a semiconductor layer, the dielectric layer contacting the first isolation region, the nitride layer disposed on the dielectric layer, the semiconductor layer disposed on the nitride layer, the semiconductor layer including a doped top portion having a silicided portion, and the silicided portion formed on an opposite end of the doped top portion. The semiconductor structure also includes a transistor structure disposed between the first isolation region and the second isolation region. The transistor structure includes an interface layer, a metal gate electrode, and source / drain regions, wherein the interface layer contacts the semiconductor substrate, the aforementioned dielectric layer is disposed on the interface layer, the nitride layer is disposed on the dielectric layer, the metal gate electrode is disposed on the nitride layer, the source / drain regions are formed in the semiconductor substrate, and the source / drain regions are adjacent to the metal gate electrode.

[0004] According to another aspect of an embodiment of the present disclosure, a method includes depositing a resist stack on a substrate, and the substrate includes a first isolation region and a second isolation region separated from each other, wherein the operation of depositing the resist stack includes depositing a metal oxide dielectric layer on the substrate; depositing a metal nitride layer on the metal oxide dielectric layer; and depositing a polysilicon layer on the metal nitride layer. Next, the method includes patterning the resist stack to form a polysilicon resistor structure on the first isolation region, and forming a gate structure between the first isolation region and the second isolation region; and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure, and forming source / drain regions in the substrate, wherein the source / drain regions are adjacent to the gate structure. Furthermore, the method includes forming a dielectric layer between the polysilicon resistor and the gate structure; replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure having a gate structure and source / drain regions; and forming a silicide on the doped layer of the polysilicon layer in the polysilicon transistor structure.

[0005] According to yet another aspect of an embodiment of the present disclosure, a structure includes a substrate and a polysilicon resistor, the substrate includes a first isolation region and a second isolation region separated from each other, and the polysilicon resistor is located on the first isolation region, wherein the polysilicon resistor includes a metal oxide dielectric layer, a metal nitride layer, and a polysilicon layer, and the polysilicon layer has a top surface with a silicided portion. Next, the structure includes a transistor structure, and the transistor structure is formed between the first isolation region and the second isolation region, wherein the transistor structure includes a metal oxide dielectric layer, a metal nitride layer, and a metal gate electrode. The structure also includes one or more contacts on the silicided portion of the polysilicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of an embodiment of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the features in the drawings are not drawn to scale. In fact, the dimensions of the illustrated features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a top view schematic diagram of a polysilicon resistor structure according to some embodiments of the present disclosure;

[0008] Figure 2 is a three-dimensional schematic diagram of a non-silicided polysilicon resistor structure according to some embodiments of the present disclosure;

[0009] Figure 3 is a three-dimensional schematic diagram of a silicided polysilicon resistor structure according to some embodiments of the present disclosure;

[0010] Figure 4 is a cross-sectional schematic diagram of a non-silicided polysilicon resistor structure according to some embodiments of the present disclosure;

[0011] Figure 5 is a cross-sectional schematic view of a polysilicon resistor structure according to some embodiments of the present disclosure;

[0012] Figure 6 is a flowchart of a method for forming silicided and non-silicided polysilicon resistors according to some embodiments of the present disclosure;

[0013] Figures 7 to 11 is a cross-sectional schematic view of silicided and non-silicided polysilicon resistors according to some embodiments of the present disclosure, and these cross-sectional schematic views are used to illustrate the manufacturing process of the silicided and non-silicided polysilicon resistors.

[0014]

Symbol Description

[0015] 100, 300, 800: resistor structure

[0016] 100L, 300L: length

[0017] 100W, 300W, 800W: width

[0018] 105, 110: contact area

[0019] 115: contact structure

[0020] 200, 710: isolation area

[0021] 210: semiconductor substrate

[0022] 220, 230, 400: dielectric layer

[0023] 240: metal nitride layer

[0024] 250: polysilicon layer

[0025] 250A: doped layer

[0026] 250B: intrinsic layer

[0027] 250T: thickness

[0028] 260: spacer structure

[0029] 270: silicided portion

[0030] 410: current

[0031] 600: method

[0032] 610, 620, 630, 640, 650, 660: operations

[0033] 700: resistor stack

[0034] 720: interface layer

[0035] 730: Hard mask layer

[0036] 810: Transistor structure

[0037] 820: Source / drain region

[0038] 830, 1010: Silicide

[0039] 900: Etch stop layer

[0040] 1000: Gate electrode

[0041] AB, A’B’, C’D’, CD: Section lines Detailed implementation manners

[0042] The following disclosure provides many different embodiments or exemplifications to implement different features of the invention. The specific exemplifications of the components and arrangements described below are for simplifying an embodiment of the present disclosure. These are of course only for exemplification purposes and are not intended to be limiting. For example, the description that the first feature is formed above or on the second feature includes embodiments where the first feature and the second feature are directly attached, and also includes embodiments where other features are formed between the first feature and the second feature, so that the first feature and the second feature are not directly attached.

[0043] In addition, the spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper”, etc., are for easily describing the relationship between the elements or features depicted in the drawings and other elements or features. The spatially relative terms include different directions of the element during use or operation in addition to the directions depicted in the drawings. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptions used herein can also be interpreted accordingly.

[0044] The term “nominal” refers to the expected value or target value of the characteristic or parameter of the element or process operation set during the design stage of the product or process, as well as the range values above and / or below this expected value. The range values are generally attributed to slight variations or tolerances during the manufacturing process.

[0045] In some embodiments, the terms “about” and “substantially” may mean that the given value is within a deviation of 5% of the target value (for example: ±1%, ±2%, ±3%, ±4%, ±5% of the target value).

[0046] The term “perpendicular” used herein means nominally perpendicular to the surface of the substrate.

[0047] A resistor is a passive electronic component used in electronic circuits. For example, a resistor is used to reduce the current flow, adjust the signal level, distribute voltage, and apply bias to active components. In integrated circuits (ICs), resistors can be combined with other IC components (such as transistors, memory arrays, capacitors, etc.) and formed simultaneously. Important parameters of resistors in ICs include sheet resistance, numerical tolerance (such as the percentage error in impedance in a resistor), the contribution of parasitic capacitance, the temperature coefficient of resistance (TCR), and the voltage coefficient of resistance (VCR). For example, TCR and VCR are metrics that can be used to evaluate the stability of resistor impedance within a temperature range or a voltage range, respectively.

[0048] In IC manufacturing, metal gate (MG) materials and high-k dielectric materials (such as high-k dielectric materials (HK dielectric materials)) can be used in the fabrication of field effect transistors (FETs). Resistors and FETs can be fabricated simultaneously in an IC. For example, MG and HK dielectric materials can be implemented during the manufacturing process of resistors to simplify, coordinate, and streamline the manufacturing processes between FETs and resistors.

[0049] When a resistor with a relatively high sheet resistance (e.g., the sheet resistance is substantially greater than 500 Ω / square) is required, titanium nitride (TiN) can replace the metal gate material in the resistor structure. This is because while a resistor with TiN (TiN resistor) has a sheet resistance of substantially 500 Ω / square to 1000 Ω / square (e.g., more than an order of magnitude higher), a resistor with an MG material (MG resistor) has a sheet resistance of substantially 30 Ω / square to 130 Ω / square. However, resistors of the aforementioned types may suffer from poor current density. For example, an MG resistor has a maximum current density (Jmax) of substantially 0.05xW mA to 0.5xW mA, and a TiN resistor has a Jmax of substantially 0.1xW mA to 1xW mA, where "W" refers to the width of the resistor structure.

[0050] Some embodiments of the present disclosure describe a method of forming a resistor incorporating HK dielectric and polysilicon to form a polysilicon resistor, which has a wider sheet resistance range, higher Jmax, and improved performance compared to TiN resistors and MG resistors. The resulting polysilicon resistor can be silicided or non-silicided, and the polysilicon resistor can be fabricated side-by-side adjacent to devices using HK / MG materials. In some embodiments, the resulting silicided resistor can have a Jmax substantially between 1xW mA and 10xW mA, and the non-silicided resistor can have a Jmax substantially between 0.1xW mA and 1xW mA. Additionally, the silicided resistor and non-silicided resistor have a lower sheet resistance range when compared to TiN resistors and MG resistors corresponding to the silicided and non-silicided resistors. Furthermore, the polysilicon resistor is compatible with the manufacturing methods for HK / MG devices.

[0051] According to some embodiments, Figure 1 FIG. 5 is a top view schematic diagram showing a polysilicon resistor structure 100 having a width of 100W and a length of 100L, wherein the ratio of the length of the resistor to the width of the resistor is greater than 1, e.g., 100L / 100W > 1. The polysilicon resistor structure 100 further includes contact regions 105 and 110, and contact structures 115 are respectively formed on the contact regions 105 and 110. In some embodiments, the contact structure 115 includes a conductive material, such as cobalt (Co) or tungsten (W). The contact structure 115 electrically connects the polysilicon resistor structure 100 to other components or regions of the IC, and for the purpose of simplicity, these other components or regions are not shown in Figure 1 FIG. 5. By way of illustration and not limitation, the electron flow (current) in the polysilicon resistor structure 100 flows from the contact structure 115 in the contact region 105 to the contact structure 115 in the contact region 110. The current in the polysilicon resistor structure 100 flows through a polysilicon layer or a silicided layer (not shown in Figure 1 FIG. 5). The resistor structure 100 is not limited to Figure 1 the description of FIG. 5, and fewer or more contact structures 115 are possible. Furthermore, the contact structure 115 can have different sizes or shapes. Similarly, depending on the resistor design and the required voltage or current, the contact regions 105 and 110 can be larger or smaller.

[0052] In some embodiments, the resistance of the polysilicon resistor structure 100 can be adjusted through its dimensions (e.g., length 100L and width 100W). According to the desired resistance value or other layout considerations (e.g., minimum spacing of adjacent structures, etc.), the dimensions of the polysilicon resistor structure 100 can be defined through patterning (e.g., by photolithography or etching operations). In some embodiments, multiple polysilicon resistor structures (such as the polysilicon resistor structure 100) having different or similar resistances can be formed throughout the IC.

[0053] In some embodiments, Figure 2 is a perspective view showing the polysilicon resistor structure 100. By way of illustration and not limitation, Figure 1 may be a top view of the polysilicon resistor structure 100. Although Figure 2 does not show Figure 1 the contact structure 115, Figure 2 shows other structural elements of the polysilicon resistor structure 100. For example, the polysilicon resistor structure 100 is formed on the isolation region 200, and the isolation region 200 is embedded in the semiconductor substrate 210. In some embodiments, the isolation region 200 is a shallow trench isolation region (e.g., a Shallow Trench Isolation (STI) region), and the shallow trench isolation region includes a dielectric material (e.g., silicon dioxide (SiO2)) or a low dielectric constant dielectric material (e.g., having a dielectric constant lower than 3.9). The isolation region 200 is formed in the semiconductor substrate 210 to provide electrical isolation between the doped regions of the semiconductor substrate 210. The isolation region 200 may extend laterally along the Figure 2 x-y plane of

[0054] Through the dielectric layer 220, the polysilicon resistor structure 100 is laterally separated from adjacent devices or structures ( Figure 2 not shown). In some embodiments, the dielectric layer 220 may be an interlayer dielectric layer such as SiO2, doped SiO2, or any other suitable dielectric material, where the other suitable dielectric material has a dielectric constant substantially equal to or less than 3.9 (e.g., substantially 3.6 or 3.3). As Figure 2 shown, by way of illustration and not limitation, the dielectric layer 220 surrounds the side surfaces of the polysilicon resistor structure 100.

[0055] In some embodiments, the polysilicon resistor structure 100 includes the following stack: (1) an HK dielectric layer 230 formed on an isolation region 200; (2) a metal nitride layer 240 formed on the HK dielectric layer 230; and (3) a polysilicon layer 250 formed on the metal nitride layer 240. By way of illustration and not limitation, the HK dielectric layer 230 may include a metal oxide (e.g., hafnium dioxide), and the metal oxide has a dielectric constant (k value) substantially greater than 3.9 (e.g., substantially between 4.0 and 40). In some embodiments, the HK dielectric layer 230 has a thickness substantially between and (e.g., substantially between and , substantially between and , substantially between and , substantially between and , substantially between and , substantially between and and substantially between and ). By way of illustration and not limitation, the metal nitride layer 240 may include titanium nitride and may have a thickness substantially between and (e.g., substantially between and , substantially between and , substantially between and , substantially between and , substantially between and , substantially between and and substantially between and ). In some embodiments, the polysilicon layer 250 has a thickness 250T in the range substantially between 10 nm and 300 nm (e.g., substantially between 10 nm and 100 nm, substantially between 50 nm and 200 nm, and substantially between 150 nm and 300 nm).

[0056] Furthermore, as Figure 2As shown, on the sidewall of the polysilicon resistor structure 100 and along the length 100L of the polysilicon resistor structure 100, the polysilicon resistor structure 100 includes a spacer structure 260 (for simplicity, it is not shown in FIG. Figure 1 By way of example but not limitation, the spacer structure 260 may include a nitride, such as silicon nitride, and the spacer structure 260 may include one or more layers.

[0057] In some embodiments, the polysilicon layer 250 includes a silicided portion 270, and the silicided portion 270 defines the contact regions 105 and 110, wherein the contact structures (eg, Figure 1 The contact structure 115 shown in FIG. 1 is formed in the contact regions 105 and 110. In some embodiments, as shown in FIG. Figure 2 As shown, the silicided portion 270 is a capping silicide layer that is separated and located at opposite ends of the polysilicon resistor structure 100. In some embodiments, as shown in FIG. Figure 3 As shown in the polysilicon resistor structure 300 , the entire top surface of the polysilicon layer 250 may be silicided.

[0058] In some embodiments, the polysilicon layer 250 includes a top doped layer and a bottom intrinsic (eg, undoped) layer thereunder, and the bottom intrinsic layer is in direct contact with the metal nitride layer 240. For example, Figure 4 It is a diagram showing the section along the section line AB. Figure 2 , wherein the polysilicon layer 250 is shown as having a top doped layer 250A and a bottom intrinsic (e.g., undoped) layer 250B. Herein, because the top doped layer 250A is thinner than the thickness 250T of the polysilicon layer 250, the polysilicon layer 250 is referred to as "partially doped". In some embodiments, when measured from the top surface of the polysilicon layer 250, the thickness of the top doped layer 250A is substantially equal to or greater than If the top doped layer 250A is substantially thinner than The resistance of the resistor structure 100 may be unacceptably high. In some embodiments, the entire thickness 250T of the polysilicon layer 250 (e.g., substantially between 10 nm and 300 nm) is doped, such as when the polysilicon layer 250 is uniformly doped, and the thickness of the bottom intrinsic layer 250B may be substantially zero. In such a case, the polysilicon layer 250 is referred to as "fully doped."

[0059] In some embodiments, the polysilicon layer 250 may be doped by an implantation process. By way of example and not limitation, the polysilicon layer 250 may be doped during a process of forming source / drain regions in a transistor device. By way of example and not limitation, the sacrificial hard mask layer ( Figure 4(not shown) may be formed on the top surface of the polysilicon layer 250 to adjust the implantation depth and the thickness of the top doped layer 250A in this manner. For example, the thickness of the resulting top doped layer 250A may be inversely proportional to the thickness of the sacrificial hard mask layer. For example, the hard mask layer may be a stack of silicon oxide and silicon nitride. In some embodiments, the thickness of the top doped layer 250A may be adjusted by the conditions of the implantation process (such as the implantation energy). In some embodiments, the doping mass range of the top doped layer 250A may be substantially in the range of 1×10 12 cm -2 to 5×10 16 cm -2 , and the dopant species may include n-type (e.g., phosphorus, arsenic, or antimony) or p-type (e.g., boron, indium, or gallium).

[0060] Figure 4 Also included is a contact structure 115 that physically contacts the silicided portion 270 of the polysilicon layer 250. By way of illustration and not limitation, the contact structure 115 includes a conductive material. For example, tungsten or cobalt. In addition, the contact structure 115 is embedded in the dielectric layer 400. In some embodiments, the dielectric layer 400 is an Interlayer Dielectric (ILD) layer, and it includes Undoped Silicate Glass (USG), Phosphosilicate Glass (PSG), Borophosphosilicate Glass (BPSG), a low dielectric constant dielectric (e.g., a dielectric constant substantially less than 3.9), or a combination of the foregoing.

[0061] According to some embodiments, as Figure 4 shown, during the operation of the resistive process, an electron flow (current 410) passes along the length 100L of the resistor through the top doped layer 250A of the polysilicon layer 250. The current 410 enters and exits the resistive structure through the contact structure 115. According to some embodiments, compared to the total resistance of the resistive structure 100, the electrical contact formed between the contact structure 115 and the silicided portion 270 has a negligible resistance.

[0062] According to some embodiments, the resistance of the resistive structure 100 can be adjusted. By way of illustration and not limitation, the resistance of the resistive structure 100 can be considered in terms of (1) the dopant concentration of the top doped layer 250A; (2) the thickness of the top doped layer 250A; (3) as Figure 1 and Figure 2The length 100L and / or width 100W of the resistive structure 100 shown in [figure reference]; or (4) a combination of the foregoing. In some embodiments, for a fixed dopant concentration and thickness of the top doped layer 250A, the resistance of the resistive structure 100 can be adjusted through the physical dimensions of the structure (e.g., length 100L and / or width 100W). In some embodiments, the physical dimensions of the resistive structure 100 can be defined by patterning, e.g., through photolithography and etching operations.

[0063] Figure 5 is a cross-sectional view taken along the cut line CD Figure 3 of the polysilicon resistive structure 300 shown. Figure 3 and Figure 5 the polysilicon resistive structure 300 shown in [figure reference] is different from Figure 2 and Figure 4 the polysilicon resistive structure 100 shown in [figure reference], because the entire top surface of the polysilicon layer 250 is silicided. In other words, the silicided portion 270 in the polysilicon resistive structure 300 covers the entire surface of the polysilicon layer 250. In some embodiments, another difference between the polysilicon resistive structures 100 and 300 lies in their operation. For example, the resistive structure 100 operates by current 410 flowing through the top doped layer 250A of the polysilicon layer 250, while the resistive structure 300 operates by current 410 flowing through the silicided portion 270 of the polysilicon layer 250. Thus, the polysilicon resistive structures 100 and 300 have different electrical properties (e.g., levels of resistance and current density). In some embodiments, the polysilicon resistive structure 100 is referred to as a "non-silicided polysilicon resistor", and the polysilicon resistive structure 300 is referred to as a "silicided polysilicon resistor". In some embodiments, a silicided polysilicon resistor (e.g., the polysilicon resistive structure 300) can be combined with a non-silicided polysilicon resistor (e.g., the polysilicon resistive structure 100) in the same IC. For example, depending on the IC's requirements for resistance and current density, a silicided polysilicon resistor (e.g., the polysilicon resistive structure 300) and a non-silicided polysilicon resistor (e.g., the polysilicon resistive structure 100) can be formed on the same substrate.

[0064] The silicide material in the silicided portion 270 of the polysilicon resistive structures 100 and 300 can be the same or different. By way of illustration but not limitation, the silicide material can be nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, or any other suitable silicide material. In some embodiments, Figure 3 and Figure 5 the thickness range of the silicided portion 270 in the resistive structure 300 shown in [figure reference] is substantially between and therebetween.

[0065] Similar to the polysilicon resistor structure 100, the polysilicon resistor structure 300 may include a partially doped or fully doped polysilicon layer 250. In other words, the polysilicon layer 250 may have a top doped layer 250A, and the top doped layer 250A extends partially within the polysilicon layer 250, or as Figure 3 shown, occupies the entire thickness 250T of the polysilicon layer 250.

[0066] In some embodiments, the polysilicon resistor structures 100 and 300 may be formed in the logic device region of an IC and share common manufacturing operations with memory and / or logic device structures. For example, when a sacrificial polysilicon gate structure is formed in a logic device (e.g., FETs), the polysilicon layer 250 may be formed. Additionally, during the process of forming source / drain regions in the memory array and / or logic device region of the IC, the polysilicon layer 250 may be doped. In other examples, the silicided portion 270 of the polysilicon layer 250 may be formed simultaneously with a silicidation process, where the silicidation process is performed for the polysilicon gates of transistors in the memory array. In other words, in some embodiments, the formation processes of the polysilicon resistor structures 100 and 300 may be combined with the formation processes of the memory array and logic device structures without additional manufacturing operations.

[0067] In some embodiments, a non-silicided polysilicon resistor (e.g., the polysilicon resistor structure 100) has a sheet resistance substantially between 500 Ω / square and 1000 Ω / square for a p-type doped polysilicon layer, and substantially between 100 Ω / square and 500 Ω / square for an n-type doped polysilicon layer. In some embodiments, a silicided polysilicon resistor (e.g., the polysilicon resistor structure 300) has a sheet resistance substantially between 1 Ω / square and 50 Ω / square for a p-type doped polysilicon layer, and substantially between 1 Ω / square and 50 Ω / square for an n-type doped polysilicon layer. In some embodiments, the silicided polysilicon resistor has a lower sheet resistance compared to the non-silicided polysilicon resistor. Therefore, the maximum current density (current carrying capability) of each polysilicon resistor (e.g., silicided or non-silicided) may be different. For example, the maximum current density (Jmax) of the non-silicided polysilicon resistor may be substantially between 0.1xW mA and 1xW mA, and the silicided polysilicon resistor may be substantially between 1xW mA and 10xW mA, where W is the width of the resistor structure (e.g., Figure 2 and Figure 3The widths 100W and 300W respectively shown). According to some embodiments, compared to MG resistors and TiN resistors, polysilicon resistor types (e.g., both non-silicided and silicided) have maximum current density (Jmax) values under limited temperature dependency. For example, these two polysilicon resistor types can carry a high proportion of the maximum current density (Jmax) over a wide temperature range. By way of illustration and not limitation, compared to the Jmax value of a polysilicon resistor operating at 125°C, a polysilicon resistor operating at 110°C has a substantially lower Jmax by 1% to 10%. In contrast, compared to MG resistors and TiN resistors operating at 125°C, MG and TiN resistors operating at 110°C have a substantially lower Jmax by 30% to 90%.

[0068] Figure 6 is a flowchart of a method 600 for forming non-silicided and silicided polysilicon resistors. Other manufacturing operations may be performed between the various operations of method 600 and may be deleted for clarity only. Some embodiments of the present disclosure do not limit method 600. Method 600 will be described with reference to Figures 1 to 5 and Figures 7 to 11 and will be illustrated.

[0069] Please refer to Figure 6 , method 600 begins with the deposition of a resistor stack having an HK layer, a metal nitride layer, and a polysilicon layer in operation 610. The resistor stack of operation 610 includes Figures 2 to 5 the same layers having polysilicon resistor structures 100 and 300 as shown, for example, an HK layer (i.e., HK dielectric layer 230), a metal nitride layer 240, and a polysilicon layer 250. In operation 610, the resistor stack may be deposited blanketly on a semiconductor substrate. For example,[[]] Figure 7 are cross-sectional schematic views taken along Figure 2 and Figure 3 of the cutting lines A'B' and C'D' respectively, and Figure 7 shows a resistor stack 700 deposited blanketly on a semiconductor substrate 210 according to operation 610. In some embodiments, the semiconductor substrate 210 includes additional isolation regions 710. In some embodiments, the isolation regions 710 are filled with a dielectric material, and the dielectric material may be different from the dielectric material of the isolation region 200. By way of illustration and not limitation, the isolation region 200 may include a low dielectric constant dielectric material (e.g., a material having a k value substantially less than 3.9), while the isolation region 710 may include silicon oxide having a k value substantially equal to 3.9.

[0070] In some embodiments, before depositing the HK layer (i.e., HK dielectric layer 230), an interface layer 720 is grown on the semiconductor substrate 210 to improve the interface quality between the semiconductor substrate 210 and the deposited HK layer (i.e., HK dielectric layer 230). In some embodiments, the interface layer 720 includes a silicon dioxide layer having a thickness substantially between and .

[0071] In some embodiments, as shown in Figure 7 , a hard mask layer 730 is deposited on the resistor stack 700. The hard mask layer 730 can be silicon oxide, silicon nitride, other suitable dielectric materials, or a combination of the foregoing. In some embodiments, the hard mask layer 730 protects the underlying layers during subsequent processes.

[0072] Please refer to Figure 6 and Figure 8 , and method 600 proceeds to operations 620 and patterning of the resistor stack 700 to form a polysilicon resistor structure 800. In some embodiments, the patterning of the resistor stack 700 is accomplished through photolithography and etching operations. During the patterning process of operation 610, the physical dimensions of the polysilicon resistor structure 800 (for example, width 800W and length ( Figure 8 not shown in Figure 2 )) can be defined with reference to the content discussed for the polysilicon resistor structures 100 and 300 in Figure 3 .

[0073] In some embodiments, as shown in Figure 8 , along the sides of the polysilicon resistor structure 800, transistor structures 810 can be formed on the semiconductor substrate 210 and between the isolation regions 200 and 710. The physical dimensions of the transistor structures 810 can be independent of the physical dimensions of the polysilicon resistor structure 800. In other words, the design rules for controlling the transistor structures 810 and the polysilicon resistor structure 800 can be different. This is because the transistor structures 810 are active devices and have different functions from the polysilicon resistor structure 800. In addition, before or during the process of forming the polysilicon resistor structure 800 and the transistor structures 810, additional devices (such as transistors and capacitors) or arrays (such as memory arrays) can be formed in other regions of the semiconductor substrate 210. For simplicity, these other structures are not shown in Figure 8 , and these other structures are within the spirit and scope of an embodiment of the present disclosure.

[0074] In some embodiments, during the patterning process described in operation 620, multiple resistor structures (such as the polysilicon resistor structure 800) can be defined (formed). In addition, not all of the polysilicon resistor structures formed according to method 600 can have the same physical dimensions.

[0075] In some embodiments, a lightly doped implant may be used to form the source / drain extension regions of the transistor structure 810. For simplicity, these extension regions are not shown in Figure 8 . According to some embodiments, as Figure 8 shown, a spacer structure 260 is formed on the sidewall surfaces of the polysilicon resistor structure 800 and the transistor structure 810. By way of illustration and not limitation, the spacer structure 260 may be formed by blanket deposition of a spacer material (such as silicon nitride), and then by an anisotropic etching process, where the anisotropic etching process selectively removes the spacer material from the horizontal surfaces of the structures as shown in Figure 8 .

[0076] Referring to Figure 6 , method 600 proceeds to operation 630, where the polysilicon layer 250 of the polysilicon resistor structure 800 is implanted with dopants to form a top doped layer 250A. In some embodiments, referring to Figure 8 , and during the implantation process described in operation 630, source / drain regions of the transistor structure 810 may be formed in the semiconductor substrate 210 adjacent to the spacer structure 260. In other words, during operation 630, the top doped layer 250A in the polysilicon resistor structure 800 and the source / drain regions 820 in the transistor structure 810 may be formed simultaneously. Thus, the source / drain regions 820 and the top doped layer 250A may share the same type of dopant (e.g., n-type or p-type). According to some embodiments, the advantage of operation 630 is that the top doped layer 250A in the resistor structure and the source / drain regions 820 in the transistor structure are formed from a single operation (operation 630). This approach eliminates the need for separate process operations that would otherwise be used to form the top doped layer 250A and the source / drain regions 820.

[0077] In some embodiments, when measured from the top surface of the polysilicon layer 250, the thickness of the top doped layer 250A is substantially between 5 nm and 200 nm or substantially the total thickness 250T of the polysilicon layer 250, where the total thickness 250T of the polysilicon layer 250 may range substantially from 10 nm to 300 nm (e.g., substantially between 10 nm and 100 nm, substantially between 50 nm and 200 nm, and substantially between 150 nm and 300 nm).

[0078] According to some embodiments, a silicide 830 may be formed on the source / drain regions 820 of the transistor structure 810. For example, by blanket depositing a metal (such as titanium, nickel, cobalt, tungsten, etc.) and subsequently annealing the semiconductor substrate 210 to initiate a silicidation reaction between the metal deposited in the source / drain regions 820 and the semiconductor material (such as silicon), the silicide 830 may be formed. Any unreacted metal may be removed by a wet etching process.

[0079] In some embodiments, as Figure 9 shown, the hard mask layer 730 is removed from the polysilicon resistor structure 800 and the transistor structure 810, and an etch stop layer 900 may be formed on the polysilicon resistor structure 800 and the transistor structure 810. The etch stop layer 900 may extend over the isolation regions 200 and 710, the exposed portions of the source / drain regions 820, and the semiconductor substrate 210. In some embodiments, the etch stop layer 900 may cover other structures (such as a memory array) on the semiconductor substrate 210, where these other structures are not shown in Figure 9 . It should be noted that, for simplicity, the etch stop layer 900 is not shown in Figure 2 and Figure 3 .

[0080] Please refer to Figure 6 , method 600 proceeds to operation 640 and the process of forming a dielectric layer around the polysilicon resistor structure 800. In some embodiments, the dielectric layer of operation 640 is the dielectric layer 220 shown in Figures 2 to 5 . By way of illustration and not limitation, a dielectric layer (such as the dielectric layer 220) may be formed by blanket depositing a dielectric material on the exposed portions of the polysilicon resistor structure 800, the transistor structure 810, the isolation regions 200 and 710, the source / drain regions 820, and the semiconductor substrate 210. In some embodiments, the dielectric layer may cover other structures (such as a memory array) on the semiconductor substrate 210, and these other structures are not shown in Figure 10 . As Figure 10 shown, a Chemical Mechanical Polishing (CMP) process may then be performed to planarize and remove excess dielectric material from the tops of the polysilicon resistor structure 800 and the transistor structure 810. In some embodiments, the etch stop layer 900 serves as the stop layer for the CMP process of operation 640.

[0081] In a subsequent operation, the semiconductor material (i.e., the aforementioned polysilicon layer 250) in the transistor structure 810 is removed and replaced with a metal gate electrode 1000. In some embodiments, the metal gate electrode 1000 includes one or more metal layers.

[0082] Please refer toFigure 6 With Figure 10 , method 600 proceeds to operation 650, where silicide 1010 is formed on the top surface of polysilicon layer 250 of polysilicon resistor structure 800. According to some embodiments, the surface area of silicide 1010 is equivalent to Figure 2 With Figure 3 the silicided portion 270 shown. As previously Figure 2 With Figure 3 discussed, the silicided portion 270 can extend to the entire surface of polysilicon layer 250 as shown in Figure 3 to form a silicided polysilicon resistor structure 800. In some embodiments, as shown in Figure 2 , silicide 1010 is confined to the "edges" of the resistor structure, resulting in a non-silicided polysilicon resistor structure 800. If a non-silicided resistor structure (such as resistor structure 100 in Figure 2 ) is desired, the non-silicided portion of the top polysilicon layer 250 can be covered with a hard mask layer (such as an oxide or nitride) before the silicidation process. If a silicided resistor structure (such as resistor structure 300 in Figure 3 ) is desired, the polysilicon layer 250 can be exposed during the silicidation process.

[0083] The silicidation process can be similar to the silicidation process described previously for the source / drain regions 820. In some embodiments, during the silicidation process of operation 650, other structures on semiconductor substrate 210 can also be silicided. For example, polysilicon gate structures in a memory array (such as a non-volatile memory array like an embedded flash memory array) can be silicided simultaneously with the resistor structure. This eliminates the need for a separate silicidation process, which is the process of forming silicide 1010 in polysilicon resistor structure 800 and on other structures of semiconductor substrate 210.

[0084] Please refer to Figure 6 With Figure 11 , method 600 proceeds to operation 660 and the process of forming contacts on polysilicon resistor structure 800. This operation can be completed by depositing another dielectric layer (such as dielectric layer 400 shown in Figure 4 With Figure 5 ) on dielectric layer 220. In some embodiments, the dielectric layer (e.g., dielectric layer 400) of operation 660 is deposited blanketly on the structures of semiconductor substrate 210 and is subsequently planarized as shown in Figure 11 . Then, dielectric layer 400 is etched to form contact openings, where the contact openings partially expose silicide 1010 of polysilicon resistor structure 800. Conductive material is deposited to fill the etched openings. The excess conductive material on the top surface of dielectric layer 400 is then planarized to formFigure 11 The contact structure 115 shown.

[0085] In some embodiments, more than one contact structure 115 may be formed simultaneously on a polysilicon resistor structure 800 as Figure 1 shown. Further, the contact structures 115 are aligned and physically connected to a silicided portion 270 of a polysilicon layer 250 as Figures 2 to 5 shown. This ensures a low contact resistance between the contact structure 115 and the polysilicon resistor structure 800. According to some embodiments, additional contacts may be formed on other structures of the IC, and these additional contacts include contacts to source / drain regions 820, contacts to metal gate electrodes 1000, and contacts to Figure 11 other structures not shown (such as memory arrays, capacitor structures, etc.).

[0086] Some embodiments of the present disclosure disclose methods of forming polysilicon resistors, and these polysilicon resistors incorporate HK dielectrics and polysilicon. These polysilicon resistors may be silicided or non-silicided, have a wide range of sheet resistances, and have a higher current-carrying capacity over a larger temperature range compared to MG resistors and TiN resistors. According to some embodiments of the present disclosure, the resulting polysilicon resistors can be fabricated along with HK / MG FETs and other devices (such as memory arrays) at a lower cost and with no substantial process changes. In some embodiments, the resulting silicided and non-silicided polysilicon resistors provide current densities substantially between 1xW mA and 10xW mA and between 0.1xW mA and 1xW mA, respectively, where W is the width of the resistor structure. Additionally, the polysilicon resistors described herein are compatible with the manufacturing methods for HK / MG devices.

[0087] In some embodiments, a semiconductor structure includes a semiconductor substrate having a first isolation region and a second isolation region formed therein and separated therefrom, where the first isolation region is wider than the second isolation region. The semiconductor substrate further includes a resistor structure disposed on the first isolation region, where the resistor structure includes a dielectric layer, a nitride layer, and a semiconductor layer, the dielectric layer contacting the first isolation region, the nitride layer disposed on the dielectric layer, the semiconductor layer disposed on the nitride layer, the semiconductor layer including a doped top portion having a silicided portion, and the silicided portion formed on an opposite end of the doped top portion. The semiconductor structure also includes a transistor structure disposed between the first isolation region and the second isolation region. The transistor structure includes an interface layer, a metal gate electrode, and source / drain regions, where the interface layer contacts the semiconductor substrate, the aforementioned dielectric layer is disposed on the interface layer, the nitride layer is disposed on the dielectric layer, the metal gate electrode is disposed on the nitride layer, the source / drain regions are formed in the semiconductor substrate, and the source / drain regions are adjacent to the metal gate electrode.

[0088] According to some embodiments of the present disclosure, the aforementioned silicided portion includes a contact region, and this contact region is located on the semiconductor layer.

[0089] According to some embodiments of the present disclosure, the aforementioned semiconductor layer has a thickness substantially ranging from 10 nm to 300 nm.

[0090] According to some embodiments of the present disclosure, the aforementioned doped top portion extends along the top surface of the semiconductor layer.

[0091] According to some embodiments of the present disclosure, the doped top portion of the aforementioned semiconductor layer has a thickness substantially ranging from 10 nm to 300 nm.

[0092] According to some embodiments of the present disclosure, the aforementioned dielectric layer includes a high-k dielectric.

[0093] According to some embodiments of the present disclosure, the aforementioned interface layer includes a silicon-based dielectric.

[0094] According to some embodiments of the present disclosure, the aforementioned semiconductor structure further includes one or more conductive structures, and these or these conductive structures are located on the silicided portion.

[0095] In some embodiments, the method includes depositing a resist stack on a substrate, and this substrate includes a separated first isolation region and a second isolation region, wherein the operation of depositing the resist stack includes depositing a metal oxide dielectric layer on the substrate; depositing a metal nitride layer on the metal oxide dielectric layer; and depositing a polysilicon layer on the metal nitride layer. Next, the method includes patterning the resist stack to form a polysilicon resistor structure on the first isolation region and forming a gate structure between the first isolation region and the second isolation region; and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and forming source / drain regions in the substrate, wherein the source / drain regions are adjacent to the gate structure. Furthermore, the method includes forming a dielectric layer between the polysilicon resistor and the gate structure; replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure having a gate structure and source / drain regions; and forming a silicide on the doped layer of the polysilicon layer in the polysilicon transistor structure.

[0096] According to some embodiments of the present disclosure, the operation of doping the polysilicon resistor structure includes forming a doped layer having a thickness substantially ranging from 10 nm to 300 nm when measured from the top surface of the polysilicon resistor structure.

[0097] According to some embodiments of the present disclosure, the operations of doping the polysilicon resistor structure and the transistor structure include forming a doped layer and source / drain regions having the same dopant.

[0098] According to some embodiments of the present disclosure, the operation of forming a silicide on the doped layer includes forming a silicide on the top surface of the polysilicon layer of the polysilicon resistor structure.

[0099] According to some embodiments of the present disclosure, the operation of forming a silicide on the doped layer includes forming a silicide on multiple opposite ends of the polysilicon resistor structure.

[0100] According to some embodiments of the present disclosure, the operation of patterning a resistor stack to form a polysilicon resistor structure and a gate structure includes forming a hard mask layer on the resistor stack; patterning the hard mask layer; and removing the resistor stack not covered by the hard mask layer.

[0101] According to some embodiments of the present disclosure, the operation of depositing a metal oxide dielectric layer on a substrate includes depositing a metal oxide having a dielectric constant substantially higher than 3.9.

[0102] In some embodiments, a structure includes a substrate and a polysilicon resistor. The substrate includes a separated first isolation region and a second isolation region, and the polysilicon resistor is located on the first isolation region. The polysilicon resistor includes a metal oxide dielectric layer, a metal nitride layer, and a polysilicon layer, and the polysilicon layer has a top surface with a silicided portion. Secondly, the structure includes a transistor structure formed between the first isolation region and the second isolation region, and the transistor structure includes a metal oxide dielectric layer, a metal nitride layer, and a metal gate electrode. The structure also includes one or more contacts on the silicided portion of the polysilicon layer.

[0103] According to some embodiments of the present disclosure, the aforementioned silicided portion covers the entire top surface of the polysilicon layer.

[0104] According to some embodiments of the present disclosure, the aforementioned polysilicon layer includes another silicided portion separated from the silicided portion.

[0105] According to some embodiments of the present disclosure, the aforementioned polysilicon layer is uniformly doped with multiple dopants, and the polysilicon layer has a thickness substantially from 10 nm to 300 nm.

[0106] According to some embodiments of the present disclosure, the aforementioned polysilicon layer includes a doped layer, and the doped layer contacts the silicided portion of the top surface.

[0107] It should be understood that the detailed description (rather than the abstract) is intended to interpret the claims. The abstract may present one or more (but not all) embodiments of the present disclosure as conceived by the inventors, and thus is not intended to limit the appended claims of the present disclosure in any way.

[0108] The foregoing has outlined features of several embodiments in order that those skilled in the art may better understand the aspects of one embodiment of the present disclosure. Those skilled in the art should understand that they can readily use the aspects of one embodiment of the present disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or achieving the same advantages as those introduced herein. Those skilled in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the aspects of one embodiment of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the aspects of one embodiment of the present disclosure.

Claims

1. A polysilicon resistor structure, characterized in that, The polysilicon resistor structure includes: A semiconductor substrate having a first isolation region and a second isolation region formed in the semiconductor substrate and separated from each other, wherein the first isolation region is wider than the second isolation region; A resistor structure disposed on the first isolation region, wherein the resistor structure includes: A dielectric layer contacting the first isolation region; A nitride layer disposed on the dielectric layer; and A semiconductor layer disposed on the nitride layer, and the semiconductor layer includes a doped top portion having a silicided portion, the semiconductor layer is uniformly doped, and the silicided portion covers the entire top surface of the semiconductor layer; and A transistor structure disposed between the first isolation region and the second isolation region, wherein the transistor structure includes: An interface layer contacting the semiconductor substrate, wherein the dielectric layer is disposed on the interface layer; A metal gate electrode disposed on the dielectric layer; and A source / drain region formed in the semiconductor substrate and adjacent to the metal gate electrode.

2. The polysilicon resistor structure according to claim 1, wherein The silicided portion includes a contact region, and the contact region is located on the semiconductor layer.

3. The polysilicon resistor structure according to claim 1, characterized in that, The semiconductor layer has a thickness substantially between 10 nm and 300 nm.

4. The polysilicon resistor structure according to claim 1, wherein The doped top portion extends along a top surface of the semiconductor layer.

5. The polysilicon resistor structure according to claim 1, wherein, The doped top portion of the semiconductor layer has a thickness substantially between 10 nm and 300 nm.

6. The polysilicon resistor structure according to claim 1, wherein, The dielectric layer includes a high-k dielectric.

7. The polysilicon resistor structure according to claim 1, characterized in that The interface layer includes a silicon-based dielectric.

8. The polysilicon resistor structure according to claim 1, wherein The polysilicon resistor structure includes one or more conductive structures, and the one or more conductive structures are located on the silicided portion.

9. A manufacturing method of a polysilicon resistor structure, characterized in that, The manufacturing method includes: Depositing a resistor stack on a substrate, wherein the substrate includes a first isolation region and a second isolation region separated from each other, and the operation of depositing the resistor stack includes: Depositing a metal oxide dielectric layer on the substrate; Depositing a metal nitride layer on the metal oxide dielectric layer; and Depositing a polysilicon layer on the metal nitride layer; Patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and to form a gate structure between the first isolation region and the second isolation region; Doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and to form a source / drain region in the substrate, wherein the substrate is adjacent to the gate structure, and the polysilicon layer is uniformly doped; Forming a dielectric layer between the polysilicon resistor structure and the gate structure; Replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure, wherein the transistor structure includes the gate structure and the source / drain region; and Forming a silicide on the doped layer of the polysilicon layer, wherein the polysilicon layer is in the transistor structure, and the silicide covers the entire top surface of the polysilicon layer.

10. The manufacturing method of the polysilicon resistor structure according to claim 9, characterized in that, The operation of doping the polysilicon resistor structure includes: Forming the doped layer having a thickness substantially between 10 nm and 300 nm when measured from a top surface of the polysilicon resistor structure.

11. The manufacturing method of the polysilicon resistor structure according to claim 9, characterized in that, The operation of doping the polysilicon resistor structure and the transistor structure includes: Forming the doped layer and the source / drain region having the same dopant.

12. The manufacturing method of the polysilicon resistor structure according to claim 9, characterized in that The operation of forming the silicide on the doped layer includes: Forming the silicide on a top surface of the polysilicon layer of the polysilicon resistor structure.

13. The manufacturing method of the polysilicon resistor structure according to claim 9, characterized in that, The operation of patterning the resistor stack to form the polysilicon resistor structure and the gate structure includes: Forming a hard mask layer on the resistor stack; Patterning the hard mask layer; and Removing the resistor stack not covered by the hard mask layer.

14. The manufacturing method of the polysilicon resistor structure according to claim 9, characterized in that, The operation of depositing the metal oxide dielectric layer on the substrate includes: Depositing a metal oxide having a dielectric constant substantially higher than 3.

9.

15. A polysilicon resistor structure, characterized in that, The polysilicon resistor structure includes: A substrate including a first isolation region and a second isolation region separated from each other; A polysilicon resistor on the first isolation region, wherein the polysilicon resistor includes: A metal oxide dielectric layer; A metal nitride layer; and A polysilicon layer having a top surface including a silicided portion, wherein the polysilicon layer includes a doped layer, the polysilicon layer is uniformly doped, and the silicided portion covers the entire top surface of the polysilicon layer; A transistor structure formed between the first isolation region and the second isolation region; wherein the transistor structure includes: The metal oxide dielectric layer; The metal nitride layer; and A metal gate electrode; and One or more contacts on the silicided portion of the polysilicon layer.

16. The polysilicon resistor structure according to claim 15, wherein And the polysilicon layer has a thickness substantially of 10 nm to 300 nm.

17. The polysilicon resistor structure according to claim 15, wherein The doped layer contacts the silicided portion of the top surface.

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