Semiconductor devices

Abstract

A semiconductor device is provided. The semiconductor device includes: a peripheral circuit region located on a first substrate and including a circuit device; a memory cell region located on a second substrate covering the first substrate, wherein the memory cell region includes gate electrodes stacked spaced apart from each other in a first direction perpendicular to the upper surface of the second substrate; and a channel structure extending vertically on the second substrate and penetrating the gate electrode. The channel structure may include a channel layer. The semiconductor device includes a through wiring region having a through contact plug, the through contact plug extending in the first direction and electrically connecting the memory cell region and the peripheral circuit region to each other, wherein the through wiring region includes an insulating region surrounding the through contact plug. The through wiring region also includes a dummy channel structure regularly arranged throughout the through wiring region and including a channel layer.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0101591 filed on August 20, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety for all purposes by reference. Technical Field

[0002] The inventive concept relates to a semiconductor device. Background Art

[0003] Semiconductor devices are becoming smaller and smaller, and require larger and larger capacities to perform operations such as data processing. Therefore, it is desirable to increase the integration of semiconductor elements constituting such semiconductor devices. One proposed method for increasing the integration of semiconductor devices is to incorporate a vertical transistor structure instead of a planar transistor structure of the related art. Summary of the invention

[0004] Aspects of the present disclosure provide a semiconductor device having improved reliability.

[0005] According to one aspect of the present invention, a semiconductor device includes: a peripheral circuit region located on a first substrate and including a circuit device; a memory cell region located on a second substrate arranged above the first substrate, wherein the memory cell region includes gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, wherein the memory cell region includes a channel structure penetrating the gate electrode and extending vertically on the second substrate, wherein the channel structure includes a channel layer; and a through wiring region electrically connecting the memory cell region and the peripheral circuit region. The through wiring region includes: a through contact plug extending in a first direction and penetrating through the memory cell region, and electrically connecting the memory cell region and the circuit device; an insulating region surrounding the through contact plug, wherein the insulating region includes a first insulating layer parallel to the second substrate and a second insulating layer and a third insulating layer alternately stacked on the first insulating layer; and a dummy channel structure penetrating the second insulating layer and the third insulating layer and including a channel layer. The dummy channel structures are arranged in rows and columns so that at least one dummy channel structure is located between through contact plugs adjacent to each other.

[0006] According to one aspect of the present invention, a semiconductor device includes: a peripheral circuit region located on a first substrate and including a circuit device; a memory cell region located on a second substrate arranged above the first substrate, the memory cell region including a stacked structure having a spaced-apart gate electrode above the second substrate, the memory cell region including a channel structure extending vertically to the second substrate and penetrating through the gate electrode. The channel structure may include a channel layer. The semiconductor device may include a through wiring region, the through wiring region including a through contact plug extending in a first direction and electrically connecting the memory cell region and the peripheral circuit region to each other, wherein the through wiring region includes an insulating region surrounding the through contact plug. The through wiring region also includes a dummy channel structure regularly arranged throughout the through wiring region and including a channel layer.

[0007] According to some aspects of the present inventive concept, a semiconductor device includes: a first substrate; a circuit device located on the first substrate; a second substrate located on the circuit device; gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate; a channel structure penetrating through the gate electrode and extending vertically on the second substrate. The channel structure may include a channel layer. The semiconductor device may include a separation region extending in a second direction perpendicular to the first direction and penetrating the gate electrode, wherein the separation regions are spaced apart from each other and parallel to each other. The semiconductor device may include a through wiring region positioned between adjacent separation regions and spaced apart from adjacent separation regions, wherein the through wiring region includes a through contact plug that electrically connects the circuit device and the gate electrode to each other, an insulating region surrounding the through contact plug, and a dummy channel structure including a channel layer provided in a number at least the same as the number of through contact plugs. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a schematic block diagram of a semiconductor device according to some example embodiments;

[0010] Figure 2 is an equivalent circuit diagram of a cell array of a semiconductor device according to some example embodiments;

[0011] Figure 3 is a schematic layout diagram showing an arrangement of a semiconductor device according to some example embodiments;

[0012] Figure 4 is a schematic plan view of a semiconductor device according to some example embodiments;

[0013] Figure 5A and Figure 5Bis a schematic cross-sectional view of a semiconductor device according to some example embodiments;

[0014] Figure 6 is a schematic enlarged view showing a portion of a semiconductor device according to some example embodiments;

[0015] 7A to 7C is a plan view of a semiconductor device according to some example embodiments;

[0016] Figure 8 and Fig. 9 are schematic plan views and cross-sectional views of semiconductor devices according to some example embodiments;

[0017] Fig. 10A and Fig. 10B is a partial enlarged view of a semiconductor device according to some example embodiments;

[0018] Fig.11 is a schematic cross-sectional view of a semiconductor device according to some example embodiments;

[0019] FIG. 12A to FIG. 12C is a schematic cross-sectional view of a semiconductor device according to some example embodiments;

[0020] FIG. 13A to FIG. 13E is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to some example embodiments; and

[0021] FIG. 14A to FIG. 14F is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to some example embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, some example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0023] Figure 1 is a schematic block diagram of a semiconductor device according to some example embodiments.

[0024] Reference Figure 1 , the semiconductor device 10 may include a memory cell array (or simply referred to as a “cell array”) 20 and a peripheral circuit 30. The peripheral circuit 30 may include a row decoder 32, a page buffer 34, an input / output (I / O) buffer 35, a control logic 36, and a voltage generator 37.

[0025] The memory cell array 20 may include a plurality of memory blocks, and each of the memory blocks may include a plurality of memory cells. The plurality of memory cells may be connected to a row decoder 32 via a string selection line SSL, one or more word lines WL, and a ground selection line GSL, and may be connected to a page buffer 34 via one or more bit lines BL. In some example embodiments, the plurality of memory cells may be arranged in rows and columns. In some example embodiments, a plurality of memory cells arranged in the same row may be connected to the same word line WL, and a plurality of memory cells arranged in the same column may be connected to the same bit line BL.

[0026] The row decoder 32 may receive an input address ADDR from the control logic 36, and may decode the input address ADDR to generate and transmit a driving signal of the word line WL. The row decoder 32 may provide corresponding word line voltages generated from the voltage generator 37 to the selected word line WL and the unselected word line WL in response to the control of the control logic 36.

[0027] The page buffer 34 may be connected to the memory cell array 20 through the bit line BL to read the information stored in the memory cell. Depending on the operation mode, the page buffer 34 may temporarily store the data to be stored in the memory cell or may read out the data stored in the memory cell. The page buffer 34 may include a column decoder and a sense amplifier. The column decoder may selectively activate the bit line BL of the memory cell array 20 in response to a signal received from the control logic 36, and the sense amplifier may sense the voltage of the bit line BL selected by the column decoder during a read operation to read the data stored in the selected memory cell.

[0028] The input / output buffer 35 may receive data DATA to transfer the data to the page buffer 34 during a program operation, and may output data received from the page buffer 34 to the outside during a read operation. The input / output buffer 35 may transfer an input address or a command to the control logic 36.

[0029] The control logic 36 may control the operations of the row decoder 32 and the page buffer 34. The control logic 36 may receive one or more control signals and an external voltage transmitted from a source outside the semiconductor device 10, and may operate in response to the received one or more control signals. The control logic 36 may control the read, write, and / or erase operations of the semiconductor device 10 in response to the one or more control signals.

[0030] The voltage generator 37 can generate voltages required for internal operations, such as programming voltages, reading voltages, erasing voltages, etc. These voltages can be generated from external voltages or by using external voltages. The voltages generated by the voltage generator 37 can be transmitted to the memory cell array 20 through the row decoder 32.

[0031] Figure 2 is an equivalent circuit diagram of a cell array of a semiconductor device according to example embodiments.

[0032] Reference Figure 2 , the memory cell array 20 may include a plurality of memory cell strings S. Each memory cell string S may include memory cells MC connected in series to each other, a ground selection transistor GST at one end of a series of memory cells MC, and string selection transistors SST1 and SST2 at the other end of a series of memory cells MC. Two or more of the plurality of memory cell strings S may be connected in parallel to corresponding bit lines BL0 to BL2. The plurality of memory cell strings S may be commonly connected to a common source line CSL. For example, the plurality of memory cell strings S may be between a plurality of bit lines BL0 to BL2 and a common source line CSL. In some example embodiments, in the case of a common source line CSL, the plurality of common source lines may be arranged two-dimensionally.

[0033] The memory cells MC connected in series to each other may be controlled by word lines WL0 to WLn for selecting the memory cells MC. Each of the memory cells MC may include a data storage element. The gate electrodes of the memory cells MC having substantially the same distance from the common source line CSL may be commonly connected to one of the word lines WL0 to WLn to be in an equipotential state. Alternatively, although the gate electrodes of the memory cells MC may be substantially the same distance from the common source line CSL, the gate electrodes in different rows or columns may be independently controlled.

[0034] The ground selection transistor GST may be controlled by a ground selection line GSL and may be connected to a common source line CSL. The string selection transistors SST1 and SST2 may be controlled by string selection lines SSL1_1, SSL1_2, SSL1_3, SSL2_1, SSL2_2, and SSL2_3 and may be connected to the bit lines BL0 to BL2. Figure 2A structure in which one ground selection transistor GST and two string selection transistors SST1 and SST2 are respectively connected to a plurality of memory cells MC connected in series with each other is shown, but a structure in which one string selection transistor SST1, SST2 are respectively connected to a plurality of memory cells MC connected in series with each other or a plurality of ground selection transistors GST are connected to a plurality of memory cells MC connected in series with each other may also be provided. One or more dummy lines DWL or buffer lines may be between the topmost word line WLn among the word lines WL0 to WLn and the string selection lines SSL1_1, SSL1_2, SSL1_3, SSL2_1, SSL2_2, and SSL2_3. In some example embodiments, one or more dummy lines DWL may also be between the bottommost word line WL0 and the ground selection line GSL.

[0035] In some embodiments, when a signal is applied to the string selection transistors SST1 and SST2 through the string selection lines SSL1_1, SSL1_2, SSL1_3, SSL2_1, SSL2_2, and SSL2_3, the signal applied through the bit lines BL0 to BL2 is transmitted to the memory cells MC connected in series with each other, and thus, data reading and writing operations can be performed. In addition, by applying a predetermined erase voltage through the substrate, an erase operation of erasing data written to the memory cells MC can be performed. In some example embodiments, the memory cell array 20 may include at least one dummy memory cell string electrically isolated from the bit lines BL0 to BL2.

[0036] Figure 3 is a schematic layout diagram illustrating an arrangement of a semiconductor device according to some example embodiments.

[0037] Reference Figure 3 , the semiconductor device 10A may include a first region R1 and a second region R2 stacked in a vertical direction. The first region R1 may include Figure 1 The second region R2 may include a peripheral circuit 30 , and the second region R2 may include a memory cell array 20 .

[0038] The first region R1 may include one or more row decoders DEC, one or more page buffers PB, and other peripheral circuits PERI. The second region R2 may include memory cell arrays MCA1 and MCA2 and first and second through-wiring regions TB1 and TB2.

[0039] In the first region R1, the row decoder DEC may correspond to the above reference Figure 1 The row decoder 32 described above and the page buffer PB may correspond to the area corresponding to the page buffer 34. Other peripheral circuits PERI may include Figure 1The control logic 36 and the voltage generator 37 may include, for example, a latch circuit, a cache circuit and / or a sense amplifier. The first region R1 may also include a separate pad region. For example, the pad region may include Figure 1 The area of ​​the input / output buffer 35 may include an electrostatic discharge (ESD) device or a data input / output circuit.

[0040] At least a portion of the various circuit regions DEC, PB, and PERI in the first region R1 may be below the memory cell arrays MCA1 and MCA2 of the second region R2. For example, the page buffer PB may be arranged below the memory cell arrays MCA1 and MCA2 so that the memory cell arrays MCA1 and MCA2 overlap with the page buffer PB. In some embodiments, various changes may be made to the circuits included in the first region R1 and the arrangement of the circuits. Therefore, various changes may also be made to the circuits overlapped by the memory cell arrays MCA1 and MCA2.

[0041] In the second region R2, the memory cell arrays MCA1 and MCA2 may be arranged side by side, and in some embodiments may be spaced apart from each other. In some embodiments, various changes may be made to the number and arrangement of the memory cell arrays MCA1 and MCA2 in the second region R2. For example, the memory cell arrays MCA1 and MCA2 may be arranged continuously and repeatedly. Figure 3 Memory cell arrays MCA1 and MCA2 of the example embodiment shown in FIG.

[0042] The first through-wiring area TB1 and the second through-wiring area TB2 may be areas including a wiring structure penetrating through the second area R2 and connected to the first area R1. The first through-wiring area TB1 may be arranged on a first side of the memory cell arrays MCA1 and MCA2, and may include, for example, a wiring structure such as a contact plug electrically connected to a row decoder DEC of the first area R1. The second through-wiring area TB2 may be located in the memory cell arrays MCA1 and MCA2 at predetermined intervals, and may include, for example, a wiring structure of a page buffer PB electrically connected to the first area R1. The number of the first through-wiring areas TB1 may be greater than the number of the second through-wiring areas TB2, and various changes may be made to the shapes, numbers, and positions of the first through-wiring areas TB1 and the second through-wiring areas TB2 in various embodiments.

[0043] Figure 4 is a schematic plan view of a semiconductor device according to some example embodiments.

[0044] Figure 5A and Figure 5B is a schematic cross-sectional view of a semiconductor device according to some example embodiments. Figure 5A and Figure 5B The Figure 4 A cross section taken along line II' and line II-II'.

[0045] Figure 6 is a schematic partial enlarged view of a semiconductor device according to some example embodiments, and is a diagram showing Figure 4 Magnified view of area "C".

[0046] Reference Figures 4 to 6 , the semiconductor device 100 may include a memory cell region CELL and a peripheral circuit region PERI. The memory cell region CELL may be on the peripheral circuit region PERI. In some example embodiments, the memory cell region CELL may be below the peripheral circuit region PERI.

[0047] The memory cell region CELL may include a substrate 101 having a first region A and a second region B, a stack structure GS of a gate electrode 130 stacked on the substrate 101, first and second separation regions MS1 and MS2 extending in a first direction ("X" direction) and penetrating into the stack structure GS of the gate electrode 130 in a third direction ("Z" direction), an upper separation region SS penetrating through a portion of the stack structure GS, a channel structure CH penetrating through the stack structure GS, and first and second through wiring regions TB1 and TB2 penetrating through the stack structure GS and the substrate 101 and connected to the peripheral circuit region PERI. The memory cell region CELL may also include an interlayer insulating layer 120, wirings 175, and a cell region insulating layer 190 alternately stacked with the gate electrode 130 on the substrate 101.

[0048] The first region A of the substrate 101 is a region in which the gate electrodes 130 are vertically stacked and the channel structures CH are arranged, and may be Figure 1 The memory cell array 20 and Figure 3 The second region B is a region in which the gate electrode 130 extends at different lengths and may include Figure 1 The second region B may be located on at least one end of the first region A in at least one direction (eg, X direction).

[0049] The substrate 101 may have an upper surface extending in the X direction and in a second direction ("Y" direction). The substrate 101 may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer or an epitaxial layer.

[0050] The gate electrodes 130 may be stacked to be spaced apart in a vertical direction on the substrate 101 to form a stacked structure GS. Figure 5A and Figure 5B As best seen, the stacked structure GS may include a Figure 2 The lower gate electrode 130G of the gate of the ground selection transistor GST, the plurality of memory gate electrodes 130M forming the plurality of memory cells MC, and the upper gate electrode 130S forming the gate of the string selection transistors SST1 and SST2. The number of the memory gate electrodes 130M constituting the memory cells MC may be determined according to the capacity of the semiconductor device 100. According to some example embodiments, the number of the upper gate electrodes 130S of the string selection transistors SST1 and SST2 and the lower gate electrode 130G of the ground selection transistor GST may be one, or two or more, respectively, and the upper gate electrode 130S and the lower gate electrode 130G may have the same structure as that of the memory gate electrode 130M of the memory cell MC or a different structure. A portion of the gate electrode 130 (e.g., the memory gate electrode 130M adjacent to the upper gate electrode 130S or the lower gate electrode 130G) may be a dummy gate electrode.

[0051] The gate electrodes 130 may be stacked to be vertically spaced apart from each other on the first region A, and may extend from the first region A to the second region B at different lengths to form a stair-like step. The gate electrodes 130 may be formed in the X direction with respect to Figure 5A The steps of the sacrificial insulating layer 180 shown in the figure are the same steps, and steps can also be formed in the Y direction. Through the step portion, because the first gate electrode 130 can extend farther than the second gate electrode 130 above the first gate electrode 130 or the distance from the upper surface of the substrate 101 is farther, the gate electrode 130 can provide an upwardly exposed pad area. The gate electrode 130 can be connected to a separate contact plug in the pad area to connect to the wiring 175 of the upper part. In addition to the upper gate electrode 130S and the lower gate electrode 130G among the gate electrode 130, at least part of the memory gate electrode 130M can form a stack. For example, a predetermined number of memory gate electrodes 130M (for example, four memory gate electrodes 130M) can form a single stack, and steps can be formed between the stacks. The four memory gate electrodes 130M constituting the single stack can be arranged to have steps in the Y direction.

[0052] like Figure 4As shown in , the gate electrodes 130 may be separated from each other in the Y direction by the first separation region MS1 ​​extending in the X direction. The gate electrodes 130 between a pair of first separation regions MS1 may form a single memory block, but the scope of the memory block is not limited thereto. Portions of the gate electrodes 130 (e.g., each of the memory gate electrodes 130M) may form a single layer in one memory block.

[0053] The gate electrode 130 may include a metal material such as tungsten (W). According to some example embodiments, the gate electrode 130 may include polysilicon or a metal silicide material. In some example embodiments, the gate electrode 130 may further include a diffusion barrier, for example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0054] The interlayer insulating layer 120 may be between the gate electrodes 130. Like the gate electrodes 130, the interlayer insulating layers 120 may be spaced apart from each other in a direction perpendicular to the upper surface of the substrate 101 and extend in the X direction. The interlayer insulating layer 120 may include an insulating material such as silicon oxide or silicon nitride.

[0055] The first separation region MS1 ​​and the second separation region MS2 may extend in the X direction while penetrating into the gate electrode 130 in the first region A and the second region B along the Z direction. The first separation region MS1 ​​and the second separation region MS2 may be parallel to each other. The first separation region MS1 ​​and the second separation region MS2 may be connected to the substrate 101 by penetrating all of the gate electrodes 130 stacked on the substrate 101. The first separation region MS1 ​​may extend across the first region A and across the second region B, and the second separation region MS2 may only partially extend across the first region A and / or the second region B. The first separation region MS1 ​​and the second separation region MS2 may not overlap with the first through-wiring region TB1 and the second through-wiring region TB2, and may be spaced apart from the first through-wiring region TB1 and the second through-wiring region TB2. However, in some example embodiments, the arrangement order, number, etc. of the first separation region MS1 ​​and the second separation region MS2 are not limited to Figure 4 The arrangement order, quantity, etc. shown in .

[0056] like Figure 5AAs shown in , the isolation insulating layer 107 and the conductive layer 110 insulated from the gate electrode 130 by the isolation insulating layer 107 may be on at least part of the first separation region MS1 ​​and the second separation region MS2. The conductive layer 110 may have a shape whose width decreases toward the substrate 101 due to a relatively high aspect ratio, but the present disclosure is not limited thereto. For example, the conductive layer 110 may have a side surface perpendicular to the upper surface of the substrate 101. In some example embodiments, the impurity region may be disposed on the substrate 101 in contact with the conductive layer 110.

[0057] In some example embodiments, the conductive layer 110 may be on both the first separation region MS1 ​​and the second separation region MS2. Figure 2 The conductive layer 110 of the second separation region MS2 may correspond to the common source line CSL described above, and the conductive layer 110 of the second separation region MS2 may correspond to the dummy common source line. Therefore, the conductive layer 110 forming the second separation region MS2 may be in a floating state in which the conductive layer 110 is not connected to the elements driving the semiconductor device 100 and / or the electrical signal may not be applied to the conductive layer 110. In some example embodiments, the conductive layer 110 may be omitted. As such, in some example embodiments, the common source line CSL may be formed as a doped layer in the substrate 101 or a conductive layer on the substrate 101, and the first separation region MS1 ​​and the second separation region MS2 may be filled with only an insulating material.

[0058] The upper separation region SS may extend in the X direction between the first separation region MS1 ​​and the second separation region MS2. In a region of the semiconductor device 100 where the first through-wiring region TB1 and the second through-wiring region TB2 do not exist, the upper separation region SS may be parallel to a portion of the second separation region MS2. The upper separation region SS may be in a portion of the second region B and in the first region A to penetrate through a portion of the gate electrode 130 including the uppermost upper gate electrode 130S among the gate electrodes 130. The upper separation region SS may separate a total of three gate electrodes 130 including the upper gate electrode 130S from each other in the Y direction. However, the present disclosure is not limited thereto, and in example embodiments, the number of gate electrodes 130 separated by the upper separation region SS may vary differently. The upper gate electrodes 130S separated by the upper separation region SS may form different string selection lines SSL1_1, SSL1_2, SSL1_3, SSL2_1, SSL2_2, and SSL2_3 (see Figure 2 ). The upper separation region SS may include an insulating layer.

[0059] In some example embodiments, the semiconductor device 100 may further include an insulating layer separating the lower gate electrodes 130G among the gate electrodes 130. For example, in a region where the second separation regions MS2 are linearly spaced apart from each other in the X direction, an insulating layer may be between the second separation regions MS2 to separate the lower gate electrodes 130G from each other.

[0060] Each of the channel structures CH may form a memory cell string S (see Figure 2 ), and may be spaced apart from each other in rows and columns on the first region A. The channel structure CH may form a grid, or may be in a zigzag form in one direction. The channel structure CH may have a columnar shape, and may have an inclined side according to the aspect ratio. In some example embodiments, the channel structure CH on the end of the first region A adjacent to the second region B and the channel structure CH adjacent to the first through wiring region TB1 and the second through wiring region TB2 may be dummy channels that do not substantially constitute a memory cell string. In addition, a pad channel structure DCH' having the same structure as that of the channel structure CH may be in the pad region of the gate electrode 130. The pad channel structure DCH' may have the same size as that of the channel structure CH or a size larger than that of the channel structure CH. For example, four pad channel structures DCH' may be provided in each pad region, but the present disclosure is not limited thereto.

[0061] The channel layer 140 may be disposed in the channel structure CH. In the channel structure CH, the channel layer 140 may be formed in a ring shape having a channel insulating layer 150 surrounding it, but according to some example embodiments, the channel layer 140 may have a cylindrical or prismatic shape without the channel insulating layer 150. A lower portion of the channel layer 140 may be connected to the epitaxial layer 105. The channel layer 140 may include a semiconductor material such as polycrystalline silicon or single crystal silicon, and the semiconductor material may be an undoped material or a material including p-type or n-type impurities. The channel structure CH may be arranged in a straight line along the Y direction between the first separation region MS1 ​​or the second separation region MS2 and the upper separation region SS, and may be respectively connected to different bit lines BL0 to BL2 (see FIG. 1 ) according to the arrangement of the upper wiring structure connected to the channel pad 155. Figure 2 ).

[0062] The channel pad 155 may be on the channel layer 140 in the channel structure CH. The channel pad 155 may cover an upper surface of the channel insulating layer 150 and be electrically connected to the channel layer 140. The channel pad 155 may include, for example, doped polysilicon.

[0063] The gate dielectric layer 145 may be between the gate electrode 130 and the channel layer 140. Although not specifically shown, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer sequentially stacked from the channel layer 140. The tunneling layer may tunnel charges into the charge storage layer, and may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In some example embodiments, at least a portion of the gate dielectric layer 145 may extend along the gate electrode 130 in a horizontal direction.

[0064] The epitaxial layer 105 may be disposed on the lower end of the channel structure CH to be located on the substrate 101, and may be on the side of at least one gate electrode 130. The epitaxial layer 105 may be in a recessed region of the substrate 101. The height of the upper surface of the epitaxial layer 105 may be higher than the height of the upper surface of the lowermost gate electrode 130, and may be lower than the height of the lower surface of the gate electrode 130 on the lowermost gate electrode 130, but the present disclosure is not limited thereto. In some example embodiments, the epitaxial layer 105 may be omitted, and in these embodiments, the channel layer 140 may be directly connected to the substrate 101 or may be connected to another conductive layer on the substrate 101.

[0065] The first through-wiring region TB1 and the second through-wiring region TB2 may be regions including wiring structures for electrically connecting the memory cell region CELL and the peripheral circuit region PERI to each other. The first through-wiring region TB1 and the second through-wiring region TB2 may include a through-contact plug 170 extending in the Z direction to penetrate into the stacked structure GS of the gate electrode 130 and the substrate 101, an insulating region IR surrounding the through-contact plug 170, and a dummy channel structure DCH penetrating a portion through the insulating region IR. The first through-wiring region TB1 may be in the second region B, for example, one first through-wiring region TB1 may be provided for each one or more memory blocks. The second through-wiring region TB2 may be in the first region A, and one second through-wiring region TB2 may be provided for each plurality of memory blocks. However, in example embodiments, the first through-wiring region TB1 may be provided for each one or more memory blocks. Figure 4 The number, size, arrangement, form, and shape of the first through-wiring region TB1 and the second through-wiring region TB2 shown in FIG. 1 are variously changed.

[0066] The first through wiring area TB1 and the second through wiring area TB2 may be spaced apart from the first separation area MS1 and the second separation area MS2. For example, the first through wiring area TB1 and the second through wiring area TB2 may be centrally disposed between the first separation area MS1 and the second separation area MS2 adjacent to each other in the Y direction, thereby being spaced apart from the adjacent first separation area MS1 and the second separation area MS2. By such an arrangement, an insulating area IR of the first through wiring area TB1 and the second through wiring area TB2 may be formed, which will be referred to below. Fig. 13C Describe in more detail.

[0067] The insulating region IR may be a region formed of an insulating material, and the gate electrode 130 may not exist in the insulating region IR. The insulating region IR may include a base insulating layer 160 which may be a first insulating layer parallel to the base 101 at the same level (height) as the base 101, and may include an interlayer insulating layer 120 and a sacrificial insulating layer 180 which may be a second insulating layer and a third insulating layer alternately stacked on the upper surface of the base 101.

[0068] The base insulating layer 160 may be in a region from which a portion of the base 101 is removed. The base insulating layer 160 may be surrounded by the base 101. The base insulating layer 160 may have an upper surface substantially coplanar with the upper surface of the base 101, and the lower surface of the base insulating layer 160 may be coplanar with the lower surface of the base 101 or may be disposed at a level lower than the lower surface of the base 101. The interlayer insulating layer 120 may form an insulating region IR in the first through wiring region TB1 and the second through wiring region TB2 while forming a stacked structure GS with the gate electrode 130. The sacrificial insulating layer 180 may be positioned at the same level as the gate electrode 130 and positioned in such a manner that its side surface contacts the gate electrode 130 at the boundary of the first through wiring region TB1 and the second through wiring region TB2.

[0069] The base insulating layer 160, the interlayer insulating layer 120, and the sacrificial insulating layer 180 forming the insulating region IR may be formed of an insulating material. For example, the base insulating layer 160, the interlayer insulating layer 120, and the sacrificial insulating layer 180 may each include silicon oxide, silicon nitride, or silicon oxynitride. In some example embodiments, even in the case where portions of the base insulating layer 160, the interlayer insulating layer 120, and the sacrificial insulating layer 180 are formed of the same material, the physical properties may vary according to the formation process, composition, etc., and therefore, their boundaries may be distinguished from each other. The base insulating layer 160 and the sacrificial insulating layer 180 may have the same or different widths.

[0070] The through contact plug 170 may extend perpendicularly to the upper surface of the substrate 101, may penetrate through the insulating region IR, and may electrically connect the memory cell region CELL with the circuit device 220 of the peripheral circuit region PERI. For example, the through contact plug 170 may electrically connect the gate electrode 130 and the channel structure CH of the memory cell region CELL with the circuit device 220 of the peripheral circuit region PERI. However, the wiring structure for electrically connecting the memory cell region CELL with the circuit device 220 of the peripheral circuit region PERI is not limited to the through contact plug 170 in the first through wiring region TB1 and the second through wiring region TB2. For example, an additional wiring structure may be in an outer region of the second region B, etc. The upper portion of the through contact plug 170 may be connected to the wiring 175, but may also be connected to a separate contact plug according to an example embodiment. The lower portion of the through contact plug 170 may be connected to the circuit wiring 280.

[0071] The through contact plug 170 may penetrate the sacrificial insulating layer 180 and the interlayer insulating layer 120 through the insulating region IR, and may penetrate the base insulating layer 160 on the bottom of the through contact plug 170. In example embodiments, the number, form, and shape of the through contact plug 170 arranged in one insulating region IR may vary variously. In some example embodiments, the through contact plug 170 may have a form of connecting a plurality of plugs. According to some example embodiments, in addition to the through contact plug 170, a wiring structure in the form of wiring may also be provided in the insulating region IR. The through contact plug 170 may include a conductive material. For example, the through contact plug 170 may include tungsten (W), copper (Cu), aluminum (Al), etc.

[0072] The dummy channel structures DCH may be regularly arranged between the through contact plugs 170 in the first through wiring area TB1 and the second through wiring area TB2. The arrangement of the dummy channel structures DCH is not limited to a specific area in the corresponding first through wiring area TB1 and the second through wiring area TB2, and may be regularly and uniformly arranged throughout the first through wiring area TB1 and the second through wiring area TB2. Figure 4 As shown in , the dummy channel structures DCH may be arranged in rows and columns so that at least one or more of the dummy channel structures DCH may be positioned between two adjacent through-contact plugs 170. In more detail, the dummy channel structure DCH may be centrally located between two adjacent through-contact plugs 170 in the X direction and centrally located between two adjacent through-contact plugs 170 in the Y direction. In this case, the dummy channel structure DCH may be provided without deteriorating the electrical function of the through-contact plug 170.

[0073] In some example embodiments, the dummy channel structures DCH may be arranged in a pattern substantially the same as the through contact plugs 170. The dummy channel structures DCH may be arranged in the same density as the through contact plugs 170 or in a higher density than the through contact plugs 170, for example, in the same number per unit area. For example, when the size of the dummy channel structures DCH is relatively small, the dummy channel structures DCH may be arranged in a higher density than the through contact plugs 170. The dummy channel structures DCH may be arranged in a pattern different from that of the channel structure CH and may be arranged at a relatively low density. Alternatively, the dummy channel structures DCH may also be arranged in a pattern the same as that of the channel structure CH and in a density the same as that of the channel structure CH. In this case, the dummy channel structures DCH may be arranged in a continuous pattern from the channel structure CH. Unlike the channel structure CH in the semiconductor device 100, the dummy channel structure DCH may not be electrically connected to the upper wiring structure and / or may not form a memory cell string S (see Figure 2 ).

[0074] like Figure 6 As shown in the enlarged view of , the through contact plug 170 may have a first maximum diameter D1, and the dummy channel structure DCH may have a second maximum diameter D2 that is smaller than the first maximum diameter D1. In some embodiments, the first maximum diameter D1 may be in a range from about 250nm to about 350nm, and the second maximum diameter D2 may be in a range from about 70nm to about 130nm. The second maximum diameter D2 may be equal to or less than the maximum diameter of the channel structure CH, but the present disclosure is not limited thereto. When the dummy channel structure DCH has a diameter smaller than the maximum diameter of the channel structure CH, the dummy channel structure DCH may be spaced apart from the through contact plug 170. The through contact plug 170 may be arranged at a first pitch P1, and the dummy channel structure DCH may be arranged at a second pitch P2. The second pitch P2 may be equal to the first pitch P1, but the present disclosure is not limited thereto. As used herein, "pitch" means a length from center to center or from one end to one end relative to a configuration.

[0075] At least a portion of the dummy channel structure DCH may have a structure corresponding to the channel structure CH. For example, the dummy channel structure DCH may include a structure identical to that of the channel structure CH in a position corresponding to that of the channel structure CH. The channel layer 140 may be in the dummy channel structure DCH, and in addition to including the channel layer 140, the dummy channel structure DCH may also include a gate dielectric layer 145, a channel insulating layer 150, and a channel pad 155. The epitaxial layer 105 may not be present in the dummy channel structure DCH. In some example embodiments, in the case where the channel structure CH has a structure without the epitaxial layer 105, the dummy channel structure DCH may have a structure identical to that of the channel structure CH.

[0076] The arrangement of the dummy channel structure DCH and the through contact plug 170 in the first through wiring region TB1 and the second through wiring region TB2 may be the same as or different from each other. Figure 4 As shown in , the dummy channel structure DCH and the through contact plug 170 may have different patterns and densities in the first through wiring region TB1 and the second through wiring region TB2. Since the dummy channel structure DCH is in the first through wiring region TB1 and the second through wiring region TB2, the continuity of the arrangement of the channel structure CH may be ensured in the first region A, and the continuity of the arrangement of the pad channel structure DCH' may be ensured in the second region B. Therefore, even in the region adjacent to the first through wiring region TB1 and the second through wiring region TB2, the channel structure CH and the pad channel structure DCH' may be formed to have a uniform size and shape.

[0077] The wiring 175 may construct a wiring structure electrically connected to the memory cell in the memory cell region CELL. For example, the wiring 175 may be electrically connected to the gate electrode 130 or the channel structure CH. In various embodiments, the number of wirings and contact plugs constituting the wiring structure may vary. The wiring 175 may include a metal, such as tungsten (W), copper (Cu), aluminum (Al), etc.

[0078] The cell region insulating layer 190 may cover the substrate 101, the gate electrode 130 on the substrate 101, and the peripheral region insulating layer 290. The cell region insulating layer 190 may be formed of an insulating material.

[0079] The peripheral circuit region PERI may include a base substrate 201 , a circuit device 220 on the base substrate 201 , a circuit contact plug 270 , and a circuit wiring 280 .

[0080] The base substrate 201 may have an upper surface extending in the X direction and the Y direction. In the base substrate 201, a separate device isolation layer may be formed to define an active region. A source region / drain region 205 including impurities may be in a portion of the active region. The base substrate 201 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0081] The circuit devices 220 may include planar transistors. Each of the circuit devices 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. The source / drain regions 205 may be disposed on both sides of the circuit gate electrode 225 in the base substrate 201.

[0082] The peripheral region insulating layer 290 may be on the circuit device 220 on the base substrate 201. The circuit contact plug 270 may penetrate through the peripheral region insulating layer 290 and may be connected to the source / drain region 205. An electrical signal may be applied to the circuit device 220 through the circuit contact plug 270. In an area not shown, the circuit contact plug 270 may also be connected to the circuit gate electrode 225. The circuit wiring 280 may be connected to the circuit contact plug 270 and may be in multiple layers.

[0083] 7A to 7C is a plan view of a semiconductor device according to example embodiments. Fig. 7A and Figure 7B Shown with Figure 4 The area "C" in the figure corresponds to the enlarged area. Figure 7C Shown with Figure 4 The area corresponding to "TB1" in.

[0084] Reference Fig. 7A In some example embodiments, in the second through wiring region TB2, the through contact plug 170 and the dummy channel structure DCH may be configured as described with reference to FIG. Figure 4 and Figure 6 The dummy channel structure DCH may be arranged in a pattern different from the pattern in the described example embodiments. For example, the dummy channel structure DCH may be on one side of each through contact plug 170 in the Y direction, rather than being centered between two adjacent through contact plugs 170 in the X direction and between two adjacent through contact plugs 170 in the Y direction. Thus, in some example embodiments, various changes may be made to the pattern in which the dummy channel structure DCH is arranged.

[0085] Reference Figure 7B , in some example embodiments, with reference to Figure 4 and Figure 6Unlike the example embodiments described, in the second through wiring region TB2, the dummy channel structure DCH may have a different separation distance from the through contact plug 170 in one direction. In more detail, the second through wiring region TB2 may include a dummy channel structure DCH whose separation distance from the through contact plug 170 is a first length L1 and a dummy channel structure DCH whose separation distance from the through contact plug 170 is a second length L2 that is smaller than the first length L1. In addition, at least one dummy channel structure DCH may be disposed to overlap the through contact plug 170. In this case, since the dummy channel structure DCH is formed first and then the through contact plug 170 is formed, the through contact plug 170 may be formed to penetrate through the dummy channel structure DCH. Such a structure may be formed in the semiconductor device 100 in the case where misalignment occurs due to a difference in pattern density, a process error, etc. However, even in this case, since the dummy channel structure DCH and the through-contact plug 170 are surrounded by the insulating region IR, degradation of electrical characteristics may be avoided or mitigated.

[0086] Reference Figure 7C In the first through wiring region TB1, the dummy channel structure DCH may be Figure 4 For example, the dummy channel structure DCH may be arranged on the outer side of the through contact plug 170 in the Y direction and between the through contact plugs 170 in the Y direction, and between two adjacent through contact plugs 170 in the X direction. The dummy channel structure DCH may be further arranged in a zigzag form with the through contact plug 170.

[0087] exist Figure 7C , the dummy channel structures DCH are illustrated as being further arranged in three rows along the X direction, but the number of additional rows of the dummy channel structures DCH is not limited to the illustration in the drawings. For example, in some embodiments, the row of dummy channel structures DCH between the through contact plugs 170 in the Y direction may be omitted. As such, in example embodiments, various changes may be made to the arrangement, form, and pattern of the dummy channel structures DCH in the first through wiring region TB1.

[0088] Figure 8 and Fig. 9 are schematic plan views and cross-sectional views of semiconductor devices according to some example embodiments. Fig. 9 Shown along Figure 8 A cross section taken along line III-III'.

[0089] Reference Figure 8 and Fig. 9 , in the semiconductor device 100a, and with reference Figures 4 to 6Unlike the example embodiment described above, the dummy channel structures DCHa in the first through wiring region TB1a and the second through wiring region TB2a may overlap with the through contact plugs 170, respectively. Fig. 9 As shown in , the dummy channel structure DCHa may be in the through contact plug 170. In this way, the defect of electrical short circuit between the through contact plugs 170 due to the dummy channel structure DCHa contacting two or more adjacent through contact plugs 170 may be prevented. Figure 7B Similar to the example embodiment of FIG. 1 , a portion of the dummy channel structure DCHa may not be completely within the through-contact plug 170 but may overlap with the through-contact plug 170 .

[0090] In the through contact plug 170, the dummy channel structure DCHa may have a structure corresponding to the channel structure CH. For example, the dummy channel structure DCHa may have the same structure as the channel structure CH except for the epitaxial layer 105. In some example embodiments, the bottom of the dummy channel structure DCHa may be lower than the bottom of the channel structure CH or higher than the bottom of the channel structure CH.

[0091] Fig. 10A and Fig. 10B is a partially enlarged view of a semiconductor device according to some example embodiments. Fig. 10A and Fig. 10B is with Fig. 9 The area in area "D" corresponds to the enlarged view.

[0092] Reference Fig. 10A In the semiconductor device 100b, the dummy channel structure DCHb in the through contact plug 170 may not include certain components, for example, the gate dielectric layer 145. Therefore, the dummy channel structure DCHb may include only the channel layer 140, the channel insulating layer 150, and the channel pad 155. Such a structure may be formed by removing the material of the gate dielectric layer 145 together when forming the contact hole for forming the through contact plug 170.

[0093] Reference Fig. 10B In the semiconductor device 100c, the dummy channel structure DCHc in the through contact plug 170 may not include certain components, such as the channel insulating layer 150 and the channel pad 155. Therefore, the dummy channel structure DCHc may include only the channel layer 140 and the gate dielectric layer 145. Such a structure may be formed by removing the channel pad 155 and removing the channel insulating layer 150 thereunder when forming a contact hole for forming the through contact plug 170. According to some example embodiments, the dummy channel structure DCHc may include only the channel layer 140, which may be changed according to the etchant and etching conditions of the contact hole.

[0094] Fig.11 is a schematic cross-sectional view of a semiconductor device according to some example embodiments. Fig.11 Shown with Figure 5B The corresponding cross section.

[0095] Reference Fig.11 In the semiconductor device 100d, the stack structure of the gate electrode 130 may include a first stack structure GS1 and a second stack structure GS2 stacked vertically, each of the channel structures CHd may include a first channel structure CH1 and a second channel structure CH2 stacked vertically, and each of the dummy channel structures DCHd may include a first dummy channel structure DCH1 and a second dummy channel structure DCH2 stacked vertically. The structure of the channel structure CHd and the dummy channel structure DCHd may be introduced so that the channel structure CHd and the dummy channel structure DCHd are formed to be structurally stable even when the number of stacked gate electrodes 130 is relatively large.

[0096] The channel structure CHd may have a form in which the first channel structure CH1 of the first stacked structure GS1 and the second channel structure CH2 of the second stacked structure GS2 are connected to each other, and may have a bent portion formed due to a difference in width. The channel layer 140, the gate dielectric layer 145, and the channel insulating layer 150 may be connected to each other between the first channel structure CH1 and the second channel structure CH2. The channel pad 155 may be only on the upper end of the second channel structure CH2. However, in some example embodiments, each of the first channel structure CH1 and the second channel structure CH2 may include a channel pad 155, so that the channel pad 155 of the first channel structure CH1 may be connected to the channel layer 140 of the second channel structure CH2. With reference to Figure 5A and Figure 5B Unlike the described example embodiments, the channel structure CHd may omit the epitaxial layer 105 , but the present disclosure is not limited thereto.

[0097] The dummy channel structure DCHd may have a structure substantially similar to that of the channel structure CHd. For example, the dummy channel structure DCHd may also have a form in which the first dummy channel structure DCH1 and the second dummy channel structure DCH2 are connected. A relatively thick upper interlayer insulating layer 125 may be on top of the first stacked structure GS1. However, in example embodiments, various changes may be made to the shapes of the interlayer insulating layer 120 and the upper interlayer insulating layer 125. For at least some configurations, the above reference may be applied. Figures 4 to 6 Provide a description.

[0098] FIG. 12A to FIG. 12C is a schematic cross-sectional view of a semiconductor device according to some example embodiments. FIG. 12A to FIG. 12C Shown with Fig.11The corresponding cross section.

[0099] Reference Fig. 12A In the semiconductor device 100e, at least a portion of the dummy channel structure DCHe may have a form in which the first dummy channel structure DCH1 and the second dummy channel structure DCH2 may be offset in a horizontal direction (e.g., a Y direction) due to a process error in the formation of the dummy channel structure DCHe. In more detail, in the case where the process conditions are determined by preferentially forming the channel structure CHd, such a structure may be formed in the dummy channel structure DCHe where the memory cell string is substantially not formed.

[0100] Reference Fig. 12B , the semiconductor device 100f may have a form in which at least parts of the dummy channel structure DCHf (e.g., the first dummy channel structure DCH1 and the second dummy channel structure DCH2) are spaced apart from each other in a vertical direction (e.g., in the Z direction). The first dummy channel structure DCH1 and the second dummy channel structure DCH2 may be spaced apart from each other by a predetermined length L3 and are not connected to each other. In example embodiments, the length L3 may be variously changed, and the lengths may be different from each other in two or more dummy channel structures DCHf.

[0101] The first dummy channel structure DCH1 of the lower portion may have a structure different from that of the second dummy channel structure DCH2 of the upper portion. In more detail, the first dummy channel structure DCH1 may have a structure in which the channel sacrificial layer 185 is filled. For example, if the channel sacrificial layer 185 is not removed by forming the channel hole of the second dummy channel structure DCH2 in the manufacture of the dummy channel structure DCHf but remains, this structure may be formed.

[0102] Reference Fig. 12C In the semiconductor device 100g, at least a portion of the dummy channel structure DCHg may have a structure different from that of the lower first dummy channel structure DCH1 and that of the upper second dummy channel structure DCH2. Fig. 12B Similar to the described example embodiment, at least one of the first dummy channel structures DCH1 may have a structure filled with a channel sacrificial layer 185. However, similar to the example embodiment described with reference to FIG. Fig. 12B Unlike the example embodiment described above, the first dummy channel structure DCH1 may have such a structure even when the first dummy channel structure DCH1 and the second dummy channel structure DCH2 are connected to each other. In the case where the width of the first dummy channel structure DCH1 is relatively small, this structure may be formed if the channel sacrificial layer 185 is not removed by forming the channel hole of the second dummy channel structure DCH2 in manufacturing the dummy channel structure DCHg.

[0103] FIG. 13A to FIG. 13Eis a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to some example embodiments. FIG. 13A to FIG. 13E In the figure, it is shown that Figure 5A The area shown in corresponds to the area.

[0104] Reference Fig.13A A peripheral circuit region PERI including a circuit device 220 and a lower wiring structure can be formed on a base substrate 201, a substrate 101 on which a memory cell region is disposed and a substrate insulating layer 160 can be formed on the peripheral circuit region PERI, and then, sacrificial insulating layers 180 and interlayer insulating layers 120 can be alternately stacked.

[0105] First, a circuit gate dielectric layer 222 and a circuit gate electrode 225 may be sequentially formed on a base substrate 201. The circuit gate dielectric layer 222 and the circuit gate electrode 225 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 may be formed of silicon oxide, and the circuit gate electrode 225 may be formed of at least one of polysilicon and a metal silicide layer, but their exemplary embodiments are not limited thereto. Next, a spacer layer 224 and a source / drain region 205 may be formed on both sidewalls of the circuit gate dielectric layer 222 and both sidewalls of the circuit gate electrode 225. In some exemplary embodiments, the spacer layer 224 may also be formed of a plurality of layers. Subsequently, the source / drain region 205 may be formed by performing an ion implantation process.

[0106] The circuit contact plug 270 of the lower wiring structure may be formed by forming a portion of the peripheral region insulating layer 290 and then performing partial etching and removal and filling with a conductive material. The lower wiring 280 may be formed by, for example, depositing a conductive material and then patterning the conductive material.

[0107] The peripheral region insulating layer 290 may be formed of a plurality of insulating layers. The peripheral region insulating layer 290 may be partially formed in the corresponding step of forming the lower wiring structure, and the peripheral region insulating layer 290 may be formed to eventually cover the circuit device 220 and the lower wiring structure by forming a portion of the peripheral region insulating layer 290 on the uppermost lower wiring 280.

[0108] Next, a substrate 101 may be formed on the peripheral region insulating layer 290. The substrate 101 may be formed of, for example, polysilicon and may be formed by a CVD process. The polysilicon constituting the substrate 101 may include impurities. The substrate 101 may be formed to be smaller than or equal to the size of the base substrate 201.

[0109] The base insulating layer 160 may be formed by removing a portion of the base 101 from the region corresponding to the first through wiring region TB1 and the second through wiring region TB2 and then filling the insulating material. After the insulating material is filled, a planarization process may be further performed using a chemical mechanical polishing (CMP) process. As a result, the upper surface of the base insulating layer 160 may be substantially coplanar with the upper surface of the base 101.

[0110] The sacrificial insulating layer 180 may be a portion of the sacrificial insulating layer 180 that is replaced by the gate electrode 130 (see Figure 5A ) is replaced by a layer. The sacrificial insulating layer 180 may be formed of a material different from that of the interlayer insulating layer 120, and may be formed of a material that can be etched using an etching selectivity relative to the interlayer insulating layer 120 under specific etching conditions. For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 180 may be formed of a material selected from silicon, silicon oxide, silicon carbide, and silicon nitride and different from that of the interlayer insulating layer 120. In some example embodiments, the thickness of the interlayer insulating layer 120 may not be completely the same. The thicknesses of the interlayer insulating layer 120 and the sacrificial insulating layer 180 and the number of the interlayer insulating layer 120 and the sacrificial insulating layer 180 may be variously changed from those shown in the drawings.

[0111] exist Figure 4 In the second region B, a photolithography process and an etching process for the sacrificial insulating layer 180 may be repeatedly performed using a mask layer so that the upper sacrificial insulating layer 180 extends less than the lower sacrificial insulating layer 180. As a result, the sacrificial insulating layer 180 may have a stepped shape and a pad region may be provided.

[0112] Next, a cell region insulating layer 190 may be formed to cover an upper portion of the stack structure of the sacrificial insulating layer 180 and the interlayer insulating layer 120 .

[0113] Reference Fig. 13B , the channel structure CH and the dummy channel structure DCH may be formed to penetrate through the stack structure of the sacrificial insulating layer 180 and the interlayer insulating layer 120 .

[0114] First, a portion of the sacrificial insulating layer 180 and the interlayer insulating layer 120 may be removed to Fig. 13B A string separation region SS is formed in an area not shown in FIG. Figure 4 ). The string separation region SS may be formed by exposing a region where the string separation region SS is to be formed using a separate mask layer, removing a predetermined number of the sacrificial insulating layer 180 and the interlayer insulating layer 120 from the uppermost portion, and then depositing an insulating material. The string separation region SS may extend to a greater extent than the region where the string separation region SS is formed. Figure 4 The position of the region of the upper gate electrode 130S is low.

[0115] The channel structure CH and the dummy channel structure DCH may be formed by anisotropically etching the sacrificial insulating layer 180 and the interlayer insulating layer 120, and may be formed by forming a channel hole in the form of a hole and then filling the channel hole. The channel hole for the dummy channel structure DCH may be formed together with the channel hole for the channel structure CH in the region where the first through wiring region TB1 and the second through wiring region TB2 are to be formed, so that the channel hole may be formed continuously, and thus discontinuity may be avoided. Therefore, the channel hole may be formed to have a uniform size and shape regardless of the region, thereby ensuring the electrical characteristics of the channel structure CH.

[0116] Due to the height of the stacked structure, the sidewalls of the channel structure CH and the sidewalls of the dummy channel structure DCH may not be perpendicular to the upper surface of the substrate 101. In some example embodiments, the channel structure CH and the dummy channel structure DCH may be formed to recess portions of the substrate 101 and the substrate insulating layer 160, respectively. Next, an epitaxial layer 105 may be formed in the channel structure CH, and at least a portion of the gate dielectric layer 145, the channel layer 140, the channel insulating layer 150, and the channel pad 155 may be sequentially formed in the channel structure CH and the dummy channel structure DCH.

[0117] In the channel structure CH, the epitaxial layer 105 may be formed using selective epitaxial growth (SEG). The epitaxial layer 105 may be formed of a single layer or a plurality of layers. The epitaxial layer 105 may include polycrystalline germanium doped with impurities or without impurities, single crystal germanium, single crystal silicon, or polycrystalline silicon. In some embodiments, the epitaxial layer 105 may be omitted.

[0118] The gate dielectric layer 145 may be formed to have a uniform thickness using an ALD or CVD process. In this step, all or a portion of the gate dielectric layer 145 may be formed, and a portion of the gate dielectric layer extending perpendicularly to the substrate 101 along the channel structure CH and the dummy channel structure DCH may be formed in this step. A channel layer 140 may be formed on the gate dielectric layer 145 in the channel structure CH and the dummy channel structure DCH. A channel insulating layer 150 may be formed to fill the channel structure CH and the dummy channel structure DCH, and may be an insulating material. In some example embodiments, a conductive material instead of the channel insulating layer 150 may also be filled between the channel layers 140. The channel pad 155 may be formed of a conductive material, for example, polysilicon.

[0119] Reference Fig. 13C , the opening OP is formed to penetrate through the stacked structure of the sacrificial insulating layer 180 and the interlayer insulating layer 120 , and a portion of the sacrificial insulating layer 180 may be removed through the opening OP to form the tunneling portion LT.

[0120] First, before forming the opening OP, a cell region insulating layer 190 may be formed on the channel structure CH and the dummy channel structure DCH. Figure 4 The opening OP is formed in the positions of the first separation region MS1 ​​and the second separation region MS2. The opening OP may be formed by forming a mask layer using a photolithography process and anisotropically etching the stacked structure. The opening OP may be formed in a groove shape extending in the Y direction, and the substrate 101 may be exposed at a lower portion of the opening OP.

[0121] The wiring pattern may be formed from the outside of the insulating region IR (eg, the first through-wiring region TB1 and the second through-wiring region TB2 (see Figure 4 ) is removed from the sacrificial insulating layer 180. As a result, an insulating region IR of a first through wiring region TB1 and a second through wiring region TB2 including the interlayer insulating layer 120, the sacrificial insulating layer 180, and the base insulating layer 160 may be defined. The sacrificial insulating layer 180 may be selectively removed relative to the interlayer insulating layer 120 and the base insulating layer 160, for example, using wet etching. Therefore, a plurality of tunnel portions LT may be formed between the interlayer insulating layers 120, and some sidewalls of the gate dielectric layer 145 of the channel structure CH may be exposed through the second tunnel portions.

[0122] The region where the first through wiring region TB1 and the second through wiring region TB2 are formed may be spaced apart from the opening OP so that the etchant may not reach the region, and therefore, the region may be a region where the sacrificial insulating layer 180 remains. Therefore, the first through wiring region TB1 and the second through wiring region TB2 may be centered between adjacent openings OP. The region where the sacrificial insulating layer 180 remains may not be precisely matched with the region where the base insulating layer 160 is disposed.

[0123] Reference Fig.13D , the gate electrode 130 is formed by filling the tunnel portion LT in which the sacrificial insulating layer 180 has been partially removed with a conductive material, and the isolation insulating layer 107 and the conductive layer 110 may be formed in the opening OP.

[0124] The conductive material forming the gate electrode 130 may fill the tunnel portion LT. The conductive material may include a metal, polysilicon, or a metal silicide material. The side surface of the gate electrode 130 may contact the side surface of the sacrificial insulating layer 180 of the insulating region IR. After forming the gate electrode 130, the conductive material deposited in the opening OP may also be removed by an additional process.

[0125] The isolation insulating layer 107 may be formed in the opening OP in the form of a spacer. For example, after depositing the insulating material, the isolation insulating layer 107 may be formed by removing the insulating material formed on the substrate 101 below the opening OP. Next, a conductive material may be deposited on the isolation insulating layer 107 to form a conductive layer 110. For example, the isolation insulating layer 107 and the conductive layer 110 may be formed in the first separation region MS1 ​​and the second separation region MS2 in the same process to have the same structure. In this case, as described above, for example, the conductive layer 110 in the first separation region MS1 ​​may be used as a common source line CSL, and the conductive layer 110 in the second separation region MS2 may be used as a dummy common source line. In some example embodiments, the process of forming the conductive layer 110 may be omitted.

[0126] Reference Fig.13E , a contact hole VH for forming a through contact plug 170 may be formed.

[0127] Before forming the contact hole VH, the cell region insulating layer 190 may be formed to cover the isolation insulating layer 107. Next, a contact hole VH penetrating through the cell region insulating layer 190 and the insulating region IR may be formed from an upper portion of the insulating region IR. The circuit wiring 280 of the peripheral circuit region PERI may be exposed to a lower end of the contact hole VH.

[0128] Next, let’s refer to Figure 5B and Fig.13E , a through contact plug 170 may be formed by filling the contact hole VH with a conductive material to form a first through wiring region TB1 and a second through wiring region TB2 , and the semiconductor device 100 may be manufactured by forming a wiring 175 connected to an upper end of the through contact plug 170 .

[0129] Refer to above FIG. 13A to FIG. 13E The manufacturing method described is used to manufacture reference Figures 4 to 6 An example of the semiconductor device 100 is described, and the semiconductor device 100 may be manufactured by various manufacturing methods.

[0130] FIG. 14A to FIG. 14F is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to some example embodiments. FIG. 14A to FIG. 14F In the figure, it is shown that Fig.11 In the following, for the sake of brevity, the above reference will be omitted. FIG. 13A to FIG. 13E Description of duplicate description.

[0131] Reference Fig.14AAfter forming the peripheral circuit region PERI and forming a substrate 101 provided with a memory cell region and a substrate insulating layer 160 on the peripheral circuit region PERI, a first stacked structure GS1 may be formed. The first stacked structure GS1 may include alternately stacked sacrificial insulating layers 180 and interlayer insulating layers 120. A first channel hole CHH1 may be formed and the first channel hole CHH1 may be filled with a channel sacrificial layer 185.

[0132] An upper interlayer insulating layer 125 relatively thicker than the interlayer insulating layer 120 may be formed as the uppermost interlayer insulating layer. The channel sacrificial layer 185 may be formed of a material that can be etched with an etching selectivity with respect to the sacrificial insulating layer 180 and the interlayer insulating layer 120. For example, the channel sacrificial layer 185 may include silicon (Si).

[0133] Reference Fig. 14B , the second stack structure GS2 may be formed by alternately stacking sacrificial insulating layers 180 and interlayer insulating layers 120 on the first stack structure GS1.

[0134] Similar to the first stacked structure GS1 , the second stacked structure GS2 may be formed by alternately stacking sacrificial insulating layers 180 and interlayer insulating layers 120 on the upper interlayer insulating layers 125 and the channel sacrificial layers 185 and forming a cell region insulating layer 190 .

[0135] Reference Fig. 14C , the second channel hole CHH2 penetrating the second stacked structure GS2 may be formed, and the channel sacrificial layer 185 in the first channel hole CHH1 may be removed.

[0136] First, the second channel holes CHH2 may be formed to be aligned with the first channel holes CHH1, respectively. In more detail, after patterning the photoresist layer on the second stacked structure GS2 to expose a portion of the second stacked structure GS2, the second stacked structure GS2 may be etched in the exposed region to form the second channel holes CHH2. Next, a channel hole CHH in which the first channel hole CHH1 and the second channel hole CHH2 are connected may be formed by removing the channel sacrificial layer 185 exposed through the second channel hole CHH2.

[0137] In addition to the region in which the channel structure CHd is provided, the channel hole CHH may be formed in the region in which the dummy channel structure DCHd is provided, and therefore, the channel hole CHH may be continuously patterned to have a uniform size and shape. Therefore, through subsequent processes, in the channel structure CHd formed adjacent to the first through wiring region TB1 and the second through wiring region TB2, defects due to patterning problems may be prevented, and electrical characteristics may be ensured.

[0138] Reference Fig.14D , a channel structure CHd and a dummy channel structure DCHd may be formed.

[0139] The channel structure CHd and the dummy channel structure DCHd may be formed in such a manner that the first channel structure CH1 and the second channel structure CH2 and the first dummy channel structure DCH1 and the second dummy channel structure DCH2 are connected as one. The channel structure CHd and the dummy channel structure DCHd may be formed by sequentially forming at least a portion of the gate dielectric layer 145, the channel layer 140, the channel insulating layer 150, and the channel pad 155 in the channel hole CHH. A portion of the gate dielectric layer 145 may be removed from the lower end of the channel hole CHH so that the channel layer 140 may be in direct contact with the substrate 101 and the substrate insulating layer 160.

[0140] Reference Fig.14E , you can Fig.14E Openings are formed in the regions not shown in FIG. Fig. 13C ) to penetrate the first stacked structure GS1 and the second stacked structure GS2, and the sacrificial insulating layer 180 may be partially removed through the opening.

[0141] First, a cell region insulating layer 190 may be formed. Figure 4 The openings are formed in the positions of the first separation region MS1 ​​and the second separation region MS2. The insulation region IR can be connected from the outside (for example, the first through wiring region TB1 and the second through wiring region TB2 (see FIG. Figure 4 ) The sacrificial insulating layer 180 is removed from the outer region of the interlayer insulating layer 120. As a result, the insulating region IR of the first through wiring region TB1 and the second through wiring region TB2 including the interlayer insulating layer 120, the sacrificial insulating layer 180, and the base insulating layer 160 may be defined.

[0142] Reference Fig.14F , the gate electrode 130 may be formed by filling the region in which the sacrificial insulating layer 180 has been removed with a conductive material. The opening may be filled, and then a contact hole VH for forming the through contact plug 170 may be formed.

[0143] The opening may be filled with an insulating material or with an insulating material and a conductive material. Before forming the contact hole VH, a cell region insulating layer 190 may be formed. Next, a contact hole VH penetrating through the cell region insulating layer 190 and the insulating region IR may be formed from the upper portion of the insulating region IR. The circuit wiring 280 of the peripheral circuit region PERI may be exposed to the lower end of the contact hole VH.

[0144] Next, let’s refer to Fig.11 and Fig.14FA through contact plug 170 is formed by filling the contact hole VH with a conductive material to form a first through wiring region TB1 and a second through wiring region TB2, and a wiring 175 connected to an upper end of the through contact plug 170 may be formed, thereby manufacturing the semiconductor device 100d.

[0145] Refer to above FIG. 14A to FIG. 14F The described manufacturing method is for manufacturing Fig.11 The semiconductor device 100d is an example of the semiconductor device 100d, and the semiconductor device 100d can be manufactured by various manufacturing methods.

[0146] As set forth above, according to some example embodiments, regularly positioning dummy channel structures in a through-wiring region may provide a semiconductor device having improved reliability.

[0147] While certain example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A peripheral circuit region, located on the first substrate and including circuit devices; a memory cell region located on a second substrate covering the first substrate, wherein the memory cell region includes gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, wherein the memory cell region includes a channel structure penetrating the gate electrode and vertically extending to the second substrate, wherein the channel structure includes a channel layer; and A through wiring region is provided to electrically connect the memory cell region and the peripheral circuit region. Wherein, the through wiring area includes: a through contact plug extending in the first direction to penetrate the memory cell region, wherein the through contact plug electrically connects the memory cell region and the circuit device; an insulating region surrounding the through-contact plug, wherein the insulating region includes a first insulating layer and a second insulating layer alternately stacked; and A dummy channel structure penetrates the first insulating layer and the second insulating layer, wherein the dummy channel structure includes the channel layer, wherein the dummy channel structures are arranged in rows and columns such that at least one dummy channel structure is positioned between mutually adjacent through contact plugs.

2. The semiconductor device according to claim 1, wherein In the through wiring region, the number of the through contact plugs is equal to the number of the dummy channel structures.

3. The semiconductor device according to claim 1, wherein At least one of the dummy channel structures includes a structure corresponding to a structure of the channel structure.

4. The semiconductor device according to claim 3, wherein: Each of the channel structure and the dummy channel structure includes a gate dielectric layer contacting the gate electrode, a channel layer on the gate dielectric layer, and a channel insulating layer on the channel layer.

5. The semiconductor device according to claim 1, wherein Each of the dummy channel structures has a maximum diameter between 70 nm and 130 nm, wherein each of the through-contact plugs has a maximum diameter between 250 nm and 350 nm.

6. The semiconductor device according to claim 1, wherein Each of the channel structures includes a first channel structure and a second channel structure stacked in the first direction, and Each of the dummy channel structures includes a first dummy channel structure and a second dummy channel structure stacked in the first direction.

7. The semiconductor device according to claim 6, wherein: At least a portion of the first dummy channel structure and at least a portion of the second dummy channel structure are spaced apart from each other in the first direction and disconnected from each other.

8. The semiconductor device according to claim 6, wherein: At least a portion of the first dummy channel structure and at least a portion of the second dummy channel structure are offset from each other in a second direction perpendicular to the first direction.

9. The semiconductor device according to claim 6, wherein: At least one of the first dummy channel structures includes a structure different from a structure of the first channel structure.

10. The semiconductor device according to claim 1, wherein The memory cell region further includes a separation region penetrating the gate electrode and extending in a second direction perpendicular to the first direction, wherein the separation region is spaced apart from the through-wiring region.

11. The semiconductor device according to claim 10, wherein The through wiring region is centered between two adjacent separation regions.

12. The semiconductor device according to claim 1, wherein The memory cell region further includes an interlayer insulating layer arranged alternately with the gate electrodes, and The first insulating layer and the interlayer insulating layer are at the same height level, and the second insulating layer and the gate electrode are at the same height level.

13. A semiconductor device, comprising: A peripheral circuit region, disposed on the first substrate and including circuit devices; a memory cell region disposed on a second substrate covering the first substrate, wherein the memory cell region comprises a stacked structure above the second substrate, the stacked structure comprising spaced-apart gate electrodes, wherein the memory cell region comprises a channel structure vertically extending to the second substrate and penetrating the gate electrode, wherein the channel structure comprises a channel layer; and a through wiring region including a through contact plug extending vertically and electrically connecting the memory cell region and the peripheral circuit region to each other, wherein the through wiring region includes an insulating region surrounding the through contact plug, and wherein the through wiring region further includes a dummy channel structure which is regularly arranged throughout the through wiring region and includes the channel layer, Wherein, at least a portion of the dummy channel structure is located in the through contact plug.

14. The semiconductor device according to claim 13, wherein: The dummy channel structure in the through-contact plug has a structure different from that of the channel structure.

15. The semiconductor device according to claim 14, wherein: Each of the channel structures includes a gate dielectric layer contacting the gate electrode, the channel layer on the gate dielectric layer, and a channel insulating layer on the channel layer, and Wherein, each dummy channel structure in the through contact plug includes the channel layer.

16. The semiconductor device according to claim 13, wherein: Portions of the dummy channel structure are located between corresponding pairs of through-contact plugs adjacent to each other in at least one direction.

17. A semiconductor device, comprising: first base; A circuit device is located on the first substrate; A second substrate, located on the circuit device; gate electrodes spaced apart from each other in a first direction; a channel structure penetrating the gate electrode and extending vertically from the second substrate, wherein the channel structure comprises a channel layer; separation regions extending in a second direction perpendicular to the first direction, wherein the separation regions extend through the gate electrode and are spaced apart from and parallel to each other; and a through wiring region located between adjacent separation regions and spaced apart from the adjacent separation regions, wherein the through wiring region includes: a through contact plug electrically connecting the circuit device and the gate electrode to each other, or electrically connecting the circuit device and the channel structure to each other; an insulating region surrounding the through contact plug; and a dummy channel structure including the channel layer and provided in a number at least the same as the number of the through contact plugs, The dummy channel structure is spaced apart from the gate electrode and penetrates the insulating region.

18. The semiconductor device according to claim 17, wherein: The through contact plugs and the dummy channel structures are arranged in the same pattern as each other.

19. The semiconductor device according to claim 18, wherein: The dummy channel structure overlaps the through contact plug.

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