Display device and method of manufacturing the same

Abstract

A display device and a method of manufacturing the display device are provided. The display device includes a bent region. In the bent region, there are a bent peripheral opening passing through a first interlayer insulating film and a first gate insulating film, and a bent opening located in the bent peripheral opening and passing through a second interlayer insulating film and a buffer layer to expose a substrate. A first sidewall of the bent peripheral opening includes a side surface of the first interlayer insulating film and a side surface of the first gate insulating film. The second interlayer insulating film covers the first sidewall of the bent peripheral opening. The bent opening includes a second sidewall, where the second sidewall includes a side surface of the buffer layer and a part of a side surface of the second interlayer insulating film aligned with the side surface of the buffer layer, and a first via layer fills the bent opening.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2019 - 0103567, filed on Aug. 23, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Aspects in accordance with some exemplary embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. Background art

[0004] With the development of multimedia, display devices have become increasingly important. In response thereto, various types of display devices such as liquid crystal displays (LCDs), organic light - emitting diode (OLED) displays, and the like are being used. Among different types of display devices, OLED displays display images by using OLEDs that generate light by recombining electrons and holes. The OLED display includes a plurality of transistors that supply driving current to the OLEDs.

[0005] The above - disclosed information in this background art section is only for enhancing the understanding of the background, and thus the information discussed in this background art section does not necessarily constitute prior art. Summary of the invention

[0006] Aspects in accordance with some exemplary embodiments of the present disclosure include a display device in which the number of masks used in the manufacturing process can be reduced.

[0007] Aspects in accordance with some exemplary embodiments of the present disclosure may also include a method of manufacturing a display device in which the number of masks used in the manufacturing process can be reduced.

[0008] The scope of the embodiments in accordance with the present disclosure is not limited to the above features, and other features not mentioned can be clearly understood by those skilled in the art through the following description.

[0009] According to some exemplary embodiments of the present disclosure, in a display device including a main region having a display area and a bent region connected to one side of the main region and bent with respect to the main region in the thickness direction of the display device, the display device includes a substrate, a buffer layer located on the substrate, a first semiconductor layer located on the buffer layer, a first gate insulating film located on the first semiconductor layer, a first gate conductive layer located on the first gate insulating film, a first interlayer insulating film located on the first gate conductive layer, a second gate conductive layer located on the first interlayer insulating film, a second interlayer insulating film located on the second gate conductive layer, a first data conductive layer located on the second interlayer insulating film, and a first via layer located on the first data conductive layer, wherein the bent region includes a bent peripheral opening and a bent opening, wherein the bent peripheral opening penetrates the first interlayer insulating film and the first gate insulating film, and the bent opening is located in the bent peripheral opening and penetrates the second interlayer insulating film and the buffer layer to expose the substrate, a first sidewall of the bent peripheral opening includes a side surface of the first interlayer insulating film and a side surface of the first gate insulating film, the second interlayer insulating film covers the first sidewall of the bent peripheral opening, the bent opening includes a second sidewall, wherein the second sidewall includes a side surface of the buffer layer and a portion of a side surface of the second interlayer insulating film aligned with the side surface of the buffer layer, and the first via layer fills the bent opening.

[0010] According to some exemplary embodiments of the present invention, in a method of manufacturing a display device, the display device includes a first transistor having a channel, a second transistor having a channel, and a capacitor, wherein the channels of the first transistor and the second transistor are formed of different semiconductor layers, the method includes: forming a buffer layer on a substrate; forming a first semiconductor pattern on the buffer layer, wherein the first semiconductor pattern is formed of a first semiconductor layer and includes a semiconductor pattern of the first transistor; forming a first gate insulating film on the first semiconductor layer; forming a first gate conductive layer on the first gate insulating film; forming a first interlayer insulating film on the first gate conductive layer; forming a second gate conductive layer on the first interlayer insulating film; forming a second interlayer insulating film on the second gate conductive layer; forming a first data conductive layer on the second interlayer insulating film; and forming a first via layer on the first data conductive layer, wherein the formation of the second gate conductive layer further includes: forming a bent peripheral opening penetrating the first interlayer insulating film and the first gate insulating film, the formation of the first data conductive layer further includes: forming a bent opening penetrating the second interlayer insulating film and the buffer layer and exposing the substrate, a first sidewall of the bent peripheral opening includes a side surface of the first interlayer insulating film and a side surface of the first gate insulating film, the second interlayer insulating film covers the first sidewall of the bent peripheral opening, the bent opening includes a second sidewall, wherein the second sidewall includes a side surface of the buffer layer and a portion of a side surface of the second interlayer insulating film aligned with the side surface of the buffer layer, and the first via layer fills the bent opening.

[0011] In a display device and a method of manufacturing a display device according to some exemplary embodiments of the present invention, the number of masks can be reduced, thereby reducing processing or manufacturing costs and improving processing or manufacturing efficiency.

[0012] The features of the embodiments of the present disclosure are not limited by the above features, and more various features can be learned from more details described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] By referring to the drawings and describing in detail aspects of some exemplary embodiments of the present disclosure, the above and other aspects and features of the embodiments according to the present disclosure will become more apparent, in the drawings:

[0014] Figure 1 is a plan view of a display device according to some exemplary embodiments;

[0015] Figure 2 is Figure 1 a side view of the display device;

[0016] Figure 3 is an equivalent circuit diagram of a pixel of a display device according to some exemplary embodiments;

[0017] Figure 4 is a cross-sectional view showing an exemplary cross-section of the periphery of a bent region of a pixel and a non-display region;

[0018] Figure 5 is a flowchart showing a method of manufacturing a display device according to some exemplary embodiments;

[0019] Figures 6 to 8 is a cross-sectional view showing process operations before a process operation of forming an oxide semiconductor pattern in a method of manufacturing a display device according to some exemplary embodiments;

[0020] Figure 9 is a flowchart showing process operations of a process of forming an oxide semiconductor pattern according to some exemplary embodiments;

[0021] Figures 10 to 14 is a cross-sectional view showing process operations of a process of forming an oxide semiconductor pattern in a method of manufacturing a display device according to some exemplary embodiments;

[0022] Figures 15 to 25 is a cross-sectional view showing process operations after a process operation of forming an oxide semiconductor pattern in a method of manufacturing a display device according to some exemplary embodiments;

[0023] Figure 26 is a cross-sectional view of a display device according to some exemplary embodiments;

[0024] Figure 27 is a cross-sectional view of a display device according to some exemplary embodiments;

[0025] Figure 28 is a cross-sectional view of a display device according to some exemplary embodiments;

[0026] Figure 29 is a cross-sectional view of a display device according to some exemplary embodiments;

[0027] Figure 30 is a cross-sectional view of a display device according to some exemplary embodiments;

[0028] Figure 31 is a cross-sectional view of a display device according to some exemplary embodiments;

[0029] Figure 32 is a partial flowchart showing a method of manufacturing a display device according to some exemplary embodiments; and

[0030] Figures 33 to 35 is a cross-sectional view showing a process operation of a method of manufacturing a display device according to some exemplary embodiments. DETAILED DESCRIPTION

[0031] Hereinafter, aspects of some exemplary embodiments of the present invention will be described more fully with reference to the accompanying drawings showing some exemplary embodiments of the present invention. However, the embodiments according to the present disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. On the contrary, these exemplary embodiments are provided so that the present disclosure will be more thorough and complete, and will more fully convey the scope of the present invention to those skilled in the art.

[0032] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer can be directly on the other layer or substrate, or an intermediate layer may also be present. Throughout the specification, the same reference numerals indicate the same components. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

[0033] Although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. Thus, without departing from the teachings of one or more embodiments, the first element discussed below may be referred to as the second element. The description of an element as a "first" element may not require or imply the existence of a second element or other elements. Terms such as "first", "second", etc. may also be used herein to distinguish different classes or groups of elements. For the sake of brevity, terms such as "first", "second", etc. may respectively represent "first class (or first group)", "second class (or second group)", etc.

[0034] Upon concluding the detailed description, those skilled in the art will realize that many changes and modifications can be made to the exemplary embodiments without substantially departing from the principles of the embodiments according to the present disclosure. Therefore, the disclosed exemplary embodiments according to the present disclosure are used only in a general and descriptive sense and not for purposes of limitation.

[0035] Hereinafter, aspects of some exemplary embodiments will be described in more detail with reference to the accompanying drawings.

[0036] Figure 1 is a plan view of a display device 1 according to some exemplary embodiments. Figure 2 is Figure 1 a side view of the display device 1. Figure 2 shows the shape of a side surface of a display device bent in its thickness direction.

[0037] The display device 1 may be a device for displaying moving (e.g., video) images or still (e.g., static) images, and the display device 1 can be used as a display screen for portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile personal computers (UMPCs), and can be used as a display screen for various products such as televisions, laptop computers, monitors, billboards, and Internet of Things devices.

[0038] The display device 1 according to some exemplary embodiments may have a substantially rectangular shape (e.g., in a direction perpendicular or orthogonal to the plane of the display surface) in a plan view. The display device 1 may have a rectangular shape with right-angled corners in a plan view. However, the embodiments according to the present disclosure are not limited thereto, and the display device 1 may have a rectangular shape with rounded corners in a plan view. However, the embodiments are not limited to the display device 1 having a rectangular shape, and according to some exemplary embodiments, the display device 1 may have any suitable shape according to the design of the display device 1.

[0039] In the drawings, a first direction DR1 represents a lateral direction of the display device 1 in a plan view, and a second direction DR2 represents a longitudinal direction of the display device 1 in a plan view. Additionally, a third direction DR3 represents a thickness direction of the display device 1. The first direction DR1 and the second direction DR2 are perpendicular to and intersect each other, and the third direction DR3 is a direction intersecting the plane in which the first direction DR1 and the second direction DR2 are located and intersecting, so as to be perpendicular to both the first direction DR1 and the second direction DR2. However, for convenience of description, the directions to be described in the embodiments should be understood as indicating relative directions, and the embodiments are not limited to the described directions.

[0040] Unless otherwise defined, in this specification, the terms "upper part", "upper surface" or "upper side" represented with respect to the third direction DR3 indicate the side of the display surface with respect to the display panel 100, and the terms "lower part", "lower surface" or "lower side" indicate the opposite side of the display surface with respect to the display panel 100.

[0041] Referring to Figure 1 and Figure 2 , the display device 1 may include a display panel 100. The display panel 100 may be a flexible substrate including a flexible polymer material such as polyimide or the like. Accordingly, the display panel 100 may be flexible, bendable, foldable or rollable.

[0042] The display panel 100 may be an organic light emitting display panel. In the following embodiments, examples in which an organic light emitting display panel is applied as the display panel 100 are shown, but the embodiments according to the present disclosure are not limited thereto, and other types of display panels such as liquid crystal displays (LCDs), quantum dot organic light emitting display panels (QD-OLEDs), quantum dot LCDs (QD-LCDs), quantum nano light emitting display panels (nano-emissive displays (NEDs)), micro LEDs and the like may be applied as the display panel 100.

[0043] The display panel 100 may include a display area DA for displaying an image and a non-display area NDA for not displaying an image. That is, the display area DA may be an area of the display panel 100 configured to display a still image or a video image, and the non-display area NDA may be an area outside the display area DA of the display panel 100 where a still image or a video image is not displayed (for example, outside the covering area of the display area DA) (for example, a border area). In a plan view, the display panel 100 may be divided into a display area DA and a non-display area NDA. The non-display area NDA may be arranged to surround the display area DA. The non-display area NDA may form a border.

[0044] The display area DA may have a rectangular shape with right-angled corners in a plan view, or a rectangular shape with rounded corners in a plan view. According to some embodiments, the display area DA may have a short side and a long side. The short side of the display area DA may be the side extending in the first direction DR1. The long side of the display area DA may be the side extending in the second direction DR2. However, the planar shape of the display area DA is not limited to a rectangle, and according to the design of the display panel 100, the display area DA may have any other suitable shape, such as a circular shape, an oval shape, or any other suitable shape.

[0045] The display area DA may include a plurality of pixels. The pixels may be arranged in a matrix arrangement. Each of the plurality of pixels may include a light-emitting layer and a circuit layer for controlling the amount of light emitted by the light-emitting layer. The circuit layer may include lines, electrodes, and at least one transistor. The light-emitting layer may include an organic light-emitting material. The light-emitting layer may be sealed by a packaging film. More details of the configuration of the pixels will be described below.

[0046] The non-display area NDA may be positioned adjacent to the two short sides and the two long sides of the display area DA. In this case, the non-display area NDA may surround all sides of the display area DA and form the edge of the display area DA. However, according to the embodiments of the present disclosure, this is not limited thereto, and the non-display area NDA may be positioned adjacent to only two short sides or two long sides of the display area DA.

[0047] The display panel 100 may include a main area MA and a bending area BA, and the main area MA includes the display area DA. The bending area BA is connected to one side of the main area MA in the second direction DR2. As Figure 2 described, the display panel 100 may further include a sub-area SA. One side of the sub-area SA is connected to the bending area BA in the second direction DR2, and the bending area BA is bent in its thickness direction so that the sub-area SA overlaps the main area MA in the thickness direction.

[0048] The display area DA may be located in the main area MA. The non-display area NDA may be located at the peripheral edge portion of the display area DA in the main area MA.

[0049] The main area MA may have a shape similar to the shape of the exterior of the display device 1 in a plan view. The main area MA may be a flat area positioned in one surface. However, according to the embodiments of the present disclosure, this is not limited thereto, and at least one of the remaining edges except for the edge (side) of the main area MA connected to the bending area BA may be bent to form a curved surface or may be bent in the vertical direction.

[0050] When at least one of the remaining edges other than the edge (side) of the main area MA connected to the bending area BA is bent or curved, the display area DA can also be located at the corresponding edge. However, according to an embodiment of the present disclosure, this is not limited thereto. The non-display area NDA that does not display an image can be located at the bent or curved edge, or the display area DA and the non-display area NDA can be arranged together at the bent or curved edge.

[0051] The non-display area NDA of the main area MA can be in a region extending from the outer boundary of the display area DA to the edge of the display panel 100. The signal line for applying a signal to the display area DA or the driving circuit can be located in the non-display area NDA of the main area MA.

[0052] The bending area BA can be connected to a short side of the main area MA. The width of the bending area BA (e.g., the width in the first direction DR1) can be smaller than the width of the main area MA (e.g., the width of the short side). The connection portion between the main area MA and the bending area BA can have an L-shaped cut shape to reduce the width of the border.

[0053] In the bending area BA, the display panel 100 can be bent with a curvature in a direction opposite to the direction of its display surface. Since the display panel 100 is bent in the bending area BA, the surface of the display panel 100 can be reversed. That is, one surface of the display panel 100 facing upward can face the outside of the side surface of the display panel 100 through the bending area BA and then can be changed to face downward.

[0054] The sub-area SA extends from the bending area BA. The sub-area SA can extend from the bending end point in a direction parallel to the main area MA. The sub-area SA can overlap the main area MA in the thickness direction of the display panel 100. The sub-area SA can overlap the non-display area NDA at the edge of the main area MA and can also overlap the display area DA of the main area MA. The width of the sub-area SA can be the same as the width of the bending area BA, but according to an embodiment of the present disclosure, this is not limited thereto.

[0055] The pad portion can be located on the sub-area SA of the display panel 100. An external device can be mounted (or attached) to the pad portion. Examples of the external device can include a driving chip 200, a driving substrate 300 formed as a flexible printed board or a rigid printed board, and the like. In addition, a wire connection film, a connecting member, and the like can be mounted on the pad portion as an external device. One or more external devices can be mounted on the sub-area SA. For example, as Figure 1 and Figure 2As shown in [Fig.], the driving chip 200 may be located on the sub-region SA of the display panel 100, and the driving substrate 300 may be attached to an end of the sub-region SA. In this case, the display panel 100 may include both a pad portion connected to the driving chip 200 and a pad portion connected to the driving substrate 300. As another example, the driving chip 200 may be mounted on a film, and the film may be attached to the sub-region SA of the display panel 100.

[0056] The driving chip 200 may be mounted on one surface of the display panel 100 that is coplanar with the display surface of the display panel 100. As described above, since the bending region BA is bent and inverted, the driving chip 200 may be mounted on the surface of the display panel 100 that faces downward in the thickness direction, and thus the upper surface of the driving chip 200 may face downward.

[0057] The driving chip 200 may be attached to the display panel 100 by using an anisotropic conductive film or may be attached to the display panel 100 by ultrasonic bonding. The lateral width of the driving chip 200 may be smaller than the lateral width of the display panel 100. The driving chip 200 may be located at the central portion of the sub-region SA in the lateral direction (the first direction DR1), and the left and right edges of the driving chip 200 may be spaced apart from the left and right edges of the sub-region SA, respectively.

[0058] The driving chip 200 may include an integrated circuit for driving the display panel 100. In an embodiment, the integrated circuit may be a data driving integrated circuit that generates and provides data signals, but is not limited thereto according to embodiments of the present disclosure. The driving chip 200 is connected to wire pads provided in the pad portion of the display panel 100 to provide data signals to the wire pads. A plurality of wires connected to the plurality of wire pads extend to a plurality of pixels to apply data signals to respective pixels.

[0059] Figure 3 is an equivalent circuit diagram of a pixel of a display device according to some exemplary embodiments.

[0060] Referring to Figure 3 , the circuit of a pixel of an organic light emitting display device includes an organic light emitting diode OLED, a plurality of transistors T1 to T7, and a capacitor Cst. The circuit of the pixel is applied with a data signal DATA, a first scan signal Gw-p, a second scan signal Gw-n, a third scan signal GI, a light emission control signal EM, a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage VINT.

[0061] The organic light emitting diode OLED includes an anode and a cathode. The capacitor Cst includes a first electrode and a second electrode.

[0062] The plurality of transistors T1 to T7 may include a first transistor T1 to a seventh transistor T7. Each of the plurality of transistors T1 to T7 includes a gate electrode, a first source / drain electrode, and a second source / drain electrode. Either the first source / drain electrode or the second source / drain electrode of each of the plurality of transistors T1 to T7 becomes a source electrode, and the other becomes a drain electrode.

[0063] Each of the plurality of transistors T1 to T7 may be a thin film transistor. Each of the plurality of transistors T1 to T7 may be either a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. According to some exemplary embodiments, the first transistor T1 serving as a driving transistor, the second transistor T2 serving as a data transfer transistor, the fifth transistor T5 serving as a first light-emitting control transistor, and the sixth transistor T6 serving as a second light-emitting control transistor are PMOS transistors. According to some exemplary embodiments, the third transistor T3 serving as a compensation transistor, the fourth transistor T4 serving as a first initialization transistor, and the seventh transistor T7 serving as a second initialization transistor are NMOS transistors. PMOS transistors and NMOS transistors have different characteristics. The third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be formed as NMOS transistors having relatively high off characteristics, and thus leakage of driving current during the emission period of the organic light-emitting diode OLED may be reduced.

[0064] Hereinafter, more details of various components will be described in more detail.

[0065] The gate electrode of the first transistor T1 is connected to the first electrode of the capacitor Cst. The first source / drain electrode of the first transistor T1 is connected to the terminal of the first power supply voltage ELVDD via the fifth transistor T5. The second source / drain electrode of the first transistor T1 is connected to the anode of the organic light-emitting diode OLED via the sixth transistor T6. That is, according to some exemplary embodiments, the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the organic light-emitting diode OLED may be electrically connected in series (with or without other intermediate components). The first transistor T1 receives a data signal DATA according to the switching operation of the second transistor T2, and supplies a driving current to the organic light-emitting diode OLED. That is, according to some exemplary embodiments, the first source / drain electrode of the first transistor T1 may be electrically connected to the data line supplying the data signal DATA.

[0066] The gate electrode of the second transistor T2 is connected to the terminal of the first scan signal Gw-p. The first source / drain electrode of the second transistor T2 is connected to the terminal configured to receive the data signal DATA. The second source / drain electrode of the second transistor T2 is connected to the terminal of the first power supply voltage ELVDD via the fifth transistor T5 while being connected to the first source / drain electrode of the first transistor T1. Accordingly, the node between the first transistor T1 and the fifth transistor T5 can be configured to receive the data signal DATA passing through the second transistor T2 in response to the first scan signal Gw-p applied to the gate electrode of the second transistor T2. The second transistor T2 is turned on according to the first scan signal Gw-p to perform a switching operation of transmitting the data signal DATA to the first source / drain electrode of the first transistor T1.

[0067] The gate electrode of the third transistor T3 is connected to the terminal of the second scan signal Gw-n. The first source / drain electrode of the third transistor T3 is connected to the anode of the organic light-emitting diode OLED via the sixth transistor T6 while being connected to the second source / drain electrode of the first transistor T1. The second source / drain electrode of the third transistor T3 is connected to the first electrode of the capacitor Cst, the first source / drain electrode of the fourth transistor T4, and the gate electrode of the first transistor T1. The third transistor T3 is turned on according to the second scan signal Gw-n to connect the gate electrode and the second source / drain electrode of the first transistor T1 and diode-connect the first transistor T1. Accordingly, a voltage difference is generated between the first source / drain electrode and the gate electrode of the first transistor T1 by the threshold voltage of the first transistor T1. Therefore, in the case where the data signal DATA is adjusted or compensated according to the threshold voltage of the first transistor T1, the data signal DATA can be supplied to the gate electrode of the first transistor T1 so that the deviation of the threshold voltage of the first transistor T1 can be compensated.

[0068] The gate electrode of the fourth transistor T4 is connected to the terminal of the third scan signal GI. The second source / drain electrode of the fourth transistor T4 is connected to the terminal of the initialization voltage VINT. The first source / drain electrode of the fourth transistor T4 is connected to the first electrode of the capacitor Cst, the second source / drain electrode of the third transistor T3, and the gate electrode of the first transistor T1. The fourth transistor T4 is turned on according to the third scan signal GI to perform an operation of transmitting the initialization voltage VINT to the gate electrode of the first transistor T1 to initialize the voltage of the gate electrode of the first transistor T1.

[0069] The gate electrode of the fifth transistor T5 is connected to the terminal of the light emission control signal EM. The first source / drain electrode of the fifth transistor T5 is connected to the terminal of the first power supply voltage ELVDD. The second source / drain electrode of the fifth transistor T5 is connected to the first source / drain electrode of the first transistor T1 and the second source / drain electrode of the second transistor T2. According to some exemplary embodiments, the second source / drain electrode of the fifth transistor T5, the first source / drain electrode of the first transistor T1, and the second source / drain electrode of the second transistor T2 may form a node.

[0070] The gate electrode of the sixth transistor T6 is connected to the terminal of the light emission control signal EM. The first source / drain electrode of the sixth transistor T6 is connected to the second source / drain electrode of the first transistor T1 and the first source / drain electrode of the third transistor T3. The second source / drain electrode of the sixth transistor T6 is connected to the anode of the organic light emitting diode OLED.

[0071] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the light emission control signal EM so that a driving current flows into the organic light emitting diode OLED.

[0072] The gate electrode of the seventh transistor T7 is connected to the terminal of the light emission control signal EM. The first source / drain electrode of the seventh transistor T7 is connected to the anode of the organic light emitting diode OLED. The second source / drain electrode of the seventh transistor T7 is connected to the terminal of the initialization voltage VINT. The seventh transistor T7 is turned on according to the light emission control signal EM to initialize the anode of the organic light emitting diode OLED.

[0073] The seventh transistor T7 receives the same light emission control signal EM as the fifth transistor T5 and the sixth transistor T6. However, since the seventh transistor T7 is an NMOS transistor and the fifth transistor T5 and the sixth transistor T6 are PMOS transistors, the seventh transistor T7 may be turned on at a different timing from the fifth transistor T5 and the sixth transistor T6. That is, when the light emission control signal EM is at a high level, the seventh transistor T7 is turned on and the fifth transistor T5 and the sixth transistor T6 are turned off. When the light emission control signal EM is at a low level, the seventh transistor T7 is turned off and the fifth transistor T5 and the sixth transistor T6 are turned on. Therefore, the initialization operation performed by the seventh transistor T7 may not be executed at the emission time point when the fifth transistor T5 and the sixth transistor T6 are turned on, and the initialization performed by the seventh transistor T7 may be executed at the non-emission time point when the fifth transistor T5 and the sixth transistor T6 are turned off.

[0074] In this embodiment, an example is shown in which the gate electrode of the seventh transistor T7 receives the light emission control signal EM. However, as another example, the circuit of the pixel may be configured such that the gate electrode of the seventh transistor T7 receives the third scan signal GI.

[0075] The second electrode of the capacitor Cst is connected to the terminal of the first power supply voltage ELVDD. The first electrode of the capacitor Cst is connected to the gate electrode of the first transistor T1, the second source / drain electrode of the third transistor T3, and the first source / drain electrode of the fourth transistor T4. The cathode of the organic light-emitting diode OLED is connected to the terminal of the second power supply voltage ELVSS. The organic light-emitting diode OLED receives a driving current from the first transistor T1 and emits light to display an image.

[0076] Hereinafter, reference will be made to Figure 4 describe in detail the cross-sectional structure of the display panel 100. Figure 4 An example of a cross-sectional structure of a pixel in the display area DA and a non-display area NDA including a bent area BA of the display panel 100 is shown.

[0077] Figure 4 is a cross-sectional view showing an exemplary cross-section of the periphery of the pixel in the display area DA and the bent area BA of the non-display area NDA.

[0078] First, reference will be made to Figure 4 describe the display area DA of the display panel 100 in more detail.

[0079] The display area DA may include a silicon transistor area AR1 and an oxide transistor area AR2. In the silicon transistor area AR1, a non-oxide inorganic semiconductor transistor including polysilicon used as a channel (abbreviated as "silicon transistor" hereinafter) is located. In the oxide transistor area AR2, an oxide semiconductor transistor including an oxide semiconductor used as a channel (abbreviated as "oxide transistor" hereinafter) is located. The silicon transistor located in the silicon transistor area AR1 may be a PMOS transistor, and in Figure 4 , the first transistor T1 used as a driving transistor is shown as an example of a silicon transistor. The oxide transistor located in the oxide transistor area AR2 may be an NMOS transistor, and in Figure 4 , the third transistor T3 used as a compensation transistor is shown as an example of an oxide transistor. According to some exemplary embodiments, the second transistor T2, the fifth transistor T5, and the sixth transistor T6, which are other silicon transistors located in the silicon transistor area AR1, may have substantially the same stacked structure as the first transistor T1, and the fourth transistor T4 and the seventh transistor T7, which are other oxide transistors located in the oxide transistor area AR2, may have substantially the same stacked structure as the third transistor T3. More details of the silicon transistor and the oxide transistor will be described below.

[0080] The base substrate 101, the barrier layer 102, the buffer layer 103, the silicon semiconductor layer 105, the first gate insulating film GI1, the first conductive layer 110, the second gate insulating film GI2, the second conductive layer 120, the first interlayer insulating film ILD1, the oxide semiconductor layer 135, the third gate insulating film GI3, the third conductive layer 140, the second interlayer insulating film ILD2, the fourth conductive layer 150, the first via layer VIA1, the fifth conductive layer 160, the second via layer VIA2, the anode ANO, and the pixel defining film PDL may be sequentially positioned in the display area DA of the display panel 100. Each of the above-described multiple layers may be formed as a single-layer film or may be formed as a stacked film including multiple layers. Another layer may be further positioned between these layers.

[0081] The base substrate 101 supports the respective layers located above it. The base substrate 101 may be made of an insulating material such as a polymer resin or the like, for example. Examples of the polymer material may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a composition thereof. The base substrate 101 may include a metal material.

[0082] The base substrate 101 may be a flexible substrate that is bendable, foldable, or rollable. Examples of the material for forming the flexible substrate may include PI, but are not limited thereto according to embodiments of the present disclosure.

[0083] When the organic light-emitting display device is a back or double-sided emission type, a transparent substrate may be used. When the organic light-emitting display device is a top emission type, not only a transparent substrate but also a semi-transparent or opaque substrate may be used.

[0084] The barrier layer 102 may be located on the base substrate 101. The barrier layer 102 may prevent or reduce the diffusion of impurity ions, prevent or reduce the penetration of moisture or external air, and perform a surface flattening function. The barrier layer 102 may include silicon nitride, silicon oxide, silicon oxynitride, or the like. The barrier layer 102 may be omitted according to the type of the base substrate 101, process conditions, or the like.

[0085] The buffer layer 103 may be located on the barrier layer 102. The buffer layer 103 may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and the like. The buffer layer 103 may be omitted according to the type of the base substrate 101, process conditions, or the like.

[0086] The silicon semiconductor layer 105 may be located on the buffer layer 103. The silicon semiconductor layer 105 may be located in the silicon transistor region AR1.

[0087] The silicon semiconductor layer 105 may be made of polysilicon, single-crystalline silicon, amorphous silicon, or the like. In the case where the silicon semiconductor layer 105 is made of polysilicon, the polysilicon may be formed by crystallizing amorphous silicon using a crystallization method such as a rapid thermal annealing (RTA) method, a solid-phase crystallization (SPC) method, an excimer laser annealing (ELA) method, a metal-induced crystallization (MIC) method, a metal-induced lateral crystallization (MILC) method, a sequential lateral solidification (SLS) method, or the like.

[0088] The silicon semiconductor layer 105 may include a channel region 105c, a first source / drain region 105a, and a second source / drain region 105b. The channel region 105c is arranged to overlap with the first gate electrode 111 above it in its thickness direction, and the first source / drain region 105a and the second source / drain region 105b are located on one side and the other side of the channel region 105c, respectively. The first source / drain region 105a and the second source / drain region 105b of the silicon semiconductor layer 105 may include a plurality of carrier ions and thus may have a higher conductivity and a lower resistance than the channel region 105c.

[0089] The silicon semiconductor layer 105 may be the semiconductor layer of each of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 described above, and may form the channel of the corresponding transistor.

[0090] The first gate insulating film GI1 may be located on the silicon semiconductor layer 105. Except for the portions where a plurality of contact holes CNT1 and CNT2 are formed, the first gate insulating film GI1 may cover the upper surface of the silicon semiconductor layer 105 and may also cover the side surface of the silicon semiconductor layer 105. The first gate insulating film GI1 may be formed to cover the entire (or most of) the surface of the base substrate 101.

[0091] The first gate insulating film GI1 may include a silicon compound, a metal oxide, or the like. For example, the first gate insulating film GI1 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. The above materials may be used alone or in combination. The first gate insulating film GI1 may be a single film or a multi-layer film formed of stacked films of different materials.

[0092] The first conductive layer 110 is located on the first gate insulating film GI1. The first conductive layer 110 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 110 may be a single film or a multi-layer film.

[0093] The first conductive layer 110 may be a gate conductive layer and may include a first gate electrode 111 located in the silicon transistor region AR1. The first gate electrode 111 may be the gate electrode of the silicon transistor. The first gate electrode 111 may be connected to the first electrode of the capacitor Cst. The first electrode of the capacitor Cst may be formed by using the first gate electrode 111 itself, or may be formed by using a portion extending from the first gate electrode 111. For example, a portion of the pattern of the integrally formed first conductive layer 110 may overlap with the silicon semiconductor layer 105 to act as the first gate electrode 111 at the corresponding portion, and other portions of the pattern may not overlap with the silicon semiconductor layer 105 to act as the first electrode of the capacitor Cst, and the first electrode of the capacitor Cst overlaps with the second electrode 121 of the capacitor Cst above it.

[0094] The second gate insulating film GI2 may be located on the first conductive layer 110. The second gate insulating film GI2 may cover the upper surface of the first gate electrode 111 except for the portions where the plurality of contact holes CNT1 and CNT2 are formed, and may also cover the side surface of the first gate electrode 111. The second gate insulating film GI2 may be formed to cover the entire (or most of) surface of the first gate insulating film GI1.

[0095] The second gate insulating film GI2 may include a silicon compound, a metal oxide, or the like. For example, the second gate insulating film GI2 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. The above materials may be used alone or in combination. The second gate insulating film GI2 may be a single film or a multilayer film formed of stacked films of different materials.

[0096] The second conductive layer 120 is located on the second gate insulating film GI2. The second conductive layer 120 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second conductive layer 120 may be a single film or a multilayer film.

[0097] The second conductive layer 120 may be the conductive layer of the capacitor Cst and may include the second electrode 121 of the capacitor Cst located in the silicon transistor region ARI. The second electrode 121 of the capacitor Cst and the first electrode of the capacitor Cst connected to the first gate electrode 111 below it may form the capacitor Cst with the second gate insulating film GI2 interposed therebetween.

[0098] The first interlayer insulating film ILD1 is located on the second conductive layer 120. The first interlayer insulating film ILD1 may include a silicon compound, a metal oxide, or the like. For example, the first interlayer insulating film ILD1 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. The above materials may be used alone or in combination. The first interlayer insulating film ILD1 may be a single film or a multilayer film formed of stacked films of different materials.

[0099] The oxide semiconductor layer 135 is located on the first interlayer insulating film ILD1. The oxide semiconductor layer 135 is located in the oxide transistor region AR2. The oxide semiconductor layer 135 may include an oxide semiconductor. The oxide semiconductor may include one or more oxides selected from gallium indium zinc oxide (GIZO), zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), hafnium (Hf), and combinations thereof. The oxide semiconductor may include at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium tin oxide (ITO), and the like.

[0100] The oxide semiconductor layer 135 may include a channel region 135c, a first source / drain region 135a, and a second source / drain region 135b. The channel region 135c is arranged to overlap with the third gate electrode 142 above it in its thickness direction. The first source / drain region 135a and the second source / drain region 135b are located on one side and the other side of the channel region 135c, respectively. The first source / drain electrode regions 135a and 135b of the oxide semiconductor layer 135 may be conductive regions and may have a higher conductivity and a lower resistance than the channel region 135c.

[0101] The oxide semiconductor layer 135 may be the semiconductor layer of each of the above-mentioned third transistor T3, fourth transistor T4, and seventh transistor T7, and may form the channel of the corresponding transistor.

[0102] The third gate insulating film GI3 is located on the oxide semiconductor layer 135. Different from the first gate insulating film GI1 and the second gate insulating film GI2, the third gate insulating film GI3 may be located only in a partial region. That is, the third gate insulating film GI3 may cover the channel region 135c of the oxide semiconductor layer 135 to expose the side surfaces of the first source / drain electrode regions 135a and 135b of the oxide semiconductor layer 135. The third gate insulating film GI3 may have a pattern shape substantially the same as the pattern shape of the third gate electrode 142 above it.

[0103] The third gate insulating film GI3 may include a silicon compound, a metal oxide, or the like. For example, the third gate insulating film GI3 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. The above materials may be used alone or in combination thereof. The third gate insulating film GI3 may be a single film or a multilayer film formed of stacked films of different materials.

[0104] The third conductive layer 140 is located on the third gate insulating film GI3. The third conductive layer 140 may be a gate conductive layer and may include a third gate electrode 142 of a transistor located in the oxide transistor region AR2. The third conductive layer 140 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer 140 may be a single film or a multilayer film.

[0105] The second interlayer insulating film ILD2 is located on the third conductive layer 140. The second interlayer insulating film ILD2 may include a silicon compound, a metal oxide, or the like. For example, the second interlayer insulating film ILD2 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. The above materials may be used alone or in combination thereof. The second interlayer insulating film ILD2 may be a single film or a multilayer film formed of stacked films of different materials.

[0106] The fourth conductive layer 150 is located on the second interlayer insulating film ILD2. The fourth conductive layer 150 may include one or more metals selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fourth conductive layer 150 may be a single film or a multilayer film.

[0107] The fourth conductive layer 150 may be a data conductive layer and may include a first source / drain electrode 151 and a second source / drain electrode 152 of a transistor located in the silicon transistor region AR1 and a first source / drain electrode 153 and a second source / drain electrode 154 of a transistor located in the oxide transistor region AR2.

[0108] In a transistor located in the silicon transistor region AR1, the first source / drain electrode 151 can be connected to the first source / drain region 105a of the silicon semiconductor layer 105 through a first contact hole CNT1 that passes through the second interlayer insulating film ILD2, the second gate insulating film GI2, and the first gate insulating film GI1 and exposes the first source / drain region 105a of the silicon semiconductor layer 105. The second source / drain electrode 152 can be connected to the second source / drain region 105b of the silicon semiconductor layer 105 through a second contact hole CNT2 that passes through the second interlayer insulating film ILD2, the second gate insulating film GI2, and the first gate insulating film GI1 and exposes the second source / drain region 105b of the silicon semiconductor layer 105.

[0109] In a transistor located in the oxide transistor region AR2, the first source / drain electrode 153 can be connected to the first source / drain region 135a of the oxide semiconductor layer 135 through a third contact hole CNT3 that passes through the second interlayer insulating film ILD2 and exposes the first source / drain region 135a of the oxide semiconductor layer 135. The second source / drain electrode 154 can be connected to the second source / drain region 135b of the oxide semiconductor layer 135 through a fourth contact hole CNT4 that passes through the second interlayer insulating film ILD2 and exposes the second source / drain region 135b of the oxide semiconductor layer 135.

[0110] The first via layer VIA1 is located on the fourth conductive layer 150. The first via layer VIA1 can include an inorganic insulating material or an organic insulating material, such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB), or the like. The first via layer VIA1 can be a single film or a multilayer film formed of stacked films of different materials.

[0111] The first via layer VIA1 can be arranged above the second interlayer insulating film ILD2 to completely cover the upper surface of the second interlayer insulating film ILD2. When the first via layer VIA1 is formed of an organic film, the upper surface of the first via layer VIA1 can be flat even though there are steps below the first via layer VIA1.

[0112] The fifth conductive layer 160 is located on the first via layer VIA1. The fifth conductive layer 160 can include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fifth conductive layer 160 can be a single film or a multilayer film.

[0113] The fifth conductive layer 160 may include a connection electrode 161. A fifth contact hole CNT5 exposing the second source / drain electrode 152 of the transistor located in the silicon transistor region AR1 may be located on the first via layer VIA1, and the connection electrode 161 may be connected to the second source / drain electrode 152 through the fifth contact hole CNT5.

[0114] A second via layer VIA2 is located on the connection electrode 161. The second via layer VIA2 may include an inorganic insulating material or an organic insulating material, such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, BCB, or the like. The second via layer VIA2 may be a single film or a multilayer film formed as a stacked film of different materials.

[0115] An anode ANO is located on the second via layer VIA2. The anode ANO may be arranged separately for each pixel. The anode ANO may be electrically connected to the connection electrode 161 through a sixth contact hole CNT6 that passes through the second via layer VIA2 and exposes a part of the connection electrode 161.

[0116] The embodiment according to the present disclosure is not limited thereto, and according to some exemplary embodiments, the anode ANO may have a stacked film structure in which a material layer having a high work function (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3)) and a reflective material layer (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a mixture thereof) are stacked. The layer having a high work function may be arranged above the reflective material layer and positioned close to the light-emitting layer EL. The anode ANO may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, and ITO / Ag / ITO, but the embodiment according to the present disclosure is not limited thereto.

[0117] A pixel defining film PDL may be located on the anode ANO. The pixel defining film PDL may include an opening that partially exposes the anode ANO. The pixel defining film PDL may be made of an organic insulating material or an inorganic insulating material. For example, the pixel defining film PDL may include at least one of polyimide resin, acrylic resin, silicone compound, polyacrylic resin, and the like.

[0118] A light-emitting layer EL is located on the anode ANO exposed by the pixel defining film PDL. The light-emitting layer EL may include an organic material layer. The organic material layer of the light-emitting layer EL may include an organic light-emitting layer and may also include a hole injection / transport layer and / or an electron injection / transport layer.

[0119] The cathode CAT may be located on the light-emitting layer EL. The cathode CAT may be a common electrode formed over the entirety of a plurality of pixels without distinguishing the plurality of pixels. Each of the anode ANO, the light-emitting layer EL, and the cathode CAT may form an organic light-emitting element.

[0120] The cathode CAT may include a material layer having a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, its compounds, or a mixture thereof (e.g., a mixture of Ag and Mg, etc.). The cathode CAT may further include a transparent metal oxide layer located on the material layer having a low work function.

[0121] The anode ANO, the light-emitting layer EL, and the cathode CAT may constitute an organic light-emitting element.

[0122] A thin film encapsulation layer 170 including a first inorganic film 171, a first organic film 172, and a second inorganic film 173 is located over the cathode CAT. The first inorganic film 171 and the second inorganic film 173 may be in contact with each other at an end portion of the thin film encapsulation layer 170. The first organic film 172 may be sealed by the first inorganic film 171 and the second inorganic film 173.

[0123] Each of the first inorganic film 171 and the second inorganic film 173 may include silicon nitride, silicon oxide, silicon oxynitride, or the like. The first organic film 172 may include an organic insulating material.

[0124] Hereinafter, more details of the non-display area NDA will be described.

[0125] In the non-display area NDA of the display panel 100, a base substrate 101, a barrier layer 102, a buffer layer 103, a first gate insulating film GI1, a second gate insulating film GI2, a first interlayer insulating film ILD1, a second interlayer insulating film ILD2, a first via layer VIA1, a connection line 165 formed of a fifth conductive layer 160, a second via layer VIA2, and a pixel defining film PDL may be sequentially arranged.

[0126] The non-display area NDA may include a bending area BA. The bending area BA may include a plurality of openings OP1 and OP2 formed by partially removing one or more insulating films to expose the base substrate 101. For example, the plurality of openings OP1 and OP2 may be formed by partially removing one or more insulating films in a portion where the barrier layer 102, the buffer layer 103, the first gate insulating film GI1, the second gate insulating film GI2, the first interlayer insulating film ILD1, and the second interlayer insulating film ILD2 overlap each other. Each of the plurality of openings OP1 and OP2 may be defined by sidewalls of the partially removed insulating films. Further details thereof will be described below.

[0127] The plurality of openings OP1 and OP2 in the bending region BA may include a bending opening OP2 and a bending peripheral opening OP1.

[0128] As Figure 4 shown, the bending opening OP2 is formed to intersect the bending region BA in the width direction of the bending region BA (that is, the first direction DR1). The bending peripheral opening OP1 is located around the bending opening OP2. The width of the bending peripheral opening OP1 (the width in the second direction DR2) may be greater than the width of the bending opening OP2 (the width in the second direction DR2). Due to the formation of the bending opening OP2, the bending stress that may occur when the display device 1 is bent in the bending region BA can be prevented.

[0129] In a plan view, the bending opening OP2 may be located in the bending peripheral opening OP1. One side wall of the bending peripheral opening OP1 may be located on one side of the bending opening OP2 in the second direction DR2, and the other side wall of the bending peripheral opening OP1 may be located on the other side of the bending opening OP2 in the second direction DR2.

[0130] The bending peripheral opening OP1 is formed to penetrate the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1. The first side wall SW1 of the bending peripheral opening OP1 may be formed by the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1. The first side wall SW1 may be an etched surface formed by etching. The side surfaces of the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1 forming the first side wall SW1 may be arranged with each other. The bending peripheral opening OP1 may expose the buffer layer 103 thereunder. The buffer layer 103 and the barrier layer 102 thereunder may protrude from the first side wall SW1 of the bending peripheral opening OP1 to the bending opening OP2. The first side wall SW1 of the bending peripheral opening OP1 may be covered by the second interlayer insulating film ILD2 thereabove. That is, the second interlayer insulating film ILD2 may be in direct contact with the side surface of the first interlayer insulating film ILD1, the side surface of the second gate insulating film GI2, and the side surface of the first gate insulating film GI1 forming the first side wall SW1 of the bending peripheral opening OP1, and furthermore, may be in direct contact with the upper surface of the buffer layer 103 protruding from the side surface of the first gate insulating film GI1 to the bending opening OP2.

[0131] A bent opening OP2 is formed in a bent peripheral opening OP1 to pass through a second interlayer insulating film ILD2, a buffer layer 103, and a barrier layer 102 located on the buffer layer 103 exposed through the bent peripheral opening OP1. The bent opening OP2 may include a second sidewall SW2, a third sidewall SW3 located above an upper portion of the second sidewall SW2, and a step portion GP located between the second sidewall SW2 and the third sidewall SW3. The second sidewall SW2, the third sidewall SW3, and the step portion GP may be located inside a first sidewall SW1 of the bent peripheral opening OP1 described above.

[0132] The second sidewall SW2 of the bent opening OP2 may be formed by portions of side surfaces of the barrier layer 102, the buffer layer 103, and the second interlayer insulating film ILD2. The portions of the side surfaces of the barrier layer 102, the buffer layer 103, and the second interlayer insulating film ILD2 may be arranged with each other. The second sidewall SW2 may be an etched surface formed by etching.

[0133] The third sidewall SW3 of the bent opening OP2 may be formed by other portions of the side surface of the second interlayer insulating film ILD2. The third sidewall SW3 may be formed by conformally forming along the first sidewall SW1 of the bent peripheral opening OP1 where the second interlayer insulating film ILD2 is located above the first sidewall SW1. Different from the first sidewall SW1 or the second sidewall SW2, the third sidewall SW3 may be an unetched surface formed by conformally depositing without etching.

[0134] The step portion GP formed by an upper surface of the second interlayer insulating film ILD2 may be located between the second sidewall SW2 and the third sidewall SW3 of the bent opening OP2. The step portion GP may overlap with the buffer layer 103 and the barrier layer 102 protruding from the first sidewall SW1 of the bent peripheral opening OP1 into the bent opening OP2. The upper surface of the step portion GP may be flat, but is not limited thereto according to an embodiment of the present disclosure.

[0135] A length d1 by which the second sidewall SW2 located at the other side of the bent opening OP2 protrudes from the first sidewall SW1 located at the other side of the bent peripheral opening OP1 in a second direction DR2 may be different from a length d2 by which the second sidewall SW2 located at one side of the bent opening OP2 protrudes from the first sidewall SW1 located at one side of the bent peripheral opening OP1 in the second direction DR2.

[0136] The second sidewall SW2 of the bent opening OP2 may protrude more from the first sidewall SW1 of the bent peripheral opening OP1 than the third sidewall SW3. That is, in the bent region BA, the distance between the second sidewalls SW2 located on one side and the second sidewalls SW2 located on the other side may be less than the distance between the third sidewalls SW3 located on one side and the third sidewalls SW3 located on the other side, and the distance between the second sidewalls SW2 and the distance between the third sidewalls SW3 may be less than the distance between the first sidewalls SW1 of the bent peripheral opening OP1.

[0137] The space vacated due to the bent opening OP2 is filled with the first via layer VIA1. The first via layer VIA1 covers the upper surface of the base substrate 101 exposed through the bent opening OP2. In addition, the first via layer VIA1 may be in contact with the second sidewall SW2, the third sidewall SW3, and the step portion GP that are the inner surfaces of the bent opening OP2. As described above, the first via layer VIA1 may be located above the second interlayer insulating film ILD2 to completely cover the upper surface of the second interlayer insulating film ILD2. When the first via layer VIA1 is formed of an organic film, although there are steps below the first via layer VIA1, the upper surface of the first via layer VIA1 may be flat.

[0138] The connection line 165 is located on the upper surface of the first via layer VIA1. The connection line 165 may be formed of the fifth conductive layer 160. The connection line 165 may be formed together with the above-described connection electrode 161 and may be made of the same material as the material forming the connection electrode 161.

[0139] The second via layer VIA2 and the pixel defining film PDL may be located on the connection line 165. In the non-display area NDA, at least one of the second via layer VIA2 and the pixel defining film PDL may be omitted.

[0140] Hereinafter, a method of manufacturing the display device 1 according to some exemplary embodiments will be described in more detail.

[0141] Figure 5 is a flowchart showing a method of manufacturing the display device 1 according to some exemplary embodiments.

[0142] Figures 6 to 8 is a cross-sectional view showing process operations before the process operation of forming an oxide semiconductor pattern in a method of manufacturing the display device 1 according to some exemplary embodiments.

[0143] Refer to Figure 5 and Figure 6, first, a display area DA including a silicon transistor area AR1 and an oxide transistor area AR2 and a non-display area NDA arranged around the display area DA are defined. A base substrate 101 on which a silicon semiconductor layer 105 is positioned is provided in the silicon transistor area AR1, and the silicon semiconductor layer 105 (S01) is formed.

[0144] For example, a barrier layer 102 and a buffer layer 103 may be sequentially stacked on the base substrate 101, and a silicon semiconductor layer may be formed on the buffer layer 103 and then patterned by a photolithography process so that the silicon semiconductor layer 105 can be formed as Figure 6 shown.

[0145] Subsequently, referring to Figure 7 , a first gate insulating film GI1 is formed on the silicon semiconductor layer 105, and a first conductive layer 110 including a first gate electrode 111 is formed on the first gate insulating film GI1 (S02).

[0146] For example, the first gate insulating film GI1 may be formed on the entire surface of the buffer layer 103 on which the silicon semiconductor layer 105 is formed. Subsequently, the first gate electrode 111 is formed on the first gate insulating film GI1. That is, a material layer for the first conductive layer 110 may be deposited on the entire surface of the first gate insulating film GI1 and then patterned by a photolithography process so that the first gate electrode 111 can be formed as Figure 7 shown.

[0147] Subsequently, referring to Figure 8 , a second gate insulating film GI2 is formed on the first gate electrode 111, and a second electrode 121 of a capacitor Cst is formed on the second gate insulating film GI2 (S03). [[ID=,21]]

[0148] For example, the second gate insulating film GI2 may be formed on the entire surface of the first gate insulating film GI1 on which the first gate electrode 111 is formed. Subsequently, the second electrode 121 of the capacitor Cst is formed on the second gate insulating film GI2. That is, a material layer for the second conductive layer 120 may be deposited on the entire surface of the second gate insulating film GI2 and then patterned by a photolithography process so that the second electrode 121 of the capacitor Cst can be formed as Figure 8 shown.

[0149] Figure 9 is a flowchart of process operations showing a process of forming an oxide semiconductor pattern according to some exemplary embodiments.

[0150] Figures 10 to 14 is a cross-sectional view of process operations showing a process of forming an oxide semiconductor pattern in a method of manufacturing a display device 1 according to some exemplary embodiments.

[0151] Hereinafter, reference will be made to Figures 9 to 14 operation S04 of forming the oxide semiconductor layer 135 will be described in detail.

[0152] Referring to Figures 9 to 11 , a first interlayer insulating film ILD1 is formed on the second electrode 121 of the capacitor Cst, a material OX for the oxide semiconductor layer and a photoresist PRO for the oxide semiconductor layer are applied on the first interlayer insulating film ILD1, and then exposure (S04_1) is performed by using a halftone mask HFM.

[0153] For example, a material OX for the oxide semiconductor layer and a photoresist PRO for the oxide semiconductor layer may be applied on the first interlayer insulating film ILD1, and then exposure may be performed by using a halftone mask HFM so that a photoresist pattern can be formed.

[0154] According to the transmittance (or light transmittance) in one mask, the halftone mask HFM may be divided into a light-blocking portion BL, a first light-transmitting portion HT, and a second light-transmitting portion TR. The light transmittance of the second light-transmitting portion TR may be greater than the light transmittance of the first light-transmitting portion HT.

[0155] The photoresist PRO for the oxide semiconductor layer may be divided into a first region R1, a second region R2, and a third region R3. The first region R1 may correspond to the first light-transmitting portion HT of the halftone mask HFM, and the second region R2 may correspond to the second light-transmitting portion TR of the halftone mask HFM. In addition, the third region R3 may correspond to the light-blocking portion BL of the halftone mask HFM.

[0156] The light-blocking portion BL may block the light provided from the outside to prevent the light from reaching the third region R3 of the photoresist PRO for the oxide semiconductor layer. The first light-transmitting portion HT may transmit only some of the light provided from the outside by controlling the light transmittance, and only allow some of the light to reach the first region R1 of the photoresist PRO for the oxide semiconductor layer. The second light-transmitting portion TR may transmit most of the light provided from the outside, and allow most of the light to reach the second region R2 of the photoresist PRO for the oxide semiconductor layer.

[0157] For example, in the case of a positive photoresist, a photosensitizer is decomposed in the exposed photoresist and an acid is formed. As a result, the region where the photosensitizer is decomposed has the property of being sufficiently melted in a developer. In this case, any part of the photoresist on the substrate can be selectively removed by using a developer (e.g., a set or predetermined developer) according to the chemical changes between the light-exposed part and the non-light-exposed part, thereby forming a photoresist pattern. However, in the case of using a halftone mask HFM, only a part of the photoresist can be removed from the part corresponding to the part that only partially transmits some of the light provided from the outside (e.g., the first light-transmitting part HT) (e.g., the first region R1), and the remaining part can be retained without being removed. Therefore, the photoresist PRO for the oxide semiconductor layer in the third region R3 can be retained to the first height h1, and the photoresist PRO for the oxide semiconductor layer in the first region R1 can be retained to the second height h2. The first height h1 can be greater than the second height h2. In addition, the photoresist in the second region R2 can be completely removed, and a part of the upper surface of the material OX for the oxide semiconductor layer can be exposed in the second region R2. However, in the case of a negative photoresist, whether the photoresist PRO for the oxide semiconductor layer is retained in the third region R3 can be opposite to whether the photoresist PRO for the oxide semiconductor layer is retained in the second region R2.

[0158] Subsequently, referring to Figure 12 , in the second region R2 where the photoresist PRO for the oxide semiconductor layer has been completely removed, the material OX for the oxide semiconductor layer, the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1 are etched so that a bent peripheral opening OP1 is formed (S04_2).

[0159] For example, in the second region R2 where the photoresist PRO for the oxide semiconductor layer has been completely removed, the material OX for the oxide semiconductor layer can be etched by using a wet etching method, and then the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1 can be etched by using a dry etching method so that a bent peripheral opening OP1 is formed. In the etching process for forming the bent peripheral opening OP1, the exposed buffer layer 103 can be further etched after etching the first gate insulating film GI1. In this case, the sidewall of the bent peripheral opening OP1 can be formed by a part of the buffer layer 103 and the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1.

[0160] Subsequently, referring to Figure 13 and Figure 14, etch a portion of the first interlayer insulating film ILD1, the second gate insulating film GI2, the first gate insulating film GI1, and the buffer layer 103, and then perform an ashing process (S04_3) thereon. Thereafter, an oxide semiconductor pattern is formed (S04_4).

[0161] For example, the photoresist PRO of the oxide semiconductor layer for the third region R3 can be partially removed by an ashing process so that a certain amount (e.g., a set amount or a predetermined amount) of the photoresist PRO for the oxide semiconductor layer can remain, and the photoresist PRO of the oxide semiconductor layer for the first region R1 can be completely removed. Accordingly, the material OX of the oxide semiconductor layer for the third region R3 may not be exposed, but the material OX of the oxide semiconductor layer for the first region R1 may be exposed.

[0162] The exposed material OX of the oxide semiconductor layer for the first region R1 can be removed by etching, and accordingly, an oxide semiconductor pattern including the oxide semiconductor layer 135 can be formed (S04_4).

[0163] Hereinafter, the process operations after the process operation of forming the oxide semiconductor pattern will be described.

[0164] Figures 15 to 25 is a cross-sectional view showing the process operations after the process operation of forming the oxide semiconductor pattern in the method of manufacturing the display device 1 according to the embodiment.

[0165] Refer again to Figure 5 and Figure 15 , a third gate insulating film GI3 is formed on the oxide semiconductor layer 135, and a third gate electrode 142 is formed on the third gate insulating film GI3 (S05).

[0166] For example, a patterned third gate insulating film GI3 and a patterned third gate electrode 142 may be formed through a masking process. A material layer for the third gate insulating film GI3 is deposited on the entire surface of the first interlayer insulating film ILD1 on which the oxide semiconductor layer 135 is formed, and then, a material layer for the third gate electrode 142 is deposited on the entire deposition surface of the material layer for the third gate insulating film GI3. Subsequently, a photoresist layer is deposited on the material layer for the third gate electrode 142, a photoresist pattern is formed through exposure and development, and then, the material layer for the third gate electrode 142 and the material layer for the third gate insulating film GI3 are sequentially etched by using the photoresist pattern as an etching mask. Thereafter, the photoresist pattern is removed through a lift-off or ashing process. The case where the photoresist pattern is used as an etching mask until the third gate insulating film GI3 is patterned is shown above. However, the patterned upper layer may be used as a hard mask for etching the layer therebelow. In this case, the photoresist pattern may be used as an etching mask together with the hard mask. As another example, after the hard mask is formed, the photoresist pattern may be removed, and the layer below the hard mask may be etched by using the hard mask as an etching mask.

[0167] Subsequently, referring to Figures 16 to 19 , a second interlayer insulating film ILD2 is stacked on the third gate electrode 142, and a first contact hole CNT1, a second contact hole CNT2, a third contact hole CNT3, a fourth contact hole CNT4, and a bend opening OP2 (S06) are formed.

[0168] For example, the second interlayer insulating film ILD2 may be formed on the entire surface of the first interlayer insulating film ILD1 where the third gate insulating film GI3 and the third gate electrode 142 are located, and the first contact hole CNT1 and the second contact hole CNT2 are first formed in the second interlayer insulating film ILD2.

[0169] The first contact hole CNT1 and the second contact hole CNT2 can be formed through a masking process. The first contact hole CNT1 and the second contact hole CNT2 can be formed simultaneously by using the same mask. For example, an insulating layer for the second interlayer insulating film ILD2 can be deposited on the entire surface of the first interlayer insulating film ILD1 on which the oxide semiconductor layer 135, the third gate insulating film GI3, and the third gate electrode 142 are formed. Subsequently, a first photoresist pattern PR1 exposing a region corresponding to a portion of the silicon semiconductor layer 105 is formed on the insulating layer for the second interlayer insulating film ILD2, and the insulating layer for the second interlayer insulating film ILD2, the second gate insulating film GI2, and the first gate insulating film GI1 are etched by using the first photoresist pattern PR1 as an etching mask so that the first contact hole CNT1 and the second contact hole CNT2 exposing the portion of the silicon semiconductor layer 105 are formed. In this case, the first photoresist pattern PR1 may not include a pattern exposing a portion of the oxide semiconductor layer 135. That is, in the above process, the upper portion of the oxide semiconductor layer 135 may be covered and protected by the first photoresist pattern PR1 and may not be etched.

[0170] After the first contact hole CNT1 and the second contact hole CNT2 are formed, a third contact hole CNT3 and a fourth contact hole CNT4 can be formed in the second interlayer insulating film ILD2.

[0171] The third contact hole CNT3 and the fourth contact hole CNT4 can be formed through a masking process. The third contact hole CNT3 and the fourth contact hole CNT4 can be formed simultaneously by using the same mask. For example, a second photoresist pattern PR2 exposing a region corresponding to a portion of the oxide semiconductor layer 135 is formed on the second interlayer insulating film ILD2 in which the first contact hole CNT1 and the second contact hole CNT2 are formed, and the second interlayer insulating film ILD2 is etched by using the second photoresist pattern PR2 as an etching mask so that the third contact hole CNT3 and the fourth contact hole CNT4 exposing the portion of the oxide semiconductor layer 135 are formed. In this case, the second photoresist pattern PR2 may cover and protect the first contact hole CNT1 and the second contact hole CNT2 exposing the portion of the silicon semiconductor layer 105, and the portion of the silicon semiconductor layer 105 exposed by the first contact hole CNT1 and the second contact hole CNT2 may be etched. Additionally, as will be described in more detail below, the bend opening OP2 can be formed in the process of forming the first contact hole CNT1 and the second contact hole CNT2, and the bend opening OP2 can also be covered and protected by the second photoresist pattern PR2.

[0172] In addition, the bent opening OP2 can be formed in the non-display area NDA by the operation S06 of forming the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4 without any additional process.

[0173] The thicknesses of the second interlayer insulating film ILD2, the buffer layer 103, and the barrier layer 102 in the bending area BA can be similar to those of the second interlayer insulating film ILD2, the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1 in the silicon transistor area AR1. That is, when etching the second interlayer insulating film ILD2, the buffer layer 103, and the barrier layer 102 in the bending area BA, the method of etching the above components can be substantially the same as the method of etching the second interlayer insulating film ILD2, the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1, and a separate process may be unnecessary. Therefore, the second interlayer insulating film ILD2, the buffer layer 103, and the barrier layer 102 can be etched in the bending area BA by the operation S06 so that the bent opening OP2 can be formed.

[0174] For example, the first photoresist pattern PR1 can be formed to expose the areas corresponding to the part of the silicon semiconductor layer 105 and the bent opening OP2 of the bending area BA. When etching is performed using the first photoresist pattern PR1, the second interlayer insulating film ILD2, the buffer layer 103, and the barrier layer 102 in the bending area BA can be etched simultaneously in the process of forming the first contact hole CNT1 and the second contact hole CNT2, and thus the part of the base substrate 101 in the corresponding area can be exposed.

[0175] However, the bent opening OP2 can be formed not only by the process of forming the first contact hole CNT1 and the second contact hole CNT2, but also by the process of forming the first contact hole CNT1 and the second contact hole CNT2 and the process of forming the third contact hole CNT3 and the fourth contact hole CNT4.

[0176] Subsequently, referring to Figure 20, a patterned fourth conductive layer 150 is formed on the second interlayer insulating film ILD2 (S07). The fourth conductive layer 150 may include a first source / drain electrode 151 and a second source / drain electrode 152 of a transistor located in the silicon transistor region AR1, and a first source / drain electrode 153 and a second source / drain electrode 154 of a transistor located in the oxide transistor region AR2. The patterned fourth conductive layer 150 may be formed by a masking process. For example, a material layer for the fourth conductive layer 150 may be deposited on the entire surface of the second interlayer insulating film ILD2. In the deposition process, the material layer for the fourth conductive layer 150 may be deposited on the inner sides of the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4. Accordingly, the first source / drain electrode 151 and the second source / drain electrode 152 of the transistor located in the silicon transistor region AR1, and the first source / drain electrode 153 and the second source / drain electrode 154 of the transistor located in the oxide transistor region AR2 may be connected to the silicon semiconductor layer 105 and the oxide semiconductor layer 135, respectively. Subsequently, a photoresist layer is deposited on the material layer for the fourth conductive layer 150, a photoresist pattern is formed by exposure and development, and then the material layer for the fourth conductive layer 150 is etched by using the photoresist pattern as an etching mask. Thereafter, the photoresist pattern is removed by a lift-off or ashing process, and accordingly, the patterned fourth conductive layer 150 is formed exactly as Figure 20 shown therein.

[0177] Subsequently, referring to Figure 21 , a first via layer VIA1 is formed on the fourth conductive layer 150, and a fifth contact hole CNT5 is formed to expose portions of the first source / drain electrode 151 and the second source / drain electrode 152 of the transistor located in the silicon transistor region AR1 (S08).

[0178] The first via layer VIA1 may include, for example, an organic material including a photosensitive material. The first via layer VIA1 may be stacked above the display area DA and the non-display area NDA, and may have a substantially flat surface. In this case, the bending opening OP2 of the bending area BA of the non-display area NDA may also be filled with the first via layer VIA1. After depositing the organic material layer for the first via layer VIA1, the fifth contact hole CNT5 may be formed in the first via layer VIA1 by exposure and development to expose portions of the first source / drain electrode 151 and the second source / drain electrode 152 of the transistor located in the silicon transistor region AR1.

[0179] Subsequently, referring to Figure 22 , a fifth conductive layer 160 is formed on the first via layer VIA1 (S09).

[0180] The fifth conductive layer 160 may include a connection electrode 161 located in the display area DA and a connection line 165 located in the non-display area NDA. The patterned fifth conductive layer 160 may be formed through a masking process. For example, a material layer for the fifth conductive layer 160 may be deposited on the entire surface of the first via layer VIA1. During the deposition process, the material layer for the fifth conductive layer 160 may be deposited on the inner side of the fifth contact hole CNT5. Accordingly, the connection electrode 161 may be connected to the first source / drain electrode 151 and the second source / drain electrode 152 of the transistor located in the silicon transistor area AR1. Subsequently, a photoresist layer is deposited on the material layer for the fifth conductive layer 160, a photoresist pattern is formed through exposure and development, and then the material layer for the fifth conductive layer 160 is etched by using the photoresist pattern as an etching mask. After that, the photoresist pattern is removed through a lift-off or ashing process, and accordingly, the patterned fifth conductive layer 160 is formed exactly as Figure 21 shown in

[0181] Subsequently, referring to Figure 23 , a second via layer VIA2 is formed on the fifth conductive layer 160, and a sixth contact hole CNT6 (S10) that exposes a portion of the connection electrode 161 is formed.

[0182] The second via layer VIA2 may include, for example, an organic material including a photosensitive material. The second via layer VIA2 may be stacked only in the display area DA and may have a substantially flat surface. After depositing the organic material layer for the second via layer VIA2, the sixth contact hole CNT6 that exposes a portion of the connection electrode 161 may be formed in the second via layer VIA2 through exposure and development.

[0183] Subsequently, referring to Figure 24 , an anode ANO (S11) is formed on the second via layer VIA2 on which the fifth conductive layer 160 is formed.

[0184] The patterned anode ANO may be formed through a masking process. For example, a material layer for the anode ANO may be deposited on the entire surface of the second via layer VIA2. During the deposition process, the material layer for the anode ANO may be deposited on the inner side of the sixth contact hole CNT6 and connected to the connection electrode 161.

[0185] Subsequently, referring to Figure 25 , a patterned pixel defining layer PDL (S12) is formed on the second via layer VIA2 on which the anode ANO is formed.

[0186] The pixel defining layer PDL may include, for example, an organic material including a photosensitive material. In this case, the patterned pixel defining layer PDL may be formed by applying the organic material layer for the pixel defining layer PDL and then performing exposure and development.

[0187] The pixel definition layer PDL may be formed along the boundaries of the pixels and may overlap partially with the anode ANO. The pixel definition layer PDL may be formed to overlap with the sixth contact hole CNT6. When the internal space of the sixth contact hole CNT6 is partially filled with the anode ANO, the remaining internal space of the sixth contact hole CNT6 may be completely filled with the pixel definition layer PDL.

[0188] As described above, according to some exemplary embodiments, a separate mask process for forming the bending opening OP2 is not required. Therefore, the number of mask processes can be reduced, thereby improving the process efficiency.

[0189] Hereinafter, other embodiments will be described. In the following embodiments, the configurations that are the same as those in the above embodiments will be omitted or simplified, and the differences between the following embodiments and the above embodiments will be mainly described.

[0190] Figure 26 is a cross-sectional view of the display device 1_1 according to some exemplary embodiments.

[0191] Referring to Figure 26 , the display device 1_1 according to the present embodiment is different from the display device 1 in the embodiment of Figure 4 in that the oxide electrode 131_1 is positioned instead of the second electrode 121 of the capacitor Cst.

[0192] For example, different from the embodiment of Figure 4 in which the second electrode 121 of the capacitor Cst is located on the second gate insulating film GI2, the display device 1_1 according to the present embodiment may not include the second electrode 121 of the capacitor Cst, and the oxide semiconductor layer 135 may be located on the second gate insulating film GI2. In addition, the oxide electrode 131_1 may be located in the silicon transistor region AR1 on the second gate insulating film GI2 where the oxide semiconductor layer 135 is positioned. The oxide semiconductor layer 135 and the oxide electrode 131_1 may be formed simultaneously on the same layer using the same mask and may be formed of the same material. Furthermore, similar to the second electrode 121 of the capacitor Cst in the embodiment of Figure 4 , the oxide electrode 131_1 may be used as the second electrode of the capacitor Cst. That is, the first gate electrode 111 and the oxide electrode 131_1 may form the capacitor Cst by using the second gate insulating film GI2 located therebetween as a dielectric.

[0193] As in Figure 4In the embodiment, only the third gate insulating film GI3 in the partial region is different. The third gate insulating film GI3_1 can be stacked over the entire region of the second gate insulating film GI2 where the oxide semiconductor layer 135 and the oxide electrode 131_1 are located.

[0194] The first interlayer insulating film ILD1_1 can be stacked on the third gate insulating film GI3_1, and the fourth conductive layer 150 can be located on the first interlayer insulating film ILD1_1. The first via VIA1 can be stacked on the fourth conductive layer 150, and the display device 1_1 according to some exemplary embodiments may not include the second interlayer insulating film ILD2.

[0195] In addition, the first sidewall SW1 of the bent peripheral opening OP1 can be formed by the third gate insulating film GI3_1, the second gate insulating film GI2, and the first gate insulating film GI1, and the second sidewall SW2 of the bent opening OP2 can be formed by the first interlayer insulating film ILD1_1, the buffer layer 103, and the barrier layer 102. Therefore, the first gate insulating film GI1, the second gate insulating film GI2, and the third gate insulating film GI3_1 can be located outside the first interlayer insulating film ILD1_1 forming the second sidewall SW2 of the bent opening OP2.

[0196] In this embodiment, a separate mask for forming the bent opening OP2 can be unnecessary, and thus the number of masks required for the process can be reduced. In addition, a separate conductive layer for forming a capacitor Cst with the first gate electrode 111 can be unnecessary, and a mask for forming the separate conductive layer can be unnecessary, and thus the number of masks required for the process can be further reduced.

[0197] Figure 27 is a cross-sectional view of a display device 1_2 according to some exemplary embodiments.

[0198] Referring to Figure 27 and, the display device 1_2 according to the present embodiment is different from the display device 1 in the Figure 4 embodiment in that the display device 1_2 further includes a lower light-blocking pattern 112_2 in the oxide transistor region AR2.

[0199] According to some exemplary embodiments, the first conductive layer 110 can include a first gate electrode 111 located in the silicon transistor region AR1 and a lower light-blocking pattern 112_2 located in the oxide transistor region AR2. The first gate electrode 111 and the lower light-blocking pattern 112_2 can be formed simultaneously on the same layer using the same mask, and thus a separate mask for forming the lower light-blocking pattern 112_2 can be unnecessary. In addition, the first gate electrode 111 and the lower light-blocking pattern 112_2 can include the same material.

[0200] The lower light-blocking pattern 112_2 can be used to prevent light incident from the lower direction of the display panel 100 from entering the oxide semiconductor layer 135 located above it. The lower light-blocking pattern 112_2 can overlap with the channel region 135c of the oxide semiconductor layer 135. In addition, the lower light-blocking pattern 112_2 can be used as another gate electrode of the oxide transistor. In this case, the lower light-blocking pattern 112_2 can be electrically connected to the third gate electrode 142 or either the first source / drain electrode 153 and the second source / drain electrode 154 of the transistor located in the oxide transistor region AR2.

[0201] Even in this embodiment, a separate mask for forming the bending opening OP2 may be unnecessary, and thus the number of masks required for the process can be reduced.

[0202] Figure 28 is a cross-sectional view of a display device 1_3 according to some exemplary embodiments.

[0203] Referring to Figure 28 , the display device 1_3 according to this embodiment is different from the display device 1 in the embodiment of Figure 4 in that the first sidewall SW1_3 of the bending peripheral opening OP1_3 is formed by a part of the side surface of the buffer layer 103 and the side surfaces of the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1.

[0204] For example, in the process of forming the bending peripheral opening OP1_3, the upper part of the buffer layer 103 and the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1 can be etched. Therefore, the bending peripheral opening OP1_3 can expose a part of the buffer layer 103, and the first sidewall SW1_3 of the bending peripheral opening OP1_3 can be formed by a part of the side surface of the buffer layer 103 and the side surfaces of the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1.

[0205] Accordingly, the thickness of the buffer layer 103 in the region where the bending peripheral opening OP1_3 overlaps with the buffer layer 103 can be smaller than the thickness of the buffer layer 103 in the region where the bending peripheral opening OP1_3 does not overlap with the buffer layer 103. In addition, the second interlayer insulating film ILD2 forming the third sidewall SW3 of the bending opening OP2_3 can cover and surround the side surface of the buffer layer 103 and the side surfaces of the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1.

[0206] Even in the present embodiment, a separate mask for forming the bent opening OP2_3 may be unnecessary, and thus the number of masks required for the process may be reduced.

[0207] Figure 29 is a cross-sectional view of a display device 1_4 according to some exemplary embodiments.

[0208] Referring to Figure 29 , the display device 1_4 according to the present embodiment is different from the display device 1 in the embodiment of Figure 28 in that the bent peripheral opening OP1_4 exposes portions of the buffer layer 103 and the barrier layer 102.

[0209] For example, in the process of forming the bent peripheral opening OP1_4, most of the buffer layer 103, the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1 may be etched, and only a portion of the buffer layer 103 may remain on the upper surface of the barrier layer 102. The portion of the buffer layer 103 may remain on the upper surface of the barrier layer 102 in an island shape. Accordingly, the bent peripheral opening OP1_4 may expose a portion of the buffer layer 103 and a portion of the upper surface of the barrier layer 102, and the first sidewall SW1_4 of the bent peripheral opening OP1_4 may be formed by the side surface of the buffer layer 103 and the side surfaces of the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1.

[0210] Accordingly, the second interlayer insulating film ILD2 forming the third sidewall SW3_4 of the bent opening OP2_4 may cover and surround the side surface of the buffer layer 103 and the side surfaces of the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1. In addition, most of the second sidewall SW2_4 of the bent opening OP2_4 may be formed by the second interlayer insulating film ILD2 and the barrier layer 102.

[0211] According to some exemplary embodiments, a separate mask for forming the bent opening OP2_4 may be omitted, and thus the number of masks required for the process may be reduced.

[0212] Figure 30 is a cross-sectional view of a display device 1_5 according to some exemplary embodiments.

[0213] Referring to Figure 30 , the display device 1_5 according to the present embodiment is different from the display device 1_4 in the embodiment of Figure 29 in that the bent peripheral opening OP1_5 exposes only a portion of the barrier layer 102.

[0214] For example, in the process of forming the bent peripheral opening OP1_5, the entire buffer layer 103, the first interlayer insulating film ILD1, the second gate insulating film GI2, and the first gate insulating film GI1 can be etched. Accordingly, the bent peripheral opening OP1_5 can expose only the upper surface of the barrier layer 102, and the first sidewall SW1_5 of the bent peripheral opening OP1_5 can be formed by the side surface of the buffer layer 103, the side surface of the first interlayer insulating film ILD1, the side surface of the second gate insulating film GI2, and the side surface of the first gate insulating film GI1.

[0215] Correspondingly, the second interlayer insulating film ILD2 forming the third sidewall SW3_5 of the bent opening OP2_5 can cover and surround the side surface of the buffer layer 103, the side surface of the first interlayer insulating film ILD1, the side surface of the second gate insulating film GI2, and the side surface of the first gate insulating film GI1. In addition, the second sidewall SW2_5 of the bent opening OP2_5 can be formed by the second interlayer insulating film ILD2 and the barrier layer 102.

[0216] According to some exemplary embodiments, a separate mask for forming the bent opening OP2_5 can be omitted, so the number of masks required for the process can be reduced.

[0217] Figure 31 is a cross-sectional view of a display device 1_6 according to some exemplary embodiments.

[0218] Referring to Figure 31 , the display device 1_6 according to the present embodiment is different from the display device 1 in the embodiment of Figure 4 in that the display device 1_6 does not include the second via layer VIA2 and the fifth conductive layer 160, and includes a bent via layer VIA0 located in the non-display area NDA.

[0219] For example, in the non-display area NDA, the bent via layer VIA0 can be used to fill the bent opening OP2 instead of the first via layer VIA1. The bent via layer VIA0 can include an inorganic insulating material or an organic insulating material, such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, BCB, or the like. The bent via layer VIA0 can be a single film or a multilayer film formed as a stacked film of different materials. The bent via layer VIA0 can be made of the same material as the first via layer VIA1, but is not limited thereto according to the embodiments of the present disclosure.

[0220] The non-display area line 155_6 may be located on the via layer VIA0. The non-display area line 155_6 may be formed by the fourth conductive layer 150. The non-display area line 155_6 may be formed together with the first source / drain electrode 151 and the second source / drain electrode 152 of the transistor located in the silicon transistor region AR1 and the first source / drain electrode 153 and the second source / drain electrode 154 of the transistor located in the oxide transistor region AR2 described above, and may be made of the same material as that forming the first source / drain electrode 151 and the second source / drain electrode 152 and the first source / drain electrode 153 and the second source / drain electrode 154.

[0221] The first via layer VIA1 may be located on the non-display area line 155_6, and the first via layer VIA1 may be formed simultaneously with the first via layer VIA1 in the display area DA to have a height substantially the same as that of the first via layer VIA1 in the display area DA.

[0222] In the display area DA, the anode ANO and the pixel defining film PDL may be formed on the first via layer VIA1, and the anode ANO may be stacked in the fifth contact hole CNT5.

[0223] Even in this case, a separate mask for forming the bending opening OP2 may be unnecessary, and thus the number of masks required for the process may be reduced.

[0224] Hereinafter, a method of manufacturing the display device 1_6 according to some exemplary embodiments as shown in, for example, Figure 31 will be described.

[0225] Figure 32 is a partial flowchart showing a method of manufacturing the display device 1_6 according to the embodiment of Figure 31 is a cross-sectional view showing a process operation of a method of manufacturing the display device 1_6 according to the embodiment of Figures 33 to 35 is a partial flowchart showing a method of manufacturing the display device 1_6 according to the embodiment of Figure 31 is a cross-sectional view showing a process operation of a method of manufacturing the display device 1_6 according to the embodiment of

[0226] Referring to Figure 32 and Figure 33 , as described above, the bending opening OP2 may be formed by operations S04 and S06 of forming an oxide semiconductor pattern and the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4. After operations S04 and S06, a bending via layer VIA0 may be formed on the bending opening OP2 (S06_6). The bending opening OP2 may be filled with the bending via layer VIA0, and the bending via layer VIA0 may contact the upper surface of the base substrate 101 in the bending opening OP2 and the side surfaces and the upper surface of the barrier layer 102, the buffer layer 103, and the second interlayer insulating film ILD2.

[0227] Subsequently, referring to Figure 34 and Figure 35 , a fourth conductive layer 150 (S07) can be formed on the second interlayer insulating film ILD2 and the via-through layer VIA0. The fourth conductive layer 150 can include a first source / drain electrode 151 and a second source / drain electrode 152 of a transistor located in the silicon transistor region AR1, a first source / drain electrode 153 and a second source / drain electrode 154 of a transistor located in the oxide transistor region AR2, and a non-display region line 155_6 located on the via-through layer VIA0.

[0228] A first via layer VIA1 (S08) can be formed on the fourth conductive layer 150. The first via layer VIA1 can have the same height in the display region DA and the non-display region NDA.

[0229] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that various modifications can be made without departing from the scope of the present disclosure and without changing the essential features. Therefore, the above embodiments should be considered only in a descriptive sense and not for the purpose of limitation. Thus, the scope of the embodiments of the present disclosure is defined by the appended claims and their equivalents.

Claims

1. A display device, the display device includes a main area having a display area and a bent area connected to one side of the main area and bent relative to the main area in the thickness direction of the display device, the display device includes: A substrate; A buffer layer, the buffer layer is located on the substrate; A first semiconductor layer, the first semiconductor layer is located on the buffer layer; A first gate insulating film, the first gate insulating film is located on the first semiconductor layer; A first gate conductive layer, the first gate conductive layer is located on the first gate insulating film; A first interlayer insulating film, the first interlayer insulating film is located on the first gate conductive layer; A second gate conductive layer, the second gate conductive layer is located on the first interlayer insulating film; A second interlayer insulating film, the second interlayer insulating film is located on the second gate conductive layer; A first data conductive layer, the first data conductive layer is located on the second interlayer insulating film; And A first via layer, the first via layer is located on the first data conductive layer, wherein The bent area includes: A bent peripheral opening, the bent peripheral opening penetrates the first interlayer insulating film and the first gate insulating film; And A bent opening, the bent opening is located in the bent peripheral opening and penetrates the second interlayer insulating film and the buffer layer to expose the substrate, A first side wall of the bent peripheral opening includes a side surface of the first interlayer insulating film and a side surface of the first gate insulating film, The second interlayer insulating film covers the first side wall of the bent peripheral opening, The bent opening includes a second side wall, the second side wall includes a side surface of the buffer layer and a part of a side surface of the second interlayer insulating film aligned with the side surface of the buffer layer, and The first via layer fills the bent opening.

2. The display device according to claim 1, wherein, The bent opening further includes: A third side wall, the third side wall is formed by other parts of the side surface of the second interlayer insulating film covering the first side wall; and A step portion, the step portion is located between the second side wall and the third side wall.

3. The display device according to claim 2, wherein, The step portion is formed by a partial upper surface of the second interlayer insulating film.

4. The display device according to claim 1, further includes: A second gate insulating film, the second gate insulating film is located on the first gate conductive layer; And A conductive layer of a capacitor, the conductive layer of the capacitor is located on the second gate insulating film, Wherein, the first side wall of the bent peripheral opening further includes a side surface of the second gate insulating film.

5. The display device according to claim 4, wherein, The first side wall further includes a partial side surface on the upper side of the buffer layer.

6. The display device according to claim 5, wherein, The thickness of the buffer layer in the area where the bent peripheral opening overlaps with the buffer layer is less than the thickness of the buffer layer in the area where the bent peripheral opening does not overlap with the buffer layer.

7. The display device according to claim 1, further includes: A barrier layer, the barrier layer is located on the substrate, Wherein, the barrier layer is located between the substrate and the buffer layer, and The second side wall of the bent opening further includes a side surface of the barrier layer.

8. The display device according to claim 1, further includes: A second semiconductor layer, the second semiconductor layer being located on the first interlayer insulating film; And A third gate insulating film, the third gate insulating film being located on the second semiconductor layer.

9. The display device according to claim 8, wherein, The third gate insulating film overlaps with the second gate conductive layer.

10. The display device according to claim 2, wherein, The second sidewall and the third sidewall are formed on the inner side of the first sidewall.

11. The display device according to claim 10, wherein, The distance by which the second sidewall protrudes from the first sidewall is greater than the distance by which the third sidewall protrudes from the first sidewall.

12. The display device according to claim 1, wherein, The distance by which the second sidewall protrudes from the first sidewall at one side of the bending region is different from the distance by which the second sidewall protrudes from the first sidewall at the other side of the bending region.

13. A display device, the display device including a main region having a display region and a bending region connected to one side of the main region and bent relative to the main region in the thickness direction of the display device, the display device including: A substrate; A first transistor, the first transistor including a non-oxide semiconductor located on the substrate; A second transistor, the second transistor including an oxide semiconductor in a layer different from the non-oxide semiconductor on the substrate; A capacitor, the capacitor being located on the substrate; A first inorganic film, the first inorganic film being located on the substrate; A second inorganic film, the second inorganic film being located on the first inorganic film and including a first sidewall; And A third inorganic film, the third inorganic film being located on the second inorganic film, the first sidewall, and a portion of the first inorganic film protruding from the second inorganic film, and source / drain electrodes of the first transistor being located on the third inorganic film, Wherein, the bending region includes: A bending peripheral opening defined by the first sidewall; and A bending opening defined by a second sidewall, a third sidewall, and a step portion connecting the second sidewall and the third sidewall, The second sidewall is formed by a side surface of the first inorganic film and a portion of a side surface of the third inorganic film on the portion of the first inorganic film protruding from the second inorganic film, The third sidewall is formed by other portions of an upper surface of the third inorganic film on the first sidewall, and A portion of the third inorganic film on the portion of the first inorganic film protruding from the second inorganic film is formed in the same layer as a semiconductor layer of the non-oxide semiconductor of the first transistor.

14. The display device according to claim 13, wherein, The bending opening is filled with an organic layer, and the organic layer is in direct contact with the substrate.

15. The display device according to claim 13, wherein, Either the first transistor or the second transistor is a p-type metal oxide semiconductor transistor, and the other is an n-type metal oxide semiconductor transistor.

16. A method of manufacturing a display device, wherein, The display device includes a first transistor having a channel, a second transistor having a channel, and a capacitor, wherein the channel of the first transistor and the channel of the second transistor are formed by different semiconductor layers, the method including: Forming a buffer layer on the substrate; Forming a first semiconductor pattern on the buffer layer, wherein the first semiconductor pattern is formed by a first semiconductor layer and includes a semiconductor pattern of the first transistor; Form a first gate insulating film on the first semiconductor layer; Form a first gate conductive layer on the first gate insulating film; Form a first interlayer insulating film on the first gate conductive layer; Form a second gate conductive layer on the first interlayer insulating film; Form a second interlayer insulating film on the second gate conductive layer; Form a first data conductive layer on the second interlayer insulating film; and Form a first via layer on the first data conductive layer, wherein, before the formation of the second gate conductive layer, the method further includes: Form a bent peripheral opening penetrating through the first interlayer insulating film and the first gate insulating film, before the formation of the first data conductive layer, the method further includes: Form a bent opening penetrating through the second interlayer insulating film and the buffer layer and exposing the substrate, a first sidewall of the bent peripheral opening includes a side surface of the first interlayer insulating film and a side surface of the first gate insulating film, the second interlayer insulating film covers the first sidewall of the bent peripheral opening, the bent opening includes a second sidewall, the second sidewall includes a side surface of the buffer layer and a portion of a side surface of the second interlayer insulating film aligned with the side surface of the buffer layer, and the first via layer fills the bent opening.

17. The method according to claim 16, wherein, The bent opening further includes: a third sidewall formed by other portions of the side surface of the second interlayer insulating film covering the first sidewall; and a step portion located between the second sidewall and the third sidewall.

18. The method according to claim 16, further including: Form a second gate insulating film on the first gate conductive layer; and Form a conductive layer of the capacitor on the second gate insulating film, wherein the first sidewall of the bent peripheral opening further includes a side surface of the second gate insulating film.

19. The method according to claim 16, further including: Form a second semiconductor layer on the first interlayer insulating film; and Form a third gate insulating film on the second semiconductor layer.

20. The method according to claim 19, wherein, The third gate insulating film overlaps with the second gate conductive layer.

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