Data transmission circuit and method, core, chip, electronic device and storage medium

Abstract

The present invention provides a data transmission circuit and method, core, chip, electronic device and storage medium. The data transmission circuit includes a receiving unit, a control unit, a register unit and a selection unit. The receiving unit is used to receive and parse the original data packet from Fabric, so as to send the original data in the original data packet to the selection unit and send the original control bit of the header of the original data packet to the control unit; the control unit is used to determine whether the original data in the original data packet needs to be relayed according to the original control bit; in response to the original data needing to be relayed, the control unit is used to control the first input end of the selection unit to be effective; the selection unit is used to send a new data packet to Fabric via the first input end, wherein the new data packet includes: the original data and the new header stored in the register unit. The power consumption of the data transmission circuit can be effectively reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip design, and specifically relates to a data transmission circuit, a data transmission method, a processor core, a multi-core structure chip, an electronic device and a computer-readable storage medium. Background Art

[0002] With the development of science and technology, human society is rapidly entering the intelligent era. An important feature of the intelligent era is that people obtain more and more types of data, the amount of data obtained is increasing, and the speed of processing data is getting higher and higher. Chips are the cornerstone of data processing, which fundamentally determines people's ability to process data. From the perspective of application fields, there are two main routes for chips: one is the general chip route, such as CPU, etc., which can provide great flexibility, but the effective computing power is relatively low when processing algorithms in specific fields; the other is the dedicated chip route, such as TPU, etc., which can play a higher effective computing power in certain specific fields, but in the face of flexible and changeable more general fields, their processing capabilities are relatively poor or even unable to process. Due to the wide variety and huge amount of data in the intelligent era, chips are required to have both extremely high flexibility, able to process algorithms in different fields and changing with each passing day, and extremely strong processing capabilities, able to quickly process huge and rapidly growing amounts of data.

[0003] In multi-core (many) core architecture chips, data or control information often needs to be transmitted between cores to complete single (multiple) tasks. Therefore, data transmission between cores becomes crucial and even becomes a key influencing factor in the computing power of multiple (many) cores.

[0004] Data transmission between cores can be carried out in a broadcasting manner. When a core receives a data packet through Fabric, it first determines whether the data packet is sent to the core. If so, the data packet is retained and stored in its own memory Mem; if not, the data packet is discarded and not stored in the memory Mem. In this way, when the source core needs to transmit data to the destination core, it needs to occupy Fabric to broadcast the data to all cores, which can easily cause data congestion, especially when data transmission is required between multiple cores. Data transmission becomes a serial processing method, which greatly reduces the utilization rate of Fabric; in addition, the broadcast method allows non-destination cores to receive data packets sent by the source core and make subsequent responses, which increases the burden and energy consumption of the circuit.

[0005] Data transmission between cores can also be carried out in the form of relay multicast. When the source core needs to send data to multiple cores, the source core first sends the data to one of the destination cores. After receiving the data packet, the core stores the data locally, and then checks whether the data packet needs to be sent to other cores. If so, the data packet is taken out from the memory, the destination address of the data packet is set to the address of another destination core, and the data is sent to the other destination core through Fabric; after the other destination core receives the data, the above process is repeated until it is no longer necessary to send it to other cores, and the data transmission process ends. In the case of data transmission between cores in the form of relay multicast, after receiving the data, the intermediate core needs to write the data into the memory Mem, and then take it out from the memory Mem and send it. This process requires the core's own memory Mem, affecting the access of its own program to the memory Mem and reducing the utilization rate of the memory Mem; in addition, the relay transfer of data requires the participation of a special control unit in the core to repack and send the data, which is a complicated process; and the whole process consumes a lot of power, has a long delay, and the waiting time of the subsequent destination core is long. Summary of the invention

[0006] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a data transmission circuit, a data transmission method, a processor core, a multi-core structure chip, an electronic device and a computer-readable storage medium.

[0007] A first aspect of the present invention provides a data transmission circuit, the data transmission circuit comprising a receiving unit, a control unit, a register unit and a selection unit; wherein:

[0008] The input end of the receiving unit is used to be connected to the output end of the Fabric, and the output end of the receiving unit is respectively connected to the input end of the control unit and the first input end of the selection unit;

[0009] The output end of the control unit is connected to the control end of the selection unit;

[0010] The receiving unit is used to receive and parse the original data packet from the Fabric, so as to send the original data in the original data packet to the selecting unit and send the original control bit of the header of the original data packet to the controlling unit;

[0011] The control unit is used to determine whether the original data in the original data packet needs to be relayed according to the original control bit;

[0012] In response to the original data needing to be relayed, the control unit is used to control the first input end of the selection unit to be effective; the selection unit is used to send a new data packet to the Fabric via the first input end, wherein the new data packet includes: the original data and a new packet header stored in the storage unit.

[0013] Optionally, the selecting unit is used to send the new data packet to the Fabric via the first input end, including:

[0014] The register unit is used to store the new packet header and send the new packet header to the selection unit;

[0015] The selection unit is used to send the new data packet to the Fabric via the first input end.

[0016] Optionally, the data transmission circuit further includes a merging unit;

[0017] The input end of the merging unit is connected to the output end of the register unit and the output end of the receiving unit respectively;

[0018] The control end of the merging unit is connected to the output end of the control unit;

[0019] The selection unit is used to send the new data packet to the Fabric via the first input end, including:

[0020] The register unit is used to store the new packet header and send the new packet header to the merging unit;

[0021] The merging unit is used for packaging the new packet header and the original data to form the new data packet, and sending the new data packet to the selecting unit;

[0022] The selection unit is used to send the new data packet to the Fabric via the first input end.

[0023] Optionally, the selection unit further includes a second input terminal, and the second input terminal is used to be connected to the storage unit;

[0024] In response to the original data not needing to be relayed, the control unit is further used to control the second input end of the selection unit to be valid; the selection unit is used to send the local data stored in the storage unit as a second data packet to the Fabric via the second input end.

[0025] Optionally, the selection unit includes a selection subunit and a sending subunit;

[0026] The input end of the sending subunit is connected to the output end of the selecting subunit;

[0027] The output end of the sending subunit is used to connect to the Fabric;

[0028] The sending subunit is used to send the data packet output from the selecting subunit to the Fabric.

[0029] Optionally, the sending subunit includes a control subunit and a level setting subunit corresponding to the control subunit, wherein:

[0030] The level setting subunit is used to set the sending levels of the new data packet and the second data packet;

[0031] The control subunit is used to send the new data packet and the second data packet according to the sending level.

[0032] Optionally, the control unit includes a judgment subunit and a transmission subunit; wherein the judgment subunit is used to judge whether the original data packet needs to be relayed according to the value of the original control bit, and if so, set its output value to 1, and if not, set its output value to 0;

[0033] The transmission subunit is used to transmit the output value of the judgment subunit to the selection unit; or, the transmission subunit is used to transmit the output value of the judgment subunit to the selection unit and the merging unit respectively.

[0034] Optionally, the data transmission circuit further includes a modification unit, and the modification unit is connected to the receiving unit; wherein,

[0035] The receiving unit is further used to receive a change request, wherein the change request carries a new packet header;

[0036] The changing unit is used to change the header of the original data packet received by the receiving unit according to the changing request.

[0037] Optionally, the data transmission circuit further includes:

[0038] The output end of the receiving unit is used to be connected to the storage unit and send the original data in the original data packet to the storage unit.

[0039] Optionally, the data transmission circuit further includes a positioning unit, and the register unit includes a plurality of registers, wherein:

[0040] The positioning unit is connected to the storage unit;

[0041] The positioning unit is used to locate a register among the multiple registers, and transmit the value of the register as a new packet header to the selection unit, or to the merging unit.

[0042] Optionally, the output end of the receiving unit is connected to the first input end of the selecting unit via the merging unit; the output end of the register unit is connected to the first input end of the selecting unit via the merging unit.

[0043] The second aspect of the present invention provides a processor core, comprising a storage unit and a data transmission circuit, wherein the data transmission circuit adopts the data transmission circuit provided by the first aspect of the present invention; wherein,

[0044] The output end of the receiving unit is connected to the input end of the storage unit, and the second input end of the selecting unit is connected to the output end of the storage unit.

[0045] The third aspect of the present invention provides a multi-core structure chip, including multiple processor cores and a Fabric that connects the processor cores to each other, at least one data transmission circuit provided by the first aspect of the present invention, or at least one processor core provided by the second aspect of the present invention.

[0046] A fourth aspect of the present invention provides a data transmission method, which specifically comprises the following steps:

[0047] Receive and parse the original data packet from Fabric, the header of the original data packet carrying the original control bit;

[0048] Determining whether the original data in the original data packet needs to be relayed according to the original control bit;

[0049] In response to the original data needing to be relayed, a new data packet is sent to the Fabric, wherein the new data packet includes: the original data and a new packet header stored in the storage unit.

[0050] Optionally, the step of sending the new data packet to the Fabric specifically includes:

[0051] Packing the new packet header and the original data into the new data packet;

[0052] Send the new data packet to the Fabric.

[0053] Optionally, the method further comprises:

[0054] In response to the original data not needing to be relayed, the local data stored in the storage unit is sent to the Fabric as a second data packet.

[0055] Optionally, the method further comprises:

[0056] Setting the sending levels of the new data packet and the second data packet;

[0057] The new data packet and the second data packet are transmitted according to the transmission level.

[0058] Optionally, the sending level includes that the sending level of the new data packet is higher than the sending level of the second data packet; or,

[0059] The transmission level includes alternately transmitting the new data packet and the second data packet.

[0060] Optionally, the step of determining whether the original data in the original data packet needs to be relayed according to the original control bit specifically includes:

[0061] It is determined whether the original data packet needs to be relayed according to the value of the original control bit. If so, its output value is set to 1; if not, its output value is set to 0.

[0062] Optionally, the method further comprises:

[0063] receiving a change request, wherein the change request carries a new packet header;

[0064] The header of the original data packet is modified according to the modification request.

[0065] A fifth aspect of the present invention provides an electronic device, comprising:

[0066] one or more processors;

[0067] A storage unit is used to store one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors can implement the data transmission method provided in the fourth aspect of the present invention.

[0068] A sixth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon.

[0069] When the computer program is executed by a processor, it can implement the data transmission method provided in the fourth aspect of the present invention.

[0070] The data transmission circuit provided by the present invention includes a receiving unit, a control unit, a register unit and a selection unit. After receiving a data packet, if relay transfer is required, the data does not need to be first stored in a storage unit and then taken out, which can reduce power consumption and storage unit utilization; the data relay transfer and sending the data to the storage unit are carried out in parallel, with less delay, reducing the waiting time for subsequent receivers to wait for data; the whole process is parsed by the local circuit of the data transmission circuit, and does not need to occupy the microcontroller of the core; by parsing the original control bit in the data packet to indicate whether the data needs relay transfer, it saves area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] Figure 1 It is a structural schematic diagram of a data transmission circuit according to a first embodiment of the present invention;

[0072] Figure 2 is a schematic structural diagram of a data transmission circuit according to a second embodiment of the present invention;

[0073] Figure 3 is a schematic structural diagram of a selection unit in a data transmission circuit according to a third embodiment of the present invention;

[0074] Figure 4 is a schematic structural diagram of a control unit in a data transmission circuit according to a fourth embodiment of the present invention;

[0075] Figure 5 A schematic diagram of a data transmission path according to a fifth embodiment of the present invention;

[0076] Figure 6 FIG. 6 is a flow chart of a data transmission method according to a sixth embodiment of the present invention. DETAILED DESCRIPTION

[0077] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0078] like Figure 1 As shown, a first aspect of an embodiment of the present invention provides a data transmission circuit TR, comprising a receiving unit Rx, a control unit Ctrl, a register unit Reg and a selection unit Sx. The input end of the receiving unit Rx is used to connect to the output end of Fabric, and the output end of the receiving unit Rx is respectively connected to the input end of the control unit Ctrl and the first input end In1 of the selection unit Sx. The output end of the control unit Ctrl is connected to the control end of the selection unit Sx.

[0079] The receiving unit Rx receives and parses the original data packet from Fabric. It should be noted that the original data packet received from Fabric in the embodiment of the present invention at least includes the following contents:

[0080] <![CDATA[C0]]> Addr_dest Data

[0081] Specifically, a data packet includes a header and data. The header includes the original control bit C0 and Addr_dest, and Data is the data. Among them, the original control bit C0 is used to indicate whether the data packet needs to be relayed. The original control bit C0 can be represented by a single bit binary or a multi-bit binary, which is set according to the actual application. It should be noted that Addr_dest is the destination address of the data packet, which can be the destination core address or the destination core address plus the destination storage address.

[0082] like Figure 1 As shown, the receiving unit Rx receives and parses the original data packet from Fabric, and sends the original data Data in the original data packet to the selection unit Sx, and sends the original control bit C0 of the header of the original data packet to the control unit Ctrl. The control unit Ctrl determines whether the original data Data in the original data packet needs to be relayed according to the original control bit C0, and the control unit Ctrl transmits the output value C1 to the control end of the selection unit Sx.

[0083] like Figure 1 As shown, the output end of the register unit Reg is connected to the first input end In1 of the selection unit Sx. The register unit Reg is used to store a new packet header, which includes a new control bit and the next destination address Addr_dest1 to which the original data Data needs to be relayed.

[0084] If the original control bit C0 indicates that the original data Data in the original data packet needs to be relayed, the control unit Ctrl controls the first input terminal In1 of the selection unit Sx to be valid. The register unit Reg sends the new packet header H stored thereon to the first input terminal In1 of the selection unit Sx, and the selection unit Sx sends the new packet consisting of the new packet header H and the original data Data to the Fabric via the first input terminal In1.

[0085] In the data transmission circuit TR of the embodiment of the present invention, after receiving the original data packet, the receiving unit Rx directly sends the original data Data to the first input terminal In1 of the selection unit Sx, and determines whether the original data Data in the original data packet needs to be relayed according to the original control bit C0 in the received original data packet. In response to the original data Data needing to be relayed, the register unit Reg sends the new packet header H to the first input terminal In1 of the selection unit Sx, and the control unit Ctrl selects the first input terminal In1 of the selection unit Sx to be valid, and sends the new data packet to the Fabric via the first input terminal In1.

[0086] The data transmission circuit TR of the present embodiment responds to the process of relaying data transmission, and there is no need to store the original data Data into the storage unit Memory of the core first and then retrieve it from the storage unit Memory of the core, which can reduce power consumption; the entire data relay transfer process is analyzed by the local circuit of the data transmission circuit TR, and there is no need to occupy the microcontroller MCR (Microcontroller Unit) of the core; and the data transmission circuit TR in the present embodiment can save area and power consumption by analyzing the original control bit C0 in the data packet to indicate whether the data needs to be relayed.

[0087] Optional, such as Figure 2 As shown, the data transmission circuit TR of the embodiment of the present invention further includes a merging unit Merge. The input end of the merging unit Merge is respectively connected to the output end of the register unit Reg and the output end of the receiving unit Rx. The control end of the merging unit Merge is connected to the output end of the control unit Ctrl.

[0088] Since the merging unit Merge is added, it can be understood that the output end of the receiving unit Rx is connected to the first input end In1 of the selecting unit Sx via the merging unit Merge; the output end of the register unit Reg is connected to the first input end In1 of the selecting unit Sx via the merging unit Merge.

[0089] It should be noted that there is no limitation on the specific structure of the merging unit Merge. For example, the merging unit Merge may be a simple splicing circuit that splices together the pure data Data and the new packet header H stored in the register unit Reg.

[0090] It can be understood that the following description of the data transmission circuit TR including the merging unit Merge is also applicable to the aforementioned case without the merging unit Merge, and the difference between the two is the location of packaging the original data Data and the new packet header H. The data transmission circuit TR without the merging unit Merge packages and splices the original data Data and the new packet header H in the selection unit Sx, and the data transmission circuit TR including the merging unit Merge packages and splices the original data Data and the new packet header H in the merging unit Merge. Those skilled in the art can understand that other descriptions are applicable to both optional embodiments.

[0091] In the data transmission circuit TR of the embodiment of the present invention, in response to the original data Data needing to be relayed, the register unit Reg sends the new packet header H to the merging unit Merge, and the merging unit Merge packages the new packet header H and the original data Data into a new data packet and sends it to the selection unit Sx. The selection unit Sx sends the new data packet to Fabric via the first input terminal In1.

[0092] Specifically, after receiving the original data packet from Fabric, the receiving unit Rx parses the original data packet, sends the original data Data in the original data packet to the merging unit Merge, and sends the original control bit C0 of the data packet header to the control unit Ctrl. The control unit Ctrl determines whether the original data Data needs to be relayed according to the original control bit C0, transmits the output value C1 to the merging unit Merge, turns on the merging function of the merging unit Merge, and the control unit Ctrl simultaneously transmits the output value C1 to the selection unit Sx, and controls the first input terminal In1 of the selection unit Sx to be effective. The merging unit Merge takes out the data H in the register unit Reg, splices it with the original data Data to form a new data packet, and sends the new data packet to the first input terminal In1 of the selection unit Sx. The selection unit Sx sends the new data packet to Fabric via the first input terminal In1.

[0093] In the above relay process, if the data received by the receiving unit Rx does not need to be relayed, the control unit Ctrl can control the merging unit Merge to turn off the packing function to save power. Of course, the merging unit Merge packing function can also be selected to be not turned off, which is set according to application requirements.

[0094] When the data transmission circuit TR of the embodiment of the present invention responds to the relay transfer of data, the control unit Ctrl determines whether the original data Data needs to be relayed according to the original control bit C0, and then transmits the output value C1 to the merging unit Merge and the selection unit Sx at the same time. The register unit Reg stores a new packet header H. After the merging function of the merging unit Merge is turned on, the data H in the register unit Reg is taken out and spliced ​​with the original data Data to form a new data packet. At this time, the first input terminal In1 of the selection unit Sx is an effective input terminal, and the selection unit Sx sends the new data packet to the Fabric via the first input terminal In1. The data relay transfer process is carried out in parallel with a short delay, which can greatly reduce the time for subsequent data receivers to wait for data.

[0095] Optional, such as Figure 1 and Figure 2 As shown, the selection unit Sx of the data transmission circuit TR in the embodiment of the present invention further includes a second input terminal In0 , and the second input terminal In0 is connected to the storage unit Memory.

[0096] In response to the original data packet not needing relay, the control unit Ctrl controls the second input terminal In0 of the selection unit Sx to be valid. At this time, the selection unit Sx sends the local data stored in the storage unit Memory as the second data packet to the Fabric via the second input terminal In0.

[0097] Optionally, the control unit Ctrl controls the second input terminal In0 of the selection unit Sx to be valid, which only means that the second input terminal In0 is connected to the storage unit Memory, but at this time, the selection unit Sx can choose not to output, and of course can also send signals such as ending relay transmission to the inter-core interconnection structure.

[0098] It should be noted that when the core Core where the data transmission circuit TR is located is used as the source core (i.e., the data sending core), the control unit Ctrl sends the control signal C1 to the control end of the selection unit Sx, controls the second input end In0 of the selection unit Sx to be valid, and then, the data stored in the storage unit Memory is sent to Fabric via the second input end In0 of the selection unit Sx, and then sent to the target core by Fabric.

[0099] The data transmission circuit TR of the embodiment of the present invention can ensure the external transmission of local data when there is no need for relay transmission of response data; in addition, when the data transmission circuit TR is in relay transmission of response data, the data Data does not need to be first stored in the storage unit Memory and then taken out, thereby reducing power consumption, and does not need to occupy the storage unit Memory due to reading the storage unit Memory, thereby reducing the consumption of the storage unit Memory.

[0100] Optional, such as Figure 3 As shown, the selection unit Sx of the data transmission circuit TR of the embodiment of the present invention includes a selection subunit S and a sending subunit Tx. Among them, the input end of the sending subunit Tx is connected to the output end of the selection subunit S, and the output end of the sending subunit Tx is connected to the Fabric. The sending subunit Tx is used to send the data packet output from the selection subunit S to the Fabric. By setting the selection subunit S and the sending subunit Tx, the selection unit S can selectively enable the first input terminal In1 or the second input terminal In0 according to the output value C1 of the control unit Ctrl, and then select to transmit a new data packet or a second data packet to the Fabric, thereby increasing the data transmission flexibility of the data transmission circuit TR.

[0101] Optional, such as Figure 3As shown, the sending subunit Tx includes a control subunit Tx_1 and a level setting subunit Tx_2 corresponding to the control subunit Tx_1, wherein the level setting subunit Tx_2 is used to set the sending levels of the new data packet and the second data packet. The control subunit Tx_1 is used to send the new data packet and the second data packet according to the sending level. For example, the sending level of the new data packet can be set to be higher than the sending level of the second data packet. When the data transmission circuit TR transmits local data, if a new data packet that needs to be relayed needs to be sent, the new data packet is sent first. The sending level of the new data packet can also be set to be equal to the sending level of the second data packet, that is, when the data transmission circuit TR transmits local data, if a new data packet that needs to be relayed needs to be sent, the sending right is evenly distributed, and the new data packet that needs to be relayed and the local data are sent in turn.

[0102] By setting the sending level for the new data packet and the second data packet, when the data transmission circuit TR sends local data, if it needs to send a data packet that needs to be relayed, different processing strategies can be adopted according to specific application requirements, thereby improving the system resource utilization and system performance of the core.

[0103] Optional, such as Figure 4 As shown, the control unit Ctrl includes a judgment subunit Ctrl_1 and a transmission subunit Ctrl_2. The judgment subunit Ctrl_1 is used to judge whether the original data packet needs to be relayed according to the value of the original control bit C0. If yes, its output value C1 is set to 1, and if no, its output value C1 is set to 0. The transmission subunit Ctrl_2 is used to transmit the output value C1 of the judgment subunit Ctrl_1 to the selection unit Sx; or the transmission subunit Ctrl_2 is used to transmit the output value C1 of the judgment subunit Ctrl_1 to the selection unit Sx and the merging unit Merge respectively.

[0104] Optionally, the data transmission circuit TR further includes a modification unit (not shown in the figure), which is connected to the receiving unit Rx. The receiving unit Rx is further used to receive a modification request, which carries a new packet header. The modification unit is used to modify the packet header of the original data packet received by the receiving unit Rx according to the modification request.

[0105] Specifically, Figure 5 As shown, for example, core C1 needs to send multicast data to core C2 and core C3, and plans to first send data to core C2, and then core C2 relays the data to core C3. When the data packet arrives at core C2, the register unit Reg of core C2 is configured with new packet header information, that is, the original control bit C0 is a value indicating that relaying is not required, for example, it can be configured as C0 = '0', and the destination address is core C3, that is, when core C3 receives the data, it no longer needs to relay.

[0106] When the data packet arrives at core C2, it is necessary to transmit the data to core C4 at this time, and it is planned that core C2 first transmits the data to core C4, and then core C4 relays the data to core C3. At this time, the change unit of the receiving unit Rx receives a change request, which includes modifying the value of the original control bit C0 to C0='1', and modifying the destination address in the new packet header to core C4, that is, core C2 relays the data to core C4, and core C4 needs to relay the data after receiving the data. The data transmission circuit TR of this embodiment can modify the relay transmission path of the data as needed to achieve flexible configuration of the destination address.

[0107] Optionally, the output end of the receiving unit Rx of the data transmission circuit TR can also be connected to the storage unit Memory, and the original data Data in the original data packet is sent to the storage unit Memory. After receiving the original data packet, the receiving unit Rx parses the original data packet and directly sends the original data Data in the original data packet to the storage unit Memory of the core, so as to reduce the waiting time of the core for the original data Data.

[0108] Optionally, the data transmission circuit TR further includes a positioning unit (not shown in the figure), and the register unit Reg includes a plurality of registers. The positioning unit is connected to the register unit Reg. The positioning unit is used to locate a register among the plurality of registers, and transmit the value of a register as a new packet header to the selection unit Sx or to the merging unit Merge. By using a plurality of registers to pre-store a plurality of transfer destination addresses in the data transmission path, and accurately configuring a new packet header to the register unit Reg through the positioning unit, the response speed of the data transmission circuit TR in processing data transfer can be accelerated.

[0109] A second aspect of this embodiment provides a processor core, such as Figure 1 and Figure 2 As shown, the processor core Core includes a storage unit Memory and a data transmission circuit TR. The specific structure of the data transmission circuit TR is described above and will not be repeated here. The output end of the receiving unit Rx is connected to the input end of the storage unit Memory, and the second input end of the selection unit Sx is connected to the output end of the storage unit Memory.

[0110] The third aspect of this embodiment provides a multi-core structure chip, which includes multiple processor cores and a Fabric that connects the cores to each other, wherein at least one processor core is the data transmission circuit TR described above, or at least one processor core adopts the processor core provided by the second aspect of this embodiment.

[0111] like Figure 6As shown, the fourth aspect of this embodiment provides a data transmission method S100, which specifically includes the following steps:

[0112] Step S110, receiving and parsing the original data packet from Fabric, the header of the original data packet carrying the original control bit;

[0113] Step S120, determining whether the original data in the original data packet needs to be relayed according to the original control bit;

[0114] Step S130: In response to the original data needing to be relayed, a new data packet is sent to the Fabric, wherein the new data packet includes: the original data and a new packet header stored in the storage unit.

[0115] The data transmission method provided by the embodiment of the present invention does not need to send the original data to the storage unit of the current core and then take it out when responding to the relay transmission of data, which can reduce power consumption, reduce the utilization rate of the storage unit, and greatly reduce the time for subsequent data receivers to wait for the original data; the entire data relay process is analyzed by the local circuit and does not need to occupy the microcontroller MCR (Microcontroller Unit) of the current core.

[0116] Optionally, the step of sending the new data packet to the Fabric specifically includes: packing the new packet header and the original data to form a new data packet, and then sending the new data packet to the Fabric.

[0117] Optionally, the data transmission method further includes step S140, in response to the original data packet not needing relay transfer, sending the local data stored in the storage unit as a second data packet to the Fabric, so that when the relay transmission of the response data is not required, the local data is guaranteed to be sent externally.

[0118] Optionally, the data transmission method further includes: setting a sending level of the new data packet and the second data packet, and sending the new data packet and the second data packet according to the sending levels.

[0119] Optionally, the sending level includes that the sending level of the new data packet is higher than the sending level of the second data packet, or the sending level includes alternately sending the new data packet and the second data packet.

[0120] By setting the sending level for the new data packet and the second data packet, when the data transmission circuit TR sends local data, if it needs to send a data packet that needs to be relayed, different processing strategies can be adopted according to specific application requirements to improve the core system resource utilization and system performance.

[0121] Optionally, the step of determining whether the original data in the original data packet needs to be relayed according to the original control bit specifically includes: judging whether the original data packet needs to be relayed according to the value of the original control bit, if so, setting its output value to 1, if not, setting its output value to 0.

[0122] Optionally, the data transmission method further includes: receiving a change request, the change request carrying a new header, and changing the header of the original data packet according to the change request. The data transmission method provided by the embodiment of the present invention can modify the relay transmission path of the data packet as needed to achieve flexible configuration of the destination address.

[0123] A fifth aspect of this embodiment provides an electronic device, including:

[0124] one or more processors;

[0125] A storage unit is used to store one or more programs. When the one or more programs are executed by one or more processors, the one or more processors can implement the data transmission method provided in the fourth aspect of this embodiment. The specific content of the data transmission method is as recorded above and will not be repeated here.

[0126] A sixth aspect of this embodiment provides a computer-readable storage medium having a computer program stored thereon.

[0127] When the computer program is executed by the processor, it can implement the data transmission method provided according to the fourth aspect of this embodiment. The specific content of the data transmission method is as recorded above and will not be repeated here.

[0128] The computer-readable medium may be included in the apparatus, device, or system of the present invention, or may exist independently.

[0129] Among them, computer readable storage media can be any tangible media that contains or stores a program, which can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment. More specific examples include, but are not limited to: a portable computer disk, hard disk, optical fiber, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0130] The computer-readable storage medium may also include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code, specific examples of which include but are not limited to electromagnetic signals, optical signals, or any suitable combination thereof.

[0131] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A data transmission circuit, characterized in that: The data transmission circuit includes a receiving unit, a control unit, a storage unit and a selection unit; wherein, The input end of the receiving unit is used to be connected to the output end of the Fabric, and the output end of the receiving unit is respectively connected to the input end of the control unit and the first input end of the selection unit; The output end of the control unit is connected to the control end of the selection unit; The receiving unit is used to receive and parse the original data packet from the Fabric, so as to send the original data in the original data packet to the selecting unit and send the original control bit of the header of the original data packet to the controlling unit; The control unit is used to determine whether the original data in the original data packet needs to be relayed according to the original control bit; In response to the original data needing to be relayed, the control unit is used to control the first input end of the selection unit to be valid, thereby causing the selection unit to send a new data packet to the Fabric, wherein the new data packet includes: the original data and a new packet header stored in the storage unit.

2. The data transmission circuit according to claim 1, characterized in that: The selection unit sends the new data packet to the Fabric, including: The storage unit is used to store the new packet header and send the new packet header to the selection unit; The selection unit is used to send the new data packet to the Fabric.

3. The data transmission circuit according to claim 1 or 2, characterized in that: The selection unit further includes a second input terminal, wherein the second input terminal is used to be connected to the storage unit; In response to the original data not needing to be relayed, the control unit is further used to control the second input end of the selection unit to be valid, thereby causing the selection unit to send the local data stored in the storage unit as a second data packet to the Fabric.

4. The data transmission circuit according to claim 3, characterized in that: The selection unit includes a selection subunit and a sending subunit; The input end of the sending subunit is connected to the output end of the selecting subunit; The output end of the sending subunit is used to connect to the Fabric; The sending subunit is used to send the data packet output from the selecting subunit to the Fabric.

5. The data transmission circuit according to claim 4, characterized in that: The sending subunit includes a control subunit and a level setting subunit corresponding to the control subunit, wherein: The level setting subunit is used to set the sending levels of the new data packet and the second data packet; The control subunit is used to send the new data packet and the second data packet according to the sending level.

6. The data transmission circuit according to claim 1 or 2, characterized in that: The data transmission circuit further includes a modification unit, which is connected to the receiving unit; wherein, The receiving unit is further used to receive a change request, wherein the change request carries a new packet header; The changing unit is used to change the header of the original data packet received by the receiving unit according to the changing request.

7. The data transmission circuit according to claim 3, characterized in that: Also includes: The output end of the receiving unit is used to be connected to the storage unit and send the original data in the original data packet to the storage unit.

8. The data transmission circuit according to claim 1, characterized in that: The control unit includes a judgment subunit and a transmission subunit; wherein, The judging subunit is used to judge whether the original data packet needs relay transfer according to the value of the original control bit, and if so, set its output value to 1, and if not, set its output value to 0; The transmission subunit is used to transmit the output value of the determination subunit to the selection unit.

9. The data transmission circuit according to claim 1, characterized in that: The data transmission circuit further includes a positioning unit, and the register unit includes a plurality of registers, wherein: The positioning unit is connected to the storage unit; The positioning unit is used for positioning a register among the multiple registers, and transmitting the value of the register as a new packet header to the selection unit.

10. A data transmission circuit, characterized in that: The data transmission circuit includes a receiving unit, a control unit, a storage unit and a selection unit; wherein, The input end of the receiving unit is used to be connected to the output end of the Fabric, and the output end of the receiving unit is respectively connected to the input end of the control unit and the first input end of the selection unit; The output end of the control unit is connected to the control end of the selection unit; The receiving unit is used to receive and parse the original data packet from the Fabric, so as to send the original data in the original data packet to the selecting unit and send the original control bit of the header of the original data packet to the controlling unit; The control unit is used to determine whether the original data in the original data packet needs to be relayed according to the original control bit; In response to the original data needing to be relayed, the control unit is used to control the first input end of the selection unit to be effective, so that the selection unit sends a new data packet to the Fabric, wherein the new data packet includes: the original data and a new packet header stored in the storage unit; The data transmission circuit also includes a merging unit; The input end of the merging unit is connected to the output end of the register unit and the output end of the receiving unit respectively; The control end of the merging unit is connected to the output end of the control unit; The selection unit sends the new data packet to the Fabric, including: The storage unit is used to store the new packet header and send the new packet header to the merging unit; The merging unit is used for packaging the new packet header and the original data to form the new data packet, and sending the new data packet to the selecting unit; The selection unit is used to send the new data packet to the Fabric.

11. The data transmission circuit according to claim 10, characterized in that: The selection unit further includes a second input terminal, wherein the second input terminal is used to be connected to the storage unit; In response to the original data not needing to be relayed, the control unit is further used to control the second input end of the selection unit to be valid, thereby causing the selection unit to send the local data stored in the storage unit as a second data packet to the Fabric.

12. The data transmission circuit according to claim 11, characterized in that: The selection unit includes a selection subunit and a sending subunit; The input end of the sending subunit is connected to the output end of the selecting subunit; The output end of the sending subunit is used to connect to the Fabric; The sending subunit is used to send the data packet output from the selecting subunit to the Fabric.

13. The data transmission circuit according to claim 12, characterized in that: The sending subunit includes a control subunit and a level setting subunit corresponding to the control subunit, wherein: The level setting subunit is used to set the sending levels of the new data packet and the second data packet; The control subunit is used to send the new data packet and the second data packet according to the sending level.

14. The data transmission circuit according to claim 10, characterized in that: The data transmission circuit further includes a modification unit, which is connected to the receiving unit; wherein, The receiving unit is further used to receive a change request, wherein the change request carries a new packet header; The changing unit is used to change the header of the original data packet received by the receiving unit according to the changing request.

15. The data transmission circuit according to claim 11, characterized in that: Also includes: The output end of the receiving unit is used to be connected to the storage unit and send the original data in the original data packet to the storage unit.

16. The data transmission circuit according to claim 10, characterized in that: The control unit includes a judgment subunit and a transmission subunit; wherein, The judging subunit is used to judge whether the original data packet needs relay transfer according to the value of the original control bit, and if so, set its output value to 1, and if not, set its output value to 0; The transmission subunit is used to transmit the output value of the determination subunit to the selection unit and the merging unit respectively.

17. The data transmission circuit according to claim 10, characterized in that: The data transmission circuit further includes a positioning unit, and the register unit includes a plurality of registers, wherein: The positioning unit is connected to the storage unit; The positioning unit is used to locate a register among the multiple registers, and transmit the value of the register as a new packet header to the merging unit.

18. A processor core, characterized in that: It comprises a storage unit and a data transmission circuit, wherein the data transmission circuit adopts the data transmission circuit according to any one of claims 1 to 17; wherein, The output end of the receiving unit is connected to the input end of the storage unit, and the second input end of the selecting unit is connected to the output end of the storage unit.

19. A multi-core chip, comprising a plurality of processor cores and a fabric interconnecting the processor cores, characterized in that: At least one of the processor cores includes the data transmission circuit described in any one of claims 1 to 17, or at least one of the processor cores is the processor core described in claim 18.

20. A data transmission method, characterized in that: The data transmission circuit according to any one of claims 1 to 17 specifically comprises the following steps: Receive and parse the original data packet from Fabric, the header of the original data packet carrying the original control bit; Determining whether the original data in the original data packet needs to be relayed according to the original control bit; In response to the original data needing to be relayed, a new data packet is sent to the Fabric, wherein the new data packet includes: the original data and a new packet header stored in the storage unit.

21. An electronic device, characterized in that: include: one or more processors; A storage unit, used to store one or more programs, which, when executed by the one or more processors, enable the one or more processors to implement the data transmission method according to claim 20.

22. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, it can implement the data transmission method according to claim 20.

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