Chips and electronic devices

Abstract

The present disclosure provides a chip and an electronic device. The chip includes a storage module, a pin, a control module, a first connection and a second connection. The storage module includes a first storage array group and a second storage array group, and the first storage array group and the second storage array group respectively include a plurality of storage arrays; the pin is located on the side of the first storage array group away from the second storage array group; the control module is located between the first storage array group and the second storage array group; the first connection connects the pin and the control module; and the second connection connects the control module and the first storage array group and the second storage array group; wherein the length of the first connection is less than the length from the control module to the side of the second storage array group away from the control module. The chip disclosed in the present disclosure reduces the parasitic capacitance introduced by the first connection.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a chip and an electronic device comprising the chip. Background Art

[0002] Under the condition of meeting the existing packaging requirements, achieving high-speed and low-power chip layout is a very important link in DRAM (Dynamic Random Access Memory) design. The packaging of some existing DRAM chips requires that the chip pins are on one side of the chip, usually on the short side of the chip. Such a chip layout has an adverse effect on the performance of the chip. Instructions need to enter from one side of the chip pins, and after decoding, they are transmitted to one side of the chip storage array to operate the storage array. The data obtained from the storage array needs to be transmitted from the storage array side of the chip across the entire chip to the side where the pins are located. This results in a slower chip operation speed, and due to the long-distance transmission of large amounts of data, the chip power consumption is also relatively large.

[0003] In order to solve the above problems, the designer introduced a layer of top-level wiring. The transmission speed of this layer of wiring is faster. Through the introduction of this layer of wiring, the pin-related circuits and control circuits of the chip can be set to the middle of the chip, and then the pin-related circuits and control circuits can be connected to the external pins through the introduced fast wiring. This layout allows the instructions entering through the pins to quickly reach the middle of the chip, and the data returned from the storage array only needs to be transmitted to the pin-related circuits and control circuits in the middle of the chip, and then the data is transmitted to the external pins of the chip through the introduced top-level wiring. This chip layout has obvious improvements on transmission speed, chip power consumption, and power distribution inside the chip. However, as the chip capacity increases, the length of the top-level wiring increases, resulting in the additional parasitic capacitance introduced to have a greater impact on the transmission of high-speed signals, and even cause eye diagram closure.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The present disclosure provides a chip and an electronic device, thereby overcoming or improving the problem of large parasitic capacitance of top-layer wiring or low transmission speed in the prior art at least to a certain extent.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to a first aspect of the present disclosure, a chip is provided, including:

[0008] A storage module, comprising a first storage array group and a second storage array group, wherein the first storage array group and the second storage array group respectively comprise a plurality of storage arrays;

[0009] A pin located at a side of the first storage array group away from the second storage array group;

[0010] A control module, located between the first storage array group and the second storage array group;

[0011] A first connection line connecting the pin and the control module; and

[0012] A second connection line connects the control module with the first storage array group and the second storage array group;

[0013] The length of the first connection line is shorter than the length from the control module to the second storage array group away from the control module.

[0014] In one embodiment, the control module includes a control circuit and a pin circuit.

[0015] In one embodiment, the first connection includes an instruction address connection and a data connection, and the second connection includes an instruction address bus and a data bus.

[0016] In one embodiment, the ratio of the number of storage arrays included in the first storage array group to the number of storage arrays included in the second storage array group is 1 / 5 to 1 / 3.

[0017] In one embodiment, the ratio of the number of storage arrays included in the first storage array group to the number of storage arrays included in the second storage array group is 1 / 3.

[0018] In one embodiment, the ratio of the number of storage arrays included in the first storage array group to the number of storage arrays included in the second storage array group is 1 / 5.

[0019] In one embodiment, the ratio of the number of storage arrays included in the first storage array group to the number of storage arrays included in the second storage array group is 1 / 2.

[0020] In one embodiment, the control module is located in the middle of two adjacent side surfaces of the first storage array group and the second storage array group.

[0021] In one embodiment, the storage module further includes a third storage array group, the third storage array group includes a plurality of storage arrays, and the control module includes a third side and a fourth side;

[0022] The storage array included in the third storage array group is located on the third side surface or the fourth side surface of the control module.

[0023] In one embodiment, the storage module further includes a third storage array group, the third storage array group includes a plurality of storage arrays, and the control module includes a third side and a fourth side;

[0024] The storage arrays included in the third storage array group are respectively located on the third side surface and the fourth side surface of the control module.

[0025] In one embodiment, the first connection line is a top-level connection line and communicatively connects the pin and the control module.

[0026] In one embodiment, the storage module is rectangular, and the pins are located on one side of one of two short sides of the rectangle.

[0027] According to a second aspect of the present disclosure, an electronic device is provided, comprising the chip according to any one of the above embodiments.

[0028] The present disclosure has the following beneficial effects:

[0029] The present disclosure reduces the parasitic capacitance introduced by the top-level wiring by improving the layout of the control circuit and the pin circuit, reduces the adverse effect of the parasitic capacitance on the chip, and improves the operating speed of the chip to a certain extent.

[0030] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0032] Figure 1 It is a schematic diagram of the structural layout of a chip of the related technology;

[0033] Figure 2 It is a schematic diagram of the structural layout of a chip of the related technology;

[0034] Figure 3 is a schematic diagram of the structural layout of a chip according to an embodiment of the present disclosure;

[0035] Figure 4 is a schematic diagram of the structural layout of a chip according to an embodiment of the present disclosure;

[0036] Figure 5 is a schematic diagram of the structural layout of a chip according to an embodiment of the present disclosure;

[0037] Figure 6 is a schematic diagram of the structural layout of a chip according to an embodiment of the present disclosure;

[0038] Figure 7 It is a schematic diagram of the structural layout of a chip according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0040] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.

[0041] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0042] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0043] It should be understood that although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Therefore, the first component discussed below can be referred to as the second component without departing from the teachings of the disclosed concepts. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more.

[0044] Those skilled in the art will appreciate that the drawings are merely schematic diagrams of example embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing the present disclosure, and therefore cannot be used to limit the protection scope of the present disclosure.

[0045] Figure 1 Schematic diagram of the structural layout of a chip 100 in the related art.

[0046] like Figure 1 As shown, the chip 100 of the related technology includes a storage module (including multiple storage arrays 101), a pin 102, a control module 103 (control circuit and pin circuit) and a second connection (instruction address bus 104 and data bus 105). Among them, the pin 102 is communicatively connected with the control circuit and the pin circuit 103, and this connection belongs to the well-known technology in the art and will not be repeated here. The control circuit and the pin circuit 103 are communicatively connected with the multiple storage arrays 101 through the instruction address bus 104 and the data bus 105, and the connection between the control circuit and the pin circuit 103 and the instruction address bus 104 and the data bus 105 and the connection between the instruction address bus 104 and the data bus 105 and the multiple storage arrays 101 belong to the well-known technology in the art and will not be repeated here. Among them, the instruction address bus 104 is in Figure 1 In other embodiments, the instruction address bus 104 may be two separate lines (instruction bus and address bus). Figure 1 The instruction address bus 104 and the data bus 105 are shown as two separate lines, but in other embodiments the instruction address bus 104 and the data bus 105 may be one line.

[0047] refer to Figure 1 When the pin 102 receives the operation instruction, after the control circuit and the pin circuit 103 decode and other operations, the instruction is transmitted to one side of the multiple storage arrays 101 through the instruction address bus 104, so as to operate the multiple storage arrays 101. After the instruction is transmitted to the multiple storage arrays 101 through the instruction address bus 104, the data obtained from the multiple storage arrays 101 needs to be transmitted to the control circuit and the pin circuit 103 through the data bus 105, and then the data is transmitted through the pin 102.

[0048] Figure 1 The layout of the chips in the chip makes the reading and storage speed of the chip slower and the power consumption higher due to the long-distance transmission of instructions and data.

[0049] Figure 2 FIG. 2 is a schematic diagram of the structural layout of a chip 200 in the related art.

[0050] like Figure 2As shown, the chip 200 of the related art includes a storage module (including multiple storage arrays 201), a pin 202, a control module 203 (control circuit and pin circuit), a second connection (an instruction address bus 204 and a data bus 205) and a first connection (an instruction address connection 206 and a data connection 207). Among them, the instruction address connection 206 and the data connection 207 have parasitic capacitance, which is caused by the wiring of the instruction address connection 206 and the data connection 207 on the oxide layer. Figure 2 Capacitors are used to indicate that the instruction address line 206 and the data line 207 cause parasitic capacitance.

[0051] refer to Figure 2 , pin 202 is connected to control circuit and pin circuit 203 through instruction address connection 206 and data connection 207, which is a well-known technology in the art and will not be described in detail here. Control circuit and pin circuit 203 are connected to multiple storage arrays 201 through instruction address bus 204 and data bus 205, wherein the connection between control circuit and pin circuit 203 and instruction address bus 204 and data bus 205 and the connection between instruction address bus 204 and data bus 205 and multiple storage arrays 201 are well-known technologies in the art and will not be described in detail here. Figure 2 In the example shown as one line, the instruction address bus 204 may be two separate lines in other embodiments. Figure 2 In the embodiment, the instruction address bus 204 and the data bus 205 are shown as two separate lines, but in other embodiments, the instruction address bus 204 and the data bus 205 can be one line.

[0052] refer to Figure 2 , multiple storage arrays 201 are arranged on both sides of the control circuit and pin circuit 203, and the number of storage arrays 201 arranged on both sides of the control circuit and pin circuit 203 is equal (4 in number). The control circuit and pin circuit 203 and the pin 202 are connected to each other through the instruction address connection 206 and the data connection 207, wherein the instruction address connection 206 and the data connection 207 are both top-layer connections of the chip, and the top-layer connection is arranged on the top layer of the chip, so the width and thickness of the top-layer connection are relatively large relative to other metal layers of the chip, and the large width and thickness make the resistance of the top-layer connection relatively low, so the top-layer connection has a faster transmission speed and lower power loss, so that high-speed data transmission between the control circuit and pin circuit 203 and the pin 202 can be realized.

[0053] Also refer to Figure 2When the pin 202 receives the operation instruction, it transmits the instruction to the control circuit and the pin circuit 203 through the instruction address connection 206. After the control circuit and the pin circuit 203 decode and other operations, the instruction is transmitted to the multiple storage arrays 201 through the instruction address bus 204 to operate the multiple storage arrays 201. After the instruction is transmitted to the multiple storage arrays 101 through the instruction address bus 204, the data obtained from the multiple storage arrays 201 is transmitted to the control circuit and the pin circuit 203 through the data bus 205, and then the data is transmitted to the pin 202 through the data connection 207, so that the data is transmitted.

[0054] Figure 2 In the layout of the chip 200 in the embodiment, the control circuit and pin circuit 203 is arranged in the middle of a plurality of storage arrays 201 (the number of storage arrays 201 arranged on both sides of the control circuit and pin circuit 203 is equal), and the control circuit and pin circuit 203 is connected to the pin 201 through the instruction address connection 206 and the data connection 207. Because the control circuit and pin circuit 203 is arranged in the middle of a plurality of storage arrays 201, the speed of the control circuit and pin circuit 203 sending instructions to the storage array 201 and obtaining data from the storage array 201 is greatly improved, so that the reading and storage speed of the chip 200 is improved, and the power consumption is also low. However, due to the introduction of the instruction address connection 206 and the data connection 207 between the control circuit and pin circuit 203 and the pin 201, the chip 200 is additionally introduced with parasitic capacitance, which has an adverse effect on the signal and data transmission of the chip, and even causes the eye diagram to be closed.

[0055] Figure 3 Schematic diagram of the structural layout of a chip 300 according to an embodiment of the present disclosure.

[0056] like Figure 3 As shown, the chip 300 of the present disclosure includes a storage module (including a first storage array group 1000 and a second storage array group 2000, wherein the first storage array group 1000 and the second storage array group 2000 respectively include a plurality of storage arrays 301), a pin 302, a control module 303 (control circuit and pin circuit), a second connection (an instruction address bus 304 and a data bus 305) and a first connection (an instruction address connection 306 and a data connection 307). The instruction address connection 306 and the data connection 307 have parasitic capacitance. Figure 3 In the illustrated embodiment, the first storage array group 1000 includes two storage arrays 301, and the second storage array group 2000 includes six storage arrays, but the present invention is not limited thereto. The first storage array group 1000 may include storage arrays 301 other than two, and the second storage array group 2000 may include storage arrays other than six.

[0057] refer to Figure 3 The ratio of the number of storage arrays 201 included in the first storage array group 1000 and the number of storage arrays 201 included in the second storage array group 2000 is 1 / 3.

[0058] In one embodiment, the length of the first connection line is shorter than the length from the control module 303 to the side of the second storage array group 2000 away from the control module 303 .

[0059] In one embodiment, the memory arrays included in the memory module are evenly arranged, so the number ratio of the memory arrays can reflect the length relationship between the components of the chip. Figure 3 , the ratio of the number of storage arrays 201 included in the first storage array group 1000 and the second storage array group 2000 is 1 / 3, which can also reflect that the ratio of the length of the first connection line to the length from the control module 303 to the second storage array group 2000 away from the control module 303 is approximately 1 / 3 (the length of the first connection line is less than the length from the control module 303 to the second storage array group 2000 away from the control module 303).

[0060] refer to Figure 3 , pin 302 is connected to control circuit and pin circuit 303 through instruction address connection 306 and data connection 307, which is a well-known technology in the art and will not be described in detail here. Control circuit and pin circuit 303 are connected to multiple storage arrays 301 through instruction address bus 304 and data bus 305, wherein the connection between control circuit and pin circuit 303 and instruction address bus 304 and data bus 305 and the connection between instruction address bus 304 and data bus 305 and multiple storage arrays 201 are well-known technologies in the art and will not be described in detail here. Figure 3 In the example shown as one line, the instruction address bus 304 may be two separate lines in other embodiments. Figure 3 In the embodiment, the instruction address bus 304 and the data bus 305 are shown as two separate lines, and in other embodiments, the instruction address bus 304 and the data bus 305 can be one line.

[0061] refer to Figure 3 The control circuit and pin circuit 303 and the pin 302 are connected to each other through the instruction address connection 306 and the data connection 307, wherein the instruction address connection 306 and the data connection 307 are both top-level connections, which can realize high-speed data transmission between the control circuit and pin circuit 303 and the pin 302.

[0062] Also refer to Figure 3When the pin 302 receives the operation instruction, it transmits the instruction to the control circuit and the pin circuit 303 through the instruction address connection 306. After the control circuit and the pin circuit 303 decode and other operations, the instruction is transmitted to the multiple storage arrays 301 through the instruction address bus 304 to operate the multiple storage arrays 301. After the instruction is transmitted to the multiple storage arrays 301 through the instruction address bus 304, the data obtained from the multiple storage arrays 301 is transmitted to the control circuit and the pin circuit 303 through the data bus 305, and then the data is transmitted to the pin through the data connection 307 to transmit the data out.

[0063] Figure 3 In the layout of the chip 300 in FIG. 1 , the control circuit and pin circuit 203 is arranged between the first storage array group 1000 and the second storage array group 2000 (the ratio of the number of storage arrays 201 arranged on both sides of the control circuit and pin circuit 303 is 1 / 3), and the control circuit and pin circuit 303 is connected to the pin 201 through the instruction address connection 306 and the data connection 307. Because the control circuit and pin circuit 303 is arranged in the middle of multiple storage arrays 301, the speed of the control circuit and pin circuit 303 sending instructions to the storage array 301 and obtaining data from the storage array 301 is relatively fast. Figure 1 The chip 100 shown is greatly improved, so that the reading and storage speed of the chip 300 is relatively Figure 1 The layout is improved and the power consumption is relatively low. Figure 2 Compared with the chip 200 shown in FIG. 1 , the lengths of the instruction address connection line 306 and the data connection line 307 between the control circuit and the pin circuit 303 and the pin 301 are respectively smaller than the lengths of the instruction address connection line 206 and the data connection line 207, so that the parasitic capacitance introduced by the chip 300 is smaller than the parasitic capacitance of the chip 200, thereby Figure 2 The layout method reduces the adverse effect of the introduction of parasitic capacitance on the signal transmission of the chip 300, and is relatively Figure 1 The layout method improves the transmission and reading speed of the chip 300.

[0064] Figure 3 The ratio of the number of storage arrays of the first storage array group 1000 and the second storage array group 2000 shown in the figure is exemplary, the number of storage arrays 301 of the first storage array group 1000 is less than the number of storage arrays 301 of the second storage array group 2000 and the parasitic capacitance introduced is within the first threshold value, so that the chip 300 can operate normally. The first threshold value refers to the maximum parasitic capacitance value that allows the chip to operate normally.

[0065] In one embodiment, the ratio of the number of storage arrays included in the first storage array group 1000 and the second storage array group 2000 is greater than or equal to 1 / 5 and less than or equal to 1 / 3.

[0066] In one embodiment, reference is also made to Figure 3 The control circuit and the pin circuit 303 are located in the middle of the adjacent sides of the first storage array group 1000 and the second storage array group 2000 .

[0067] In one embodiment, reference is also made to Figure 3 The first connection (instruction address connection 306 and data connection 307) is located at a different layer from the chip 300, and communicatively connects the pin 302 and the control module 303.

[0068] In one embodiment, reference is also made to Figure 3 The storage module composed of the first storage array group 1000 and the second storage array group 2000 is rectangular, and the pin 302 is located on one side of one of the two short sides of the rectangle.

[0069] Figure 4 Schematic diagram of the structural layout of a chip 400 according to an embodiment of the present disclosure.

[0070] like Figure 4 As shown, the chip 400 disclosed in the present invention includes a storage module (including a first storage array group 1000' and a second storage array group 2000', wherein the first storage array group 1000' and the second storage array group 2000' respectively include a plurality of storage arrays 401), a pin 402, a control module 403 (control circuit and pin circuit), a second connection (an instruction address bus 404 and a data bus 405) and a first connection (an instruction address connection 406 and a data connection 407). The instruction address connection 406 and the data connection 407 have parasitic capacitance. Figure 4 In the illustrated embodiment, the ratio of the number of storage arrays 401 in the first storage array group 1000 ′ to that in the second storage array group 2000 ′ is 1 / 5.

[0071] exist Figure 4 In the illustrated embodiment, the first storage array group 1000' includes two storage arrays 401, and the second storage array group 2000' includes ten storage arrays 401, but the present invention is not limited thereto. The first storage array group 1000' may include storage arrays 401 other than two, and the second storage array group 2000' may include storage arrays other than ten.

[0072] Figure 5 Schematic diagram of the structural layout of a chip 500 according to an embodiment of the present disclosure.

[0073] like Figure 5 As shown, the chip 500 disclosed in the present invention includes a storage module (including a first storage array group 1000" and a second storage array group 2000", wherein the first storage array group 1000" and the second storage array group 2000" respectively include multiple storage arrays 501), a pin 502, a control module 503 (control circuit and pin circuit), a second connection (an instruction address bus 504 and a data bus 505) and a first connection (an instruction address connection 506 and a data connection 507). The instruction address connection 506 and the data connection 507 have parasitic capacitance. Figure 5 In the illustrated embodiment, the ratio of the number of storage arrays 401 in the first storage array group 1000 ″ to the number of storage arrays 401 in the second storage array group 2000 ″ is 1 / 2.

[0074] exist Figure 5 In the illustrated embodiment, the first storage array group 1000" includes four storage arrays 501, and the second storage array group 2000" includes eight storage arrays, but the present invention is not limited thereto. The first storage array group 1000" may include storage arrays 301 other than four, and the second storage array group 2000" may include storage arrays other than eight.

[0075] Figure 6 Schematic diagram of the structural layout of a chip 600 according to an embodiment of the present disclosure.

[0076] like Figure 6 As shown, the chip 600 disclosed in the present invention includes a storage module (including a first storage array group 1000, a second storage array group 2000 and a third storage module 3000, wherein the first storage array group 1000, the second storage array group 2000 and the third storage module 3000 respectively include a plurality of storage arrays 601), a pin 602, a control module 603 (control circuit and pin circuit), a second connection (an instruction address bus 604 and a data bus 605) and a first connection (an instruction address connection 606 and a data connection 607). The instruction address connection 606 and the data connection 607 have parasitic capacitance. Figure 6 In the illustrated embodiment, the number of storage arrays 601 in the first storage array group 1000 is less than the number of storage arrays 601 in the second storage array group 2000 , and the number of storage arrays 601 in the third storage module 3000 is less than the number of storage arrays 601 in the second storage array group 2000 .

[0077] exist Figure 6In the illustrated embodiment, the first storage array group 1000 includes two storage arrays 601, the second storage array group 2000 includes six storage arrays, and the third storage array group 3000 includes one storage array, but the present invention is not limited thereto. The first storage array group 1000 may include storage arrays 601 other than two, the second storage array group 2000 may include storage arrays other than six, and the third storage array group 3000 may include storage arrays other than one.

[0078] refer to Figure 6 The control circuit and pin circuit 603 includes a first side surface L1, a second side surface L2, a third side surface L3 and a fourth side surface L4. Figure 6 In the embodiment, the third storage array group 3000 is located on the third side L3 of the control circuit and pin circuit 603. In other embodiments, the third storage array group 3000 is located on the fourth side L4 of the control circuit and pin circuit 603.

[0079] Figure 7 FIG. 7 is a schematic diagram of the structural layout of a chip 700 according to an embodiment of the present disclosure.

[0080] like Figure 7 As shown, the chip 700 disclosed in the present invention includes a storage module (including a first storage array group 1000', a second storage array group 2000' and a third storage module 3000', wherein the first storage array group 1000', the second storage array group 2000' and the third storage module 3000' respectively include a plurality of storage arrays 701), a pin 702, a control module 703 (control circuit and pin circuit), a second connection (an instruction address bus 704 and a data bus 705) and a first connection (an instruction address connection 706 and a data connection 707). The instruction address connection 706 and the data connection 707 have parasitic capacitance. Figure 7 In the illustrated embodiment, the number of storage arrays 701 in the first storage array group 1000' is less than the number of storage arrays 701 in the second storage array group 2000', and the number of storage arrays 701 in the third storage module 3000' is less than the number of storage arrays 701 in the second storage array group 2000'.

[0081] exist Figure 7 In the illustrated embodiment, the first storage array group 1000' includes three storage arrays 601, the second storage array group 2000' includes nine storage arrays, and the third storage array group 3000' includes two storage arrays, but the present invention is not limited thereto. The first storage array group 1000' may include storage arrays 301 other than three, the second storage array group 2000' may include storage arrays other than nine, and the third storage array group 3000' may include storage arrays other than two.

[0082] refer to Figure 7 The control circuit and pin circuit 703 includes a first side surface L1, a second side surface L2, a third side surface L3 and a fourth side surface L4. Figure 7 In the embodiment, the third memory array group 3000 includes a memory array 701 which is located on the third side surface L4 and the fourth side surface L5 of the control circuit and the pin circuit 703 respectively.

[0083] In one embodiment, the chip of the present disclosure is a DRAM (Dynamic Random Access Memory).

[0084] The present disclosure also provides an electronic device, which includes any chip disclosed in the above embodiments.

[0085] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0086] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not claimed by the present invention. The specification and examples are to be considered exemplary only, and the true scope and spirit of the present invention are indicated by the claims.

[0087] It should be understood that the present invention is not limited to the detailed structures, drawings or implementations shown herein, but rather the present invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A chip, characterized in that: include: A storage module, comprising a first storage array group and a second storage array group, wherein the first storage array group and the second storage array group respectively comprise a plurality of storage arrays; A pin located at a side of the first storage array group away from the second storage array group; A control module, located between the first storage array group and the second storage array group; A first connection line, connecting the pin and the control module; as well as A second connection line connects the control module with the first storage array group and the second storage array group; The length of the first connection line is shorter than the length from the control module to the second storage array group away from the control module.

2. The chip according to claim 1, characterized in that: The control module includes a control circuit and a pin circuit.

3. The chip according to claim 1, characterized in that: The first connection includes an instruction address connection and a data connection, and the second connection includes an instruction address bus and a data bus.

4. The chip according to claim 1, characterized in that: The ratio of the number of storage arrays included in the first storage array group to the number of storage arrays included in the second storage array group is 1 / 5 to 1 / 3.

5. The chip according to claim 1, characterized in that: The ratio of the number of storage arrays included in the first storage array group to the number of storage arrays included in the second storage array group is 1 / 3.

6. The chip according to claim 1, characterized in that: The ratio of the number of storage arrays included in the first storage array group to the number of storage arrays included in the second storage array group is 1 / 5.

7. The chip according to claim 1, characterized in that: The ratio of the number of storage arrays included in the first storage array group to the number of storage arrays included in the second storage array group is 1 / 2.

8. The chip according to claim 1, characterized in that: The control module is located in the middle of two adjacent side surfaces of the first storage array group and the second storage array group.

9. The chip according to claim 1, characterized in that: The storage module further comprises a third storage array group, the third storage array group comprises a plurality of storage arrays, the control module comprises a first side surface and a second side surface opposite to each other, and a third side surface and a fourth side surface opposite to each other; the direction from the first side surface toward the second side surface is perpendicular to the direction from the third side surface toward the fourth side surface; the pin and the first storage array group are located on the first side surface of the control module, and the second storage array group is located on the second side surface of the control module; The storage array included in the third storage array group is located on the third side surface or the fourth side surface of the control module.

10. The chip according to claim 1, characterized in that: The storage module further comprises a third storage array group, the third storage array group comprises a plurality of storage arrays, the control module comprises a first side surface and a second side surface opposite to each other, and a third side surface and a fourth side surface opposite to each other; the direction from the first side surface toward the second side surface is perpendicular to the direction from the third side surface toward the fourth side surface; the pin and the first storage array group are located on the first side surface of the control module, and the second storage array group is located on the second side surface of the control module; The storage arrays included in the third storage array group are respectively located on the third side surface and the fourth side surface of the control module.

11. The chip according to claim 1, characterized in that: The first connection line is a top-level connection line and communicatively connects the pin and the control module.

12. The chip according to claim 1, characterized in that: The storage module is rectangular, and the pins are located on one side of one of the two short sides of the rectangle.

13. An electronic device, characterized in that: A chip comprising any one of claims 1-12.

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