Device and method for logging failed authentication attempts

Abstract

The present application relates to authentication recording using circuit degradation. The present invention provides apparatus and methods related to recording failed authentication attempts. Failed authentication attempts can be recorded in the circuit by degrading the circuit. The degradation can represent a failed authentication attempt, and the amount of the degradation can represent the timing of the error.

Description

Technical Field

[0001] The present invention relates generally to memory and, more particularly, to apparatus and methods associated with logging authentication attempts through circuit degradation. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory may provide persistent data by retaining stored data when not powered and may include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

[0003] The memory is also used as volatile and non-volatile data storage for a wide range of electronic applications, including but not limited to personal computers, portable memory sticks, digital cameras, cellular phones, portable music players (e.g., MP3 players, movie players), and other electronic devices. The memory cells may be arranged in an array, where the array is used in a memory device.

[0004] Various computing systems include a number of processing resources coupled to a memory (e.g., a memory system) that is accessed in association with executing a set of instructions (e.g., a program, an application, etc.). The memory system may receive commands from multiple sources for various reasons. Some commands may be authorized while other commands are unauthorized. Unauthorized commands received at the memory may pose a security threat to the memory and / or data stored in the memory. It may be desirable to limit security threats to the memory. Summary of the invention

[0005] In one aspect, the present application provides a device comprising: a memory array; a peripheral circuit coupled to the memory array and comprising a command decoder configured to receive a trigger to execute an authentication sequence; a first portion of the peripheral circuit coupled to the memory array and configured to execute the authentication sequence in response to receipt of the trigger; and a second portion of the peripheral circuit coupled to the memory array and configured to respond to an error in the authentication sequence by recording the error in the authentication sequence in the circuit by degrading one or more components in the second portion of the circuit.

[0006] On the other hand, the present application further provides a method, comprising: in response to receiving a trigger, executing a first authentication sequence and a second authentication sequence; in response to a first error in the first authentication sequence, downgrading a first circuit to reflect the first error in the first authentication sequence; and in response to a second error in the second authentication sequence, downgrading a second circuit to reflect the second error in the second authentication sequence.

[0007] On the other hand, the present application further provides a device comprising: a circuit for capturing failed authentication attempts; a control circuit configured to: execute a first authentication sequence and a second authentication sequence in response to receipt of a trigger; in response to a first error in the first authentication sequence, downgrade the circuit to reflect the first error in the first authentication sequence; and in response to a second error in the second authentication sequence, downgrade the circuit to reflect the second error in the second authentication sequence. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an apparatus in the form of a computing system including a memory device according to several embodiments of the invention.

[0009] Figure 2 is a block diagram for logging failed authentication attempts according to several embodiments of the present invention.

[0010] Figure 3 is a block diagram of a method for logging failed authentication attempts according to several embodiments of the present invention.

[0011] Figure 4 is a block diagram of a degradation circuit according to several embodiments of the present invention.

[0012] Figure 5 An example illustrating the relationship between power cycling and failed authentication sequences according to several embodiments of the present invention.

[0013] Figure 6 An example flow chart illustrating a method for logging failed authentication attempts according to several embodiments of the invention.

[0014] Figure 7 An example machine is illustrated of a computer system within which a set of instructions for causing the machine to perform the various methodologies discussed herein may be executed. DETAILED DESCRIPTION

[0015] The present invention includes apparatus and methods related to using degradation circuits to record authentication attempts. In several instances, devices may be subject to security threats. It may be desirable to identify which devices may have been subject to security threats.

[0016] As used herein, a security threat is unauthorized use of a device. A device may be used by providing a command to the device. For example, if the device is a memory device, use of the device may be unauthorized if the device receives and / or processes an unauthorized command. A command may be unauthorized if the command is provided by a source that is not authorized to provide the command to the device.

[0017] In some examples, if a device has received and / or processed an unauthorized command, the device may be identified as having been subjected to a security compromise. The device may perform an authentication procedure to determine whether a process is authorized to provide the command to the device. In various examples, the device may perform an authentication procedure to authenticate itself to the process providing the command.

[0018] The device may record whether the authentication procedure is successful or whether the authentication procedure fails. The authentication procedure may not prevent the device from being damaged so that the device is subject to security threats. However, the device may record the error of the authentication procedure and / or may record the time associated with the error of the authentication procedure. As used herein, the error of the authentication process may include the failure of the authentication process and / or the abnormality of the authentication process. The error may cause deviation from the successful authentication and / or deviation from the successful authentication procedure. Recording the error of the authentication procedure and / or the time of the error provides the ability to evaluate the log to determine the duration of possible security threats and / or the existence of security threats. For example, if the device shows signs of security threats, the log can be checked to determine whether the authentication procedure fails. The time of the failed authentication procedure can be used to determine the duration of the operation of the device under security threats. Determining the time of the error can be used to further investigate the possible damage of data and / or unauthorized access to data. As used herein, the reference to the time of the error includes a reference to the power event associated with the error. For example, if the error occurs during a specific power-on event, the time of the error can describe the power event in which the error occurs. Although the examples described herein are provided in the context of a memory device, the examples described herein may also be applied to other types of devices, such as processing devices and / or graphics devices, as well as other types of devices.

[0019] As used herein, "a number" of something may refer to one or more such things. For example, a number of memory devices may refer to one or more memory devices. A "number" of something is intended to be two or more. Additionally, designators such as "N," as used herein, particularly with respect to reference numerals in the accompanying drawings, indicate that a number of a particular feature so designated may be included in several embodiments of the invention.

[0020] Figures herein follow a numbering convention, wherein the first or first few digits correspond to the accompanying figure number and the remaining digits identify the elements or components in the accompanying drawings. Similar elements or components between different figures can be identified by using similar numbers. It will be appreciated that the elements shown in various embodiments herein can be added, exchanged and / or eliminated in order to provide several additional embodiments of the present invention. In addition, the ratios and relative dimensions of the elements provided in the figures are intended to illustrate various embodiments of the present invention and are not used in a limiting sense.

[0021] Figure 1 is a block diagram of an apparatus in the form of a computing system 100 including a memory device 103, according to several embodiments of the present invention. As used herein, memory device 103, memory array 110, and / or host 102, for example, may also be individually considered to be an "apparatus."

[0022] In this example, system 100 includes a host 102 coupled to a memory device 103 via an interface 104. Computing system 100 may be a personal laptop computer, a desktop computer, a digital camera, a mobile phone, a memory card reader, or an Internet of Things (IoT) enabled device, among various other types of systems. Host 102 may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry) that are capable of accessing memory device 103. System 100 may include separate integrated circuits, or both host 102 and memory device 103 may be on the same integrated circuit. For example, host 102 may be a system controller of a memory system that includes multiple memory devices 103, where the system controller provides access to the respective memory devices 103 through another processing resource, such as a central processing unit (CPU).

[0023] exist Figure 1 In the example shown in , host 102 is responsible for executing an operating system (OS) and / or various applications (e.g., processes) that may be loaded thereto (e.g., from memory device 103 via control circuit 105). Host 102 may trigger an authentication process to verify that host 102 is authorized to provide commands to memory device 103.

[0024] The authentication process may be any one of a plurality of authentication processes. For example, the authentication process may consist of a plurality of authentication sequences. The authentication sequence may be a form of authentication such that the authentication process may perform a plurality of different authentications. Each of the different authentication sequences may be independent of other different authentication sequences such that an error or pass of a first authentication sequence does not affect an error or pass of a second authentication sequence. Each of the authentication sequences may be of a different type. For example, a first authentication sequence may be a key-based (e.g., password) authentication, while a second authentication sequence may be based on a communication protocol, wherein the authentication is performed based on whether the communication complies with the protocol. The authentication process may be described as including different types of authentication (e.g., authentication sequences). Each of the authentication sequences may include a plurality of steps and / or aspects.

[0025] For clarity, system 100 has been simplified to focus on features that are particularly relevant to the present invention. For example, memory array 110 may be a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a NAND flash memory array, and / or a NOR flash memory array. Array 110 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines). Although in Figure 1 A single array 110 is shown in FIG. 1 , but embodiments are not limited thereto. For example, the memory device 103 may include several arrays 110 (eg, several banks of DRAM cells).

[0026] The memory device 103 includes an address circuit 106 to latch an address signal provided through the interface 104. The interface may include, for example, a physical interface that employs a suitable protocol (e.g., a data bus, an address bus, and a command bus, or a combined data / address / command bus). This protocol may be custom or proprietary, or the interface 104 may employ a standardized protocol, such as Peripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, etc. The address signal is received and decoded by a row decode 108 and a column decode 112 to access the memory array 110. Data may be read from the memory array 110 by sensing voltage and / or current changes on a sense line using a sense circuit 111. The sense circuit 111 may include, for example, a sense amplifier that can read and latch a page (e.g., a row) of data from the memory array 110. The I / O circuit 107 may be used for bidirectional data communication with the host 102 through the interface 104. The read / write circuit 113 is used to write data to or read data from the memory array 110. As examples, circuitry 113 may include various drivers, latch circuits, and the like.

[0027] The control circuit 105 decodes the signals provided by the host 102. The signals may be commands provided by the host 102. These signals may include chip enable signals, write enable signals, and address latch signals for controlling operations performed on the memory array 110, including data read operations, data write operations, and data erase operations. In various embodiments, the control circuit 105 is responsible for executing instructions from the host 102. The control circuit 105 may include a state machine, a sequencer, and / or some other type of control circuit, which may be implemented in the form of hardware, firmware, or software, or any combination of the three. In some examples, the host 102 may be a controller external to the memory device 103. For example, the host 102 may be a memory controller coupled to a processing resource of a computing device.

[0028] The control circuit 105 may be coupled to the degradation circuit 109. Figure 4 The degradation circuit 109 is further described in . The degradation circuit 109 may include a circuit that can be degraded to store data. For example, the circuit may store binary data by degrading the circuit so that any degradation can represent the value of a binary bit and no degradation can represent a different value of the binary bit. The degradation amount may also be used to store additional data associated with the binary bit. For example, if the data stored in the degradation circuit describes a pass or fail of a processing sequence, then the degradation amount value may describe the time associated with the pass or fail of the processing sequence. The greater the degradation of the circuit, the more time has passed since the authentication sequence failed or passed.

[0029] The degradation circuit 109 may be referred to as a data logger circuit for recording data generated by the control circuit 105 and / or from other components of the memory device 103. The data logger circuit may include a complementary metal oxide semiconductor (CMOS) device (e.g., a p-type metal oxide semiconductor (PMOS) device or an n-type metal oxide semiconductor (NMOS) device) configured to degrade according to target usage information (e.g., negative bias temperature instability (NBTI) based degradation or channel hot carrier (CHC) based degradation). The memory device 103 may further adjust or change the amount of degradation that occurs each time to compensate for other factors or conditions that affect degradation (e.g., operating temperature). In some embodiments, the memory device 103 may adjust the amount of degradation by adjusting the stress voltage used to degrade the CMOS. In some embodiments, the memory device 103 may adjust the duty cycle of the stress input used to degrade the CMOS. Although in Figure 1 Although shown as a separate functional block in FIG. 1 , the memory device 103 may include the degradation circuit 109 within any of the other components described above (eg, the control circuit 105, the input / output circuit 107, etc.).

[0030] In various examples, the control circuit 105, the destage circuit 109, the address circuit 106, the row decode 108, the I / O circuit 107, the read / write circuit 113, and / or the column decode 112 may be considered as peripheral circuits. The peripheral circuits may be coupled to the memory array 110. The peripheral circuits may also include a command decoder (not shown). The command decoder may be part of the control circuit 105 or may be separate from the control circuit 105. The command decoder may be configured to decode commands received from the host 102. The command decoder may be configured to receive a trigger command. The command decoder may receive a trigger command to perform an authentication sequence.

[0031] A first portion of peripheral circuitry coupled to the memory array may be configured to perform an authentication sequence in response to receipt of a trigger. The first portion of peripheral circuitry may be, for example, control circuitry 105 or a portion of control circuitry 105. The first portion may be a portion of control circuitry 105 separate from a command decoder also included in control circuitry 105.

[0032] A second portion of the peripheral circuit coupled to the memory array 110 may be configured to record an error of the authentication sequence in the circuit by degrading one or more components in the second portion of the circuit in response to an error of the authentication sequence. The second portion may be, for example, degradation circuit 109. The second portion of the peripheral circuit may include one or more components configured to degrade based at least in part on the error of the authentication sequence and the time associated with the error. The second portion of the peripheral circuit may also include a voltage regulator configured to shift a threshold voltage of the circuit. The shift in the threshold voltage may identify the error. The shift in the threshold voltage may also identify the specific authentication sequence that suffered the error.

[0033] For example, the first portion of the peripheral circuitry may include logic configured to execute an authentication sequence to authenticate a process executed by a processing resource of the host 102. The first portion of the peripheral circuitry may also include logic configured to execute an authentication sequence to unlock the memory device 103.

[0034] The memory device 103 may also include at least one of a non-volatile memory configured to store failed authentication attempts based on an error, a fuse in a peripheral circuit (e.g., degradation circuit 109), or a portion of the memory array 110, or any combination thereof. The trigger for performing the authentication sequence may be a power event, such as power-on of the memory device 103 or power-off of the memory device 103. The power event may also include a sleep event and / or a refresh event, as well as other events that may be used by the memory device 103 to conserve energy or to carry out functions of the memory device 103.

[0035] In various examples, the peripheral circuitry may include complementary metal oxide semiconductor (CMOS) circuitry located on the same plane as the memory array or located below the memory array. For example, the peripheral circuitry may be implemented below the memory array such that the peripheral circuitry resides on a different plane than the memory array.

[0036] Figure 2 2 is a block diagram for logging failed authentication attempts according to several embodiments of the present invention. An authentication trigger 220 may initiate an authentication sequence 221-1. The authentication trigger 220 may be provided as a power event such as power up and / or power down. The authentication trigger 220 may also be provided by a process performed by a host. For example, the host may provide a command to a memory device. The command may instruct the memory device to perform an authentication process.

[0037] Trigger 220 may be associated with data used in the authentication process. For example, a trigger may be associated with a key and other types of data that may be used in the authentication process. Figure 1 The trigger is provided through the interface 104 in the embodiment, and the data associated with the trigger is provided through the data interface.

[0038] In some examples, a trigger may be associated with different types of data that may be used in different authentication sequences. For example, a first data set may be used in authentication sequence 221-1 and a second data set may be used in authentication sequence 221-2. The first data set may be of a different type than the second data set. For example, the first data set may be a key and the second data set includes one or more commands. The data associated with the trigger may be provided simultaneously with the trigger and / or may be provided incrementally. For example, the first data set may be received by the memory device upon receiving the trigger or upon executing authentication sequence 221-1, and the second data set may be received upon receiving the trigger or upon executing authentication sequence 221-2.

[0039] In response to receiving trigger 220, the control circuit may execute that authentication sequence 221-1. There may be multiple results for executing authentication sequence 221-1. For example, authentication sequence 221-1 may pass or fail. If authentication sequence 221-1 fails, then the control circuit may degrade circuit 223-1. If authentication sequence 221-1 passes, then the control circuit may execute authentication sequence 221-2.

[0040] In response to the authentication sequence 221-2 passing, the controller may grant access 227 to the memory device. Figure 2 Access to the memory device is described as being granted 227 in response to authentication sequence 221-1 and authentication sequence 221-2 passing, but other actions may be performed in response to authentication sequence 221-1 and / or 221-2 passing.

[0041] In response to authentication sequence 221-2 failing, control circuitry may degrade circuitry 223-2. If the circuitry is used to record the results of a single authentication sequence, the circuitry may also be used to record the timing of the error. The degradation amount may define the timing element of the error of the authentication sequence.

[0042] Circuits 223-1 and 223-2 may also be used to record the passing of authentication sequence 221-1 and authentication sequence 221-2, respectively. For example, in response to authentication sequence 221-1 and authentication sequence 221-2 passing, circuits 223-1 and 223-2 are not degraded, which may indicate that authentication sequence 221-1 and 221-2 passed.

[0043] exist Figure 2 In the example, two different circuits 223-1 and 223-2 are used to record (eg, log) errors of authentication sequence 221-1 and authentication sequence 221-2, respectively. However, in a different example, a single circuit may be used to record errors of authentication sequence 221-1 and authentication sequence 221-2.

[0044] Figure 2 It is shown that if authentication sequence 221-1 passes, then authentication sequence 221-2 may be executed. In other examples, authentication sequence 221-2 may be executed regardless of whether authentication sequence 221-2 passes. In various examples, additional actions may be performed in response to authentication sequence 221-1 and / or authentication sequence 221-2 failing. For example, access to a memory device may be denied in response to authentication sequences 221-1 and 221-2 failing.

[0045] Figure 2 While the execution of two authentication sequences is shown, various examples may execute more or less than two authentication sequences. For example, the authentication process may consist of a single authentication sequence or three or more authentication sequences. The number of authentication sequences may be scaled based on security considerations. For example, the number of authentication sequences may be scaled based on the security considerations of the memory manufacturer.

[0046] Figure 3 is a block diagram of a method for logging failed authentication attempts according to several embodiments of the present invention. Figure 3 Demonstrate possible relationships between authentication processes and power events. For example, Figure 3 N power events 330-1, 330-2, 330-3, ... and 330-N are shown, which are referred to as power events 330. The power-up event Figure 3 Used as power events.

[0047] Power events 330 may be used to trigger authentication processes. For example, power event 330-1 may trigger authentication process 332-1, power event 330-2 may trigger authentication process 332-2, power event 330-3 may trigger authentication process 332-3, ..., and power event 330-N may trigger authentication process 332-N. Each authentication process may be triggered by Figure 3 The first authentication sequence and the second authentication sequence described as step 1 and step 2 are composed of.

[0048] Assuming the corresponding authentication sequence passes, then the authentication process 332-1 passes. The passing of the authentication sequence corresponding to the authentication process 332-1 may be recorded in circuits 323-1 and 323-2. The passing of the authentication sequence corresponding to the authentication process 332-2 may be recorded by not degrading the circuits 323-1 and 323-2. The passing of the authentication process 332-2 may be recorded in circuits 323-3 and 323-4 by avoiding degrading the circuits 323-3 and 323-4. The error of the authentication process 332-3 may be recorded in circuits 323-5 and 353-6. The passing of the authentication process 332-4 may be recorded in circuits 323-N-1 and 323-N.

[0049] exist Figure 3 Authentication process 332-2 may fail. Authentication process may fail because the first authentication sequence fails. Errors of the first authentication sequence may be recorded in circuit 323-5 by degrading circuit 323-5. Authentication process 332-3 may fail because the first authentication sequence fails even if the second authentication sequence passes. Figure 3 Different numbers of circuits are shown that can be used to record the results of an authentication process spanning multiple power events.

[0050] Figure 4 4 is a block diagram of a degradation circuit 409 according to several embodiments of the present invention. The degradation circuit 409 may include stress / measurement logic 442, a CMOS degradation based sensor 446, and an operational amplifier reader 447.

[0051] The stress / measurement logic 442 may include logic circuitry configured to determine the occurrence of a specified condition or event in the target data 451 and generate a stress input 445 (e.g., a signal or voltage) that stresses / degrades the CMOS degradation-based sensor 446. For example, the target data 451 may include data representing an error of an authentication process, including an error of an authentication sequence that includes the authentication process. The error of the authentication process may be a specific condition or event that stresses / degrades the CMOS degradation-based sensor 446.

[0052] The operational amplifier reader 447 may be configured to use a reference input 449 (Vref) to generate a read output 448 corresponding to the amount or degree of degradation in the CMOS degradation based sensor 446. The operational amplifier reader 447 provides the ability to read the CMOS degradation based sensor 446. For example, the read circuit and / or control circuit may scan the reference input 449 to generate the read output 448. As the CMOS degradation based sensor 446 degrades, the reference voltage required to trigger the operational amplifier will shift in proportion to the threshold voltage (Vt) shift of the sensor core. The amount of degradation may be obtained by comparing the trigger voltage to a reference sensor or an unstressed sensor or a time zero reading taken and / or stored at the factory during manufacturing or initial testing.

[0053] In some embodiments, the CMOS degradation based sensor 446 may include a PMOS device configured to degrade according to NBTI. For a PMOS device, the gate may be connected to the stress / measurement logic 442, the source may be connected to a voltage source (e.g., a known voltage level V), and the drain may be connected to an op amp reader 447, a feedback line to the stress / measurement logic 442, a resistor connected to ground, or a combination thereof. In some embodiments, the CMOS degradation based sensor 446 may include an NMOS device configured to degrade according to CHC. For an NMOS device, the gate may be connected to the stress / measurement logic 442, the drain may be connected to a voltage source, and the source may be connected to an op amp reader 447, a feedback line, a resistor, or a combination thereof.

[0054] In some embodiments, the degradation of the sensor 446 based on CMOS degradation may be affected by one or more operating conditions. For example, a higher operating temperature of the sensor 446 based on CMOS degradation may increase the amount of degradation. Therefore, the stress / measurement logic 442 may receive one or more related condition (e.g., operating temperature) information in addition to the observed condition or event. The stress / measurement logic 442 may include a control profile 450 representing an adjustment of the stress input 445 based on the one or more related condition information. In other words, the stress / measurement logic 442 may generate the stress input 445 based on the control profile 450 so that the degradation of the sensor 446 based on CMOS degradation depends on the observed condition and is not affected by other environmental conditions.

[0055] In some embodiments, the stress / measurement logic 442 may include a stress voltage control circuit 443 and / or a stress time control circuit 444 configured to control the stress input 445 to achieve an appropriate amount of stress or degradation. For example, the stress voltage control circuit 443 may be configured to control the voltage of the stress input 445 to adjust the stress voltage (e.g., between the voltage source V and the stress input 445). For operating temperature, the stress voltage control circuit 443 may decrease the stress voltage as the temperature increases. Also, the stress time control circuit 444 may be configured to control the duty cycle of the stress input 445. For operating temperature, the stress time control circuit 444 may decrease the duty cycle as the temperature increases.

[0056] Figure 5 An example of the relationship between the powers 530 - 1 , 530 - 2 , and 530 - 3 and the failed authentication sequence 521 - 5 according to several embodiments of the present invention is described. Figure 5 Power cycles 530-1, 530-2, and 530-3 are shown and are referred to as power cycle 530. Power cycle 530 may be an example of a power event. Figure 5 Also shown are the passes of authentication sequences 521-1, 521-2, 521-3, 521-4, and 521-5, and the error of authentication sequence 521-5.

[0057] The failed authentication sequence 521-5 may be recorded in a circuit configured by setting a circuit threshold voltage. Assuming that an error in the authentication sequence 521-5 may indicate possible access to the memory device by a source that is not authorized to access the memory device, malicious activity may describe the failed authentication sequence 521-5. The failed authentication sequence 521-5 may occur during a power cycle 530-3.

[0058] Associating failed authentication sequence 521-5 with power cycle 530-3 may indicate that malicious activity may have occurred after power cycle 530-3 and may continue to occur after power cycle 530-3. Associating failed authentication sequence 521-5 may indicate that a security threat exists in the memory device after power cycle 530-3.

[0059] Figure 6 An example flow chart illustrating a method for logging failed authentication attempts according to several embodiments of the present invention. At 660, in response to receiving a trigger, a first authentication sequence and a second authentication sequence may be executed. In some examples, if the first authentication sequence passes, the second authentication sequence may be executed.

[0060] At 662, in response to a first error of the first authentication sequence, the first circuit is degraded to reflect the first error of the first authentication sequence. At 664, in response to a second error of the second authentication sequence, the second circuit is degraded to reflect the second error of the second authentication sequence. Each error of the authentication sequence can be recorded in a different circuit. The result of using a circuit to record each of the authentication sequences can provide for simultaneous recording of timing elements in the same circuit. For example, errors of the authentication sequence and timing components corresponding to the errors can be stored in the circuit by degrading the circuit.

[0061] The number of degrade circuits may be associated with different authentication sequences. For example, a first degrade circuit may be associated with a first failed authentication sequence, and a second degrade circuit may also be associated with a second failed authentication sequence. Degrading the first degrade circuit may indicate a first authentication attempt failed. Degrading the second degrade circuit may indicate a second authentication attempt failed. The timing components of the first failed authentication sequence and the second failed authentication sequence may correspond to a failure of the first authentication sequence prior to a failure of the second authentication sequence.

[0062] Degrading the first circuit may include degrading the first circuit to reflect the timing of a first error of the first authentication sequence.Degrading the second circuit may further include degrading the second circuit to reflect the timing of a second error of the second authentication sequence.

[0063] In some embodiments, degrading the first circuit and the second circuit may further include degrading the first circuit and the second circuit to reflect multiple attempts at the first authentication sequence and the second authentication sequence. The first authentication sequence may be executed multiple times in response to repeated errors of the first authentication sequence until a threshold of errors of the first authentication sequence is reached. The second authentication sequence may also be executed multiple times in response to repeated errors of the first authentication sequence. The number of executions of the first authentication sequence and the second authentication sequence may be different. The number of errors of the first authentication sequence may be recorded in the circuit by degrading the circuit. The degradation amount may represent the number of errors of the first authentication sequence, while the degradation amount may represent the number of errors of the second authentication sequence.

[0064] In response to a plurality of first errors of the first authentication sequence and the second authentication sequence, the first circuit may be degraded a first plurality of times and the second circuit may be degraded a second plurality of times. Each of the errors may trigger a degrade of the circuit such that the circuit may be degraded a number of times equal to the number of errors of the authentication sequence. Each degrade of the first circuit and the second circuit may increase a first threshold voltage of the first circuit and a second threshold voltage of the second circuit.

[0065] In some embodiments, a trigger to perform an authentication sequence may be received. In response to receiving the trigger, the authentication sequence may be performed. In response to an error in the authentication sequence, the error in the authentication sequence may be recorded in the circuit by degrading the circuit.

[0066] Degrading the circuit may reflect an error in the authentication sequence and a time associated with the error. The circuit may be degraded by shifting a threshold voltage of the circuit. Shifting the threshold voltage of the circuit may include shifting a threshold voltage of a transistor of the circuit.

[0067] Any shift in the threshold voltage may identify an error in the authentication sequence and the amount of the shift identifies the time associated with the error in the authentication sequence.

[0068] The authentication sequence may authenticate a process requesting access to a memory device or may unlock a memory device among other possible types of authentication. In some examples, the authentication sequence may authenticate the memory device to the process. Based on the authentication sequence, the process may determine whether to store data in the memory device based on whether the memory device has been authenticated.

[0069] In various cases, in response to receiving a trigger, a first authentication sequence and a second authentication sequence may be performed. In response to a first error in the first authentication sequence, the circuit may be degraded to reflect the first error in the first authentication sequence. In response to a second error in the second authentication sequence, the circuit may be degraded to reflect the second error in the second authentication sequence.

[0070] The circuit may record multiple errors for multiple authentication sequences. The multiple errors may include a first error and a second error. Capturing multiple errors in a single circuit may include capturing the multiple errors without identifying whether the multiple errors correspond to the first authentication sequence or the second authentication sequence. The multiple errors may be recorded in the circuit using multiple threshold voltages. For example, a first threshold voltage of the circuit may represent a first error, a second threshold voltage of the circuit may represent a second error, and so on.

[0071] The circuit can act as a counter by determining the amount of degradation. Multiple errors can be read by determining the degradation of the circuit.

[0072] Figure 7 An example machine illustrating a computer system 740 within which a set of instructions for causing the machine to perform the various methods discussed herein may be executed. In various embodiments, the computer system 740 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 Memory device 103) of the system (eg, Figure 1 100 ), or may be used to execute a controller (e.g., Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0073] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Furthermore, while a single machine is described, the term "machine" shall also be construed to include any collection of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any one or more of the methodologies discussed herein.

[0074] The example computer system 740 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718 that communicate with each other via a bus 730.

[0075] The processing device 702 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 702 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 740 may further include a network interface device 708 to communicate over a network 720.

[0076] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying one or more methodologies or functions described herein. The instructions 726 may also reside, in whole or in part, within the main memory 704 and / or within the processing device 702 during execution of the instructions 726 by the computer system 740, the main memory 704 and the processing device 702 also constituting machine-readable storage media.

[0077] In one embodiment, instructions 726 include instructions for implementing Figure 1The machine-readable storage medium 724 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be understood to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more methods of the present invention. Therefore, the term "machine-readable storage medium" should be understood to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0078] Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present invention is intended to cover adaptations or changes of various embodiments of the present invention. It should be understood that the above description has been made in an illustrative and non-restrictive manner. Upon reviewing the above description, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of the various embodiments of the present invention includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of the present invention should be determined with reference to the appended claims together with the full scope of equivalents enjoyed by such claims.

[0079] In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of simplifying the invention. The inventive method should not be interpreted as reflecting an intention that the disclosed embodiments of the invention must use more features than those explicitly recited in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim independently serving as a separate embodiment.

Claims

1. A device for recording failed authentication attempts, comprising: Memory array; a peripheral circuit coupled to the memory array and comprising a command decoder configured to receive a trigger to perform an authentication sequence; a first portion of the peripheral circuit coupled to the memory array and configured to execute the authentication sequence in response to receipt of the trigger; and A second portion of the peripheral circuit is coupled to the memory array and is configured to, in response to an error of the authentication sequence, record an error of the authentication sequence in the circuit by degrading one or more components in the second portion of the circuit.

2. The apparatus of claim 1, wherein the second portion of the peripheral circuit comprises one or more components configured to degrade based at least in part on the error of the authentication sequence and a time associated with the error.

3. The apparatus of claim 2, wherein the second portion of the peripheral circuit comprises a voltage regulator configured to shift a threshold voltage of the circuit. 4 . The apparatus of claim 3 , wherein a shift in the threshold voltage identifies the error and the shift identifies an authentication sequence that was subject to the error.

5. The apparatus of any one of claims 1-4, wherein the first portion of the peripheral circuitry comprises logic configured to execute the authentication sequence to authenticate a process executed by a processing resource.

6. The apparatus of any one of claims 1-4, wherein the first portion of the peripheral circuitry comprises logic configured to perform the authentication sequence to unlock the apparatus.

7. The apparatus of any one of claims 1 to 4, further comprising at least one of a non-volatile memory, a fuse in the peripheral circuit, or a portion of the memory array, or any combination thereof, configured to store failed authentication attempts based on the error.

8. The device of claim 5, wherein the triggering of performing the authentication sequence powers the device on or powers the device off.

9. The apparatus of any one of claims 1 to 4, wherein the peripheral circuitry comprises complementary metal oxide CMOS circuitry located on the same plane as the memory array or located below the memory array.

10. A method for logging failed authentication attempts, comprising: In response to receiving the trigger, executing a first authentication sequence and a second authentication sequence; responsive to a first error of the first authentication sequence, degrading a first circuit to reflect the first error of the first authentication sequence; and In response to a second error of the second authentication sequence, a second circuit is degraded to reflect the second error of the second authentication sequence.

11. The method of claim 10, wherein degrading the first circuit and the second circuit further comprises: a time to degrade the first circuit to reflect the first error of the first authentication sequence; and The second circuit is degraded to reflect a time of the second error of the second authentication sequence.

12. The method of any of claims 10-11, wherein degrading the first circuit and the second circuit further comprises degrading the first circuit and the second circuit to reflect multiple attempts of the first authentication sequence and the second authentication sequence.

13. The method of claim 12, further comprising degrading the first circuit a first plurality of times and degrading the second circuit a second plurality of times in response to a plurality of first errors of the first authentication sequence and the second authentication sequence.

14. The method of claim 13, wherein each degradation of the first circuit and the second circuit increases a first threshold voltage of the first circuit and a second threshold voltage of the second circuit, respectively.

15. An apparatus for recording failed authentication attempts, comprising: circuitry for capturing failed authentication attempts; A control circuit configured to: In response to receiving the trigger, executing a first authentication sequence and a second authentication sequence; responsive to a first error of the first authentication sequence, degrading the circuit to reflect the first error of the first authentication sequence; and In response to a second error of the second authentication sequence, the circuit is degraded to reflect the second error of the second authentication sequence.

16. The apparatus of claim 15, wherein the control circuit is further configured to capture a plurality of errors in the circuit, wherein the plurality of errors include the first error and the second error without identifying whether the plurality of errors corresponds to the first authentication sequence or the second authentication sequence.

17. The apparatus of claim 16, wherein the control circuit is further configured to utilize a plurality of threshold voltages to degrade the circuit to capture the plurality of errors.

18. The apparatus of any one of claims 16 and 17, wherein the control circuit is further configured to increase a threshold voltage of the circuit a number of times equal to the number of the plurality of errors.

19. The apparatus of claim 16, wherein the control circuit is further configured to read a plurality of errors by determining the degradation of the circuit.

20. The apparatus of any one of claims 15-17, wherein the control circuit is further configured to perform a plurality of actions corresponding to a failed authentication in response to the circuit having a threshold voltage.

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