Display device driver method

Abstract

The display device driving method includes: providing a reference voltage for compensating for the threshold voltage of a driving transistor in a pixel; and providing a data signal to the pixel, wherein the providing of the reference voltage and the providing of the data signal to the pixel are performed in a first frame period and a second frame period after the first frame period, wherein the display device driving method further includes: before the end of providing the reference voltage, providing a compensation signal generated by comparing the data signal provided in the previous frame period of each frame period with the reference voltage to the pixel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0107145, filed on August 30, 2019, which is hereby incorporated by reference herein in its entirety. Technical Field

[0003] Aspects of some example embodiments of the present disclosure relate to a display device driving method. Background Art

[0004] Organic light emitting display devices display images using organic light emitting diodes (OLEDs), which are self-luminous elements whose brightness is controlled by current or voltage.

[0005] In an organic light-emitting display device, a pixel typically includes a plurality of transistors, a storage capacitor, and an organic light-emitting diode. Due to various deviations between pixels (e.g., the distribution of the threshold voltage of the drive transistor), brightness differences may occur between the individual pixels in the organic light-emitting display device, and this brightness difference may be visually recognized or perceived by the user (e.g., as spots or defects in the displayed image). To correct for spots, various spot compensation algorithms may be utilized. For example, a method for correcting spots by compensating the threshold voltage of the drive transistor for each frame period when the organic light-emitting display device is driven may be used.

[0006] Meanwhile, as the resolution of organic light-emitting display devices increases, the time for compensating the threshold voltage of the driving transistor can be reduced. In order to compensate the threshold voltage based on the data signal, the number of data lines can be increased to extend the compensation time.

[0007] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore, the information discussed in this Background section does not necessarily constitute prior art. Summary of the Invention

[0008] Aspects of some example embodiments of the present disclosure may include a method of driving a display device that is connected to one data line for each pixel and has a sufficiently ensured time for compensating for a threshold voltage of a driving transistor.

[0009] The features of the present disclosure are not limited to the features described above, and other technical features that are not described can be more clearly understood by those skilled in the art from the following description.

[0010] A display device driving method according to some example embodiments of the present disclosure for parsing the features described above includes: providing a reference voltage for compensating for a threshold voltage of a driving transistor in a pixel; and providing a data signal to the pixel, wherein providing the reference voltage and providing the data signal to the pixel are performed in a first frame period and a second frame period after the first frame period, wherein the display device driving method further includes: before the end of providing the reference voltage, providing a compensation signal generated by comparing the data signal provided in the previous frame period of each frame period with the reference voltage to the pixel.

[0011] According to some example embodiments, the display device driving method may further include supplying an initialization voltage to the pixel to initialize a voltage level of a gate electrode of the driving transistor, the supplying of the initialization voltage to the pixel being performed during each frame period.

[0012] According to some example embodiments, in each frame period, supplying an initialization voltage, supplying a reference voltage, and supplying a data signal may sequentially start.

[0013] According to some example embodiments, in each frame period, providing the compensation signal may be performed after supplying the initialization voltage starts.

[0014] According to some example embodiments, in each frame period, supplying the initialization voltage and supplying the reference voltage may not overlap in time.

[0015] According to some example embodiments, in each frame period, a length of time in which supplying the reference voltage is performed and a length of time in which supplying the data signal is performed may be different from each other.

[0016] According to some example embodiments, the data signal and the compensation signal may be provided through the same data line.

[0017] According to some example embodiments, generating a compensation signal to be provided in the second frame period may include comparing a reference voltage provided in the first frame period with a magnitude of a data signal provided in the first frame period, and determining the compensation signal to be provided in the second frame period.

[0018] According to some example embodiments, determining the compensation signal may include determining the compensation signal by calculating the data signal provided in the first frame period and the compensation value.

[0019] According to some example embodiments, the compensation value may be determined by calculating a first parameter provided from a lookup table and a second parameter generated by comparing a reference voltage with a magnitude of a data signal, and the calculation may include multiplication.

[0020] According to some example embodiments, a pixel may include: a pixel circuit connected to a first power voltage supply line and a second power voltage supply line for providing a power voltage, a plurality of scan lines for providing a scan signal, a data line for providing a data signal, and a reference voltage supply line for providing a reference voltage; and an organic light emitting diode connected to the pixel circuit.

[0021] According to some example embodiments, a pixel circuit may include a plurality of transistors and a plurality of capacitors.

[0022] According to some example embodiments, one capacitor among the plurality of capacitors may charge the gate electrode of the driving transistor to a voltage corresponding to the data signal.

[0023] According to some example embodiments, after the compensation signal is provided, voltage levels of two electrodes of one capacitor may be the same.

[0024] According to some example embodiments, the plurality of transistors may include: a first transistor having a source / drain electrode connected between a first power voltage supply line and an anode electrode of an organic light emitting diode and a gate electrode connected to a second node, and a second transistor having a source / drain electrode connected between a data line and a first node and a gate electrode connected to a first scan line among a plurality of scan lines, and the plurality of capacitors may include a first capacitor connected between the first power voltage supply line and the first node and a second capacitor connected between the first node and the second node.

[0025] According to some example embodiments, the plurality of transistors may further include a third transistor having source / drain electrodes connected to the first node and the reference voltage supply line, and a gate electrode connected to a second scan line among the plurality of scan lines.

[0026] A display device driving method according to some example embodiments of the present disclosure for parsing the features described above includes: providing a reference voltage for compensating for a threshold voltage of a driving transistor in a pixel, providing the reference voltage being performed in a first frame period; providing a data signal to the pixel through a data line, providing the data signal to the pixel being performed in the first frame period; and generating a compensation signal to be provided to the pixel in a second frame period after the first frame period by comparing the reference voltage provided in the first frame period with the data signal.

[0027] According to some example embodiments, the compensation signal may be received in the second frame period, and a voltage across both ends of the capacitor connected to the gate electrode of the driving transistor may become zero.

[0028] According to some example embodiments, the display device driving method may further include: after generating the compensation signal, before supplying the reference voltage in the second frame period ends, supplying the compensation signal through the data line.

[0029] A display device driving method according to some example embodiments of the present disclosure, for resolving the features described above, includes: providing a reference voltage for compensating for a threshold voltage of a driving transistor in a pixel, the providing of the reference voltage being performed in a first frame period; providing a data signal to the pixel through a data line, the providing of the data signal to the pixel being performed in the first frame period; and determining a voltage level of the reference voltage provided to the pixel in a second frame period following the first frame period by comparing the reference voltage provided in the first frame period with the data signal. The voltage level of the reference voltage provided in the first frame period and the voltage level of the reference voltage provided in the second frame period may be different from each other.

[0030] Further details of other example embodiments are included in the detailed description and accompanying drawings.

[0031] According to some example embodiments of the present disclosure, through a display device driving method, time for compensating for a threshold voltage of a driving transistor may be sufficiently ensured without increasing the number of data lines.

[0032] Features according to the embodiments of the present disclosure are not limited to the above-described features, and include more various effects in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other features of the present invention will become more apparent by describing in further detail aspects of some example embodiments of the present invention with reference to the accompanying drawings, in which:

[0034] Figure 1 is a block diagram schematically illustrating a display device according to some example embodiments of the present disclosure;

[0035] Figure 2 is a block diagram schematically illustrating a power supply in a display device according to some example embodiments of the present disclosure;

[0036] Figure 3 is an equivalent circuit diagram of one pixel in a display device according to some example embodiments of the present disclosure;

[0037] Figure 4 is a flowchart illustrating a portion of a display device driving method according to some example embodiments of the present disclosure;

[0038] Figure 5 is a conceptual diagram illustrating a sequence of each frame period in a display device driving method according to some example embodiments of the present disclosure;

[0039] Figure 6is a timing diagram illustrating writing of a light emitting control signal, a scan signal, and a data signal for each of consecutive frame periods in a display device driving method according to some example embodiments of the present disclosure;

[0040] Figure 7 is a flow chart illustrating an algorithm for generating a compensation signal in a display device driving method according to some example embodiments;

[0041] Figure 8 is a conceptual diagram illustrating a sequence of each frame period in a display device driving method according to some example embodiments;

[0042] Figure 9 It is an icon Figure 8 Flowchart of an algorithm for generating a compensation signal in an embodiment of the present invention;

[0043] Figure 10 is a timing diagram illustrating writing of a light emitting control signal, a scan signal, and a data signal for each of consecutive frame periods in a display device driving method according to some example embodiments;

[0044] Figure 11 is a timing diagram illustrating writing of a light emitting control signal, a scan signal, and a data signal for each of consecutive frame periods in a display device driving method according to some example embodiments; and

[0045] Figure 12 and Figure 13 is a timing diagram illustrating writing a light emitting control signal, a scan signal, and a data signal to one pixel for each of adjacent frame periods in a display device according to some example embodiments. DETAILED DESCRIPTION

[0046] With reference to the example embodiments described in detail below and the accompanying drawings, the features and characteristics of the embodiments of the present disclosure and the methods for implementing them will become more apparent. However, the present disclosure is not limited to the example embodiments disclosed below and can be implemented in various different forms. This example embodiment is provided so that the present disclosure will be more thorough and more complete, and those skilled in the art to which the present disclosure belongs can more fully understand the scope of the present disclosure. The embodiments according to the present disclosure are defined by the scope of the claims and their equivalents.

[0047] Although the terms "first," "second," and "second" are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, within the technical spirit of the present disclosure, the first component mentioned below may be the second component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0048] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, the same or similar reference numerals are used for the same components.

[0049] Figure 1 is a block diagram schematically illustrating a display device according to some example embodiments of the present disclosure. Figure 2 is a block diagram schematically illustrating a power supply in a display device according to some example embodiments of the present disclosure.

[0050] refer to Figure 1 , a display device 1 according to some example embodiments of the present disclosure includes a display unit 10 , a scan driver 20 , a data driver 30 , a light emission control driver 40 , a timing controller 50 , a power supply 70 , and a processor 80 .

[0051] The display device 1 is a device that displays moving images (e.g., video images) or still images (e.g., static images) or a device that displays stereoscopic images, and can be used in various products such as televisions, notebook computers, monitors, billboards, and the Internet of Things, as well as portable electronic devices such as mobile communication terminals, smart phones, tablets, smart watches, and navigation systems.

[0052] Hereinafter, an organic light-emitting display device will be described as an example of the display device 1. However, the present disclosure is not limited thereto, and embodiments according to the present disclosure may include or be applied to other display devices such as a quantum dot organic light-emitting display device, a liquid crystal display device, a field emission display device, or an electrophoretic display device unless the spirit of the present disclosure is changed.

[0053] The display unit 10 includes a plurality of pixels PX disposed at intersections of a plurality of scan lines SL11 to SL1n, SL21 to SL2n, and SL31 to SL3n (n is an integer greater than 1), a plurality of data lines DL1 to DLm (m is an integer greater than 1), and a plurality of light emission control lines EL1 to ELn and arranged in a matrix form. Each pixel PX includes a pixel circuit and a light emitting element connected to the pixel circuit. According to some example embodiments, the light emitting element may be an organic light emitting diode (refer to Figure 3 of "LD").

[0054] The plurality of pixels PX may define a light emitting region that emits light of a plurality of colors. According to some example embodiments, the plurality of pixels PX may define a light emitting region that emits red, green, or blue light. According to some example embodiments, in addition to the colors described above, the pixels PX may define a light emitting region that emits light of a color such as white, magenta, or cyan.

[0055] Each pixel PX among the plurality of pixels PX receives a first power voltage (refer to Figure 3 and receives a second power voltage (referenced to “ELVDD”) through a second power voltage supply line ELVSSL. Figure 3 The first power voltage may be a high-level voltage (eg, a set or predetermined high-level voltage), and the second power voltage may be a low-level voltage (eg, a set or predetermined low-level voltage) lower than the first power voltage.

[0056] Each of the plurality of pixels PX emits light of a brightness (eg, a set or predetermined brightness) by a driving current according to a data signal (refer to FIG. 1 ) transmitted through the plurality of data lines DL1 to DLm. Figure 3 "DATA") is supplied to the light-emitting element.

[0057] A plurality of scan lines SL11 to SL1n, SL21 to SL2n, and SL31 to SL3n and a plurality of light emitting control lines EL1 to ELn may be arranged in a row direction ( Figure 1 The plurality of data lines DL1 to DLm may extend in the column direction ( Figure 1 The row direction and the column direction may be interchangeable. According to some example embodiments, each of the first power voltage supply line ELVDDL, the second power voltage supply line ELVSSL, the initialization voltage supply line VINTL, and the reference voltage supply line VREFL may extend in the row direction or the column direction.

[0058] However, the extending direction of the lines described above is not limited thereto, and the extending direction may be variously modified.

[0059] The processor 80 supplies control signals to the timing controller 50. For example, the control signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a plurality of image signals R, G, and B, a data enable signal, a clock signal, and the like.

[0060] The processor 80 supplies the power control signal PMS to the power supply 70. For example, the power control signal PMS may include a control signal for allowing the power supply 70 to adjust respective voltage levels of the first power voltage, the second power voltage, the initialization voltage, and the reference voltage.

[0061] For example, the processor 80 may be implemented as an integrated circuit (IC), an application processor (AP), a mobile AP, or a processor capable of controlling the operation of the timing controller 50 .

[0062] The scan driver 20 generates three scan signals (refer to Figure 3The scan driver 20 supplies three scan signals to each pixel PX through the plurality of scan lines SL11 to SL1n, SL21 to SL2n, and SL31 to SL3n. That is, the scan driver 20 sequentially supplies corresponding scan signals to the first scan lines SL11 to SL1n, the second scan lines SL21 to SL2n, and the third scan lines SL31 to SL3n.

[0063] The data driver 30 transmits the data signal to each pixel PX through the plurality of data lines DL1 to DLm. Figure 3 When the data signal “SCAN3”) is supplied to the third scan lines SL31 to SL3n, the data signal is supplied to the pixels PX selected by the third scan signal.

[0064] The light emission control driver 40 generates a light emission control signal (refer to Figure 3 The light emission control driver 40 is a first pixel of the present invention and a second pixel of the present invention is a second pixel of the present invention. ...

[0065] The timing controller 50 converts the plurality of image signals R, G, and B transmitted from the processor 80 into a plurality of image data signals DR, DG, and DB, and transmits the plurality of image data signals DR, DG, and DB to the data driver 30. In addition, the timing controller 50 receives a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync, generates control signals for controlling the driving of the scan driver 20, the data driver 30, and the light emission control driver 40, for example, a scan drive control signal SCS for controlling the scan driver 20, a data drive control signal DCS for controlling the data driver 30, and a light emission control signal ECS for controlling the light emission control driver 40, and transmits the scan drive control signal SCS, the data drive control signal DCS, and the light emission control signal ECS to the scan driver 20, the data driver 30, and the light emission control driver 40, respectively.

[0066] In addition to the first power voltage and the second power voltage, an initialization voltage (refer to Figure 3 "VINT") and reference voltage (reference Figure 3 “VREF”) can be supplied from the power supply 70.

[0067] The power supply 70 can receive an external input voltage and provide a power voltage to the output terminal by converting the external input voltage according to the power control signal PMS provided by the processor 80. For example, the power supply 70 can receive the external input voltage from a battery, etc., and boost the external input voltage to generate a power voltage higher than the external input voltage. For example, the power supply 70 can be configured as a power management integrated chip (PMIC). For example, the power supply 70 can be configured as an external DC / DC IC.

[0068] refer to Figure 2 , the power supply 70 may include a first power voltage controller (ELVDD controller) 71, a second power voltage controller (ELVSS controller) 72, an initialization voltage controller (VINT controller) 73, and a reference voltage controller (VREF controller) 74. According to some example embodiments, the power supply 70 may be implemented in a combined form in which the first power voltage controller 71, the second power voltage controller 72, the initialization voltage controller 73, and the reference voltage controller 74 are installed or integrated into one electronic part or component. For example, when the display device 1 is applied to a portable electronic device, the power supply 70 may be implemented in a combined type (e.g., an integrated component as described above). However, when the display device 1 is applied to a large device such as a television, a notebook computer, a monitor, a billboard, or the Internet of Things, the first power voltage controller 71, the second power voltage controller 72, the initialization voltage controller 73, and the reference voltage controller 74 may be implemented as independent or separate components.

[0069] The first power voltage controller 71 , the second power voltage controller 72 , the initialization voltage controller 73 and the reference voltage controller 74 may respectively adjust voltage levels of the first power voltage, the second power voltage, the initialization voltage and the reference voltage output to the outside of the power supply 70 .

[0070] Figure 3 is an equivalent circuit diagram of one pixel in the display device 1 according to some example embodiments of the present disclosure.

[0071] refer to Figure 3 , the pixel PX includes a pixel circuit and an organic light emitting diode LD connected to the pixel circuit. Hereinafter, as an example, a pixel PX in which the pixel circuit is connected to the j-th first scan line SL1j (here, 1≤j≤n), the j-th second scan line SL2j, the j-th third scan line SL3j, the i-th data line DLi (here, 1≤i≤m), and the j-th emission control line will be described in more detail.

[0072] The pixel circuit controls the amount of driving current supplied to the organic light emitting diode LD. To this end, the pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, and a second capacitor C2.

[0073] A first electrode of the first transistor T1 is connected to a first power voltage supply line ELVDDL, and a second electrode is connected to a first electrode of a sixth transistor T6. In addition, a gate electrode of the first transistor T1 is connected to a second node N2. According to some example embodiments, the first transistor T1 may be a driving transistor. In this specification, any one of the first and second electrodes of the transistors T1 to T7 may be an input terminal, and the other may be an output terminal. That is, any one of the first and second electrodes of the transistors T1 to T7 may be a source electrode of the transistors T1 to T7, and the other may be a drain electrode.

[0074] The first transistor T1 can control the current flowing through the organic light emitting diode LD according to the gate-source voltage (threshold voltage (Vth)). In response to the data signal DATA stored in the second capacitor C2, the first transistor T1 can control the current supplied from the first power voltage supply line ELVDDL to the organic light emitting diode LD to adjust the amount of light emitted by the organic light emitting diode LD. In other words, the first transistor T1 can control the current supplied to the organic light emitting diode LD in response to the voltage applied to the second node N2.

[0075] A first electrode and a second electrode of the second transistor T2 are respectively connected between the data line DLi and the first node N1. A gate electrode of the second transistor T2 is connected to the third scan line SL3j, and when a third scan signal SCAN3 is supplied to the third scan line SL3j, the second transistor T2 is turned on to electrically connect the data line DLi and the first node N1 to each other.

[0076] A first electrode of the third transistor T3 is connected to the second electrode of the first transistor T1, and a second electrode is connected to the second node N2. In addition, a gate electrode of the third transistor T3 is connected to the second scan line SL2j. When a second scan signal SCAN2 is supplied to the second scan line SL2j, the third transistor T3 is turned on to electrically connect the second electrode of the first transistor T1 and the second node N2 to each other. In this case, the first transistor T1 can be connected in a diode form.

[0077] A first electrode of the fourth transistor T4 is connected to the second node N2, and a second electrode is connected to the initialization voltage supply line VINTL. Furthermore, a gate electrode of the fourth transistor T4 is connected to the first scan line SL1j. When the first scan signal SCAN1 is supplied to the first scan line SL1j, the fourth transistor T4 is turned on to supply the initialization voltage VINT to the second node N2. When the first scan signal SCAN1 is supplied to the first scan line SL1j, the fourth transistor T4 is turned on to initialize the gate electrode of the first transistor T1 to the voltage of the initialization voltage VINT. Here, the initialization voltage VINT may be set to a voltage lower than the first power voltage ELVDD, for example, a voltage lower than the threshold voltage of the first transistor T1.

[0078] A first electrode of the fifth transistor T5 is connected to a reference voltage supply line VREFL, and a second electrode is connected to a first node N1. Furthermore, a gate electrode of the fifth transistor T5 is connected to a second scan line SL2j. According to some example embodiments, the second scan line SL2j may extend to electrically connect to the gate electrode of the third transistor T3 and the gate electrode of the fifth transistor T5. When a second scan signal SCAN2 is supplied to the second scan line SL2j, the fifth transistor T5 is turned on to supply a reference voltage VREF to the first node N1. Here, the reference voltage VREF may be set to a voltage higher than the data voltage for white, and may be set to a voltage lower than the data voltage for black.

[0079] A first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1, and a second electrode of the sixth transistor T6 is connected to the anode electrode of the organic light emitting diode LD. Furthermore, a gate electrode of the sixth transistor T6 is connected to a light emission control line. When a light emission control signal EM is supplied to the light emission control line, the sixth transistor T6 is turned on, and otherwise, the sixth transistor T6 is turned off.

[0080] A first electrode of the seventh transistor T7 is connected to the anode electrode of the organic light emitting diode LD, and a second electrode is connected to the initialization voltage supply line VINTL. In addition, a gate electrode of the seventh transistor T7 is connected to the first scan line SL1(j+1). The seventh transistor T7 can be referred to as an initialization transistor for the anode electrode.

[0081] The first capacitor C1 is connected between the first node N1 and a first power voltage supply line ELVDDL (eg, configured to supply a first power voltage or a high voltage). The first capacitor C1 may charge charges corresponding to a threshold voltage of the first transistor T1.

[0082] The second capacitor C2 is connected between the second node N2 and the first node N1. The second capacitor C2 can be charged with charges corresponding to the data signal DATA. In addition, the second capacitor C2 can control the voltage of the second node N2 according to the voltage change of the first node N1.

[0083] The anode electrode of the organic light emitting diode LD may be connected to the second electrode of the sixth transistor T6, and the cathode electrode may be connected to the second power voltage supply line ELVSSL (e.g., configured to supply a second power voltage or a low voltage (e.g., a ground voltage)). According to some example embodiments, the organic light emitting diode LD may be an inorganic light emitting diode or a quantum dot light emitting diode.

[0084] According to some example embodiments, transistors T1 to T7 may be P-type (PMOS) transistors. The channels of transistors T1 to T7 may be configured by polysilicon. The polysilicon transistors may be low-temperature polysilicon (LTPS) transistors. Polysilicon transistors have relatively high electron mobility, and therefore polysilicon transistors have relatively fast driving characteristics.

[0085] However, the embodiments are not limited to the type of transistors. For example, according to some example embodiments, transistors T1 to T7 may be N-type (NMOS) transistors. In this case, the channels of transistors T1 to T7 may be configured by oxide semiconductors. Compared to polysilicon transistors, oxide semiconductor transistors can be processed at low temperatures and have low charge mobility. Therefore, the amount of leakage current generated by the oxide semiconductor transistor in the off state is less than the amount of leakage current generated by the polysilicon transistor in the off state.

[0086] According to some example embodiments, the first transistor T1, the second transistor T2, and the fifth to seventh transistors T5 to T7 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors. According to some example embodiments, the seventh transistor T7 may be configured as an N-type oxide semiconductor transistor instead of a polysilicon transistor. In this case, one of the second scan line SL2(j+1) and the third scan line SL3(j+1) may be connected to the gate electrode of the seventh transistor T7 instead of the first scan line SL1(j+1).

[0087] In some embodiments, the display device 1 may include a parasitic capacitor Cp formed by coupling between the second node N2 and a line adjacent to the second node N2 .

[0088] Next, we will refer to Figures 4 to 7The driving method of the display device 1 including the pixel PX described above will be described in more detail. However, the following driving method is not limited to the display device 1 including the pixel PX having the circuit diagram described above, but can also be applied to a display device including a pixel circuit that includes two capacitors and is supplied with a reference voltage and an initialization voltage. In addition, the driving method according to the embodiments of the present disclosure can be applied to any other suitable pixel circuit without departing from the spirit and scope of the embodiments of the present invention.

[0089] Figure 4 is a flowchart illustrating a portion of a display device driving method according to some example embodiments of the present disclosure. Figure 5 is a conceptual diagram illustrating the order of each frame period in a display device driving method according to some example embodiments of the present disclosure. Figure 6 is a timing diagram illustrating writing of a light emitting control signal, a scan signal, and a data signal for each of consecutive frame periods in a display device driving method according to some example embodiments of the present disclosure.

[0090] Hereinafter, as examples, aspects of some example embodiments will be described in which each of the transistors T1 to T7 in the pixel PX is turned on as a P-type transistor in response to a low logic level signal (e.g., a set or predetermined low logic level signal) to the gate electrode (scan-on signal), and is turned off in response to a high logic level signal (e.g., a set or predetermined high logic level signal) (scan-off signal).

[0091] The pixel PX may receive a light emitting control signal EM of a high logic level to maintain the off state of the organic light emitting diode LD, and may receive a light emitting control signal EM of a low logic level to maintain the on state of the organic light emitting diode LD. According to some example embodiments, the light emitting control signal EM of a high logic level and the light emitting control signal EM of a low logic level may be alternately provided to the pixel PX. A compensation mechanism for compensating for the threshold voltage of the driving transistor may be provided to the pixel PX so that while the off state of the organic light emitting diode LD is maintained in one frame period, when the organic light emitting diode LD is turned on in the next frame period, the organic light emitting diode LD has a target brightness. That is, Figure 5 illustrates a block representing a compensation mechanism in a p-th frame ("p" frame) period, a p+1-th frame ("p+1" frame) period, and a p+2-th frame ("p+2" frame) period as arbitrary consecutive frame periods, and Figure 6 A timing diagram of a p-th frame period and a p+1-th frame period is illustrated. Hereinafter, a driving method of the display device 1 will be described based on a period in which the pixel PX receives the light emission control signal EM of a high logic level.

[0092] refer to Figures 4 to 6 , the driving method of the display device 1 includes providing a compensation signal (S200), providing a reference voltage (S300), providing a data signal (S400), and generating a compensation signal (S500) in each frame period. In exceptional cases, when the display device 1 is driven, providing the compensation signal (S200) may be omitted in the initial frame period. In this specification, each operation is described as being performed sequentially according to the flowchart, but unless the spirit of the present disclosure is changed, the operations shown as being performed continuously may be performed simultaneously (or concurrently), the order of each operation may be changed, some operations may be omitted, additional operations may be further included between each operation, or the time when each operation is performed may at least partially overlap.

[0093] Hereinafter, a description will be given about the p-th frame period, but each operation performed in other frame periods including the p+1-th frame period and the p+2-th frame period is performed substantially the same as each operation performed in the p-th frame period. Therefore, repeated descriptions will be omitted.

[0094] First, according to some example embodiments, the driving method of the display device 1 may further include supplying an initialization voltage ( S100 ) performed before the above-described operations in each frame period.

[0095] In the supply of the initialization voltage (S100), the fourth transistor T4 may be turned on in response to the first scan signal SCAN1[p] of a low logic level, and the initialization voltage VINT may be applied to the second node N2. Furthermore, the seventh transistor T7 may be turned on in response to the first scan signal SCAN1[p] of a low logic level, and the initialization voltage VINT may be applied to the anode electrode of the organic light emitting diode LD. That is, the supply of the initialization voltage (S100) corresponds to initializing the gate electrode of the driving transistor and the anode electrode of the organic light emitting diode LD to the initialization voltage VINT.

[0096] For example, the initialization voltage VINT may be -5V to 5V, but the embodiment is not limited thereto.

[0097] According to some example embodiments, supplying the initialization voltage (S100) may be performed during a period of 3 H. Here, 1 H is a time corresponding to a pulse width of the horizontal synchronization signal Hsync, and the absolute period may be set differently according to a frame rate (Hz) and a resolution set in the display device 1.

[0098] Next, according to some example embodiments, providing the reference voltage (S300) may be performed immediately (or simultaneously or concurrently) after the completion of providing the initialization voltage (S100). That is, according to some example embodiments, for each frame period, the period in which providing the initialization voltage (S100) is performed and the period in which providing the reference voltage (S300) is performed may not overlap in time.

[0099] Providing a reference voltage (S300) corresponds to charging a charge corresponding to the reference voltage VREF into the second capacitor C2 and compensating for the threshold voltage of the driving transistor. In providing the reference voltage (S300), the fifth transistor T5 can be turned on in response to the second scan signal SCAN2[p] of a low logic level, and the reference voltage VREF can be applied to the second node N2. Therefore, as much charge as the reference voltage VREF can be charged into the second capacitor C2. In addition, the third transistor T3 can be turned on in response to the second scan signal SCAN2[p] of a low logic level, and the second electrode and gate electrode of the first transistor T1 can be electrically short-circuited. The reference voltage VREF can be charged into the second electrode and gate electrode of the first transistor T1 through the second capacitor C2.

[0100] According to some example embodiments, providing the reference voltage (S300) may be performed during the same period as providing the initialization voltage (S100). For example, providing the reference voltage (S300) may be performed during a 3H period.

[0101] Meanwhile, according to some example embodiments, providing the compensation signal (S200) may be performed after the initialization voltage (S100) is started or before the reference voltage (S300) is finished. For example, providing the compensation signal (S200) may be performed in at least one period from 1 hour before the initialization voltage (S100) is finished to 1 hour after the reference voltage (S300) is started. According to some example embodiments, providing the compensation signal (S200) is performed from 1 hour before the initialization voltage (S100) is finished until the initialization voltage (S100) is finished. That is, providing the compensation signal (S200) may be performed during the 1 hour immediately before the initialization voltage (S100) is finished.

[0102] Providing the compensation signal ( S200 ) corresponds to applying the generated compensation signal to the second node N2 to charge the second capacitor C2 and control the first node N1 and the second node N2 to have the same voltage.

[0103] According to some example embodiments, in providing the compensation signal (S200), the compensation signal may be applied to the second node N2 through the data line DLi. For example, in providing the compensation signal (S200), the second transistor T2 may be turned on in response to the third scan signal SCAN3[p] of a low logic level, and the compensation signal may be provided to the second node N2 through the data line DLi. This will be referred to later. Figure 7 Describe the method for generating the compensation signal.

[0104] The providing of the compensation signal (S200) is completed before the providing of the reference voltage (S300) is completed. Therefore, the threshold voltage compensation level of the driving transistor can be maintained at the same level for each frame period and the target threshold voltage compensation level can be reached for each frame period.

[0105] Next, providing a data signal ( S400 ) may be performed immediately after providing the reference voltage ( S300 ) is finished.

[0106] Providing the data signal ( S400 ) corresponds to charging charges corresponding to the data signal DATA[p] into the second capacitor C2 , so that the organic light emitting diode LD emits light having brightness set to a target value.

[0107] For example, in supplying the data signal ( S400 ), the second transistor T2 may be turned on in response to the third scan signal SCAN3 [p] of a low logic level, and the data signal DATA [p] may be supplied to the second node N2 through the data line DLi.

[0108] At the same time, in some embodiments, since the second capacitor C2 is charged with the charge corresponding to the data signal DATA[p], the data signal provided in the previous frame period can be charged to the gate electrode of the first transistor T1 connected to the second capacitor C2. For example, the data signal D(p-2) provided in the frame period before the previous frame period (for example, the p-2 frame period), the data signal D(p-1) provided in the previous frame period (for example, the p-1 frame period), and the data signal D(p) provided in the corresponding frame period can be written to the gate electrode of the first transistor T1.

[0109] Since the independent scan signals SCAN1[p], SCAN2[p], and SCAN3[p] applied through separate scan lines (e.g., scan lines SL1j, SL2j, and SL3j) are respectively provided to different transistors, providing an initialization voltage (S100), providing a compensation signal (S200), providing a reference voltage (S300), and providing a data signal (S400) are performed. Therefore, providing an initialization voltage (S100), providing a compensation signal (S200), providing a reference voltage (S300), and providing a data signal (S400) can be performed independently without affecting the performance of each of the other operations.

[0110] The driving method of the display device 1 may further include generating a compensation signal in each frame period (S500). According to some example embodiments, the compensation signal D(p)' provided in the providing of the compensation signal (S200_1) performed during the p+1 frame period may be generated after providing the data signal (S400) in the p-th frame period and before providing the compensation signal (S200_1) in the p+1 frame period. In the accompanying drawings, the providing of the compensation signal D(p)' is performed after providing the data signal (S400) in the p-th frame period, and the providing of the compensation signal D(p)' is performed in the providing of the compensation signal (S200_1) performed during the p+1 frame period. However, embodiments according to the present disclosure are not limited thereto.

[0111] In the following, reference will be made to Figure 7 Generating the compensation signal (S500) is described in more detail. A description will be given based on a method of generating the compensation signal D(p)' provided in providing the compensation signal (S200_1) performed during the p+1th frame period.

[0112] Figure 7 is a flow chart illustrating an algorithm for generating a compensation signal in a display device driving method according to some example embodiments.

[0113] refer to Figure 7 Generating the compensation signal (S500) may include comparing a reference voltage VREF with a data signal D(p) provided in the p-th frame period (e.g., the magnitude of the data signal D(p)) (S501), and determining the compensation signal (S511). In generating the compensation signal (S500), the compensation signal D(p)' to be provided to the pixel PX during the (p+1)-th frame period may be generated based on the reference voltage VREF and the data signal D(p) provided during the p-th frame period. According to some example embodiments, the reference voltage VREF may be a constant set to a constant value.

[0114] First, in comparing the reference voltage VREF with the data signal D(p) provided in the p-th frame period (S501), the difference between the reference voltage VREF and the data signal D(p) provided in the p-th frame period is calculated. For example, the parameter α can be obtained by subtracting the data signal D(p) provided in the p-th frame period from the reference voltage VREF.

[0115] In determining the compensation signal ( S511 ), the compensation signal D(p)′ provided in the p+1th frame period may be determined by calculating the determined compensation value and the data signal D(p) provided in the pth frame period.

[0116] When the parameter α is 0, that is, when the reference voltage VREF and the data signal D(p) provided in the pth frame period have the same voltage level, it can be determined that the compensation signal D(p)′ is not provided in the providing compensation signal (S200_1) performed during the p+1th frame period.

[0117] When the parameter α is a negative value, that is, when the data signal D(p) provided in the p-th frame period has a voltage level greater than the voltage level of the reference voltage VREF, a compensation signal D(p)' may be determined corresponding to α in determining the compensation signal (S511). The compensation signal D(p)' may be obtained by calculating the parameter α and the parameter β. Here, the parameter β may be provided from a first lookup table. The first lookup table may be separate from the second lookup table used for threshold voltage compensation.

[0118] The compensation signal D(p)' to be provided in the p+1 frame period can be determined by calculating the result (compensation value) of the calculation of the parameter α and the parameter β and the data signal D(p) provided in the p-th frame period. The calculation may include multiplication. According to some example embodiments, the calculation includes multiplication, but embodiments of the present disclosure are not limited thereto, and the compensation signal D(p)' may be determined by various suitable calculations. The compensation signal D(p)' determined in determining the compensation signal (S511) may be provided to the pixel PX in providing the compensation signal (S200_1) performed during the p+1 frame period.

[0119] When the parameter α is a positive value, that is, when the data signal D(p) provided in the p-th frame period has a voltage level less than the voltage level of the reference voltage VREF, the compensation signal D(p)' may be determined corresponding to α in determining the compensation signal (S511). Similarly, the compensation signal D(p)' may be obtained by calculating the parameter α and the parameter β'. Here, the parameter β' may be provided from a first lookup table.

[0120] The compensation signal D(p)' to be provided in the p+1 frame period can be determined by calculating the result (compensation value) of the calculation of the parameter α and the parameter β' and the data signal D(p) provided in the p-th frame period. Similarly, the calculation can include multiplication. The compensation signal D(p)' determined in the determination of the compensation signal (S511) can be provided to the pixel PX in the provision of the compensation signal (S200_1) performed during the p+1 frame period.

[0121] As a comparative example, assuming that a separate compensation signal D(p)' is not provided, at the time point when the supply of the initialization voltage (S100) ends, the gate electrode of the first transistor T1 may have the voltage level of the initialization voltage VINT, and the first node N1 may have the voltage level of the data signal D(p-1) provided in the previous frame period (e.g., the p-1 frame period). When the supply of the initialization voltage (S100) ends and the supply of the reference voltage (S300) begins, the gate electrode of the first transistor T1 may transition from the voltage level of the initialization voltage VINT to a voltage level corresponding to the difference between the first power voltage ELVDD and the threshold voltage, and the first node N1 may transition from the voltage level of the data signal D(p-1) provided in the previous frame period to the voltage level of the reference voltage VREF. Depending on the voltage level of the data signal D(p-1) provided in the previous frame period, the first node N1 may have a difference in voltage level for each frame period. For example, the voltage of the first node N1 may correspond to a value obtained by multiplying the difference between the reference voltage VREF and the data signal D(p-1) provided in the previous frame period by a proportional constant K. Here, the proportional constant K may be applied to the following formula 1:

[0122] Formula 1

[0123] K=CC2 / (CC2+CCp)

[0124] Wherein CC2 is the capacitance of the second capacitor C2, and CCp is the capacitance of the parasitic capacitor Cp.

[0125] Therefore, due to the coupling effect of the parasitic capacitor Cp in providing the reference voltage ( S300 ), the voltage of the gate electrode of the first transistor T1 may be changed for each frame period.

[0126] According to some example embodiments of the present disclosure, before providing the reference voltage at the end of each frame period (S300), a compensation signal D(p)' generated based on the data signal (e.g., D(p)) provided in the previous frame period (e.g., the p-th frame period) and the reference voltage VREF is provided in 'Providing Compensation Signal (e.g., S200_1)', and thus the voltage deviation of the first node N1 and the gate electrode of the first transistor T1 can be reduced. In other words, before providing the data signal (e.g., D(p+1)), the voltage between the first node N1 and the second node N2 (i.e., the voltage between the two ends of the second capacitor C2) can be set to very close to zero by providing the compensation signal D(p)'. In this specification, the term "very close to a certain value" means a situation where "can be considered to be substantially the same as the corresponding value."

[0127] Next, a display device driving method according to some example embodiments will be described. Figures 1 to 7 The same or similar components will be described herein and the same or similar reference numerals will be used.

[0128] Figure 8 is a conceptual diagram illustrating the order of each frame period in a display device driving method according to some example embodiments. Figure 9 It is an icon Figure 8 Flowchart of an algorithm for generating a compensation signal in an embodiment of the present invention.

[0129] refer to Figure 8 and Figure 9 In the display device driving method according to some example embodiments, providing the compensation signal (S200_2) may change the voltage level of the reference voltage VREF as the compensation signal for each frame period. According to some example embodiments, the voltage level of the reference voltage VREF provided for each frame period may be different.

[0130] As a compensation signal provided in one frame period (e.g., the p+1th frame period), a reference voltage VREF' changed from the reference voltage VREF of the previous frame period (e.g., the pth frame period) may be provided. That is, according to some example embodiments, providing the compensation signal (S200_2) may correspond to changing the reference voltage VREF. In other words, providing the reference voltage (S300_1) may be performed after changing the reference voltage VREF. In addition, generating the compensation signal (S500_1) may correspond to determining the reference voltage VREF' to be changed.

[0131] The voltage level of the reference voltage VREF may be adjusted by a reference voltage controller 74 in the power supply 70 .

[0132] After providing the compensation signal (changing the reference voltage VREF) (S200_3), the reference voltage VREF' changed from the previous frame period can be applied to the second node N2 in providing the reference voltage (S300_1) to charge the second capacitor C2, and the first node N1 and the second node N2 can be controlled to have the same voltage level.

[0133] The reference voltage VREF′ changed into the compensation signal to be provided in the p+1th frame period may be determined by various methods.

[0134] As an example, the changed reference voltage VREF′ as the compensation signal to be provided in the p+1th frame period may be determined by applying (eg, multiplying) a parameter to (eg, multiplying) the reference voltage VREF provided in the pth frame period.

[0135] Generating the compensation signal (S500_1) may include comparing a reference voltage VREF provided in the p-th frame period with a data signal D(p) provided in the p-th frame period and determining the compensation signal (S511). The reference voltage VREF' to be provided in the p+1-th frame period may be determined by determining the compensation signal (S511).

[0136] First, in comparing the reference voltage VREF provided in the p-th frame period with the data signal D(p) provided in the p-th frame period, a difference between the reference voltage VREF provided in the p-th frame period and the data signal D(p) provided in the p-th frame period is calculated. For example, the parameter α can be obtained by subtracting the data signal D(p) provided in the p-th frame period from the reference voltage VREF.

[0137] When the parameter α is 0, that is, when the reference voltage VREF and the data signal D(p) provided in the pth frame period have the same voltage level, it can be determined that the compensation signal is not provided in the providing reference voltage (300_1) performed during the p+1th frame period.

[0138] When the parameter α is a negative value, that is, when the data signal D(p) provided in the p-th frame period has a voltage level greater than the voltage level of the reference voltage VREF, the reference voltage VREF' corresponding to the change in α can be determined in determining the compensation signal (S511). The changed reference voltage VREF' can be obtained by calculating the parameter α and the parameter β. Here, the parameter β can be provided from a first lookup table. The first lookup table can be separate from the second lookup table used for threshold voltage compensation.

[0139] The reference voltage VREF' to be provided as the compensation signal in the p+1 frame period can be determined by calculating the result of the calculation of the parameter α and the parameter β and the reference voltage VREF provided in the p-th frame period. The calculation may include multiplication. The reference voltage VREF' determined in determining the compensation signal (S511) can be provided to the pixel PX in providing the reference voltage (300_1) performed during the p+1 frame period.

[0140] When the parameter α is a positive value, that is, when the data signal D(p) provided in the p-th frame period has a voltage level less than the voltage level of the reference voltage VREF, the reference voltage VREF' corresponding to the change in α can be determined in determining the compensation signal (S511). Similarly, the compensation signal can be obtained by calculating the parameter α and the parameter β'. Here, the parameter β' can be provided from the first lookup table.

[0141] The reference voltage VREF' to be provided as the compensation signal in the p+1 frame period can be determined by calculating the result of the calculation of the parameter α and the parameter β' and the reference voltage VREF provided in the p-th frame period. The calculation may include multiplication. The reference voltage VREF' determined in determining the compensation signal (S511) can be provided to the pixel PX in providing the reference voltage (300_1) performed during the p+1 frame period.

[0142] Since the reference voltages VREF, VREF′, and VREF″ that are changed for each frame period are provided to the pixel in providing the reference voltage (S300 and S300_1), the voltage deviation of the first node N1 and the gate electrode of the first transistor T1 can be reduced. In other words, by changing the reference voltages VREF, VREF′, and VREF″ for each frame period, the voltage between the first node N1 and the second node N2 (i.e., the voltage between both ends of the second capacitor C2) can be set to be very close to zero.

[0143] As another example, the changed reference voltage VREF′ as the compensation signal to be provided in the p+1th frame period may be determined as a voltage level charged in the second node N2 in the pth frame period.

[0144] For example, the voltage level of the changed reference voltage VREF′ to be supplied in the p+1th frame period may be determined to be equal to the voltage level of the data signal D(p) supplied in the pth frame period.

[0145] In this way, the voltage deviation between the first node N1 and the gate electrode of the first transistor T1 can be reduced. In other words, the voltage between the first node N1 and the second node N2 (ie, the voltage between the two ends of the second capacitor C2) can be set to be very close to zero by providing the compensation signal.

[0146] Figure 10 is a timing diagram illustrating writing of a light emitting control signal, a scan signal, and a data signal for each of consecutive frame periods in a display device driving method according to some example embodiments.

[0147] refer to Figure 10 According to the display device driving method of this embodiment, Figure 6 The embodiment is different in that, in each frame period, a period during which the data signal DATA[p] is supplied to each pixel PX is different from a period during which the reference voltage VREF is supplied and a period during which the initialization voltage VINT is supplied.

[0148] According to some example embodiments, in each frame period, the period during which the data signal DATA[p] is written to each pixel PX may be longer than the period during which the reference voltage VREF is written and the period during which the initialization voltage VINT is written. That is, for each frame period, the period during which the data signal is provided (S400) may be longer than the period during which the reference voltage is provided (S300). For example, the period during which the initialization voltage VINT is written to each pixel PX may be 3 hours or less, and the period during which the data signal DATA[p] is written may be 5 hours or more.

[0149] In other words, the scan-on period of the second transistor T2 for writing the data signal DATA[p] may be longer than the scan-on periods of the third to fifth transistors T3 to T5 and the seventh transistor T7 for writing the reference voltage VREF or the initialization voltage VINT.

[0150] Due to the structure of the pixel PX including two capacitors, a period during which the data signal DATA[p] is supplied, a period during which the reference voltage VREF is written, and a period during which the initialization voltage VINT is written can be independently controlled.

[0151] Therefore, the time for writing the data signals D(p) and D(p+1) to each pixel PX can be sufficiently ensured for each frame period.

[0152] Figure 11 is a timing diagram illustrating writing of a light emitting control signal, a scan signal, and a data signal for each of consecutive frame periods in a display device driving method according to some example embodiments.

[0153] refer to Figure 11 According to the display device driving method of this embodiment, Figure 6The embodiment of the present invention is different in that the period during which the reference voltage VREF is supplied overlaps at least partially with the period during which the initialization voltage VINT is supplied. For each frame period, supplying the initialization voltage (S100) and supplying the reference voltage (S300) may overlap at least partially in time.

[0154] According to some example embodiments, the initialization voltage VINT may begin to be supplied first, and before the supply of the initialization voltage VINT ends, the reference voltage VREF may begin to be supplied. After the supply of the initialization voltage VINT ends, the supply of the reference voltage VREF may end. For example, the period during which the reference voltage VREF is supplied and the period during which the initialization voltage VINT is supplied may overlap during approximately 1H.

[0155] In other words, the scan-on periods of the third to fifth transistors T3 to T5 and the seventh transistor T7 for writing the reference voltage VREF or the initialization voltage VINT may overlap at least partially.

[0156] According to some example embodiments, the compensation signals D(p-1)' and D(p)' may be provided during a period in which the reference voltage VREF is provided and a period in which the initialization voltage VINT is provided. However, the time when the compensation signals D(p-1)' and D(p)' are provided is not limited thereto.

[0157] Figure 12 and Figure 13 is a timing diagram illustrating writing a light emitting control signal, a scan signal, and a data signal to one pixel PX for each of adjacent frame periods in the display device 1 according to some example embodiments.

[0158] refer to Figure 12 and Figure 13 According to the display device driving method of this embodiment, Figure 6 The embodiment of FIG. 1 is different in that the compensation signals D(p-1)' and D(p)' are written at different times.

[0159] like Figure 12 As shown in FIG, the compensation signals D(p-1)' and D(p)' may be provided before the initialization voltage VINT ends, and may be provided after the reference voltage VREF starts.

[0160] In addition, if Figure 13 As shown in , the compensation signals D(p-1)' and D(p)' may start to be provided when the reference voltage VREF is provided, and may end to be provided before the supply of the reference voltage VREF ends.

[0161] The electronic or electrical devices and / or any other related devices or components according to the embodiments of the present invention described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of these devices can be processes or threads that execute computer program instructions and interact with other system components in one or more computing devices, running on one or more processors to perform the various functions described herein. The computer program instructions are stored in a memory that can be implemented in a computing device using a standard storage device (such as, for example, a random access memory (RAM)). The computer program instructions can also be stored in other non-transitory computer-readable media, such as, for example, a CD-ROM or a flash drive. In addition, those skilled in the art will recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a specific computing device can be distributed across one or more other computing devices without departing from the spirit and scope of the exemplary embodiments of the present invention.

[0162] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, those skilled in the art will appreciate that the embodiments may be implemented in other specific forms without changing the technical spirit and essential features of the present disclosure. Therefore, it should be understood that the embodiments described above are illustrative in all aspects and not restrictive.

Claims

1. A display device driving method, comprising: providing a reference voltage for compensating for a threshold voltage of a drive transistor in a pixel; and providing data signals to the pixels, wherein providing the reference voltage and providing the data signal to the pixel are performed in a first frame period and a second frame period following the first frame period, The display device driving method further comprises: before the supply of the reference voltage ends, supplying a compensation signal generated by comparing a data signal supplied in a previous frame period of each frame period with a reference voltage to the pixel, The process of generating the compensation signal to be provided in the second frame period includes: comparing a reference voltage provided in the first frame period with a magnitude of a data signal provided in the first frame period; and determining the compensation signal to be provided in the second frame period, The determining of the compensation signal includes: determining the compensation signal by calculating the data signal and a compensation value provided in the first frame period.

2. The display device driving method according to claim 1, further comprising: During each frame period, an initialization voltage is supplied to the pixel to initialize a voltage level of a gate electrode of the driving transistor.

3. The display device driving method according to claim 2, wherein: In each frame period, supplying the initialization voltage, supplying the reference voltage, and supplying the data signal sequentially start, wherein in each frame period, providing the compensation signal is performed after starting to provide the initialization voltage, and In each frame period, providing the initialization voltage and providing the reference voltage do not overlap in time.

4. The display device driving method according to claim 1, wherein: In each frame period, a length of time during which supply of the reference voltage is performed and a length of time during which supply of the data signal is performed are different from each other.

5. The display device driving method according to claim 1, wherein: The data signal and the compensation signal are provided through the same data line.

6. The display device driving method according to claim 1, wherein: determining the compensation value by calculating a first parameter provided from a lookup table and a second parameter generated by comparing the reference voltage with the magnitude of the data signal, and wherein the calculation comprises multiplication.

7. The display device driving method according to claim 1, wherein: The pixels include: a pixel circuit connected to a first power voltage supply line and a second power voltage supply line configured to supply a power voltage, a plurality of scan lines configured to supply scan signals, a data line configured to supply the data signal, and a reference voltage supply line configured to supply the reference voltage; and an organic light emitting diode connected to the pixel circuit, The pixel circuit includes a plurality of transistors and a plurality of capacitors.

8. A display device driving method, comprising: providing a reference voltage for compensating for a threshold voltage of a driving transistor in a pixel during a first frame period; During the first frame period, providing a data signal to the pixel through a data line; and generating a compensation signal supplied to the pixel during a second frame period following the first frame period by comparing the reference voltage supplied during the first frame period with the data signal, The generating of the compensation signal includes: determining the compensation signal by calculating the data signal and a compensation value provided in the first frame period.

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