Memory with automatic background preprocessing at power up

Abstract

Disclosed herein are memory devices and systems with automatic background preprocessing at power-up and associated methods. In one embodiment, a memory device includes a memory array having a plurality of memory cells and a fuse array configured to store preprocessing data. The preprocessing data may identify a portion of the memory array, specify a predetermined preprocessing state, or a combination thereof. When the memory device is powered on, the memory device may be configured to automatically retrieve the preprocessing data from the fuse array and / or write memory cells in the portion of the memory array to the predetermined preprocessing state before executing an access command.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application contains subject matter related to concurrently filed U.S. patent application by Anthony D. Veches et al., entitled "Memory With Automatic Background Preprocessing at Power Up," assigned to Micron Technology, Inc., identified by attorney docket number 010829-9390.US01, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to memory systems, devices and associated methods. In particular, the present disclosure relates to memory devices with automatic background preprocessing at power up. Background Art

[0004] Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. In computers or other electronic devices, memory devices are usually provided as internal, semiconductor, integrated circuit and or external removable devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory, including static random access memory (SRAM), dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM), etc., may need to apply power to maintain its data. In contrast, non-volatile memory can maintain its stored data even when there is no external power supply. Non-volatile memory can be used in a variety of technologies, including flash memory (e.g., NAND and NOR) phase change memory (PCM), ferroelectric random access memory (FeRAM), resistance random access memory (RRAM) and magnetic random access memory (MRAM), etc. Improving memory devices can generally include increasing memory cell density, increasing read / write speed or otherwise reducing operation latency, increasing reliability, increasing data retention, reducing power consumption or reducing manufacturing costs and other metrics. Summary of the invention

[0005] In one aspect, the present disclosure relates to a memory device comprising: a memory array including a plurality of memory cells arranged at intersections of memory rows and memory columns, wherein the memory device is configured to write at least a portion of the memory array to a predetermined data state during a power-up operation of the memory device, wherein the predetermined data state comprises a plurality of bits.

[0006] In another aspect, the present disclosure relates to a method comprising: receiving an indication that a memory device is being powered on, the memory device comprising a memory array having a plurality of memory cells arranged at intersections of a plurality of memory rows and a plurality of memory columns; in response to the indication, prior to executing an access command, writing at least a portion of the memory array to a predetermined data state, wherein the predetermined data state comprises a plurality of bits.

[0007] In a further aspect, the present disclosure relates to a memory device comprising: a memory array having a plurality of memory cells; and a fuse array having a plurality of anti-fuse elements configured to store pre-processed data, wherein the memory device is configured to retrieve the pre-processed data from the fuse array when the memory device is powered on and before executing a command from a host device; and write one or more memory cells of the plurality of memory cells to a predetermined data state, wherein the predetermined data state comprises a plurality of bits, at least one of the plurality of bits having a value different from other bits of the plurality of bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Many aspects of the present disclosure may be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale. Instead, emphasis is placed on clearly illustrating the principles of the present disclosure. The drawings should not be considered to limit the present disclosure to the specific embodiments depicted, but are merely for explanation and understanding.

[0009] Figure 1 is a block diagram schematically illustrating a memory system configured according to various embodiments of the present technology.

[0010] Figure 2 is a flow chart illustrating a background pre-processing routine of a memory device configured in accordance with various embodiments of the present technology.

[0011] Figure 3 is a schematic diagram of a system including a memory device configured in accordance with various embodiments of the present technology. DETAILED DESCRIPTION

[0012] As discussed in more detail below, the techniques disclosed herein relate to memory systems and devices (and associated methods) that precondition all or a subset of a memory array to a desired state as part of a background operation that is automatically performed when the memory device is powered on. However, those skilled in the art will appreciate that the techniques may have additional embodiments and may be used without reference to the following. Figures 1 to 3The technology is practiced without the need for several details of the embodiments described. In the embodiments shown below, memory devices and systems are described primarily in the context of devices incorporating DRAM storage media. However, memory devices configured according to other embodiments of the present technology may include other types of memory devices and systems incorporating other types of storage media, including PCM, SRAM, FRAM, RRAM, MRAM, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEROM), ferroelectric, magnetoresistive and other storage media, including non-volatile, flash (e.g., NAND and / or NOR) storage media.

[0013] A host memory system typically includes one or more memory devices for storing information. The host memory system may employ one or more security measures to prevent malicious actors from reading and / or manipulating information while the memory devices are installed in the host memory system. For example, when a malicious actor issues a read request identifying a memory address corresponding to a restricted portion of a memory array of a memory device, the host memory system may prevent the malicious actor from accessing information stored in the restricted portion of the memory array by returning an error message and / or invalid data in response to the read request. As another example, the host memory system may restrict certain commands (e.g., read, write, or other access commands) to only authorized users.

[0014] When the information is stored on the memory cells of the volatile memory device, the host system is configured to periodically refresh the memory cells to prevent data loss caused by charge leakage. When the volatile memory device is powered off or otherwise disconnected from the power supply, the memory cells of the volatile memory device are no longer refreshed. In the absence of an intermediate power supply, charge leaks from the memory cells until the information stored on the memory cells is damaged (e.g., can no longer be accurately read). However, this damage process is not immediate. Therefore, the information can remain accurately readable for a period of time after the volatile memory device is powered off or otherwise disconnected from the power supply. As a result, malicious actors may potentially extract information stored on conventional memory devices by quickly transferring (e.g., hot swapping) conventional memory devices from the host memory system to a hostile memory system that does not employ the above-mentioned security measures or is configured to circumvent such security measures.

[0015] To address this problem, several embodiments of the present technology are directed to memory devices, systems including memory devices, and methods of operating memory devices, in which memory cells in a memory array of the memory device are programmed to a desired (predetermined) state as part of a background operation that is automatically performed during power-up of the memory device (e.g., before the memory device executes an access or other command received from a user, a memory controller, and / or a host device). In some embodiments, the desired state may be a known state (e.g., a predetermined data string) stored in a fuse array of the memory device. In these and other embodiments, when the memory device is powered on, the memory device may automatically program all or a subset of the memory array to a known state. In these and other embodiments, the desired state may be a random (e.g., corrupted) state, and the memory device may automatically program all or a subset of the memory array to a random state during power-up by stimulating multiple rows of memory cells in the memory array without powering corresponding sense amplifiers, so that nearby rows of memory cells overwrite each other with their data and become corrupted. Under either method, after the memory device is powered off or otherwise disconnected from a power source, any valid information remaining on the memory cells is automatically overwritten and / or corrupted when the memory device is powered on.

[0016] Figure 1 1 is a block diagram schematically illustrating a memory system 190 configured according to an embodiment of the present technology. The memory system 190 may include a memory device 100, which may be connected to any one of a plurality of electronic devices or components thereof that can utilize memory to temporarily or permanently store information. For example, the memory device 100 may be operably connected to a host device 108 and / or a memory controller 101. For example, the host device 108 may be operably connected to the memory device 100, which may be a computing device such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet, a digital reader, a digital media player), or some component thereof (e.g., a central processing unit, a coprocessor, a dedicated memory controller, etc.). The host device 108 may be a networking device (e.g., a switch, a router, etc.) or a recorder of digital images, audio, and / or video, a vehicle, an appliance, a toy, or any of a variety of other products. In one embodiment, host device 108 may be directly connected to memory device 100, although in other embodiments, host device 108 may be indirectly connected to memory device 100 (eg, through a network connection or through an intermediary device, such as through memory controller 101).

[0017] The memory device 100 may employ a plurality of external terminals, including command and address terminals coupled to a command bus and an address bus to receive a command signal CMD and an address signal ADDR, respectively. The memory device may further include a chip select terminal receiving a chip select signal CS, a clock terminal receiving clock signals CK and CKF, a data clock terminal receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI and DMI, and power supply terminals VDD, VSS and VDDQ.

[0018] The power supply terminals of the memory device 100 may be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS may be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 may generate various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS. The internal potential VPP may be used in the row decoder 140, the internal potentials VOD and VARY may be used in the sense amplifier included in the memory array 150 of the memory device 100, and the internal potential VPERI may be used in many other circuit blocks.

[0019] The power supply terminal may also be supplied with a power supply potential VDDQ. The power supply potential VDDQ may be supplied to an input / output (IO) circuit 160 together with the power supply potential VSS. In an embodiment of the present technology, the power supply potential VDDQ may be the same potential as the power supply potential VDD. In another embodiment of the present technology, the power supply potential VDDQ may be a potential different from the power supply potential VDD. However, a dedicated power supply potential VDDQ may be used for the IO circuit 160 so that the power supply noise generated by the IO circuit 160 does not propagate to other circuit blocks.

[0020] The clock terminal and the data clock terminal may be supplied with an external clock signal and a complementary external clock signal. The external clock signals CK, CKF, WCK, and WCKF may be supplied to the clock input circuit 120. The CK and CKF signals may be complementary, and the WCK and WCKF signals may also be complementary. The complementary clock signals may have opposite clock levels and simultaneously switch between opposite clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. In addition, when the clock signal is switched from a low clock level to a high clock level, the complementary clock signal is switched from a high clock level to a low clock level, and when the clock signal is switched from a high clock level to a low clock level, the complementary clock signal is switched from a low clock level to a high clock level.

[0021] An input buffer included in the clock input circuit 120 may receive an external clock signal. For example, when enabled by the CKE signal from the command decoder 115, the input buffer may receive the CK and CKF signals and the WCK and WCKF signals. The clock input circuit 120 may receive an external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK may be supplied to the internal clock circuit 130. The internal clock circuit 130 may provide various phase and frequency controlled internal clock signals based on the internal clock signal ICLK and the clock enable signal CKE received from the command decoder 115. For example, the internal clock circuit 130 may include a clock path (not shown) that receives the internal clock signal ICLK and provides various clock signals (not shown) to the command decoder 115. Figure 1 140). The internal clock circuit 130 may further provide an input / output (IO) clock signal. The IO clock signal may be supplied to the IO circuit 160 and may be used as a timing signal for determining the output timing of read data and the input timing of write data. The IO clock signal may be provided at a plurality of clock frequencies so that data may be output from the memory device 100 and input to the memory device 100 at different data rates. When a high memory speed is desired, a higher clock frequency may be desired. When lower power consumption is desired, a lower clock frequency may be desired. The internal clock signal ICLK may also be supplied to the timing generator 135, and thus may generate various internal clock signals that may be used by the command decoder 115, the column decoder 145, and / or other components of the memory device 100.

[0022] The memory device 100 may include an array of memory cells, such as the memory array 150. The memory cells of the memory array 150 may be arranged in a plurality of memory regions, and each memory region may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at the intersections of the word lines and the bit lines. In some embodiments, the memory region may be one or more memory banks, one or more memory rows in a memory bank, or another arrangement of memory cells. In these and other embodiments, the memory regions of the memory array 150 may be arranged in one or more groups (e.g., one or more memory bank groups, one or more logical memory columns or dies, etc.). The memory cells in the memory array 150 may include any of many different memory media types, including capacitive, magnetoresistive, ferroelectric, phase change, etc. The selection of the word lines WL may be performed by the row decoder 140, and the selection of the bit lines BL may be performed by the column decoder 145. A sense amplifier (SAMP) may be provided for the corresponding bit line BL and connected to at least one corresponding local I / O line pair (LIOT / B), which in turn may be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmission gate (TG), which may function as a switch. The memory array 150 may also include plate lines and corresponding circuitry for managing their operation.

[0023] The command terminal and the address terminal may be supplied with an address signal and a body address signal from outside the memory device 100. The address signal and the body address signal supplied to the address terminal may be transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 may receive the address signal and supply a decoded row address signal (XADD) to the row decoder 140, and supply a decoded column address signal (YADD) to the column decoder 145. The address decoder 110 may also receive a body address signal (BADD) and supply the body address signal to both the row decoder 140 and the column decoder 145.

[0024] The command and address terminals may be supplied with a command signal CMD, an address signal ADDR, and a chip select signal CS (e.g., from the memory controller 101 and / or the host device 108). The command signal may represent various memory commands (e.g., including access commands, which may include read commands and write commands). The selection signal CS may be used to select the memory device 100 in response to the command and address provided to the command and address terminals. When a valid CS signal is provided to the memory device 100, the command and address may be decoded and a memory operation may be performed. The command signal CMD may be provided to the command decoder 115 as an internal command signal ICMD via the command / address input circuit 105. The command decoder 115 may include a circuit that decodes the internal command signal ICMD to generate various internal signals and commands for performing memory operations, for example, a row command signal for selecting a word line and a column command signal for selecting a bit line. The internal command signal may also include output and input activation commands, such as a clock control command CMDCK (not shown) to the command decoder 115. The command decoder 115 may further include one or more registers 118 for tracking various counts or values ​​(e.g., a count of refresh commands received by the memory device 100 or self-refresh operations performed by the memory device 100; memory regions enabled for refresh operations; memory cells, memory rows, memory columns, memory banks, logical memory banks or dies, and / or other memory regions that were last programmed and / or are to be programmed; etc.).

[0025] When a read command is issued, and the row address and the column address are supplied with the read command in time, read data can be read from the memory cells in the memory array 150 specified by these row addresses and column addresses. The read command can be received by the command decoder 115, and the command decoder 115 can provide an internal command to the IO circuit 160, and the read data is output from the data terminals DQ, RDQS, DBI, and DMI via the read / write (RW) amplifier 155 and the IO circuit 160 according to the RDQS clock signal. The read data can be provided at a time defined by the read latency information RL, which can be, for example, in the mode register ( Figure 1 The read latency information RL may be defined according to a clock cycle of a CK clock signal. For example, when providing associated read data, the read latency information RL may be a number of clock cycles of the CK signal after the memory device 100 receives a read command.

[0026] When a write command is issued and the row address and column address are supplied with the command in a timely manner, write data may be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command may be received by the command decoder 115, which may provide an internal command to the IO circuit 160, so that the write data may be received by the data receiver in the IO circuit 160 and supplied to the memory array 150 via the IO circuit 160 and the RW amplifier 155. The write data may be written to the memory cell specified by the row address and the column address. The write data may be provided to the data terminal at a time defined by the write wait time WL information. The write wait time WL information may be in the memory device 100, for example, in the mode register ( Figure 1 The write latency information WL may be defined according to the clock cycle of the CK clock signal. For example, when receiving the associated write data, the write latency information WL may be a number of clock cycles of the CK signal after the memory device 100 receives the write command.

[0027] As described herein, the memory array 150 may be refreshed or maintained to prevent data loss due to charge leakage or imprinting effects. As described herein, a refresh operation may be initiated by the memory system 190 (e.g., by the host device 108, the memory controller 101, and / or the memory device 100) and may include accessing one or more rows (e.g., WLs) and discharging the cells of the accessed rows to corresponding SAMPs. When the row is opened (e.g., when the accessed WL is stimulated), the SAMP may compare the voltage generated by the discharged cell with a reference value. The SAMP may then write the logic value (e.g., charge the cell) back to the nominal value of a given logic state. In some cases, this write-back process may increase the charge of the cell to improve the discharge problem described above. In other cases, the write-back process may reverse the data state of the cell (e.g., from high to low or from low to high) to improve hysteresis shift, material depolarization, etc. Other refresh schemes or methods may also be used.

[0028] In one approach, the memory device 100 may be configured to simultaneously refresh the same row of memory cells in each memory bank of the memory array 150. In another approach, the memory device 100 may be configured to sequentially refresh the same row of memory cells in each memory bank of the memory array 150. In yet another approach, the memory device 100 may further include circuitry (e.g., one or more registers, latches, embedded memories, counters, etc.) configured to track row (e.g., word line) addresses, each row address corresponding to one of the memory banks in the memory array 150. In this approach, the memory device 100 is not limited to refreshing the same row in each memory bank of the memory array 150 before refreshing another row in one of the memory banks.

[0029] Regardless of the refresh method, the memory device 100 can be configured to refresh the memory cells in the memory array 150 within a given refresh rate or time window (e.g., 32ms, 28ms, 25ms, 23ms, 21ms, 18ms, 16ms, 8ms, etc.). In these embodiments, the memory system 190 can be configured to supply refresh commands to the memory device 100 according to a specified minimum cadence tREFI. For example, the memory system 190 can be configured to supply one or more refresh commands to the memory device 100 at least every 7.8 μs, so that approximately a minimum of 4000 refresh commands are supplied to the memory device 100 within the 32ms time window.

[0030] The memory device 100 may include a fuse array 143. The fuse array 143 may include an anti-fuse element. The anti-fuse element is an element that is insulated in an initial state and is switched to a conductive state when subjected to dielectric breakdown by a connection operation. After the anti-fuse element is switched to a conductive state, the anti-fuse element cannot return to an insulating state. Therefore, the anti-fuse elements of the fuse array 143 may be used as non-volatile and irreversible storage elements. The anti-fuse elements of the fuse array 143 may be programmed using a conventional anti-fuse programming circuit (not shown).

[0031] In some embodiments, the anti-fuse elements of fuse array 143 can be programmed to store pre-processing data. For example, the anti-fuse elements can be programmed with pre-processing data that specifies that a portion (e.g., all or a subset) of memory array 150 should be programmed to a known state when the memory device is powered on. For example, the known state can contain a predetermined string or sequence of data bits (e.g., all "1"s; all "0"s; alternating "1"s and "0"s; or another string / sequence of data bits) to be programmed into each memory row in the portion of memory array 150. In these and other embodiments, the anti-fuse elements can be programmed with pre-processing data that identifies a portion (e.g., all or a subset) of memory array 150 to be pre-processed when the memory device is powered on.

[0032] As described in more detail below, when the memory device 100 is powered on, the memory device 100 can be configured to automatically read the pre-processing data from the fuse array 143. In embodiments where the pre-processing data specifies a known state to which a portion of the memory array 150 should be programmed, the known state can be automatically loaded into the I / O circuit 160 and subsequently (automatically) written to a portion (all or a subset) of the memory array 150. In this way, any valid information remaining in the memory array 150 of the memory device 100 can be automatically overwritten when the memory device 100 is powered on. In these and other embodiments where the pre-processing data identifies a portion of the memory array 150 to be pre-processed, the pre-processing data can be automatically read into the command decoder 115 of the memory device 100. Using the pre-processing data, the command decoder 115 can generate various internal signals and commands for performing the pre-processing operation, such as row command signals and column select signals for selecting memory rows and columns, respectively, in the portion of the memory array 150 identified in the pre-processing data. Then, the memory device 100 may automatically pre-condition the portion of the memory array 150 identified in the pre-conditioning data to a desired state (eg, a known or random state).

[0033] To program the portion of the memory array 150 to a random state, the memory device 100 may be configured to automatically stimulate a plurality of memory rows in the portion of the memory array 150 without powering corresponding sense amplifiers, so that nearby memory rows overwrite each other with their data and become corrupted. Thus, when the memory device 100 is powered on, any valid information remaining in the portion of the memory array 150 may be automatically corrupted. Preprocessing a portion of the memory array 150 to a random state is faster and consumes less power than preprocessing a portion of the memory array 150 to a known state because the memory device 100 does not retrieve a known state and load it into the IO circuit 160 or another component of the memory device 100, or power the corresponding sense amplifiers, before preprocessing a portion of the memory array 150. Thus, the memory device 100 may be configured to preprocess a portion of the memory array 150 to a random state in a time-saving or power-saving manner.

[0034] Figure 2 2 is a flow chart illustrating a background pre-processing routine 250 of a memory device configured in accordance with various embodiments of the present technology. In some embodiments, the routine 250 may be performed at least in part by various components of the memory device. For example, all or a subset of the steps of the routine 250 may be performed by a fuse array, a command decoder, an IO circuit, and / or a memory array of the memory device.

[0035] Routine 250 may be started at block 251 by receiving an indication that the memory device is being powered on. In some embodiments, the indication that the memory device is being powered on may be one or more potentials supplied to and / or generated by a voltage generator of the memory device. In response to the indication, routine 250 may automatically proceed to block 252 and / or block 253. In this way, routine 250 may be automatically executed without user intervention as an internal background operation of the memory device. In other words, routine 250 may be automatically executed before the memory device executes an access (e.g., read or write) or other command executed from a user, a memory controller, and / or a host device of the memory device. In other embodiments, routine 250 may be started at block 251 when one or more other events occur. For example, routine 250 may be started at block 251 by receiving an indication that a RESET pin of the memory device is asserted and / or that a user has issued a pre-processing data command or sequence (e.g., a data "self-destruct" command).

[0036] At block 252, routine 250 retrieves preprocessing data. All or a subset of the preprocessing data may be stored in a fuse array and / or another component of a memory device. In some embodiments, the preprocessing data may include instructions to preprocess a portion of a memory array to a desired state. For example, the preprocessing data may include instructions to preprocess a portion of a memory array to a known state and / or may specify a predetermined string or sequence of data bits (e.g., all "1"s; all "0"s; alternating "1"s and "0"s; or another string / sequence of data bits) to be programmed into the portion of the memory array. In these and other embodiments, the preprocessing data may include instructions to preprocess a portion of a memory array to a random or corrupted state. In these and other embodiments, the preprocessing data may identify a portion of a memory array for preprocessing. For example, the preprocessing data may include instructions to preprocess the entire memory array to a desired state. In other embodiments, the preprocessing data may include instructions to preprocess a subset of a memory array (e.g., a specific memory row, a specific memory bank, etc.) to a desired state. After retrieving the pre-processed data, the routine 250 may automatically proceed to block 253 to pre-process a portion of the memory array.

[0037] In some embodiments, the routine 250 may be configured to automatically proceed to block 253 to pre-process a portion of the memory array from block 251 to a desired state without retrieving pre-processing data at block 252. For example, in some embodiments, the desired state may be a random or corrupted state (as described in more detail below) such that the routine 250 does not retrieve a known state specified in pre-processing data stored on the memory device. In these and other embodiments, the routine 250 may be configured to pre-process all or a subset of the memory array to a desired state (e.g., by default) such that the routine 250 does not retrieve pre-processing data stored on the memory device identifying a portion of the memory array.

[0038] At block 253, the routine 250 pre-processes a portion of the memory array to a desired state. In embodiments where a portion of the memory array is specified in the pre-processed data retrieved at block 252, the routine 250 may load the pre-processed data into a command decoder, which may issue a row select command to a row decoder and a column select command to a column decoder to pre-process the corresponding portion of the memory array to a desired state.

[0039] As discussed above, the desired state may be a known state and / or a random state. In embodiments where the desired state is a known state specified in the preprocessed data retrieved at block 252, routine 250 may preprocess a portion of a memory array (e.g., a portion identified in the preprocessed data) to the desired state by loading the known state into an IO circuit or another component of the memory device. For example, routine 250 may power up write latches and / or sense amplifiers corresponding to memory rows in the portion of the memory array to a known state. Then, routine 250 may write and / or copy the known state on the portion of the memory array such that routine 250 overwrites any valid information retained in the portion of the memory array prior to execution of routine 250.

[0040] Using a volatile double data rate fourth generation (DDR4) memory device as an example, routine 250 can pre-process the memory array of the memory device by entering write compression and writing a known desired state to all memory banks in the memory array using an X16 memory device configuration. In other embodiments, routine 250 can use a different memory device configuration (e.g., an X4 and / or X8 memory device configuration). In some embodiments, routine 250 can use a larger compression amount than the standard so that routine 250 can write more than one memory column at a time. In these and other embodiments, routine 250 can enter a test mode of the memory device to enable routine 250 to issue more than one activation command to the memory bank. In order to write a known state to the memory array, for each portion of the memory bank, routine 250 can (i) activate the memory row in the portion, (ii) write the corresponding bit of the known state to each memory column in the activated memory row, and (iii) pre-charge the memory row. Assuming that the memory row of the DDR4 memory device contains 2000 bits, routine 250 (in this example) issues 16 write commands to fully program the memory row. Thus, assuming there are 1024 memory rows and 512 sections per section in the memory array, the routine 250 (in this example) can pre-process the entire memory array in approximately 0.05 ms.

[0041] In embodiments where the desired state is a random or corrupted state, the routine 250 may pre-process a portion of the memory array (e.g., the portion identified in the pre-processed data retrieved at block 252) to a random state by stepping through the portion of the memory array in a similar manner (e.g., using compression), but by activating multiple memory rows without powering the sense amplifiers corresponding to the memory rows. In this manner, nearby (e.g., adjacent) memory rows overwrite each other with their data and become corrupted, such that the routine 250 destroys any valid information that remained in the portion of the memory array before the routine 250 was executed. As discussed above, by pre-processing the portion of the memory array to a random state, the routine 250 may save time and power to pre-process the portion of the memory array to a known state.

[0042] Although the steps of routine 250 are discussed and shown in a particular order, Figure 2 The method shown in routine 250 of the present invention is not limited thereto. In other embodiments, the method may be performed in a different order. For example, any step of routine 250 may be performed before, during, and / or after any other step of routine 250. In addition, a person of ordinary skill in the relevant art will readily recognize that the method shown may be changed and still remain within these and other embodiments of the present technology. For example, in some embodiments, the method may be omitted and / or repeated. Figure 2 One or more steps of routine 250 shown in .

[0043] In addition, although DDR4 memory devices are used in the above examples, routine 250 in other embodiments can be used to preprocess other memory devices. For example, routine 250 can be used to preprocess the memory array of a non-volatile memory device. In these and other embodiments, routine 250 can be used to preprocess a memory device using another generation of DDR (e.g., first generation DDR, second generation DDR, third generation DDR, fifth generation DDR, etc.). In these and other embodiments, routine 250 can be used to preprocess a memory array having a greater or lesser number of memory banks, sectors, sectors of each memory bank, memory rows, memory rows of each sector, memory columns, and / or memory columns of each memory row.

[0044] In some embodiments, routine 250 may be enabled or disabled permanently or temporarily. For example, routine 250 may be enabled (e.g., by a manufacturer, by a terminal party, by an intermediary party, etc.) as a security feature on a memory device. When enabled, routine 250 is automatically executed as a background operation without user intervention when the memory device is powered on (e.g., each time, next time, selected subsequent time, etc.). In these and other embodiments, routine 250 may be disabled so that routine 250 is not executed at one or more subsequent power-ups of the memory device. For example, an authorized user (e.g., a supplier, a service technician, etc.) may disable routine 250 to test the device, save power, and / or save data (e.g., in the case of an error, failure, and / or hangup in a host memory system in which a memory device is installed). In these and other embodiments, routine 250 may be disabled only when a previous power-up (e.g., most recently powered-up) of the memory device is executed.

[0045] In some embodiments, routine 250 can be enabled or disabled using the anti-fuse elements of the fuse array. For example, when a first anti-fuse element undergoes dielectric breakdown through a connection operation, routine 250 can be permanently enabled or disabled when the first anti-fuse element switches to a conductive state. In other embodiments, routine 250 can be temporarily enabled or disabled when the first anti-fuse element switches to a conductive state (e.g., until a second anti-fuse element switches to a conductive state). In these and other embodiments, routine 250 can be switched between enabled and disabled. For example, routine 250 can be disabled when the first anti-fuse element switches to a conductive state, enabled when the second anti-fuse element subsequently switches to a conductive state, disabled when the third anti-fuse element subsequently switches to a conductive state, and so on.

[0046] Figure 3 is a schematic diagram of a system including a memory device according to an embodiment of the present technology. Figure 1 and 2 Any of the foregoing memory devices described may be incorporated into any of a myriad of larger and / or more complex systems, a representative example of which is Figure 3 390 is schematically shown in FIG. 390. System 390 may include semiconductor device assembly 300, power supply 392, driver 394, processor 396, and / or other subsystems and components 398. Semiconductor device assembly 300 may include a semiconductor device assembly generally similar to the above referenced Figure 1 and 2The features of the memory device described herein and thus may include various features of automatic background pre-processing after power-up. The resulting system 390 may perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, representative system 390 may include, but is not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of system 390 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Components of system 390 may also include any of a remote device and a variety of computer-readable media.

[0047] in conclusion

[0048] The above detailed description of the embodiments of the technology is not intended to be exhaustive or to limit the technology to the precise form disclosed above. Although specific embodiments and examples of the present technology are described above for illustrative purposes, various equivalent modifications may be made within the scope of the present technology as will be appreciated by those skilled in the relevant art. For example, although the steps are presented and / or discussed in a given order, alternative embodiments may perform the steps in a different order. In addition, the various embodiments described herein may also be combined to provide further embodiments.

[0049] According to the foregoing, it will be understood that the specific embodiments of the technology are described herein for the purpose of illustration, but the well-known structures and functions are not shown or described in detail to avoid unnecessary ambiguity in the description of the embodiments of the technology. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. In addition, unless the word "or" is explicitly limited to only a single item, without involving other items in the list of two or more items, the use of "or" in these lists is interpreted as including any single item in (a) the list, all items in (b) the list, or any combination of items in (c) the list. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. In addition, the terms "include", "include", "have" and "have" are used throughout the text to at least include the listed features, so that any greater number of the same features and / or other types of other features are not excluded. As used herein, the phrase "and / or" in "A and / or B" refers to a single A, a single B, and both A and B.

[0050] Based on the foregoing, it should also be understood that various modifications can be made without departing from the technology. For example, the various components of the technology can be further divided into subcomponents, or the various components and functions of the technology can be combined and / or integrated. In addition, although the advantages associated with certain embodiments of the present technology have been described in the context of those embodiments, other embodiments may also exhibit these advantages, and not all embodiments must exhibit these advantages to fall within the scope of the present technology. Therefore, the present disclosure and associated technology may encompass other embodiments that are not explicitly shown or described herein.

Claims

1. A memory device, comprising: A memory array comprising a plurality of memory cells arranged at intersections of memory rows and memory columns, wherein the memory device is configured such that during a power-on operation of the memory device: reading pre-processed data from a fuse array in response to receiving an indication that the memory device is being powered on, the pre-processed data comprising instructions for writing a predetermined data state to a host accessible portion of the memory array; as well as According to the instructions, prior to executing an access command from a host device to addresses of memory cells in at least the portion of the memory array, at least the portion of the memory array is written to the predetermined data state, wherein the predetermined data state comprises a plurality of bits. 2 . The memory device of claim 1 , wherein the fuse array has an anti-fuse element corresponding to the memory array, and wherein the anti-fuse element is configured to store the pre-processing data.

3. The memory device of claim 2, wherein the pre-processed data identifies the portion of the memory array.

4. The memory device of claim 3, wherein the memory device is further configured to read the pre-processing data from the fuse array to identify the portion of the memory array during the power-up operation of the memory device.

5. The memory device of claim 2, wherein the predetermined data state is a predetermined string or sequence of data bits, and wherein the pre-processing data specifies the predetermined data state.

6. The memory device of claim 5, wherein the memory device is further configured to read the pre-processed data from the fuse array during the power-up operation of the memory device to retrieve the predetermined data state.

7. The memory device of claim 6, wherein the memory device is further configured to write the predetermined data state to each memory row in the portion of the memory array prior to executing the access command.

8. The memory device of claim 1, wherein the predetermined data state is a random data state.

9. The memory device of claim 1, wherein the portion of the memory array includes each memory cell of the plurality of memory cells.

10. The memory device of claim 1, wherein the portion of the memory array includes only a subset of memory cells in the plurality of memory cells.

11. The memory device of claim 1, wherein at least one bit of the plurality of bits has a different value than other bits of the plurality of bits.

12. The memory device of claim 1, wherein each bit of the plurality of bits has a same value.

13. The memory device of claim 1, wherein the memory device is a dynamic random access memory (DRAM) device.

14. A method for operating a memory device, comprising: receiving an indication that the memory device is being powered on, the memory device comprising a memory array having a plurality of memory cells arranged at intersections of a plurality of memory rows and a plurality of memory columns; as well as In response to the instruction: reading pre-processed data from a fuse array, the pre-processed data including instructions for writing a predetermined data state to a host accessible portion of the memory array; as well as According to the instructions, prior to executing an access command from a host device to addresses of memory cells in at least the portion of the memory array, at least the portion of the memory array is written to the predetermined data state, wherein the predetermined data state comprises a plurality of bits.

15. The method of claim 14, further comprising, in response to the indication, automatically reading the pre-processed data before executing the access command.

16. The method of claim 15, wherein the pre-processed data specifies the portion of the memory array, and wherein the method further comprises loading the pre-processed data into a command decoder of the memory device.

17. The method of claim 15, wherein: The predetermined data state is a predetermined string or sequence of data bits; The pre-processed data specifies the predetermined data state; and The method further includes loading the predetermined data state into a write latch of the memory device.

18. The method of claim 17, further comprising using the write latches to write the predetermined data state to the portion of the memory array prior to executing the access command. The method of claim 14 , wherein the predetermined data state is a random data state.

20. The method of claim 14, further comprising: receiving (a) an indication that a RESET pin of the memory device is asserted or (b) a pre-process data command; as well as In response to the indication that the RESET pin of the memory device is asserted or the pre-processed data command, the portion of the memory array is written to the predetermined data state prior to executing the access command.

21. A memory device comprising: a memory array having a plurality of memory cells; as well as a fuse array having a plurality of anti-fuse elements configured to store pre-processed data, Wherein, when the memory device is powered on and before executing a command from a host device directed to an address of a memory cell in the memory array, the memory device is configured to: retrieving the pre-processed data from the fuse array in response to receiving an indication that the memory device is being powered on, the pre-processed data comprising instructions for writing a predetermined data state to a host accessible portion of the memory array; as well as In accordance with the instruction, one or more memory cells of the portion of the memory array are written to the predetermined data state, wherein the predetermined data state comprises a plurality of bits, at least one bit of the plurality of bits having a different value than other bits of the plurality of bits.

22. The memory device of claim 21, wherein the predetermined data state is a predetermined string or sequence of data bits.

23. The memory device of claim 22, wherein the memory device is configured to write the predetermined string or sequence of data bits to the one or more memory cells prior to executing the command from the host device.

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