Semiconductor memory device and method of repairing a semiconductor memory device

Abstract

A semiconductor memory device and a method for controlling the repair of the semiconductor memory device are provided. The semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, input / output (I / O) gating circuitry connected between the memory cell array and the ECC engine, an error information register, and control logic circuitry. The memory cell array includes multiple rows of memory cells. The control logic circuitry controls the ECC engine, the I / O gating circuitry, and the error information register based on commands and addresses. The I / O gating circuitry provides the ECC engine with codewords read from the memory cell array through refresh operations on the multiple rows of memory cells. The ECC engine performs ECC decoding on the main data of the codeword based on the parity bits of the codeword, and provides an error generation signal to the control logic circuitry in response to the detection of a correctable error at the corresponding address due to the ECC decoding.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0106655, filed on August 29, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to memory, and more specifically, to a semiconductor memory device, a memory system including the semiconductor memory device, and a method for controlling the repair of the semiconductor memory device. Background Technology

[0003] Semiconductor memory devices can be classified into non-volatile memory devices (such as flash memory devices) and volatile memory devices (such as DRAM). The high-speed operation and cost efficiency of DRAM make it possible to use DRAM as system memory. However, due to the continuous shrinking of DRAM manufacturing design rules, the number of faulty bits in DRAM memory cells can increase rapidly, and DRAM yield can decrease.

[0004] Storage devices such as flash memory-based solid-state drives (SSDs) are widely used as high-capacity storage media in computing devices. SSDs can store data in non-volatile memory devices (such as flash memory devices) and use volatile memory devices (such as DRAM devices) as buffer memory to manage various information used to control the flash memory devices. When a fault is discovered during the manufacturing process of a DRAM device, the faulty or defective cell can be repaired using various repair schemes. However, when a fault occurs after the DRAM device has been installed in the SSD and the product has been supplied to the user (i.e., after the SSD has been used at the user level), the SSD, other than the DRAM device, may malfunction. Summary of the Invention

[0005] According to an exemplary embodiment, a semiconductor memory device includes: a memory cell array; an error correction code (ECC) engine; an input / output (I / O) gating circuit connected between the memory cell array and the ECC engine; an error information register; and control logic circuitry. The memory cell array includes a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of volatile memory cells. The control logic circuitry controls the ECC engine, the I / O gating circuitry, and the error information register based on commands and addresses received from an external memory controller. The I / O gating circuitry provides the ECC engine with codewords read from the memory cell array through refresh operations on the plurality of memory cell rows. The ECC engine performs ECC decoding on the main data of the codeword based on parity bits of the codeword, and provides an error generation signal to the control logic circuitry in response to the detection of a correctable error at a corresponding address due to the ECC decoding. The control logic circuitry stores error information in the error information register by accumulating location information with correctable errors based on the error generation signal.

[0006] According to an exemplary embodiment, a memory system includes a semiconductor memory device and a memory controller for controlling the semiconductor memory device. The semiconductor memory device includes: a memory cell array; a first error correction code (ECC) engine; an input / output (I / O) gating circuit connected between the memory cell array and the first ECC engine; an error information register; and control logic circuitry. The memory cell array includes a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of volatile memory cells. The control logic circuitry controls the first ECC engine, the I / O gating circuitry, and the error information register based on commands and addresses received from the memory controller. The I / O gating circuitry provides the first ECC engine with codewords read from the memory cell array through refresh operations on the plurality of memory cell rows. The first ECC engine performs ECC decoding on the main data of the codeword based on parity bits of the codeword and is configured to provide an error generation signal to the control logic circuitry in response to the detection of a correctable error at a corresponding address due to the ECC decoding. The control logic circuitry stores error information in the error information register by accumulating location information with correctable errors based on the error generation signal.

[0007] According to an exemplary embodiment, a method for controlling the repair of a semiconductor memory device is provided. The semiconductor memory device includes an error correction code (ECC) engine, an error information register, and a memory cell array including multiple rows of memory cells, each row of memory cells including multiple volatile memory cells. In the method, codewords including master data and parity bits, read from the memory cell array through refresh operations on the multiple rows of memory cells, are provided to the ECC engine; ECC decoding is performed on the master data based on the parity bits by the ECC engine to detect correctable errors for corresponding addresses; error information is stored in the error information register by accumulating location information with correctable errors; and a runtime repair operation is performed on the semiconductor memory device based on the error information stored in the error information register to repair the correctable errors.

[0008] Therefore, during refresh operations, semiconductor memory devices accumulate error information associated with errors occurring during the operation of the semiconductor memory device, and efficiently manage errors occurring during operation based on the accumulated error information without performing data read operations on the memory cell array. Thus, semiconductor memory devices and systems including semiconductor memory devices can benefit from enhanced performance and lifespan due to efficient error management. Attached Figure Description

[0009] The exemplary embodiments will now be described in more detail with reference to the accompanying drawings.

[0010] Figure 1 A block diagram of a memory system according to an exemplary embodiment is shown.

[0011] Figure 2 It is a diagram used to describe the on-chip ECC level based on the data bits and parity bits.

[0012] Figure 3 This illustrates an exemplary embodiment. Figure 1 A block diagram of a semiconductor memory device.

[0013] Figure 4 It shows Figure 3 An example of a first memory bank array in a semiconductor memory device.

[0014] Figure 5 This shows the write operation. Figure 3 It is part of a semiconductor memory device.

[0015] Figure 6 This illustrates the process in a read or refresh operation. Figure 3 Semiconductor memory devices.

[0016] Figure 7An exemplary embodiment is shown. Figure 3 Error information register in semiconductor memory devices.

[0017] Figure 8 This illustrates an exemplary embodiment. Figure 3 A block diagram of the ECC engine in a semiconductor memory device.

[0018] Figure 9 An exemplary embodiment is shown. Figure 8 The ECC decoder in the ECC engine.

[0019] Figure 10 A diagram illustrating a refresh operation in a patrol scan mode of a semiconductor memory device according to an exemplary embodiment.

[0020] Figure 11 This illustrates an exemplary embodiment. Figure 1 A diagram of the cumulative error table in the memory controller.

[0021] Figure 12 This is a flowchart illustrating a method for repairing a controlled semiconductor memory device according to an exemplary embodiment.

[0022] Figure 13 This is a block diagram illustrating a semiconductor memory device performing post-packaging repair operations.

[0023] Figure 14 This is a diagram illustrating the layout of a memory cell array included in a semiconductor memory device according to an exemplary embodiment.

[0024] Figure 15 and Figure 16 This is a diagram illustrating the determination of error attributes in a method for repairing a controlled semiconductor memory device according to an exemplary embodiment.

[0025] Figure 17 This is a diagram illustrating a cumulative error table of a method for repairing a controlled semiconductor memory device according to an exemplary embodiment.

[0026] Figure 18 The diagram illustrates a column repair method according to an exemplary embodiment of a repair of a controlled semiconductor memory device.

[0027] Figure 19 This is a flowchart illustrating a method for repairing a controlled semiconductor memory device according to an exemplary embodiment.

[0028] Figure 20 This is a block diagram illustrating a memory system according to an exemplary embodiment.

[0029] Figure 21This illustrates control according to an exemplary embodiment. Figure 20 A flowchart of a method for repairing a semiconductor memory device.

[0030] Figure 22 This is a block diagram illustrating a semiconductor memory device performing a post-packaging repair operation according to an example embodiment.

[0031] Figure 23 This is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment.

[0032] Figure 24 This is a diagram illustrating a semiconductor package including a stacked memory device according to an exemplary embodiment.

[0033] Figure 25 A block diagram of a solid-state drive (SSD) according to an exemplary embodiment is shown. Detailed Implementation

[0034] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, which illustrate exemplary embodiments.

[0035] Figure 1 This is a block diagram illustrating a memory system according to an exemplary embodiment.

[0036] Reference Figure 1 The memory system 20 may include a memory controller 100 and a semiconductor memory device 200. In some embodiments, the memory system 20 may be as follows: Figure 25 The solid-state drive 1000 shown is shown.

[0037] The memory controller 100 can control the overall operation of the memory system 20. The memory controller 100 can control the overall data exchange between the external host and the semiconductor memory device 200. For example, the memory controller 100 can write data to or read data from the semiconductor memory device 200 in response to a request from the host. Furthermore, the memory controller 100 can issue operating commands to the semiconductor memory device 200 to control its operation.

[0038] In some exemplary embodiments, the semiconductor memory device 200 is a memory device that includes dynamic memory cells (such as dynamic random access memory (DRAM), double data rate 4 (DDR4) synchronous DRAM (SDRAM), DDR5 SDRAM, low power DDR4 (LPDDR4) SDRAM, or LPDDR5 SDRAM).

[0039] The memory controller 100 sends the clock signal CLK, command CMD, and address (signal) ADDR to the semiconductor memory device 200 and exchanges master data MD with the semiconductor memory device 200. The semiconductor memory device 200 sends the accumulated error information AEI to the memory controller 100.

[0040] The memory controller 100 can determine an error management strategy for defective cells in the semiconductor memory device 200 based on accumulated error information AEI.

[0041] The semiconductor memory device 200 includes a memory cell array (MCA) 300 storing master data MD and parity bits, an error correction code (ECC) engine or error checking and correction engine 400, control logic circuitry 210, and an error information register (EIR) 480.

[0042] ECC engine 400 can perform ECC encoding on the written data to generate parity bits and store the written data and parity bits in the target memory cell row (target page) of memory cell array 300. It can also perform ECC decoding on the codeword CW read from the target page under the control of control logic circuitry 210. The codeword CW may include main data and parity bits. Furthermore, ECC engine 400 can perform ECC decoding on the main data based on parity bits provided by memory cell array 300 through periodic or aperiodic refresh operations on memory cell rows in memory cell array 300, and can provide an error generation signal to control logic circuitry 210 in response to the detection of correctable errors in patrol scanning mode (e.g., monitoring operation or patrol read operation). To perform refresh operations periodically or aperiodically in patrol scanning mode, the memory controller can apply commands to the semiconductor memory device. If a semiconductor memory device detects a row or column of memory cells with correctable errors during ECC decoding, the correctable errors can be corrected during a post-package repair (PPR) operation. Control logic 210 can store error information in an error information register 480 by accumulating the location information of the correctable errors based on error generation signals. The location information may include the bank address, row address, and / or column address associated with the row or column of memory cells with the correctable errors.

[0043] The memory controller 100 may include a repair manager (RPMNG) 130 and a cumulative error table (AET) 120. The RPMNG 130 may read the contents of the error information register 480 as cumulative error information AEI and may store the cumulative error information AEI in the AET 120. The repair manager 130 may determine (analyze) the error attributes of each candidate defective memory row in which correctable errors have occurred based on the cumulative error information AEI stored in the cumulative error table 120, and may determine an error management strategy for the candidate defective memory row based on the determined error attributes.

[0044] Figure 2 This is a diagram illustrating the on-die ECC level based on the data bits and parity bits.

[0045] exist Figure 2 In Chinese, SEC stands for Single Error Correction, DED stands for Double Error Detection, and DEC stands for Double Error Correction. Figure 2 The parity bit and its corresponding size overhead (parity O / H) are shown.

[0046] like Figure 2 As shown, as the number of parity bits increases relative to the same number of data bits—for example, as the ratio of parity bits to data bits increases—the ability to detect and correct errors increases. Conversely, as the number of data bits increases relative to the same error detection and correction capability, the corresponding number of parity bits increases, but the ratio of parity bits to data bits decreases.

[0047] Thus, error detection and / or error correction capabilities can increase as the ratio of the number of parity bits to the corresponding number of data bits increases. Consequently, the on-chip ECC level can increase as the ratio of the number of parity bits to the corresponding number of data bits increases. However, since the actual memory capacity decreases as the number of parity bits increases, the error correction capability is limited.

[0048] According to an exemplary embodiment, failures of the semiconductor memory device 200 can be prevented by performing a runtime repair operation based on accumulated error information and error attributes, using relatively low error correction capabilities. Here, a failure of the semiconductor memory device indicates that an error that cannot be corrected by the ECC function has occurred in the volatile memory device. A runtime repair operation refers to the operation of replacing the address where the error has occurred with a repair address while the device or system including the semiconductor memory device (volatile memory device) is operating, to prevent a correctable error from becoming an uncorrectable error. Therefore, the semiconductor memory device or memory system including the semiconductor memory device can improve performance and lifespan by effectively managing errors that occur during operation.

[0049] Figure 3 This illustrates an exemplary embodiment. Figure 1 A block diagram of a semiconductor memory device.

[0050] Reference Figure 3 The semiconductor memory device 200 includes control logic circuitry 210, address register 220, memory bank control logic 230, refresh counter 245, row address multiplexer (RA MUX) 240, column address (CA) latch 250, row decoder 260, column decoder 270, memory cell array 300, sense amplifier unit 285, I / O gate circuitry 290, ECC engine 400, error information register 480, and data I / O buffer 295.

[0051] The memory cell array 300 includes a first memory cell array 310 to an eighth memory cell array 380. The row decoder 260 includes a first memory cell row decoder 260a to an eighth memory cell row decoder 260h respectively connected to the first memory cell array 310 to the eighth memory cell array 380. The column decoder 270 includes a first memory cell column decoder 270a to an eighth memory cell column decoder 270h respectively connected to the first memory cell array 310 to the eighth memory cell array 380. The sense amplifier unit 285 includes a first memory cell sense amplifier 285a to an eighth memory cell sense amplifier 285h respectively connected to the first memory cell array 310 to the eighth memory cell array 380.

[0052] First memory arrays 310 to 380, first memory row decoders 260a to 260h, first memory column decoders 270a to 270h, and first memory sense amplifiers 285a to 285h can form first to eighth memory arrays. Each of the first memory arrays 310 to 380 includes multiple memory cells MC formed at the intersection of multiple word lines WL and multiple bit lines BTL.

[0053] Address register 220 receives address ADDR from memory controller 100, which includes bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR. Address register 220 provides the received bank address BANK_ADDR to bank control logic 230, the received row address ROW_ADDR to row address multiplexer 240, and the received column address COL_ADDR to column address latch 250.

[0054] The memory bank control logic 230 generates a memory bank control signal in response to the memory bank address BANK_ADDR. The memory bank row decoders corresponding to the memory bank address BANK_ADDR in the first memory bank row decoders 260a to the eighth memory bank row decoders 260h are activated in response to the memory bank control signal, and the memory bank column decoders corresponding to the memory bank address BANK_ADDR in the first memory bank column decoders 270a to the eighth memory bank column decoders 270h are also activated in response to the memory bank control signal.

[0055] Row address multiplexer 240 receives row address ROW_ADDR from address register 220 and refresh row address REF_ADDR from refresh counter 245. Row address multiplexer 240 selectively outputs row address ROW_ADDR or refresh row address REF_ADDR as row address RA. Row address RA output from row address multiplexer 240 is applied to first memory bank row decoders 260a to eighth memory bank row decoders 260h.

[0056] The refresh counter 245 can sequentially increase or decrease the refresh row address REF_ADDR under the control of the control logic circuit 210.

[0057] Through the memory bank control logic 230, the activated memory bank row decoders from the first memory bank row decoder 260a to the eighth memory bank row decoder 260h decode the row address RA output from the row address multiplexer 240 and activate the word line corresponding to the row address RA. For example, the activated memory bank row decoder applies a word line drive voltage to the word line corresponding to the row address RA.

[0058] Column address latch 250 receives column address COL_ADDR from address register 220 and temporarily stores the received column address COL_ADDR. In some embodiments, in burst mode, column address latch 250 generates a column address COL_ADDR' incremented from the received column address COL_ADDR. Column address latch 250 applies the temporarily stored or generated column address COL_ADDR' to the first bank column decoders 270a to the eighth bank column decoders 270h.

[0059] The activated bank column decoders in the first bank column decoder 270a to the eighth bank column decoder 270h activate the sense amplifiers corresponding to the bank address BANK_ADDR and the column address COL_ADDR' through the I / O gate circuit 290.

[0060] I / O gating circuit 290 includes circuitry for gating input / output data, and further includes input data masking logic, a read data latch for storing data output from the first memory array 310 to the eighth memory array 380, and a write driver for writing data to the first memory array 310 to the eighth memory array 380. As an example, I / O gating circuit 290 may have first memory array I / O gating circuits to eighth memory array I / O gating circuits respectively coupled to the first memory array 310 to the eighth memory array 380.

[0061] A codeword CW read from one of the memory arrays 310 to 380 is sensed by a sense amplifier of the memory array from which data is to be read and stored in a read data latch. The codeword CW stored in the read data latch can be provided to the memory controller 100 via a data I / O buffer 295 after ECC decoding is performed on the codeword CW by the ECC engine 400.

[0062] To write master data MD to one of the memory bank arrays 310 to 380, it can be provided from memory controller 100 to data I / O buffer 295 and from data I / O buffer 295 to ECC engine 400. ECC engine 400 can perform ECC encoding on master data MD to generate parity bits. ECC engine 400 can provide master data MD and parity bits to I / O gate circuit 290, and I / O gate circuit 290 can write master data MD and parity bits to a subpage of a target page in a memory bank array via a write driver.

[0063] The data I / O buffer 295 can provide the master data MD from the memory controller 100 to the ECC engine 400 during write operations of the semiconductor memory device 200 based on the clock signal CLK, and can also provide the master data MD from the ECC engine 400 to the memory controller 100 during read operations of the semiconductor memory device 200.

[0064] ECC engine 400 performs ECC decoding on codeword CW read from a subpage of the target page, and ECC engine 400 can correct at least one error bit when at least one error bit is detected in the master data MD in codeword CW during a normal read operation of semiconductor memory device 200.

[0065] ECC engine 400 can perform ECC decoding on sensed data and parity bits provided from memory cell array 300 by periodic or non-periodic refresh operations on rows of memory cells in memory cell array 300, and can provide an error generation signal EGS to control logic circuit 210 in response to the detection of a correctable error in patrol scan mode. Control logic circuit 210 can store the row address and / or column address, including the codeword CW of the correctable error, as error information EINF in error information register 480. Control logic circuit 210 can store error information EINF in error information register 480 by accumulating the location information (e.g., address) corresponding to the correctable error based on error generation signal EGS.

[0066] Control logic circuit 210 can respond to a register read command from memory controller 100 by controlling error information register 480 to provide accumulated error information EINF as accumulated error information AEI to memory controller 100. Memory controller 100 can perform a register read operation by reading the accumulated error information AEI from error information register 480 in response to the register read command. Furthermore, when the storage space of error information register 480 is full due to accumulated error information EINF, control logic circuit 210 can provide a notification signal NTS to memory controller 100. Memory controller 100 can then apply a register read command to semiconductor memory device 200 in response to the notification signal NTS.

[0067] Control logic circuit 210 can control the operation of semiconductor memory device 200. For example, control logic circuit 210 can generate control signals for semiconductor memory device 200 to perform write or read operations. Control logic circuit 210 includes command decoder 211 for decoding commands CMD received from memory controller 100 and mode register 212 for setting the operating mode of semiconductor memory device 200.

[0068] For example, the command decoder 211 can generate control signals corresponding to the command CMD by decoding write enable signals, row address strobe signals, column address strobe signals, chip select signals, etc. The control logic circuit 210 can generate a first control signal CTL1 for controlling the I / O gate circuit 290, a second control signal CTL2 for controlling the ECC engine 400, and a third control signal CTL3 for controlling the error information register 480.

[0069] Error information register 480 can respond to the third control signal CTL3 by providing accumulated error information EINF as accumulated error information AEI to memory controller 100 via one of the dedicated pins and data I / O pins.

[0070] Figure 4 It shows Figure 3 An example of a first memory array 310 in a semiconductor memory device.

[0071] Reference Figure 4 The first memory bank array 310 includes multiple word lines WL1 to WLm (m is a natural number equal to or greater than 2), multiple bit lines BTL1 to BTLn (n is a natural number equal to or greater than 2), and multiple memory cells MC disposed at the intersections between the word lines WL1 to WLm and the bit lines BTL1 to BTLn. Each memory cell MC includes a cell transistor coupled to each of the word lines WL1 to WLm and each of the bit lines BTL1 to BTLn, and a cell capacitor coupled to the cell transistor.

[0072] Figure 5 Showing in the write operation Figure 3 It is part of a semiconductor memory device.

[0073] exist Figure 5 The diagram shows control logic circuit 210, first memory array 310, I / O gate circuit 290, and ECC engine 400.

[0074] Reference Figure 5 The first storage array 310 includes a normal cell array (NCA) and a redundant cell array (RCA).

[0075] The normal cell array (NCA) includes multiple first memory blocks MB0 to MB15 (i.e., 311 to 313), and the redundant cell array (RCA) includes at least a second memory block 314. The first memory blocks 311 to 313 are memory blocks that determine the memory capacity of the semiconductor memory device 200. The second memory block 314 is used for ECC and / or redundancy repair. Because the second memory block 314 used for ECC and / or redundancy repair is used for ECC, data line repair, and block repair to repair “faulty” cells generated in the first memory blocks 311 to 313, the second memory block 314 is also referred to as an EDB block. In each of the first memory blocks 311 to 313, multiple first memory cells are arranged in rows and columns. In the second memory block 314, multiple second memory cells are arranged in rows and columns. The multiple first memory cells connected to the intersection of the word line WL and the bit line BTL can be dynamic memory cells. The multiple second memory cells connected to the intersection of the word line WL and the bit line RBTL can be dynamic memory cells.

[0076] I / O gating circuitry 290 includes multiple switching circuits (e.g., multiplexers MUX) 291a to 291d respectively connected to the first memory blocks 311 to 313 and the second memory block 314. In the semiconductor memory device 200, bit lines corresponding to data of burst length (BL) can be accessed simultaneously to support a maximum number of BLs representing accessible column locations. For example, BL can be set to 8.

[0077] The ECC engine 400 can be connected to the switching circuits 291a to 291d via the first data line GIO[0:127] and the second data line EDBIO[0:7]. The control logic circuit 210 can receive the command CMD and the address ADDR, and can decode the command CMD to generate a first control signal CTL1 for controlling the switching circuits 291a to 291d and a second control signal CTL2 for controlling the ECC engine 400.

[0078] When the command CMD is a write command, the control logic circuit 210 provides the second control signal CTL2 to the ECC engine 400. The ECC engine 400 performs ECC encoding on the master data MD to generate a parity bit associated with the master data MD, and provides the codeword CW, which includes the master data MD and the parity bit, to the I / O gating circuit 290. The control logic circuit 210 provides the first control signal CTL1 to the I / O gating circuit 290, so that the codeword CW can be stored in a subpage of the target page in the first memory array 310 through the corresponding data lines in the first data line GIO[0:127] and the second data line EDBIO[0:7].

[0079] Figure 6 This illustrates the process in a read or refresh operation. Figure 3 Semiconductor memory devices.

[0080] exist Figure 6 The diagram shows a control logic circuit 210, a first memory array 310, an I / O gate circuit 290, an ECC engine 400, and an error information register 480.

[0081] Reference Figure 6 When the command CMD is a refresh command used to specify a refresh operation (periodic or non-periodic) or a read command used to specify a read operation, the control logic circuit 210 provides the first control signal CTL1 to the I / O gate circuit 290, so that the codeword CW in the subpage of the target page stored in the first memory array 310 is provided to the ECC engine 400 through the corresponding data lines in the first data line GIO[0:127] and the second data line EDBIO[0:7].

[0082] During the refresh operation in the inspection scan mode, the ECC engine 400 performs ECC decoding on the codeword CW, and provides an error generation signal EGS to the control logic circuit 210 whenever a correctable error is detected in the codeword CW. A counter 214 in the control logic circuit 210 counts the error generation signal EGS, and the control logic circuit 210 records the error information EINF in the error information register 480. The error information EINF may include the number of errors occurring in a selected memory cell row based on the count of the error generation signal EGS.

[0083] During a read operation, the ECC engine 400 performs ECC decoding on the codeword CW of each subpage in the memory cell row. If the ECC engine 400 detects a correctable error bit in the codeword CW, it can correct the correctable error and output the corrected master data C_MD. The control logic circuit 210 can provide the second control signal CTL2 to the ECC engine 400, and the ECC engine 400 can perform ECC decoding.

[0084] Error message EINF may include address information ADDINF, the number of rectifiable errors ECNT, and the number of subpages including error bits FCWCNT.

[0085] Figure 7 An exemplary embodiment is shown. Figure 3 Error information register in semiconductor memory devices.

[0086] Reference Figure 7Each of the indices (e.g., entries) Idx1, Idx2, ..., Idxu (where u is a natural number greater than 2) can include page error information for each of some pages in the memory cell array 300. Each entry may correspond to one of the pages. The error information register 480 includes multiple columns 481, 482, and 483.

[0087] The first column 481 stores the address information ADDINF for each of some pages (candidate defective memory cell rows). In an exemplary embodiment, the address information ADDINF includes at least one of the bank group address ('BGA'), bank address ('BA'), and row address ('RA'). Although Figure 3 The diagram shows a single group of memory bank arrays (e.g., 310 to 380), but additional groups of memory bank arrays may exist. A memory bank group address can identify one of these groups. For example, if there exists a first group of memory bank arrays including arrays 310 to 380 and a second group of memory bank arrays, and the error occurs in the first group of memory bank arrays, then the BGA will identify the first group. A memory bank address can identify one of the memory bank arrays in the identified group. A row address can identify a page of a memory bank.

[0088] The second column, 482, stores the number of correctable errors (ECNT) for each of the candidate defect memory cell rows. For example, Figure 7 Error information register 480 shows that the number of correctable errors occurring on the page with address A is 2 (ECNT) and the number of correctable errors occurring on the page with address B is 4 (ECNT).

[0089] The third column 483 stores the number of subpages containing error bits (FCWCNT) for each of the aforementioned pages. For example, if the second page specified by address B has 4 error bits (ECNT = 4), and the second page has 64 subpages, but only 3 of the 64 subpages have error bits (e.g., each of subpages 1 and 12 has 1 error bit and subpage 43 has 2 error bits), then the entries for the second page will have an FCWCNT of 3.

[0090] Figure 8 This illustrates an exemplary embodiment. Figure 3 A block diagram of the ECC engine in a semiconductor memory device.

[0091] Reference Figure 8 The ECC engine 400 includes selection circuits 405 and 407, an ECC encoder 410, and an ECC decoder 430.

[0092] The ECC encoder 410 can generate a parity bit PRT associated with the write data WMD to be stored in the normal cell array NCA of the first memory array 310.

[0093] Selection circuit 405, in response to the first selection signal SS1, provides read data RMD from the first memory array 310 to one of the data I / O buffer 295 and ECC decoder 430. Selection circuit 407, in response to the first selection signal SS1, provides parity bit PRT from the first memory array 310 to one of the data I / O buffer 295 and ECC decoder 430.

[0094] ECC decoder 430 can perform ECC decoding on read data RMD based on parity bit PRT during read operations of semiconductor memory device 200. When the read data RMD includes at least one error bit as a result of ECC decoding, ECC decoder 430 corrects the error bit in the read data RMD to output corrected master data C_MD.

[0095] In an example embodiment, the ECC decoder 430 can perform ECC decoding on the read data RMD based on the parity bit PRT during a refresh operation on a memory cell row in patrol scan mode. When the read data RMD includes correctable errors as a result of ECC decoding, the ECC decoder 430 provides an error generation signal EGS to the control logic circuit 210. In an example embodiment, during a refresh operation on a memory cell row in patrol scan mode, the ECC decoder 430 may not correct the error bits in the read data RMD and may not output corrected master data C_MD.

[0096] The first selection signal SS1 may be included in the second control signal CTL2.

[0097] During a read operation, in response to the first selection signal SS1, when selection circuit 405 provides read data RMD to data I / O buffer 295 and selection circuit 407 provides parity bit PRT to data I / O buffer 295, data I / O buffer 295 can send read data RMD and parity bit PRT to memory controller 100. In this case, memory controller 100 may include an ECC engine, and the memory controller's ECC engine performs ECC operations such as ECC encoding and ECC decoding.

[0098] Figure 9 An exemplary embodiment is shown. Figure 8 The ECC decoder in the ECC engine.

[0099] Reference Figure 9The ECC decoder 430 may include a corrector generation circuit 440, an error locator 460, and a data corrector 470. The corrector generation circuit 440 may include a parity bit generator 441 and a corrector generator 443.

[0100] The parity bit generator 441 generates the parity bit CHB based on the read data RMD by performing an XOR array operation, and the corrector 443 generates the corrector SDR by comparing the corresponding bits of the parity bit PRT and the parity bit CHB.

[0101] Error locator 460 generates an error position signal EPS indicating the location of an error bit in the read data RMD, and provides the error position signal EPS to data corrector 470 when all bits of the corrector SDR are not 'zero'. Additionally, when the read data RMD includes an error bit, error locator 460 provides an error generation signal EGS to control logic circuitry 210.

[0102] The data corrector 470 receives read data RMD, and when the read data RMD includes error bits, it corrects the error bits in the read data RMD based on the error position signal EPS and outputs the corrected master data C_MD.

[0103] Figure 10 A diagram illustrating a refresh operation in a patrol scan mode of a semiconductor memory device according to an exemplary embodiment is shown.

[0104] Reference Figure 10 Multiple periodic refresh operations REFO1, REFO2, and REFO3 can be repeatedly executed. For example, each refresh operation can be performed from the start row address STADD to the end row address EDADD of the entire row address of the semiconductor memory device 200. In some examples, refresh operations can be performed non-periodically.

[0105] Figure 11 This illustrates an exemplary embodiment. Figure 1 A diagram of the cumulative error table in the memory controller.

[0106] Accumulated error tables can be generated and managed for each of multiple memory arrays. As an example, Figure 11 The diagram shows three cumulative error tables, AET1, AET2, and AET3, corresponding to three memory bank arrays, and an example of cumulative error information stored in a single cumulative error table, AET1.

[0107] Candidate defective row addresses (PFRADD) RAa to RAf with correctable errors from all row addresses of the semiconductor memory device 200, and the number (EN) 2, 1, 5, 4, 0, and 2 correctable errors corresponding to the candidate defective row addresses RAa to RAf, respectively, can be stored in the cumulative error table AET1 as cumulative error information AEI. For example, Figure 11 The diagram shows that the number of correctable errors for candidate defect line address RAa is 2, and the number of correctable errors for candidate defect line address RAD is 4, etc. ATT represents the aforementioned error attribute. N / A indicates that the error attribute was not determined and applied to the corresponding candidate defect line address. For example, ATT can be represented as N / A when the number of correctable errors for the corresponding candidate defect line address is equal to or less than the reference number 2. For example, post-encapsulation operations (PPR) may not be required for candidate defect line addresses designated as N / A. Figure 11 An example is shown where an error attribute ATT1 is applied to candidate defective line addresses RAc and RAD. For example, a post-packaging operation (PPR) can be performed to fix the error at candidate defective line addresses RAc and RAD.

[0108] The candidate defect line address (PFRADD) and the number of correctable errors (EN) can be compared with... Figure 7 The address information ADDINF corresponds to the number of correctable errors that occurred in ECNT.

[0109] Figure 12 This is a flowchart illustrating a method for repairing a controlled semiconductor memory device according to an exemplary embodiment.

[0110] Reference Figure 12 Each time a register read operation is performed, the accumulated error information AEI (S110) can be updated.

[0111] For each of the candidate defect row addresses included in the accumulated error information AEI, it is determined whether the number of correctable errors EN is greater than a first reference number RN1 (S120). When the number of correctable errors EN of at least one of the candidate defect row addresses is greater than the first reference number RN1 (S120: Yes), a post-packaging repair (PPR) operation is performed on all candidate defect row addresses corresponding to the number of correctable errors EN greater than the first reference number RN1 (S130). When the number of correctable errors EN of each of all candidate defect row addresses is not greater than the first reference number RN1 (S120: No), a refresh operation on the memory cell row is performed to update the accumulated error information AEI, and it is determined again whether a post-packaging repair operation is needed based on the updated accumulated error information AEI. In some embodiments, the first reference number RN1 may be stored in a register included in a memory controller or semiconductor memory device.

[0112] The refresh operation sequence in the patrol scan mode can be repeated until the semiconductor memory device 200 is powered off (S140: No). When the semiconductor memory device 200 is powered off, the accumulated error information AEI and error attribute ATT can be stored in the non-volatile memory device (S150). When the semiconductor memory device 200 is powered on again, the accumulated error information AEI and error attribute ATT can be loaded from the non-volatile memory device into the accumulated error table AET 120, so that even if the semiconductor memory device 200 is powered off, the method for controlling the repair of the semiconductor memory device 200 according to the example embodiment can be continuously executed.

[0113] Figure 13 This is a block diagram illustrating a semiconductor memory device performing a post-package repair operation according to an example embodiment. For ease of explanation and description, only the components used to describe the post-package repair operation are shown.

[0114] Reference Figure 13 The semiconductor memory device 500a may include a memory cell array 510, a row decoder 520, a column decoder 530, a control logic circuit 540, and a fuse circuit 550.

[0115] The memory cell array 510 may include multiple DRAM cells. DRAM cells may be connected to word lines NWL and RWL, and bit lines BTL, respectively. A portion of the DRAM cells may be normal cells, and another portion may be redundant cells 511 used to replace faulty cells within the normal cells. Word lines NWL may be normal word lines connected to normal cells, and word lines RWL may be redundant word lines connected to redundant cells 511.

[0116] The row decoder 520 can be connected to the memory cell array 510 via word lines NWL and RWL. The row decoder 520 can select one of the word lines based on the address ADDR (i.e., the row address in address ADDR) and control the voltage of the selected word line.

[0117] The column decoder 530 can be connected to the memory cell array 510 via the bit line BTL. The column decoder 530 can select a portion of the bit line based on the address ADDR (i.e., the column address in address ADDR) and control or detect the voltage of the selected bit line to output the master data MD.

[0118] Control logic circuit 540 can control the overall operation of semiconductor memory device 500a. Fuse setting operations can be performed under the control of control logic circuit 540. Control logic circuit 540 can be configured to set the fuse settings of fuse circuit 550 through a runtime repair operation. Through the fuse setting of fuse circuit 550, a normal cell can be replaced with a redundant cell 511. For example, fuse circuit 550 can receive address ADDR from the memory controller. When the row address in address ADDR corresponds to a normal word line NWL that has been determined to be a defective word line, fuse circuit 550 can output a repair address RPADDR, allowing row decoder 520 to select the redundant word line RWL instead of the normal word line NWL.

[0119] For example, fuse circuit 550 can determine fuse settings such that the row address corresponding to the defective address (also called the target defective row address, each target defective row address including a number of correctable errors greater than a reference number) can be converted into a repair address (also called a replacement row address). Row decoder 520 can select redundant word lines (RWLs) based on the repair addresses from fuse circuit 550. Fuse circuit 550 can transmit row addresses that do not correspond to the faulty address to row decoder 520 without conversion. Thus, semiconductor memory device 500a can perform post-packaging repair operations with respect to faulty addresses through the electrical fuse settings of fuse circuit 550. For example, when an access address from an external memory controller matches one of the target defective row addresses, a post-packaging repair operation is performed by outputting a replacement row address corresponding to one of the target defective row addresses.

[0120] Figure 14 This is a diagram illustrating the layout of a memory cell array included in a semiconductor memory device according to an exemplary embodiment.

[0121] Figure 14 The memory cell array region (MCA), column decoder (CDEC), and row decoder (RDEC) are shown, and other components of the semiconductor memory device are omitted for clarity. The memory cell array region (MCA) includes a dual word line structure, a junction region (CJ), a sub-word line driver region (SWD), a sense amplifier region (SA), and a sub-memory cell array region (SMCA). The dual word line structure includes a main word line (NWE) and multiple sub-word lines (SWL).

[0122] In some exemplary embodiments, the word select signal line PX, the main word line NWE, the sub-word line SWL, the column select signal line CSL, the local input / output data line LIO, and the global input / output data line GIO can be formed in the upper part of the memory cell array region MCA. For ease of explanation, in Figure 14 The power cord is omitted.

[0123] In the memory cell array region MCA, the connection region CJ, the sub-word line driver region SWD, the sense amplifier region SA, and the sub-memory cell array region SMCA are repeatedly arranged along the row direction X and the column direction Y. Memory cells MC are formed in the sub-memory cell array region SMCA and connected to the sub-word line SWL and the bit line BL. Data can be written to or read from the memory cell MC in response to signals transmitted via the word select signal line PX, the master word line NWE, and the column select signal line CSL.

[0124] The column decoder CDEC generates signals on the column select signal line CSL to select one or more columns of the array for reading or writing based on the supplied column address COL_ADDR. The row decoder XDEC decodes the row address ROW_ADDR to generate signals for selecting one of the master word lines NWE and for selecting one of the word line select lines PX.

[0125] The main word line NWE extends along the row direction X on the sub-word line driver region SWD and the sub-memory cell array region SMCA, and the word select signal line PX and the local input / output data line LIO extend along the row direction X on the connection region CJ and the sense amplifier region SA. The column select signal line CSL and the global input / output data line GIO extend along the column direction Y on the sense amplifier region SA and the sub-memory cell array region SMCA.

[0126] Figure 15 and Figure 16 This is a diagram illustrating the determination of error attributes in a method for repairing a controlled semiconductor memory device according to an exemplary embodiment.

[0127] Figure 15 An example is shown where multiple sub-word lines SWL1 to SWL4 are connected to a main word line NWE via a sub-word line driver SWD. Signals PXID1 to PXID4 and PXIB1 to PXIB4 are generated through address decoding.

[0128] Sub-word lines SWL1 to SWL4, connected to the same main word line NWE, have structural dependencies. For example, a failure in the main word line NWE and / or the driver used to drive it will increase the number of faulty sub-word lines or the total number of faults in sub-word lines SWL1 to SWL4. In this case, such as Figure 16As shown, the number of errors on sub-word line SWL3 is zero, but sub-word line SWL3 can still rapidly develop into a failure. To prevent the possibility of such a failure, an error attribute can be applied to an address group that includes row addresses RA1 to RA4 corresponding to all sub-word lines SWL1 to SWL4 connected to the same main word line NWE, and address group RA1 to RA4 can be stored in an accumulated error table as candidate defective row addresses.

[0129] In some exemplary embodiments, when the sum of the number of correctable errors in the address group is greater than the number of risky errors greater than a second reference number, a post-packaging repair operation can be performed on all row addresses RA1 to RA4 included in the address group. For example, a post-packaging repair operation can be performed on row address RA3 even if it has no errors. In some embodiments, the second reference number can be stored in a register included in a memory controller or semiconductor memory device.

[0130] exist Figure 16 In this context, AETb represents the cumulative error table before the error attribute ATT1 is determined, and AETA represents the cumulative error table after the error attribute ATT1 is determined.

[0131] In some exemplary embodiments, when the number of candidate defective row addresses included in the address group is greater than the number of third references, a main address error attribute can be determined for an address group that includes row addresses of multiple sub-word lines corresponding to the main word line of the semiconductor memory device. Figure 15 and Figure 16 In the example, the number of candidate defect row addresses corresponds to three, and the number of third references is assumed to be two. In some embodiments, the number of third references may be stored in a register included in a memory controller or semiconductor memory device.

[0132] Figure 17 This is a diagram illustrating a cumulative error table of a method for repairing a controlled semiconductor memory device according to an exemplary embodiment.

[0133] In some exemplary embodiments, for each of the candidate defect row addresses, the candidate defect column address with correctable errors can be further stored in the cumulative error table AET as cumulative error information AEI.

[0134] and Figure 11 Compared to the cumulative error table AET1, Figure 17 The cumulative error table AET can also include candidate defect column addresses (PFCADD) CAa to CAk for each of the candidate defect row addresses RAa to ARf.

[0135] In this case, when the number of candidate defect row addresses, each including the candidate defect column address CAb, is greater than the number of fourth references, the column error attribute ATT2 can be further determined for the candidate defect column address CAb.

[0136] exist Figure 17 In the example, the number of candidate defect row addresses RAa, RAc, RAd, and RAf that include the same candidate defect column address CAb is four. If the fourth reference number is set to three, the column error attribute ATT2 can be applied to the candidate defect column address CAb. A post-encapsulation repair operation can be performed on the candidate defect column address CAb to which the column error attribute ATT2 is applied.

[0137] Figure 18 The diagram illustrates a column repair method according to an exemplary embodiment of a repair of a controlled semiconductor memory device.

[0138] Reference Figure 18 This shows that based on Figure 17 The cumulative error table AET performs a post-packaging repair operation by replacing bit line BTLb with redundant bit line RBTLb for candidate defect columns combined with bit line BTLb. For ease of explanation and description, Figure 18 The diagram shows bit lines BTLa to BTLk and word lines WLa to WLf.

[0139] Figure 19 This is a flowchart illustrating a method for repairing a controlled semiconductor memory device according to an exemplary embodiment.

[0140] Reference Figures 1 to 19 A method for controlling the repair of a semiconductor memory device 200 is provided. The semiconductor memory device 200 includes a memory cell array 300 and an ECC engine 400. The memory cell array 300 may include a plurality of memory cell rows, and each of the plurality of memory cell rows may include a plurality of volatile memory cells.

[0141] In the method for repairing the semiconductor memory device 200, the I / O gate circuit 290 provides the ECC engine 400 with sensing data and parity bits sensed through refresh operations on memory cell rows (S310). When a correctable error is detected by an ECC decoding operation performed on the sensing data based on the parity bits, the control logic circuit 210 controls the ECC engine 400 to store error information in the error information register 480 by accumulating the location information of the correctable error (S320).

[0142] The memory controller 100 performs runtime repair operations (S330, S340) on at least one or at least a portion of a memory cell row based on reading error information stored in the error information register 480 and a fifth reference number.

[0143] In order to perform runtime repair operations, the memory controller 100 reads the error information stored in the error information register 480 as the cumulative error information AEI, and analyzes the error attributes of the candidate defective memory cell rows (each candidate defective memory cell row includes correctable errors) based on the comparison of the number of correctable errors with the fifth reference number (S330).

[0144] The memory controller 100 performs a post-packaging repair operation (S340) on at least one target defective memory cell row from the candidate defective memory cell rows based on analysis. The at least one target defective memory cell row from the candidate defective memory cell rows may include more than a fifth reference number of correctable errors.

[0145] Figure 19 The post-packaging repair method is executed by the semiconductor memory device 200 in response to a first mode register setting command from the memory controller 100. In some embodiments, the post-packaging repair operation can be performed during an idle period of the memory system.

[0146] Figure 20 This is a block diagram illustrating a memory system according to an exemplary embodiment.

[0147] Reference Figure 20 The memory system 20a may include a memory controller 100a and a semiconductor memory device 200.

[0148] Figure 20 The memory system 20a and Figure 1 The difference in memory system 20 is that memory controller 100a also includes ECC engine (second ECC engine) 140, and semiconductor memory device 200 also provides parity bit PRT to memory controller 100a.

[0149] Reference Figure 20Repair manager 130 can determine a first error attribute for each candidate defective memory row based on accumulated error information AEI, including the number of correctable errors and a fifth reference number. Repair manager 130 can apply a second mode register set command and a victim address to semiconductor memory device 200 based on the determined first error attribute. Control logic circuitry 210 disables ECC decoder 430 in ECC engine 400 in response to the second mode register set command. Control logic circuitry 210 can control I / O gating circuitry such that, while disabling ECC decoder 430, data and parity bits stored in the adjacent memory cell row specified by the victim address are provided to memory controller 100a. The adjacent memory cell row specified by the victim address is arranged adjacent to some memory cell rows associated with the candidate defective row addresses.

[0150] The second ECC engine 140 can calculate the number of correctable errors for each sacrificial address by performing ECC decoding on the data from each of the adjacent memory cell rows based on the parity bits from each of the adjacent memory cell rows, and can determine a second error attribute for each sacrificial address based on a comparison of the calculated number of correctable errors with a fifth reference number. The repair manager 130 can control the semiconductor memory device 200 to perform post-packaging repair operations on target sacrificial addresses, and each target sacrificial address includes a calculated number of correctable errors equal to or greater than the fifth reference number.

[0151] Figure 21 This illustrates control according to an exemplary embodiment. Figure 20 A flowchart of a method for repairing a semiconductor memory device.

[0152] Reference Figure 20 and Figure 21 The sensing data and parity bit obtained through the refresh operation are provided to the ECC engine 400 (S410). When a correctable error is detected by the ECC decoding operation performed on the sensing data based on the parity bit, the control logic circuit controls the ECC engine 400 to store the error information in the error information register 480 by accumulating the location information of the correctable error (S420).

[0153] The memory controller 100 reads the error information stored in the error information register 480 as the cumulative error information AEI, and analyzes the first error attribute of each of the candidate defect memory cell rows including the correctable errors based on a comparison of the number of correctable errors with the reference number (S430).

[0154] The memory controller 100 reads data and parity bits stored in the adjacent memory cell row specified by the sacrificial address based on the first error attribute, the sacrificial address being adjacent to some memory cell rows associated with the candidate defect row address (S440).

[0155] The second ECC engine 140 in the memory controller 100a performs ECC decoding on the data and parity bits read from the adjacent memory cell row to determine a second error attribute of the adjacent memory cell row (S450). The memory controller 100a can selectively perform post-packaging repair operations on at least some of the adjacent memory cell rows based on the second error attribute (S460).

[0156] Figure 22 This is a block diagram illustrating a semiconductor memory device performing a post-package repair operation according to an example embodiment. For ease of explanation and description, only the components used to describe the post-package repair operation are shown.

[0157] Figure 22 Semiconductor memory device 500b and Figure 13 The difference between semiconductor memory device 500a and semiconductor memory device 500b is that semiconductor memory device 500b operates in response to a third mode register set command, and error information register 480b provides defect address FLADDR to fuse circuit 550.

[0158] Error information register 480b provides the defective row address FLADDR to fuse circuit 550 as the repair address RPADDR, instead of providing the accumulated error information to memory controller 100, and fuse circuit 550 is configured by control logic circuit 540 to convert the defective address FLADDR to the repair address RPADDR and output the repair address RPADDR to row decoder 520 or column decoder 530.

[0159] Figure 23 This is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment.

[0160] Reference Figure 23 The semiconductor memory device 600 may include a buffer die 610 and a first set of dies 620.

[0161] The buffer die 610 may include at least one buffer die or logic die 611. The first set of dies 620 may include a plurality of memory dies 620-1 to 620-p, which are stacked on the buffer die 610 and transmit data through a plurality of substrate via lines (e.g., through-silicon via (TSV) lines).

[0162] Each of the memory dies 620-1 to 620-p may include a cell core 622 and a refresh counter (REF CNT) 623 for generating refresh addresses. The cell core 622 includes multiple memory cells coupled to multiple word lines and multiple bit lines.

[0163] The buffer die 610 may include an ECC engine 612 and an error information register 613 for storing error information. The ECC engine 612 corrects transmission errors and generates error-corrected data when a transmission error is detected in transmitted data received via the TSV line using transmission parity bits. The ECC engine 612 may employ... Figure 8 The ECC engine 400, and the error information register 613 can be used Figure 7 Error message register 480.

[0164] The semiconductor memory device 600 can be a stacked chip-type memory device or a stacked memory device that transmits data and control signals via TSV lines. TSV lines can also be referred to as "through electrodes".

[0165] Transmission errors occurring at the data transmission point may be due to noise occurring at the TSV line. Because data failures caused by noise at the TSV line can be distinguished from data failures caused by erroneous operation of the memory die, data failures caused by noise at the TSV line can be considered soft data failures (or soft errors). Soft data failures can be caused by transmission failures on the transmission path and can be detected and corrected through ECC operations.

[0166] The data TSV line group 632 formed at a memory die 620-p may include multiple TSV lines L1 to Lp, and the parity TSV line group 634 may include multiple TSV lines L10 to Lq.

[0167] The TSV lines L1 to Lp in the data TSV line group 632 and the parity TSV lines L10 to Lq in the parity TSV line group 634 can be connected to the microbumps MCBs correspondingly formed in the memory dies 620-1 to 620-p.

[0168] Each of the memory dies 620-1 to 620-p may include a DRAM cell, each DRAM cell including at least one access transistor and a storage capacitor.

[0169] The semiconductor memory device 600 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with the host via the data bus B10. The buffer die 610 may be connected to the memory controller 100 via the data bus B10.

[0170] Figure 24 This is a diagram illustrating a semiconductor package including a stacked memory device according to an exemplary embodiment.

[0171] Reference Figure 24 The semiconductor package 900 may include one or more stacked memory devices 910 and memory controllers (CONT) 920.

[0172] The stacked memory device 910 and the memory controller 920 can be mounted on an interposer 930, and the interposer 930 on which the stacked memory device 910 and the memory controller 920 are mounted can be mounted on a package substrate 940. The memory controller 920 can be adopted Figure 1 The memory controller 100 in the middle.

[0173] Each of the stacked memory devices 910 can be implemented in various forms and can be a high-bandwidth memory (HBM) type memory device in which multiple layers are stacked. Therefore, each of the stacked memory devices 910 may include a buffer die and multiple memory dies. The buffer die may include an ECC engine and an error information register, and each memory die may include a memory cell array.

[0174] Multiple stacked memory devices 910 can be mounted on the interposer layer 930, and the memory controller 920 can communicate with the multiple stacked memory devices 910.

[0175] Figure 25 A block diagram of a solid-state drive (SSD) according to an exemplary embodiment is shown.

[0176] Reference Figure 25 The SSD 1000 includes multiple non-volatile memory devices 1100 and an SSD controller 1200.

[0177] The non-volatile memory device 1100 may optionally be supplied with an external high voltage VPP. Each non-volatile memory device 1100 may operate as a storage medium for an SSD 1000.

[0178] SSD controller 1200 is connected to non-volatile memory device 1100 via multiple channels CH1, CH2, and CH3 to CHi, where i is an integer greater than 3. SSD controller 1200 includes one or more processors 1210, DRAM (volatile memory device) 1220, ECC block 1230, host interface 1250, and non-volatile memory (NVM) interface 1260.

[0179] DRAM 1220 operates as a buffer memory and stores data used to drive SSD controller 1200. DRAM 1220 can buffer data to be used in programming operations. DRAM 1220 can employ... Figure 3 The semiconductor memory device 200 may include an ECC engine and an error information register. The DRAM 1220 performs ECC decoding during refresh operations and accumulates error information in the error information register.

[0180] ECC block 1230 calculates the error correction code value for the data to be programmed during write operations and uses the error correction code value to correct errors in read data during read operations. In data recovery operations, ECC block 1230 corrects errors in data recovered from the non-volatile memory device 1100.

[0181] The aspects of this invention can be applied to systems using semiconductor memory devices employing volatile memory cells and ECC engines.

[0182] The foregoing is a description of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the exemplary embodiments without substantially departing from the spirit and scope of the inventive concept as set forth in the claims.

Claims

1. A semiconductor memory device comprising: an array of memory cells including a plurality of rows of memory cells, each of the plurality of rows of memory cells including a plurality of volatile memory cells; an error correction code engine; an input / output gating circuit connected between the array of memory cells and the error correction code engine; an error information register; and control logic configured to control the error correction code engine, the input / output gating circuit, and the error information register based on commands and addresses received from an external memory controller, wherein the input / output gating circuit is configured to provide the error correction code engine with codewords read from the array of memory cells by a refresh operation on the plurality of rows of memory cells, wherein the error correction code engine is configured to perform error correction code decoding on main data of the codewords based on parity bits of the codewords, and configured to provide the control logic with an error generation signal in response to detecting a correctable error for a corresponding address as a result of performing the error correction code decoding, wherein the control logic is configured to store error information in the error information register by accumulating location information having the correctable error based on the error generation signal, wherein the control logic is configured to store, in the error information register, candidate defective row addresses of candidate defective rows of memory cells in which the correctable error occurs among the plurality of rows of memory cells, and a number of the correctable errors corresponding to each of the candidate defective row addresses, wherein the control logic is configured to: store candidate defective column addresses in which the correctable error occurs for each of the candidate defective row addresses, and perform a post-package repair operation on the candidate defective column addresses when a number of the candidate defective row addresses including the candidate defective column addresses is greater than a reference number. the control logic is configured to:

2. The semiconductor memory device according to claim 1, wherein, store, in the error information register, candidate defective row addresses of candidate defective rows of memory cells in which the correctable error occurs among the plurality of rows of memory cells as error information, and in response to a register read command from the external memory controller, control the error information register to provide the error information accumulated in the error information register as accumulated error information. the control logic is configured to provide a notification signal to the external memory controller when a storage space of the error information register is full by accumulating the error information.

3. The semiconductor memory device of claim 2, wherein, 4.The semiconductor memory device of claim 2, further comprising: a fuse circuit configured to store replacement row addresses of the candidate defective row addresses corresponding to target defective row addresses among the candidate defective row addresses, wherein each of the target defective row addresses includes a number of the correctable errors greater than the reference number, and wherein the fuse circuit is configured to perform the post-package repair operation by outputting the replacement row address corresponding to one of the target defective row addresses when an access address from the external memory controller matches the one of the target defective row addresses. the control logic is configured to perform a runtime repair operation on at least one of the candidate defective row addresses based on the error information accumulated in the error information register.

5. The semiconductor memory device of claim 1, wherein, ​ 6. The semiconductor memory device of claim 5, wherein, The control logic circuit is configured to perform a runtime repair operation by performing a post-package repair operation on at least one candidate defective memory cell row of the candidate defective memory cell rows, the at least one candidate defective memory cell row containing a number of correctable errors greater than the reference number.

7. The semiconductor memory device of claim 1, further comprising: at least one buffer die; and a plurality of memory dies stacked on the at least one buffer die and transferring data through a plurality of base via lines, wherein each memory die includes an array of memory cells, and wherein the at least one buffer die includes an error correction code engine and an error information register.

8. A memory system, the memory system comprising: a semiconductor memory device; and a memory controller configured to control the semiconductor memory device, wherein the semiconductor memory device includes: an array of memory cells including a plurality of memory cell rows, each memory cell row of the plurality of memory cell rows including a plurality of volatile memory cells; a first error correction code engine; an input / output gating circuit connected between the array of memory cells and the first error correction code engine; an error information register; and a control logic circuit configured to control the first error correction code engine, the input / output gating circuit, and the error information register based on a command and an address received from the memory controller, wherein the input / output gating circuit is configured to provide the first error correction code engine with codewords read from the array of memory cells by a refresh operation on the plurality of memory cell rows, wherein the first error correction code engine is configured to perform error correction code decoding on main data of the codewords based on parity bits of the codewords, and is configured to provide the control logic circuit with an error generation signal in response to detecting a correctable error for a corresponding address as a result of performing the error correction code decoding, wherein the control logic circuit is configured to store error information in the error information register by accumulating location information having correctable errors based on the error generation signal, wherein the control logic circuit is configured to: store, as the error information in the error information register, a candidate defective row address of a candidate defective memory cell row of the plurality of memory cell rows in which a correctable error occurs, and control the error information register to provide, as accumulated error information, the error information accumulated in the error information register in response to a register read command from the memory controller, wherein the memory controller is configured to: receive the accumulated error information from the error information register, determine a first error attribute of each candidate defective row address based on a comparison of a number of correctable errors of each candidate defective row address with a first reference number, and apply a first mode register set command to the semiconductor memory device based on the determined first error attribute.

9. The memory system of claim 8, wherein: The control logic circuit is configured to perform a post-package repair operation on at least one of the candidate defective memory cell rows based on the first mode register set command, the at least one candidate defective memory cell row including a number of correctable errors that is greater than the first reference number.

10. The memory system of claim 9, wherein, The control logic circuit is configured to store candidate defective column addresses, wherein a correctable error occurs for each candidate defective row address, and wherein the memory controller is configured to determine a second error attribute based further on a comparison of a number of candidate defective row addresses including a first candidate defective column address of the candidate defective column addresses to a second reference number.

11. The memory system of claim 10, wherein, The control logic circuit is configured to perform a post-package repair operation on the first candidate defective column address when the number of candidate defective row addresses including the first candidate defective column address is greater than the second reference number.

12. The memory system of claim 8, wherein: The memory controller is configured to: apply a second mode register set command to the semiconductor memory device based on the determined first error attribute, and The control logic circuit is configured to disable an error correction code decoder in the first error correction code engine in response to the second mode register set command.

13. The memory system of claim 12, wherein, The control logic circuit is configured to control the input / output gating circuitry such that the main data and the parity bits stored in the adjacent memory cell rows specified by the sacrificial addresses adjacent to the memory cell rows associated with some of the candidate defective row addresses are provided to the memory controller while the error correction code decoder is disabled.

14. The memory system of claim 13, wherein, The memory controller includes a second error correction code engine, wherein the second error correction code engine is configured to calculate a number of correctable errors for each of the sacrificial addresses by performing error correction code decoding on the main data from each of the adjacent memory cell rows based on the parity bits from each of the adjacent memory cell rows, and is configured to determine a second error attribute for each of the sacrificial addresses based on a comparison of the calculated number of correctable errors to a second reference number, and wherein the memory controller is configured to control the semiconductor memory device to perform a post-package repair operation on target ones of the sacrificial addresses, and each of the target sacrificial addresses includes a calculated number of correctable errors that is equal to or greater than the second reference number.

15. The memory system of claim 8, wherein, The control logic circuit is configured to perform a post-package repair operation on at least one of the candidate defective memory cell rows based on a third mode register set command from the memory controller, the at least one candidate defective memory cell row including a number of correctable errors that is greater than the reference number.

16. A method of controlling repair of a semiconductor memory device including an error correction code engine, an error information register, and a memory cell array including a plurality of memory cell rows, each memory cell row including a plurality of volatile memory cells, the method comprising: providing the error correction code engine with codewords including main data and parity bits read from the memory cell array by a refresh operation on the plurality of memory cell rows; detecting correctable errors for the corresponding address based on the parity check bits through an error correction code engine; storing error information in an error information register by accumulating location information having correctable errors; storing, in the error information register, candidate defective row addresses of candidate defective memory cell rows in which correctable errors occur in the plurality of memory cell rows, and the number of correctable errors corresponding to each candidate defective row address, storing, in the error information register, candidate defective column addresses in which correctable errors occur for each candidate defective row address, and when the number of candidate defective row addresses including the candidate defective column addresses is greater than a reference number, performing a post-packaging repair operation on the candidate defective column addresses.

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