Non-volatile random access static memory device

Abstract

Non-Volatile Random Access Static Memory Device This description relates to an nvSRAM device comprising a memory cell matrix (104) each having: - two storage nodes (108A, 108B); - two access transistors (110A, 110B) coupled to two bit lines (112A, 112B) shared by the cells of the same column; - two FeCAPs (116A, 116B) each connected to one of the storage nodes and to a first plate line (118) shared by the cells of the same line; the device further comprising: - an erase circuit (126) equalizing the potential values ​​of the bit lines of the same column; - a control circuit (128) for erasing the storage nodes of certain cells, between a read / write interrupt in the storage nodes of said cells and a write, in the storage nodes of said cells, of values ​​stored in the FeCAPs of said cells. Figure for the abbreviation: Fig. 2

Description

Title of the invention: Non-volatile random access static memory device. Technical field

[0001] This description relates generally to the field of non-volatile static random-access memory devices, or nvSRAM (“non-volatile Static Random-Access Memory” in English, or non-volatile SRAM), for example used in the field of embedded electronics. Previous technique

[0002] In an electronic system comprising a central processing unit (CPU) and static random-access memory (SRAM), the memory may contain important, potentially sensitive data that must not be lost in the event of a power failure. During a power failure, several options are available to preserve this data.

[0003] One possibility is to use a BBSRAM type memory (“Battery-Backed SRAM”) which includes a battery. However, this solution has the disadvantage that the battery is bulky and contains substances harmful to the environment.

[0004] A second possibility is to transfer the data from the SRAM memory to a remote non-volatile memory following a power outage, using, for example, a discrete capacitor as an auxiliary power source for this transfer. However, this solution is not optimal because the data transfer is relatively slow since it must be transmitted serially from the SRAM memory to the remote non-volatile memory. Furthermore, because the two memories are far apart, the energy required for this transfer is significant. Finally, this transfer can be subject to attacks or unwanted disturbances on the communication bus used for this transfer.

[0005] Another possibility is to use an nvSRAM type memory in which each memory cell corresponds to an SRAM cell coupled to non-volatile memory elements. The memory elements are, for example, ferroelectric capacitors, called FeCAPs, as described, for example, in the document by T. Miwa et al., "NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors," Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, Orlando, FL, USA, 2000, pp. 65-68, or the document by S. Masui et al., "A ferroelectric memory-based secure dynamically programmable gate array," IEEE Journal of Solid-State Circuits, vol. 38, no. 5, pp. 715-725, May 2003. Compared to the previous solution of transferring data from SRAM memory to remote non-volatile memory, the use of FeCAPs within memory cells allows for faster parallel data transfer, lower power requirements and greater security because the data does not travel over a communication bus.

[0006] This type of nvSRAM memory cell has four elementary operations:

[0007] - writing to the SRAM cell: "WRITE" operation;

[0008] - reading the SRAM cell: operation “READ”;

[0009] - copying data from the SRAM cell into the FeCAPs: operation “STORE”;

[0010] - transfer of data from the FeCAPs to the SRAM cell (which results in a loss of data stored in the FeCAPs): "RECALL" operation.

[0011] The nvSRAM memory is used as SRAM most of the time, with READ and WRITE operations being performed in the SRAM memory cells. When a power interruption occurs, the memory copies the data from each memory cell to the FeCAPs (STORE operation). The circuit then shuts down, and the SRAM cells are no longer used. When the memory restarts, the data is transferred from the FeCAPs to the SRAM cells (RECALL operation) so that the memory returns to its pre-interrupt state and the SRAM cells can resume operation by again performing READ and WRITE operations.

[0012] The RECALL operation is rather delicate to implement because the FeCAPs must generate a sufficient electrical potential difference to force the SRAM cell to lock into the desired state corresponding to that stored in the FeCAPs. The implementation of this operation is particularly sensitive to manufacturing variations that cause imbalances in the SRAM cells, resulting, for example, in different threshold voltages for the two inverters in the same SRAM cell. Such an imbalance causes the SRAM cell to behave like an unbalanced differential read amplifier when reading the FeCAPs, which can lead to errors in the data transfer.

[0013] The nvSRAM memory can also be interrupted for reasons other than a power interruption, such as the detection of a memory attack, data corruption, sleep mode, or the execution of a second process with higher priority than a first process currently being executed. In some of these situations, it would be advantageous for the SRAM cells to continue operating between the STORE and RECALL operations. However, using the SRAM cells between these operations presents difficulties.

[0014] Indeed, even when the SRAM cells are no longer powered, the data stored in the SRAM cells can remain in memory for a very long time, up to a time on the order of one or more seconds, because the electrical charges corresponding to this data can only be discharged from the SRAM cells through very small leakage currents. If the SRAM cells continued to operate after a STORE operation, the data present in the SRAM cells at the time of the RECALL operation would be different from that stored in the FeCAPs at the time the STORE operation was implemented, particularly when the time between the power interruption and the RECALL operation is short. The presence of this different data in the SRAM cells can lead to errors in the data transfer performed during the RECALL operation.

[0015] Moreover, the presence of this data in the SRAM cells for this significant duration, even when the SRAM cells are no longer powered, makes the nvSRAM memory vulnerable to cold-boot attacks because it is possible to read it.

[0016] Furthermore, in nvSRAM memory, the FeCAPs are permanently connected to the internal nodes of the SRAM cells. When several WRITE operations are performed in an SRAM cell, the FeCAPs coupled to the storage nodes of that cell are subjected, at their terminals and with each implementation of a WRITE operation, to voltages that can weaken their remanent biasing. This makes the RECALL operation to be implemented subsequently even more sensitive if WRITE operations are implemented between the STORE and RECALL operations. Summary of the invention

[0017] There is a need to propose an nvSRAM type device that does not have at least some of the disadvantages mentioned above.

[0018] One embodiment overcomes all or part of the drawbacks of known devices and proposes a non-volatile random-access static memory device, nvSRAM, comprising a memory cell matrix, each cell having at least:

[0019] - two inverters connected to each other and forming at least two nodes of storage ;

[0020] - two access transistors each connected to one of the two storage nodes and to one of two bit lines shared by the memory cells of the same column of the matrix, and whose grids are connected to the same word line shared by the memory cells of the same row of the matrix;

[0021] - two first ferroelectric capacitors, FeCAPs, each connected to one of the two storage nodes and a first plate line shared by the memory cells of the same line of the matrix;

[0022] the device further comprising at least:

[0023] - an erasure circuit configured to equalize the values ​​of the electrical potentials of the two bit lines, shared by the memory cells of the same column of the matrix, controllable by an erase line;

[0024] - a control circuit configured to implement, for at least part memory cells, at least one first erasure operation of the data stored in the two storage nodes of each of said memory cells between an interruption of first read and write operations in the storage nodes of said memory cells and a write operation, in the storage nodes of said memory cells, of values ​​stored in the first FeCAPs of said memory cells.

[0025] According to a particular embodiment, the erasure circuit comprises at least one first transistor comprising conduction electrodes each coupled to one of the two bit lines and comprising a gate coupled to the erasure line, said transistor being configured to couple, in the conducting state, the two bit lines to each other.

[0026] According to a particular embodiment, the device further comprises write driver circuits, each shared by a column of memory cells, and word line driver circuits, each shared by a row of memory cells, and wherein the memory cell erasure circuits comprise:

[0027] - in each writing driver circuit, the first transistor configured to couple, in the passing state, the bit lines to each other, and a second transistor configured to cut off, in the blocked state, a power supply to the write driver circuit and the memory cells coupled to the write driver circuit;

[0028] - in each word line driver circuit, a first transistor configured for cut, in the blocked state, a power supply to the word line driver circuit, and a second transistor configured to activate, in the conducting state, the word line.

[0029] According to a particular embodiment, each of the memory cells further comprises two second FeCAPs each connected to one of the two storage nodes and to a second plate line shared by the memory cells of the same line of the matrix.

[0030] According to a particular embodiment, in each of the memory cells, a ratio between the sum of the areas of the first FeCAPs and the sum of the areas of the first and second FeCAPs is between 0.05 and 0.4.

[0031] According to a particular embodiment, during the first read and write operations in the storage nodes of said memory cells, the control circuit is configured to apply an electrical potential equal to half of a supply voltage of the matrix on the first plate line and, when each of the memory cells has the second FeCAPs, on the second plate line.

[0032] According to a particular embodiment, the control circuit is configured to implement, for said at least a part of the memory cells and between the interruption of the first read and write operations in the storage nodes of said memory cells and the first erasure operation, a write operation, in the FeCAPs, of values ​​stored in the storage nodes of said memory cells.

[0033] According to a particular embodiment, during the writing operation, in the FeCAPs, of the values ​​stored in the storage nodes of said memory cells, the control circuit is configured to apply an electrical potential greater than a coercive voltage of the FeCAPs, then an electrical potential less than the difference between a supply voltage of the matrix and the coercive voltage of the FeCAPs, on the first plate line and, when each of the memory cells has the second FeCAPs, on the second plate line.

[0034] According to a particular embodiment, the control circuit is configured to implement, for said at least a part of the memory cells and between the write operation, in the FeCAPs, of the values ​​stored in the storage nodes and the first erasure operation, the second read and write operations in the storage nodes of said memory cells.

[0035] According to a particular embodiment, the control circuit is configured to implement, for said at least a part of the memory cells, at least a second erasure operation of said memory cells successively to the interruption of the first read and write operations in the storage nodes of said memory cells.

[0036] According to a particular embodiment, the control circuit is configured to periodically implement a write operation, in the FeCAPs, of values ​​stored in the storage nodes of the memory cells.

[0037] According to a particular embodiment, the control circuit is configured to implement, for said at least a part of the memory cells and between the interruption of the first read and write operations in the storage nodes of said memory cells and the first erasure operation, the second read and write operations in the storage nodes of said memory cells.

[0038] According to a particular embodiment, the control circuit is configured to successively implement the first erasure operation of said memory cells after the interruption of the first read and write operations in the storage nodes of said memory cells, and the write operation, in the storage nodes, of the values ​​stored in the FeCAPs of said memory cells after the first erasure operation.

[0039] According to a particular embodiment, the interruption of the first read and write operations in the storage nodes of said memory cells corresponds to an interruption of the matrix's power supply or to a change of process involving the implementation of second read and write operations of data different from those used before the interruption. Brief description of the drawings

[0040] These features and advantages, as well as others, will be described in detail in the following non-limiting description of particular embodiments in relation to the accompanying figures, among which:

[0041] - Figure 1 schematically represents an nvSRAM type device according to a particular embodiment;

[0042] - Figure 2 schematically represents a first example of a memory cell of a nvSRAM type device according to a particular embodiment;

[0043] - [Fig.3] schematically represents a first example of a sequence operations implemented in an nvSRAM type device according to an embodiment;

[0044] - [Fig. 4] schematically represents examples of control signals used in an nvSRAM type device according to a particular embodiment;

[0045] - Figure 5 schematically represents examples of signals obtained in a nvSRAM type device according to a particular embodiment;

[0046] - Figure 6 schematically represents a second example of a memory cell of an nvSRAM type device according to a particular embodiment;

[0047] - Figure 7 schematically represents a second example of an embodiment of memory cell erasure circuits of an nvSRAM type device according to a particular embodiment;

[0048] - Figure 8 schematically represents examples of signals obtained in a variant embodiment of the nvSRAM type device according to a particular embodiment;

[0049] - [Fig.9] schematically represents a second example of a sequence operations implemented in an nvSRAM type device according to a particular embodiment;

[0050] - [Fig. 10] schematically represents a third example of a sequence of operations implemented in an nvSRAM type device according to a particular embodiment. Description of the implementation methods

[0051] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional, and material properties. In the figures, to facilitate their reading, the different elements and the different material layers are not shown at the same scale relative to each other.

[0052] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, the various circuits and elements of the device that are peripheral to the memory cell array, as well as the device control circuit, are not described in detail. Furthermore, the coding necessary for controlling the various operations implemented is not detailed. A person skilled in the art will be able to implement the various functions, elements, and circuits in detail using the functional description given below.

[0053] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without any intervening elements other than conductors, and when referring to two elements connected or coupled, this means that these two elements can be connected or linked via one or more other elements. Furthermore, the terms "coupled," "linked," and "connected" are used here to denote electrical couplings, links, or connections.

[0054] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures. However, these terms do not presume the actual position and orientation of the device when in use.

[0055] Similarly, unless otherwise indicated, the ranges of values ​​indicated include the bounds of these ranges.

[0056] In all the embodiments described, for each transistor, the first and second conduction electrodes correspond to two different electrodes from the other side of the same transistor, one of them corresponding to the source electrode and the other corresponding to the drain electrode.

[0057] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0058] A first example of a 100-type nvSRAM device according to a particular embodiment is described below in relation to figures 1 to 5.

[0059] The device 100 comprises a matrix 102 of memory cells 104. A first example of the realization of one of the memory cells 104 of the device 100 is shown in [Fig.2].

[0060] The memory cell 104 comprises at least two inverters 106A, 106B connected to each other in a cross-connected, or back-to-back, configuration. The two inverters 106A, 106B form, in particular, two data storage nodes 108A, 108B. The electrical potentials in the two data storage nodes 108A, 108B are respectively called "BLFI" and "BLTI". In each memory cell 104, the two inverters 106A, 106B form an SRAM cell.

[0061] The memory cell 104 also includes two access transistors 110A, 110B, each comprising a first conduction electrode connected to one of the storage nodes 108A, 108B and a second conduction electrode connected to one of two bit lines 112A, 112B shared by the memory cells 104 in the same column of the matrix 102, i.e. connected to the memory cells 104 in the same column of the matrix 102. In [Fig.2], the two bit lines 112A, 112B are called "BLF" and "BLT". The gates of the access transistors 110A, 110B are connected to the same word line 114 shared by the memory cells 104 of the same line of the matrix 102, that is to say connected to the memory cells 104 of the same line of the matrix 102.

[0062] The memory cell 104 further comprises two first FeCAPs 116A, 116B each comprising a first electrode connected to one of the storage nodes 108A, 108B and a second electrode connected to a first plate line 118 shared by the memory cells 104 of the same line of the matrix 102, i.e. connected to the memory cells 104 of the same line of the matrix 102. The signal applied to the first plate line 118 is called "PL_HIGH".

[0063] In the example described in connection with [Fig.2], each of the memory cells 104 further comprises two second FeCAPs 120A, 120B each comprising a first electrode connected to one of the storage nodes 108A, 108B and a second electrode connected to a second plate line 122 shared by the memory cells 104 of the same line of the matrix 102, i.e. connected to the memory cells 104 of the same line of the matrix 102. The signal applied to the second plate line 122 is called “PL_LOW”.

[0064] In the example described in connection with [Fig.2], the memory cells 104 are of type 6T4C, i.e. each comprising six transistors and four FeCAPs.

[0065] Memory cell 104 is coupled to a circuit for erasing the values, or data, stored in storage nodes 108A, 108B. This erasure circuit is configured to equalize the electrical potential values ​​of bit lines 112A, 112B during the erasure of data stored in storage nodes 108A, 108B of memory cell 104, thus achieving rapid erasure of the data stored in storage nodes 108A, 108B. This allows, in particular, the rapid and reliable implementation of a RECALL operation, even when storage nodes 108A, 108B are used for READ and WRITE operations after a STORE operation and before the RECALL operation. The erasure circuit is controlled by an erase line 124. The signal applied to the erase line 124 is called "ERASE".

[0066] In the example of [Fig. 2], the erasure circuit comprises at least one transistor 126 arranged at the base of a column and including conduction electrodes each coupled to one of the bit lines 112A, 112B and including a gate coupled to the erase line 124. Thus, the transistor 126 is configured to couple the bit lines 112A, 112B to each other during an erasure operation of the data stored in the storage nodes 108A, 108B of the memory cell 104. The ERASE signal can be common to all the transistors 126 located at the base of the different columns of the matrix 102, leading to the complete erasure of the matrix 102.

[0067] The device 100 further includes at least one control circuit 128 configured to implement, for at least a part of the memory cells 104 of the matrix 102, at least one first operation of erasing the data stored in the storage nodes 108A, 108B of each of said memory cells 104 between an interrupt of READ and WRITE operations implemented for said memory cells 104 and a RECALL operation, i.e. transfer, in the storage nodes 108A, 108B of said memory cells 104, of values ​​stored in the FeCAPs 116A, 116B, 120A, 120B of said memory cells 104.

[0068] A first example of a sequence of operations implemented in the device 100 is described below in relation to [Fig.3].

[0069] In this first example, between times t0 and tl, the device 100 functions as a conventional SRAM memory, that is, by implementing READ and WRITE operations in the memory cells 104, i.e., read and write operations in the storage nodes 108A, 108B of the memory cells 104 (operations symbolically designated by reference 202 and corresponding to operations of a first process executed in the memory device 100), without using the FeCAPs 116A, 116B, 120A, 120B of the memory cells 104. On the [Fig.3], the reference 204 symbolically designates the fact that the FeCAPs 116A, 116B, 120A, 120B of the memory cells 104 do not contain any particular stored data.

[0070] At time t1, an interruption of operations 202 occurs (reference 206). According to a first example, this interrupt 206 may correspond to an imminent power outage of the matrix 102. According to a second example, this interrupt 206 may correspond to an imminent change of process for which the memory cells 104 are used, the memory cells 104 being intended to be used subsequently for the implementation of READ and WRITE operations on data different from that used in operations 202 (operation of a second process executed in the memory device 100).

[0071] At time t2 (which could correspond to time t1, depending on the interrupt handling performed by device 100), a STORE operation, that is, a copy, into the FeCAPs 116A, 116B, 120A, 120B, of the values ​​stored in the storage nodes 108A, 108B of the memory cells 104, is implemented (reference 208). Following this operation 208, the last values ​​stored in the storage nodes 108A, 108 of each of the memory cells 104 are stored in the FeCAPs 116A, 116B, 120A, 120B (data storage symbolically designated by reference 210). The implementation time for operation 208 is, for example, on the order of 480 ns.

[0072] From time t3 (corresponding to the end of operation 208) until time t4, the memory cells 104 can be unused (when the interrupt corresponds for example to a power cut of matrix 102 occurring at time t3) and / or be used for the implementation of the READ and WRITE operations of the second process (reference 211).

[0073] At time t4, the requested interrupt is completed. This time t4 corresponds, for example, to the occurrence of an event such as the availability of the power supply, confirmation of the integrity of device 100, etc. A first operation to erase the data stored in the storage nodes 108A, 108B of the memory cells 104 is then implemented for each of the memory cells 104 (reference 212). At time t5, a RECALL operation, that is to say a transfer, in the storage nodes 108A, 108B of the memory cells 104, of the values ​​stored in the FeCAPs 116A, 116B, 120A, 120B of the memory cells 104, is then implemented (reference 214). For example, the execution time of operations 212 and 214 is on the order of 700 ns. At the end of operation 214, the last values ​​stored in storage nodes 108A, 108 of each of the memory cells 104 at the end of the first process and which were stored in the FeCAPs 116A, 116B, 120A, 120B between times t2 and t3 are found in the storage nodes 108A, 108B of the memory cells 104.

[0074] From time t6 (corresponding to the end of operation 214), the memory cells 104 can again be used to continue the first process from the state in which it was at the time of the interrupt 206. The READ and WRITE operations of this first process resumed from time t6 are designated by reference 202. In addition, in [Fig.3], reference 218 designates the fact that the FeCAPs 116A, 116B, 120A, 120B of the memory cells 104 no longer contain, from time t6, any particular stored data since the RECALL operation 214 is destructive for the data stored in the FeCAPs 116A, 116B, 120A, 120B.

[0075] Figure 4 schematically represents control signals used in the device 100 during the implementation of the first example of the sequence of operations described above.

[0076] In the example of [Fig.4], the “SUPPLY” signal corresponds to the supply signal of the device 100, the “ERASE” signal corresponds to the signal sent on the erase line 124 and commanding the erasure of the data stored in the storage nodes 108A, 108B of the memory cells 104, the “PL_HIGH” signal corresponds to the signal applied on the first plate line 118 and the “PL_LOW” signal corresponds to the signal applied on the second plate line 122.

[0077] During the implementation of the READ and WRITE operations 202 of the first process, between times t0 and t1, the SUPPLY signal has a constant value corresponding to the value VDD of the supply voltage of the device 100, for example equal to 1.3 V. The ERASE signal remains zero, and the values ​​of the PL_HIGH and PL_LOW signals remain constant and, in this example, equal to VDD / 2 (which prevents premature aging of the FeCAPs 116A, 116B, 120A and 120B of the memory cells 104).

[0078] During the implementation of the 208 STORE operation, i.e. between times t2 and t3, the SUPPLY signal remains at the constant value VDD, and the ERASE signal remains zero. The PL_HIGH and PL_LOW signals each transition from VDD / 2 to a value greater than the coercive value Vcoer of the FeCAPs, for example, equal to 2VDD (2.6 V in this example), to write the low values ​​stored in storage nodes 108A and 108B to the two FeCAPs subjected to a voltage higher than Vcoer during this positive pulse, i.e., FeCAPs 116A and 120A or FeCAPs 116B and 120B, depending on the data stored in the SRAM cell. Then, they transition to a value less than VDD-Vcoer, for example, equal to -VDD (-1.3 V in this example), to write the low values ​​stored in storage nodes 108A and 108B to the two FeCAPs subjected to a voltage lower than -Vcoer during this negative pulse, i.e., FeCAPs 116A and 120A. FeCAPs 116B and 120B depending on the data stored in the SRAM cell, the high values ​​stored in the storage nodes 108A, 108B. In this example, the duration of operation 208 is for example equal to 480 ns.

[0079] Between times t3 and t4, when memory cells 104 are used to implement the READ and WRITE operations of the second process, the SUPPLY, ERASE, PL_HIGH, and PL_L0W signals have the same values ​​as those of the same signals during the implementation of the READ and WRITE operations of the first process. The SUPPLY signal then changes from VDD to zero for matrix 102 (change of value shown as a solid line in [Fig. 4]), and the other signals remain unchanged. When power is also cut off for the circuits and peripheral elements connected to matrix 102 (change of value shown as a dashed line in [Fig. 4]), the PL_HIGH and PL_L0W signals change from VDD / 2 to zero.

[0080] At time t4, when the requested interrupt completes, the circuits and peripheral elements of matrix 102 are powered again (the SUPPLY signal is dashed and changes to the value VDD). The first erasure operation 212 of the data stored in the storage nodes 108A, 108B of the memory cells 104 is implemented for each of the memory cells 104 by applying a pulse of value VDD to the ERASE signal.

[0081] At time t5, the RECALL 214 operation is then implemented by setting the PL_HIGH signal to the value 2.VDD and leaving the PL_L0W signal at zero. In the example described, the duration of this operation 214 can be equal to 245 ns.

[0082] At the end of this RECALL 214 operation, matrix 102 is again electrically powered, the SUPPLY signal returns to the value VDD and the PL_HIGH and PL_L0W signals return to the value VDD / 2.

[0083] As explained previously, when the memory cells 104 are no longer powered, the data stored in the SRAM cells can remain in memory for a very long time because the charges can only be discharged through very low leakage currents. Thanks to the erase operation 212 implemented before the RECALL operation, no data present in the storage nodes 108A, 108B creates a bias preventing their replacement by the data contained in the FeCAPs 116A, 116B, 120A, 120B.

[0084] Figure 5 schematically represents the same signals as those shown on [Fig.4], as well as the signals obtained on the storage nodes 108A, 108, from time t3. On this [Fig.5], the SUPPLY signal is called "GLOBAL SUPPLY" for the supply of circuits and peripheral elements to matrix 102, and "ARRAY SUPPLY" for the supply of matrix 102.

[0085] Advantageously, due to the weakening of the polarizations of the FeCAPs 116A, 116B, 120A, 120B due to the READ and WRITE operations 211 implemented in the storage nodes 108A, 108B after the interrupt 206, and in order to maximize the reliability of the subsequent RECALL operation 214, the ratio between the sum of the areas of the FeCAPs on which a signal equal to 2.VDD is applied during the RECALL operation 214 (i.e., the sum of the areas of the first FeCAPs 116A, 116B in the described example) and the sum of the areas of all the FeCAPs 116A, 116B, 120A, 120B, in each memory cell 104, is optimized and, for example, between 0.05 and 0.4, and preferably between 0.1 and 0.2 (these values ​​may vary depending on the technology used to make device 100 and the total surface area of ​​FeCAPs 116A, 116B, 120A, 120B).Such a sizing of the FeCAPs 116A, 116B, 120A, 120B makes it possible to make the implementation of a RECALL operation more reliable, even when the polarizations of the FeCAPs are weakened by READ and WRITE operations implemented in the storage nodes 108A, 108B of the memory cells 104 connected to the FeCAPs 116A, 116B, 120A, 120B. .

[0086] A second example of the embodiment of one of the memory cells 104 of the device 100 is described below in relation to [Fig.6].

[0087] Compared to the memory cell 104 previously described in relation to [Fig. 2], the memory cell 104 shown in [Fig. 6] only has the first two FeCAPs 116A and 116B, and not the second two FeCAPs 120A and 120B. Furthermore, the memory cell 104 only has the first plate line 118, and not the second plate line 122. Such a memory cell 104 is of the 6T2C type, that is, it has six transistors and two FeCAPs. In such a memory cell 104, during a RECALL operation, the signal applied to the single plate line 118 can form a ramp from 0V to VDD before the memory cells 104 are re-energized, or it can remain at 0V. During a STORE operation, the signal applied to the single plate line 118 is similar to those applied to the plate lines 118, 122 of the memory cell 104 previously described in connection with [Fig.2].

[0088] Although not described in detail here, the device 100 includes other circuits and elements coupled to the matrix 102: write driver circuits, line decoder, read amplifier, etc.

[0089] A more detailed realization of the memory cell erasure circuits 104 is described below in relation to [Fig.7].

[0090] Following the example in [Fig. 7], the device 100 comprises write driver circuits 130, each shared by a column of memory cells 104, and word line driver circuits 132, each shared by a row of memory cells 104. In this second embodiment, the erase circuits comprise:

[0091] - in each writing driver circuit 130, a first transistor, corresponding to the transistor 126 previously described, configured to couple, in the conducting state, the bit lines 112A, 112B to each other, during a data erasure operation in one of the memory cells 104 coupled to the write driver circuit 130 triggered by a pulse on an ERASE_IO signal obtained from the ERASE signal, and a second transistor 134 configured to cut, in the blocked state, a power supply to the write driver circuit 130 and to the memory cells 104 coupled to the write driver circuit 130;

[0092] - in each driver circuit of word lines 132, a first transistor 138 configured to cut off, in the blocked state, a power supply to the driver circuit of word line 132, and a second transistor 140 configured to activate, in the conducting state, word line 114, during a data erasure operation in one of the memory cells 104 coupled to this word line 114 triggered by a pulse on an ERASE_WL signal obtained from the ERASE signal.

[0093] In [Fig.7], other components and circuits of device 100 are shown, these elements not being described here.

[0094] In device 100, the presence of data in storage nodes 108A, 108B of memory cells 104 after interrupt 206 makes device 100 vulnerable to cold-boot attacks. To avoid this vulnerability, the control circuit 128 of device 100 can be configured to perform at least one second memory cell erasure operation following interrupt 206 (this second erasure operation is therefore performed before the first erasure operation described above). Thus, the data present in storage nodes 108A, 108B of memory cells 104 is erased as soon as interrupt 206 occurs, thereby preventing a cold-boot attack on device 100.

[0095] Alternatively, the memory cell erasure circuit 104 may differ from the embodiment described above. For example, the erasure circuit of device 100 may include, in each memory cell 104, a transistor comprising its source / drain electrodes coupled to the storage nodes 108A, 108B of the memory cell 104 and configured to receive on its gate an erasure control signal such as the ERASE signal described previously. Alternatively, other solutions are possible for forming the erasure circuit of device 100.

[0096] Figure 8 schematically represents the same signals as those previously described in relation to Figure 5, with the first and second erasure operations implemented between times t3 and t5. As can be seen in Figure 8, the implementation implementation of the second erasure operation from time t3 allows erasure of the data present in the storage nodes 108A, 108B via an equalization of the potentials on the two bit lines 112A, 112B.

[0097] In the first example of a sequence of operations described above, the STORE operation 208 is implemented after an interrupt 206 from which an end of power to the matrix 102 is imminent and / or so that the memory cells 104 can be used for READ and WRITE operations related to a second process different from the first process executed before the interrupt 206.

[0098] In a second example, the STORE operation 208 is implemented periodically during the execution of the first process. This second embodiment may be relevant when it is not necessary to retain the very latest data present in the memory cells 104 when the interrupt 206 occurs. In this case, the memory cells 104 can be almost instantly available for the execution of the second process.

[0099] Figure 9 schematically represents such a second example of a sequence of operations implemented in the 100 system.

[0100] As in the first example described above, READ and WRITE operations 202 of a first process are performed in memory cells 104, with device 100 functioning as conventional SRAM during these operations. Periodically, a STORE operation 208 is performed. The storage of this data in FeCAPs 116A, 116B, 120A, 120B is designated by reference 210.

[0101] During an interrupt 206, corresponding in this example to a process change, the READ and WRITE operations 211 of the second process are executed in the memory cells 104, while the data previously stored in the FeCAPs 116A, 116B, 120A, and 120B are retained. At the end of the second process, the data erasure operation 212 followed by the RECALL operation 214 are then executed. The operations 202 of the first process are then resumed in the memory cells 104, and the STORE operations 208 can be repeated periodically to regularly store the data present in the storage nodes 108A and 108B of the memory cells 104.

[0102] In a third example, the STORE 208 operation can be implemented periodically during the execution of the first process. In this third example, these periodic backups of the data present in the storage nodes 108A, 108B of the memory cells 104 serve in case of data corruption, such as an attack or hacking of the device 100.

[0103] Fig. 10 schematically represents such a third example of a sequence of operations implemented in device 100.

[0104] As in the first and second examples described above, READ and WRITE operations 202 of a first process are performed in the memory cells 104, with the device 100 functioning as a conventional SRAM memory during these operations. Periodically, a STORE operation 208 is performed. The storage of this data in the FeCAPs 116A, 116B, 120A, 120B is designated by reference 210.

[0105] During an interrupt 206, corresponding in this example to the detection of data corruption in the storage nodes 108A and 108B of the memory cells 104, the erase operation 212 of the memory cells 104 is implemented immediately after the interrupt 206, that is, successively to this interrupt 206. The RECALL operation 214 is then implemented immediately after the erase operation 212. Given the regularly executed STORE operations 208, the data transferred to the memory cells 104 during the RECALL operation 214 corresponds to uncorrupted data previously stored in the FeCAPs by the last STORE operation 208. The READ and WRITE operations 202 can then resume in the memory cells 104.

[0106] Device 100 is advantageously used in the field of embedded electronics, for example in a parallel redundant backup system or a programmable logic controller. In one embodiment, device 100 can form the memory of an electronic system also comprising a central processing unit, or CPU, with device 100 forming a volatile working memory.

[0107] In all embodiments, the memory cell erasure circuits 104 are used judiciously to eliminate potential differences between the storage nodes 108A, 108B of the memory cells 104 and to increase the reliability and speed of execution of a RECALL operation implemented after an erasure operation. This makes it possible to implement a RECALL operation without having to wait for the discharge of charges present in the storage nodes 108A, 108B of the memory cells 104.

[0108] In the various examples, the second erasure operation can make it possible to secure the device 100 against potential cold boot attacks.

[0109] In addition, in the various examples, the optimization of the dimensions of the FeCAPs 116A, 116B, 120A, 120B makes it possible to make the RECALL operation implemented even more reliable.

[0110] The different embodiment variants described in connection with the first example sequence of operations can be applied to the second and third examples sequence of operations.

[0111] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0112] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

1. Demands A non-volatile random-access static memory device (100), nvSRAM, comprising an array (102) of memory cells (104), each comprising at least: - two inverters (106A, 106B) connected to each other and forming at least two storage nodes (108A, 108B); - two access transistors (110A, 110B) each connected to one of the two storage nodes (108A, 108B) and to one of two bit lines (112A, 112B) shared by the memory cells (104) of the same column of the matrix (102), and whose gates are connected to the same word line (114) shared by the memory cells (104) of the same line of the matrix (102); - two first ferroelectric capacities (116A, 116B), FeCAPs each connected to one of the two storage nodes (108A, 108B) and to a first plate line (118) shared by the memory cells (104) of the same line of the matrix (102); the device (100) further comprising at least: - an erasure circuit (126, 134, 138, 140) configured to equalize the values ​​of the electrical potentials of the two bit lines (112A, 112B), shared by the memory cells (104) of the same column of the matrix (102), controllable by an erasure line (124); - a control circuit (128) configured to implement, for at least part of the memory cells (104), at least one first erasure operation (212) of the data stored in the two storage nodes (108A, 108B) of each of said memory cells (104) between an interrupt (206) of first read and write operations (202) in the storage nodes (108A, 108B) of said memory cells (104) and an operation (214) of writing, in the storage nodes (108A, 108B) of said memory cells (104), of values ​​stored in the first FeCAPs (116A, 116B) of said memory cells (104).

2. Device (100) according to claim 1, wherein the erasure circuit comprises at least one first transistor (126) including conduction electrodes each coupled to one of the two bit lines (112A, 112B) and including a gate coupled to the erasure line (124), said transistor (126) being configured to couple, in the on state, the two bit lines (112A, 112B) to each other.

3. Device (100) according to claim 2, further comprising write driver circuits (130) each shared by a column of memory cells (104), and word line driver circuits (132) each shared by a row of memory cells (104), and wherein the memory cell erasure circuits (104) comprise: - in each write driver circuit (130), the first transistor (126) configured to couple, in the on state, the bit lines (112A, 112B) to each other, and a second transistor (134) configured to cut, in the off state, a power supply to the write driver circuit (130) and to the memory cells (104) coupled to the write driver circuit (130);- in each word line driver circuit (132), a first transistor (138) configured to cut off, in the blocked state, a power supply to the word line driver circuit (132), and a second transistor configured to activate, in the conducting state, the word line (114).;

4. Device (100) according to any one of the preceding claims, wherein each of the memory cells (104) further comprises two second FeCAPs (120A, 120B) each connected to one of the two storage nodes (108A, 108B) and to a second plate line (122) shared by the memory cells (104) of the same line of the matrix (102).

5. Device (100) according to claim 4, wherein, in each of the memory cells (104), a ratio between the sum of the areas of the first FeCAPs (116A, 116B) and the sum of the areas of the first and second FeCAPs (116A, 116B, 120A, 120B) is between 0.05 and 0.

4.

6. Device (100) according to any one of the preceding claims, wherein, during the first operations (202) of read and write in the storage nodes (108A, 108B) of said memory cells (104), the control circuit (128) is configured to apply an electrical potential equal to half of a supply voltage of the matrix (102) on the first plate line (118) and, when each of the memory cells (104) has the second FeCAPs (120A, 120B), on the second plate line (122).

7. Device (100) according to any one of the preceding claims, wherein the control circuit (128) is configured to implement, for said at least a portion of the memory cells (104) and between the interrupt (206) of the first read and write operations (202) in the storage nodes (108A, 108B) of said memory cells (104) and the first erase operation (212), a write operation (208) in the FeCAPs (116A, 116B, 120A, 120B) of values ​​stored in the storage nodes (108A, 108B) of said memory cells (104).

8. Device (100) according to claim 7, wherein, during the writing operation (208) of writing values ​​stored in the storage nodes (108A, 108B) of said memory cells (104) into the FeCAPs (116A, 116B, 120A, 120B), the control circuit (128) is configured to apply an electrical potential greater than a coercive voltage of the FeCAPs (116A, 116B, 120A, 120B), and then an electrical potential less than the difference between a supply voltage of the matrix (102) and the coercive voltage of the FeCAPs (116A, 116B, 120A, 120B), to the first plate row (118) and, when each of the memory cells (104) includes the second FeCAPs (120A, 120B), on the second plate line (122).

9. Device (100) according to any one of claims 7 or 8, wherein the control circuit (128) is configured to implement, for said at least a portion of the memory cells (104) and between the write operation (208) in the FeCAPs (116A, 116B) of values ​​stored in the storage nodes (108A, 108B) and the first erase operation (212) of the second read and write operations (211) in the storage nodes (108A, 108B) of said memory cells (104).

10. Device (100) according to claim 9, wherein the control circuit (128) is configured to implement, for said at least part of the memory cells (104), at least a second erasure operation of said memory cells (104) successively to the interruption (206) of the first read and write operations (202) in the storage nodes (108A, 108B) of said memory cells (104).

11. Device (100) according to any one of claims 1 to 6, wherein the control circuit (128) is configured to periodically perform a write operation (208) in the FeCAPs (116A, 116B, 120A, 120B) of values ​​stored in the storage nodes (108A, 108B) of the memory cells (104).

12. Device (100) according to claim 11, wherein the control circuit (128) is configured to implement, for said at least a portion of the memory cells (104) and between the interrupt (206) of the first read and write operations (202) in the storage nodes (108A, 108B) of said memory cells (104) and the first erase operation (212), of the second read and write operations (211) in the storage nodes (108A, 108B) of said memory cells (104).

13. Device (100) according to claim 11, wherein the control circuit (128) is configured to successively implement the first erasure operation (212) of said memory cells (104) after the interruption (206) of the first read and write operations (202) in the storage nodes (108A, 108B) of said memory cells (104), and the write operation (214), in the storage nodes (108A, 108B), of the values ​​stored in the FeCAPs (116A, 116B, 120A, 120B) of said memory cells (104) after the first erasure operation (212).

14. Device (100) according to any one of the preceding claims, wherein the interruption (206) of the first read and write operations (202) in the storage nodes (108A, 108B) of said memory cells (104) corresponds to a power interruption of the matrix (102) or to a process change involving the implementation of second read and write operations (211) of data different from those used before the interruption (206).

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