Method for forming semiconductor device

Abstract

The present disclosure provides a method for forming a semiconductor device using a high-temperature heat treatment and a selective hydrogen plasma treatment to treat source / drain recesses. The high-temperature heat treatment smoothes the surface in the recess and removes oxides and etching byproducts. The hydrogen plasma treatment expands the recess vertically and horizontally and inhibits further oxidation of the surface in the recess.

Description

Technical Field

[0001] The present disclosure relates to semiconductor technology, and more particularly to semiconductor devices and methods for forming the same. Background Art

[0002] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers onto a semiconductor substrate. The layers are then patterned using photolithography techniques to form circuit components and elements.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest feature, allowing more components to be integrated into a given area. However, when the size of the smallest feature is reduced, additional problems that need to be solved arise. Summary of the Invention

[0004] An object of the embodiments of the present disclosure is to provide a method for forming a semiconductor device to solve at least one of the above problems.

[0005] In some embodiments, a method for forming a semiconductor device is provided, the method comprising forming a fin from a substrate; forming a gate structure over the fin; etching a source / drain recess on one side of the gate structure; heating the source / drain recess to a temperature greater than 700° C. to smoothen a surface of the source / drain recess by 6% to 12%; and growing an epitaxial source / drain region in the source / drain recess.

[0006] In some other embodiments, a method for forming a semiconductor device is provided, the method comprising etching a substrate to form a fin from the substrate; forming a gate structure over the fin, the gate structure comprising a gate stack, a first gate spacer on a first side of the gate stack, and a second gate spacer on a second side of the gate stack; etching a recess in the fin on a first side of the gate structure adjacent to the first gate spacer; processing the recess to remove byproducts and oxides of material of the fin from the recess and smoothing a surface of the recess; and forming an epitaxial source / drain region in the recess.

[0007] In some other embodiments, a semiconductor device is provided, comprising a remote plasma chamber including a plasma generator and a gas source; a plasma transfer chamber; and a working chamber including a showerhead and a susceptor, wherein the showerhead and the susceptor are configured to heat a workpiece on the susceptor to provide heat of at least 700° C., the susceptor comprising a metal alloy and a metal coating over the metal alloy, wherein the plasma transfer chamber connects the remote plasma chamber to the working chamber and is configured to provide plasma products to the working chamber.

[0008] The beneficial effect of the embodiments of the present disclosure is that the embodiments of the present disclosure provide a method for treating the notch by high temperature heat treatment and selective hydrogen radical treatment. These treatments improve the surface quality of the notch, so that the epitaxial source / drain region is deposited in the notch with higher quality, resulting in less leakage current and a more efficient device. The processing device includes a processing chamber for providing high temperature heat treatment, the processing chamber includes a heated platform and a heated nozzle, the heated platform is coated with metal to prevent the platform material from diffusing into the workpiece, and the heated platform and the heated nozzle together provide high heat to the workpiece. The processing chamber may also include a remote plasma source, which provides hydrogen radicals to the workpiece for hydrogen radical treatment. The final device has increased drive current efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following detailed description and accompanying drawings provide a better understanding of the disclosed embodiments. It should be noted that, in accordance with standard industry practice, the various features shown in the figures are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced to provide clarity.

[0010] Figure 1 A three-dimensional view of an example of a Fin Field-Effect Transistor (FinFET) according to some embodiments is shown.

[0011] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 14D 、 Figure 15A 、 Figure 15B 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 19A 、 Figure 19B 、 Figure 20A and Figure 20B FIG. 1 is a schematic cross-sectional view of an intermediate stage of fabricating a FinFET according to some embodiments.

[0012] Figure 21 and Figure 22 is a schematic diagram of a processing tool according to some embodiments.

[0013] Figure 23 and Figure 24 FIG. 1 is a flow chart of a process for adding or removing a metal coating from a substrate according to some embodiments.

[0014] The reference numerals are as follows:

[0015] 50: Base

[0016] 50N,50P,89: Area

[0017] 51: Dividing line

[0018] 52: Fin

[0019] 54: Insulation material

[0020] 56: Isolation Zone

[0021] 58: Channel Area

[0022] 60: dummy dielectric layer

[0023] 62: dummy gate layer

[0024] 64: mask layer

[0025] 72: dummy gate

[0026] 74: Mask

[0027] 80: Gate sealing spacer

[0028] 82: epitaxial source / drain region

[0029] 82A: First stage source / drain region

[0030] 86: Gate spacer

[0031] 87: Contact etch stop layer

[0032] 88: first interlayer dielectric

[0033] 90,150,170: notch

[0034] 92: Gate dielectric layer

[0035] 94: Gate electrode

[0036] 94A: cushion layer

[0037] 94B: Work function adjustment layer

[0038] 94C: Filling material

[0039] 96: Gate mask

[0040] 108: Second interlayer dielectric

[0041] 110: Gate contact

[0042] 112: Source / drain contact

[0043] 155: Residue

[0044] 160: High temperature heat treatment

[0045] 165: Hydrogen radical treatment

[0046] 200: Processing tools

[0047] 205: Computer host

[0048] 210,215.220: Processing cavity

[0049] 300: working chamber

[0050] 310:Transmission cavity

[0051] 320: Remote plasma chamber

[0052] 325: Remote Plasma Generator

[0053] 330: Gas Source

[0054] 335: Remote Plasma

[0055] 340: Institution

[0056] 350: Base

[0057] 360:Metal coating

[0058] 370: Workpiece

[0059] 380: Nozzle

[0060] 410,420,430,440,450,460: Steps

[0061] h1,h2: height

[0062] s1, s2: surface smoothness

[0063] w1,w2: width DETAILED DESCRIPTION

[0064] It should be understood that the following disclosure provides many different embodiments or examples to implement different components of the provided subject matter. Specific examples of the various components and their arrangements are described below in order to simplify the description of the disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, the following disclosure describes forming a first component on or above a second component, which means that it includes an embodiment in which the formed first component and the second component are in direct contact, and also includes an embodiment in which additional components can be formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, different examples in the disclosure may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplicity and clarity, and are not intended to limit the relationship between the various embodiments and / or the described appearance structures.

[0065] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and similar terms, may be used to conveniently describe the relationship of one element or component to another element or component in the drawings. Spatially relative terms also encompass different orientations of a device in use or operation in addition to the orientations depicted in the drawings. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the descriptions of the spatially relative terms interpreted accordingly.

[0066] During the process of forming the source / drain regions of a fin field-effect transistor (FinFET), the area of ​​the fin corresponding to the source / drain regions can be recessed, and epitaxial semiconductor material can be grown in the recess. However, during the process step of recessing the source / drain regions, the recess can have a rough surface that negatively impacts the quality of the epitaxial source / drain regions. Embodiments disclosed herein include a process for providing a smooth surface for the recess prior to forming the epitaxial source / drain regions. One embodiment includes a high-temperature process in a modified processing chamber to remove oxides, while another embodiment also includes a hydrogen radical treatment to prevent reoxidation and improve cleaning efficiency. Following this process, the subsequently formed epitaxial source / drain regions provide increased device current performance. Specifically, the ratio of drive current (Ideff) to leakage current (Ioff) can be increased by 3% to 4%. In other words, leakage current is reduced. Furthermore, the process described herein achieves better epitaxial growth of the source / drain regions, which can increase on-state current. Furthermore, a yield window for better landing of the subsequent contact formation can be achieved. In other words, since the epitaxy is of higher quality, the epitaxy's top surface has a larger effective landing area to receive the contacts, thereby increasing the overall yield.

[0067] Figure 1 A three-dimensional view of an example of a fin field-effect transistor according to some embodiments is shown. The fin field-effect transistor includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). An isolation region 56 (sometimes referred to as a shallow trench isolation (STI) region) is disposed in the substrate 50, and the fin 52 protrudes above the adjacent isolation region 56. Although the isolation region 56 and the substrate 50 are described / shown separately, the term "substrate" as used herein may refer solely to a semiconductor substrate or a semiconductor substrate including an isolation region. In addition, although the fin 52 and the substrate 50 are shown as a single, continuous material, the fin 52 / or the substrate 50 may include a single material or multiple materials. As used herein, the fin 52 may refer to the portion extending between adjacent isolation regions 56.

[0068] A gate dielectric layer 92 is formed along the sidewalls and top surface of the fin 52, and a gate electrode 94 is formed over the gate dielectric layer 92. Epitaxial source / drain regions 82 are formed on both sides of the fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. Figure 1Reference cross sections for subsequent figures are also shown. Cross section AA is along the longitudinal axis of gate electrode 94 and in a direction perpendicular to, for example, the direction of current flow between epitaxial source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of fin 52 and in a direction perpendicular to, for example, the direction of current flow between epitaxial source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0069] Some embodiments described herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate use in planar devices, such as planar FETs.

[0070] Figure 2-16B 2-7 are cross-sectional views of intermediate stages of manufacturing a FinFET according to some embodiments. Figure 1 In the reference cross-section AA, there are multiple fins / FinFETs in addition to the above figures. Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A and Figure 20A Along Figure 1 The reference section AA in is shown, and Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B 、 Figure 18B 、 Figure 18C 、 Figure 19B and Figure 20B Along Figure 1 A similar cross-section BB in FIG. 1 is shown, except that there are multiple fins / FinFETs in the above figure. Figure 14C and Figure 14D along Figure 1 Reference cross section CC shows that there are multiple fins / FinFETs in addition to the above figures. Figure 11C A close-up view of the substrate surface is shown below.

[0071] exist Figure 2 In the embodiment of the present invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 50 may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), an alloy semiconductor (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or a combination thereof.

[0072] Substrate 50 has a region 50N and a region 50P. Region 50N can be used to form an n-type device, such as an n-type metal oxide semiconductor (NMOS) transistor (e.g., an n-type FinFET). Region 50P can be used to form a p-type device, such as a p-type metal oxide semiconductor (PMOS) transistor (e.g., a p-type FinFET). Region 50N can be physically separated from region 50P (by a separation line 51), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between region 50N and region 50P.

[0073] exist Figure 3 In the embodiment of the present invention, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. This etching process can be any suitable etching process, such as reactive ion etching (RIE), neutron beam etching (NBE), similar methods, or combinations thereof. This etching process can be anisotropic.

[0074] The fins can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography and self-aligned processes to create patterns with smaller pitches, for example, patterns with smaller pitches than can be achieved using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the fins can then be patterned using the remaining spacers. In some embodiments, a mask (or other layer) may remain on the fins 52.

[0075] exist Figure 4 Insulating material 54 is formed over substrate 50 and between adjacent fins 52. Insulating material 54 may be an oxide (e.g., silicon oxide), a nitride, the like, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., deposition of a CVD-based material in a remote plasma system followed by post-curing to convert it to another material, such as an oxide), the like, or a combination thereof. Other insulating materials may be formed using any suitable process. In the illustrated embodiment, insulating material 54 is silicon oxide formed by a flowable CVD process. After forming the insulating material, an annealing process may be performed. In one embodiment, insulating material 54 may be formed such that excess insulating material 54 covers fins 52. Although insulating material 54 is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown) may be initially formed along the surfaces of substrate 50 and fins 52. Subsequently, a filler material, as described above, may be formed over the liner.

[0076] exist Figure 5 In the process, a removal process is performed on the insulating material 54 to remove excess insulating material 54 above the fins 52. In some embodiments, a planarization process may be used, such as a chemical mechanical polish (CMP), an etch-back process, a combination thereof, or the like. The planarization process exposes the fins 52 such that, after the planarization process is completed, the top surface of the fins 52 is flush with the top surface of the insulating material 54. In embodiments where a mask remains on the fins 52, the planarization process may expose the mask or remove the mask such that, after the planarization process is completed, the top surface of the mask or the top surface of the fins 52, respectively, is flush with the top surface of the insulating material.

[0077] exist Figure 6 , insulating material 54 is recessed to form isolation regions 56. Insulating material 54 is recessed so that the upper portions of fins 52 in regions 50N and 50P protrude from between adjacent isolation regions 56. Furthermore, the top surface of isolation regions 56 may have a flat surface as shown, a convex surface, a concave surface (e.g., a recess), or a combination thereof. The top surface of isolation regions 56 may be formed flat, convex, and / or concave using a suitable etching process. Isolation regions 56 may be recessed using a suitable etching process, such as an etching process that is selective to the material of insulating material 54 (e.g., an etching rate that etches insulating material 54 greater than the etching rate of fins 52). For example, dilute hydrofluoric acid (dHF) may be used for oxide removal.

[0078] The process described in Figures 2-6 is only one example of how fin 52 can be formed. In some embodiments, the fin can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of substrate 50, and a trench can be etched through the dielectric layer to expose the substrate 50 below. A homoepitaxial structure can be epitaxially grown in the trench, and the dielectric layer can be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. In addition, in some embodiments, a heteroepitaxial structure can be used for fin 52. For example, Figure 5 The fin 52 in the substrate 50 is recessed, and a material different from the fin 52 is epitaxially grown over the recessed fin 52. In these embodiments, the fin 52 includes the recessed material and the epitaxially grown material disposed over the recessed material. In another embodiment, a dielectric layer can be formed over the top surface of the substrate 50, and a trench can be etched through the dielectric layer. Next, a heteroepitaxial structure can be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments of epitaxially grown homoepitaxial or heteroepitaxial structures, the epitaxially grown material can be doped in situ during growth, which can obviate the need for prior or subsequent implantation, although both in situ and implantation doping can be used together.

[0079] Furthermore, it may be advantageous to have epitaxial growth in region 50N (eg, N-type metal oxide semiconductor region) different from that in region 50P (eg, P-type metal oxide semiconductor region). In various embodiments, the upper portion of fin 52 may be made of silicon germanium (SiGe). x Ge 1-x, where x may be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a Group III-V compound semiconductor, a Group II-VI compound semiconductor, or the like. For example, materials that can be used to form the Group III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0080] exist Figure 6 In the embodiment of the present invention, suitable well regions (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a P-type well may be formed in the region 50N, and an N-type well may be formed in the region 50P. In some embodiments, either a P-type well or an N-type well may be formed in both the region 50N and the region 50P.

[0081] In an embodiment with different well types, different implantation steps for region 50N and region 50P can be achieved by using a photoresist or other mask (not shown). For example, a photoresist can be formed over the fin 52 and isolation region 56 in region 50N. The photoresist is patterned to expose region 50P (e.g., a P-type metal oxide semiconductor region) of substrate 50. The photoresist can be formed using a spin coating technique and can be patterned using a suitable photolithography technique. After the photoresist is patterned, n-type impurities are implanted into region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into region 50N (e.g., an N-type metal oxide semiconductor region). The n-type impurity can be phosphorus, arsenic, antimony, or the like in the implanted region to a concentration equal to or less than 10 18 cm -3 , for example, at about 10 16 cm -3 to about 10 18 cm -3 After implantation, the photoresist may be removed, for example, by a suitable ashing process.

[0082] After the implantation of region 50P, a photoresist is formed over fin 52 and isolation region 56 in region 50P. The photoresist is patterned to expose region 50N (e.g., an N-type metal oxide semiconductor region) of substrate 50. The photoresist may be formed using a spin coating technique and may be patterned using a suitable photolithography technique. After the photoresist is patterned, a p-type impurity is implanted into region 50N, and the photoresist may serve as a mask to substantially prevent the p-type impurity from being implanted into region 50P (e.g., a P-type metal oxide semiconductor region). The p-type impurity may be boron, boron fluoride, indium, or the like in the implanted region to a concentration equal to or less than 10 18 cm -3 , for example, at about 10 16 cm -3to about 10 18 cm -3 After implantation, the photoresist may be removed, for example, by a suitable ashing process.

[0083] After implantation of regions 50N and 50P, annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growing material of the epitaxial fins may be in-situ doped during growth, which may eliminate implantation, but both in-situ and implantation doping may be used.

[0084] exist Figure 7 In the embodiment of the present invention, a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown using suitable techniques. A dummy gate layer 62 is formed over the dummy dielectric layer 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 may be deposited over the dummy dielectric layer 60 and then planarized by chemical mechanical polishing. The mask layer 64 may be deposited over the dummy gate layer 62. The dummy gate layer 62 may be a conductive material or a non-conductive material, and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), chemical vapor deposition, sputtering deposition, or other techniques known and used in the art for depositing the selected material. The dummy gate layer 62 can be made of other materials having high etch selectivity with respect to the etching of the isolation region. The mask layer 64 can include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single layer of dummy gate layer 62 and a single layer of mask layer 64 are formed to span region 50N and region 50P. It can be noted that the dummy dielectric layer 60 is shown covering the fin 52 for illustrative purposes only. In some embodiments, the dummy dielectric layer 60 can be deposited so that the dummy dielectric layer 60 covers the isolation region 56, and the dummy dielectric layer 60 extends between the dummy gate layer 62 and the isolation region 56.

[0085] exist Figure 8A and Figure 8B, mask layer 64 is patterned using suitable photolithography and etching techniques to form mask 74. The pattern of mask 74 can then be transferred to dummy gate layer 62 to form dummy gate 72. In some embodiments (not shown), the pattern of mask 74 can also be transferred to dummy dielectric layer 60 using suitable etching techniques. Dummy gates 72 cover channel regions 58 of corresponding fins 52. The pattern of mask 74 can be used to physically separate each dummy gate 72 from adjacent dummy gates. Dummy gates 72 can also have a length direction that is substantially perpendicular to the length direction of the corresponding epitaxial fin 52.

[0086] Furthermore, in Figure 8A and Figure 8B In the embodiment of the present invention, gate sealing spacers 80 may be formed on the exposed surfaces of the dummy gate 72, the mask 74, and / or the fin 52. The gate sealing spacers 80 may be formed by thermal oxidation or deposition followed by anisotropic etching. The gate sealing spacers 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0087] After forming the gate sealing spacer 80, an implantation for lightly doped source / drain (LDD) regions (not explicitly shown) may be performed. Figure 6 For the implantation, a mask (e.g., photoresist) may be formed over region 50N while exposing region 50P, and an impurity of a suitable type (e.g., p-type) may be implanted into the exposed fin 52 in region 50P. The mask may then be removed. Thereafter, a mask (e.g., photoresist) may be formed over region 50P while exposing region 50N, and an impurity of a suitable type (e.g., n-type) may be implanted into the exposed fin 52 in region 50N. The mask may then be removed. The n-type impurity may be any of the aforementioned n-type impurities, and the p-type impurity may be any of the aforementioned p-type impurities. The lightly doped source / drain regions may have an impurity concentration of about 10 15 cm -3 to about 10 19 cm -3 Annealing can be used to repair implant damage and activate implanted impurities.

[0088] exist Figure 9A and 9B In the embodiment of the present invention, gate spacers 86 are formed on gate sealing spacers 80 along the sidewalls of dummy gate 72 and mask 74. Gate spacers 86 can be formed by conformally depositing an insulating material followed by anisotropic etching of the insulating material. The insulating material of gate spacers 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, combinations thereof, or the like.

[0089] It may be noted that the above disclosure generally describes a process for forming spacers and lightly doped source / drain regions. Other processes and sequences may be used. For example, fewer or more spacers may be used, and steps may be performed in a different order (e.g., the gate sealing spacer 80 may not be etched prior to forming the gate spacer 86, resulting in an "L-shaped" gate sealing spacer, spacers may be formed and removed, etc.). Furthermore, n-type and p-type devices may be formed using different structures and steps. For example, lightly doped source / drain regions for n-type devices may be formed prior to forming the gate sealing spacer 80, while lightly doped source / drain regions for p-type devices may be formed after forming the gate sealing spacer 80.

[0090] exist Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 14C and Figure 14D , the formation of epitaxial source / drain regions 82 is described (see, for example, Figure 14B ) process. Epitaxial source / drain regions 82 are formed in the fins 52 to apply stress in the corresponding channel regions 58, thereby improving performance. The epitaxial source / drain regions 82 are formed in the fins 52 so that each dummy gate 72 is disposed between each pair of adjacent epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into the fins 52 and may also penetrate the fins 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gate 72 at an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short-circuit the gate of the final FinFET formed subsequently.

[0091] exist Figure 10A and Figure 10BIn the embodiment of the present invention, the epitaxial source / drain regions 82 in the region 50N (e.g., N-type metal oxide semiconductor region) can be formed by masking the region 50P (e.g., P-type metal oxide semiconductor region) and etching the source / drain regions of the fin 52 in the region 50N to form a recess 150 in the fin 52. Similarly, the epitaxial source / drain regions 82 in the region 50P (e.g., P-type metal oxide semiconductor region) can be formed by masking the region 50N (e.g., N-type metal oxide semiconductor region) and etching the source / drain regions of the fin 52 in the region 50P to form a recess 150 in the fin 52. The recess 150 in the region 50N and the recess 150 in the region 50P can be formed in the same or different processes. Subsequently, the epitaxial source / drain regions 82 can be formed in each of the region 50N and the region 50P using different processes using suitable materials, as described in further detail below.

[0092] Recess 150 may be formed using any suitable process, such as dry etching (e.g., reactive ion etching (RIE)) or wet etching using a suitable material. As a result of etching recess 150, residue 155 may remain in recess 150. This residue 155 may include byproducts of the etching process and oxides of the material of fin 52.

[0093] exist Figure 11A 、 Figure 11B and Figure 11C In the embodiment, the recess 150 is subjected to a high temperature heat treatment 160, which results in a burnout residue 155, including burnout byproducts and oxides. In some embodiments, the high temperature heat treatment 160 can be performed in a hydrogen environment, thereby causing the residue 155 to react with the hydrogen, which can then be evacuated from the processing chamber containing the substrate 50. As a result of the high temperature heat treatment 160, the surface smoothness is increased, thereby providing a better base for the epitaxial source / drain region 82 in the recess 150. Figure 11C , a close-up cross-sectional schematic diagram of the substrate 50 is provided, which shows the surface smoothness s1 of the substrate 50 in the recess 150 before the high-temperature heat treatment 160 (upper figure) and the surface smoothness s2 of the substrate 50 in the recess 150 after the high-temperature heat treatment 160 (lower figure). The surface smoothness s1 and s2 are root-mean-square (RMS) calculation values ​​of the vertical distance from the vertex to the lowest point of the surface of the recess 150. In some embodiments, the surface smoothness s2 of the surface of the recess 150 after the high-temperature heat treatment 160 may be between about 0.24 nm RMS and 0.26 nm RMS, for example, about 0.25 nm RMS. The surface smoothness s1 before the high-temperature heat treatment 160 may be between about 0.26 nm RMS and 0.28 nm RMS, for example, about 0.27 nm RMS. Therefore, the nm RMS surface smoothness can be reduced by about RMS to approx. RMS, the smoothness of the notch 150 may be increased by about 6% to about 12%, although other values ​​are also contemplated.

[0094] The recess may be subjected to a high-temperature heat treatment 160 at a temperature between about 700° C. and about 900° C. (e.g., about 800° C.) for between about 60 seconds and 120 seconds (e.g., about 90 seconds). The high-temperature heat treatment 160 may be performed in a vacuum environment at a pressure of about 100 torr to about 200 torr (e.g., about 150 torr), although other values ​​may be used. In some embodiments, a hydrogen environment may be provided by introducing hydrogen into the chamber at a flow rate of between about 25,000 sccm and about 31,000 sccm (e.g., about 28,000 sccm).

[0095] In some embodiments, a separate coating process may be used to coat the base of the processing chamber with a metal coating. The base holds the substrate 50 during the high temperature heat treatment 160. The metal coating may be used to prevent the material of the base from leaching into the substrate 50 during the high temperature heat treatment 160. Figure 23-24 The coating process is further described.

[0096] The recess 150 may have a height h1 and a width w1. The height h1 may be measured vertically from the lowest point of the recess 150 to the top of the fin 52. The width w1 may be measured at the widest point of the recess 150. In some embodiments, the height h1 may be between about 40 nm and about 60 nm, for example, between about 48 nm and about 50 nm, although other values ​​are contemplated and may be used. In some embodiments, the width w1 may be between about 18 nm and about 28 nm, for example, between about 22 nm and about 24 nm, although other values ​​are contemplated and may be used.

[0097] exist Figure 12A and Figure 12B In some embodiments, a selective hydrogen radical treatment 165 may be performed. The hydrogen radical treatment 165 provides hydrogen radicals to the recess 150. The hydrogen radicals cause the recess 150 to become more recessed and widen to a lateral extent exceeding the original mask used to form the recess 150. The deeper and wider recess 170 has a height h2 and a width w2. The height h2 can be measured vertically from the lowest point of the recess 170 to the top of the fin 52. The width w2 can be measured at the widest point of the recess 170. In some embodiments, the lateral extent of the width of the recess 170 can be vertically aligned with a portion of the gate spacer 86. In some embodiments, the lateral extent of the width of the recess 170 can be vertically aligned with a portion of the gate sealing spacer 80.

[0098] In some embodiments, the height h2 may be between about 41 nm and about 71 nm, for example, between about 49 nm and about 51 nm, although other values ​​are contemplated and may be used. In some embodiments, the width w2 may be between about 20 nm and about 34 nm, for example, between about 24 nm and about 29 nm, although other values ​​are contemplated and may be used. Thus, due to the hydrogen radical treatment 165, the width may increase by about 10% to about 30%, and the height may increase by about 2% to about 7%, although other values ​​outside these ranges are achievable and contemplated. Furthermore, due to the hydrogen radical treatment 165, the width w2 of the recess 170 may increase by 2 nm to 6 nm relative to the width w1 of the recess 150, and the height h2 of the recess 170 may increase by 1 nm to 3 nm relative to the height h1 of the recess 150.

[0099] The hydrogen radical treatment 165 provides hydrogen radicals to Figure 11B The surface of the recess 150. Hydrogen radicals may be formed from a remote plasma source, such as the following reference Figure 22 As described. The plasma may be formed from hydrogen gas. The remote plasma will produce ions and radicals of hydrogen gas. The ions may be deflected by a charged transfer tube or other charged plate, which will attract the ions so that the hydrogen ions do not generally pass through the processing chamber. The hydrogen radicals enter the processing chamber and contact the substrate 50 in the recess 150. The hydrogen radicals enter the processing chamber and will react with the substrate 50 and any residual material that may be left after the high temperature heat treatment 160. In some embodiments, hydrogen may react with silicon and form a stable silicon hydride compound, such as silane, disilane, or trisilane, at the surface of the substrate 50 in the recess 170. The silicon hydride compound in the recess 170 is, for example, Figure 11B The untreated notch 150 is more resistant to oxidation.

[0100] As a result of the hydrogen radical treatment 165, the chemically stable silicon hydride compounds can reduce or prevent reoxidation of the recess 170 when the substrate 50 is moved to the deposition chamber for growing the epitaxial source / drain regions 82. The hydrogen radical treatment 165 also improves the cleaning efficiency of the high-temperature thermal treatment 160 and can also improve the cleaning efficiency of a separate cleaning process that may be performed after the hydrogen radical treatment 165 and before growing the epitaxial source / drain regions 82.

[0101] After forming the epitaxial source / drain regions 82 (described further below), in embodiments using a hydrogen radical treatment 165, a hydrogen concentration may be observed at the interface between the epitaxial source / drain regions 82 and the substrate 50. The hydrogen concentration may be greatest at the interface and have a first gradient of decreasing concentration further into the substrate 50 and a second gradient of decreasing concentration further into the subsequently formed epitaxial source / drain regions 82. During subsequent processing, hydrogen may diffuse from the substrate 50 into the epitaxial source / drain regions 82.

[0102] exist Figure 13A and Figure 13B In the embodiment, epitaxial growth of the epitaxial source / drain regions 82 in the regions 50N and 50P begins in the recess 170. Figure 13A and Figure 13B As shown, epitaxial source / drain regions 82 may be grown in two or more stages. Figure 13A and Figure 13B First-stage source / drain regions 82A are shown after first-stage epitaxial growth. The uniformity of first-stage source / drain regions 82A is improved due to high-temperature heat treatment 160 and hydrogen radical treatment 165. Because first-stage source / drain regions 82A serve as a foundation for growing the remainder of epitaxial source / drain regions 82, the uniformity of first-stage source / drain regions 82A also improves the uniformity of the remainder of subsequently formed epitaxial source / drain regions 82.

[0103] exist Figure 14A and Figure 14B The remainder of epitaxial source / drain regions 82 are formed in region 50N. In region 50N, epitaxial source / drain regions 82 (including first-stage source / drain regions 82A) may comprise any suitable material, such as a material suitable for an n-type fin field-effect transistor. For example, if fin 52 is silicon, epitaxial source / drain regions 82 in region 50N may comprise a material that imparts tensile strain in channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. Epitaxial source / drain regions 82 in region 50N may have surfaces that are raised from respective surfaces of fin 52 and may be faceted.

[0104] In region 50P, epitaxial source / drain regions 82 (including first-stage source / drain regions 82A) may comprise any suitable material, such as a material suitable for a p-type fin field-effect transistor. For example, if fin 52 is silicon, epitaxial source / drain regions 82 in region 50P may comprise a material that imparts compressive strain in channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. Epitaxial source / drain regions 82 in region 50P may also have surfaces that are raised from the respective surfaces of fin 52 and may be faceted.

[0105] Since the epitaxial source / drain regions 82 are of high quality, the landing area for the subsequently formed contacts is increased. For example, in some embodiments, the size of the landing area can be from about 50 nm to about 100 nm. 2 and 100nm 2 Increased to about 150nm 2 and 200nm 2 Therefore, the disclosed embodiment increases the landing area by between about 200% and about 300% relative to the unprocessed notch opening. Having a larger landing area means that the lithography tolerance is looser, so more contacts can be successfully produced, thereby increasing the overall device yield. Furthermore, due to the good epitaxial growth, the device's on / off current ratio (I on -I off ratio), where I on is the maximum or on-state current, and I off Therefore, the device efficiency can be increased and the drive current (I deff In particular, as described above, the leakage current (I off ).

[0106] The epitaxial source / drain regions 82 (including the first stage source / drain regions 82A) and / or the fins 52 may be implanted with dopants to form source / drain regions, using a process similar to that described above for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have an impurity concentration of approximately 10 19 cm -3 to about 10 21 cm -3 The n-type impurities and / or p-type impurities used in the source / drain regions may be any of the impurities described above. In some embodiments, the epitaxial source / drain regions 82 may be in-situ doped during growth.

[0107] Due to the epitaxial process used to form epitaxial source / drain regions 82 in regions 50N and 50P, the upper surfaces of epitaxial source / drain regions 82 have facets that extend laterally outward beyond the sidewalls of fins 52. Figure 14C As shown, these facets result in the merging of adjacent epitaxial source / drain regions 82 of the same FinFET. Figure 14D As shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 82 remain separated. Figure 14C and Figure 14DIn the embodiment shown, gate spacers 86 are formed to cover a portion of the sidewalls of fin 52, which extend above isolation region 56 to block epitaxial growth. In some other embodiments, the spacer etch used to form gate spacers 86 can be adjusted to remove spacer material so that the epitaxial growth region extends to the surface of isolation region 56.

[0108] exist Figure 15A and Figure 15B In the process, a first inter-layer dielectric (ILD) 88 is deposited on Figure 10A and Figure 10B . A first interlayer dielectric 88 may be formed of a dielectric material and may be deposited by any suitable method, such as chemical vapor deposition, plasma-enhanced CVD (PECVD), or flowable chemical vapor deposition (FCVD). The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials may be formed using any suitable process. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first interlayer dielectric 88 and the epitaxial source / drain regions 82, the mask 74, and the gate spacers 86. The CESL 87 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like. The CESL 87 may have a different etch rate than the first interlayer dielectric 88 thereover.

[0109] exist Figure 16A and Figure 16B In the process, a planarization process (e.g., chemical mechanical polishing) may be performed to make the top surface of the first interlayer dielectric 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process may also remove the mask 74 on the dummy gate 72 and the portions of the gate sealing spacer 80 and the gate spacer 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacer 80, the gate spacer 86, and the first interlayer dielectric 88 are flush. Therefore, the top surface of the dummy gate 72 exposes the first interlayer dielectric 88. In some embodiments, the mask 74 may be retained, in which case the planarization process makes the top surface of the first interlayer dielectric 88 flush with the top surface of the mask 74.

[0110] exist Figure 17A and Figure 17B In the etching step, the dummy gate 72 and, if present, the mask 74 are removed to form a recess 90. A portion of the dummy dielectric layer 60 in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, while the dummy dielectric layer 60 remains, and the recess 90 exposes the dummy dielectric layer 60. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in a first region of the die (e.g., the core logic region) and remains in the recess 90 in a second region of the die (e.g., the input / output region). In some embodiments, the dummy gate 72 is removed using an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas to selectively etch the dummy gate 72 without etching the first interlayer dielectric 88 or the gate spacers 86. Each recess 90 exposes and / or covers the channel region 58 of a corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During the removal process, the dummy dielectric layer 60 may serve as an etch stop layer when etching the dummy gate 72. Then, after the dummy gate 72 is removed, the dummy dielectric layer 60 may be selectively removed.

[0111] exist Figure 18A and Figure 18B In the embodiment, a gate dielectric layer 92 and a gate electrode 94 are formed as a replacement gate. Figure 18C for Figure 18B Detailed view of region 89 of FIG. A gate dielectric layer 92 is conformally deposited in recess 90 , for example, on the top surface and sidewalls of fin 52 and on the sidewalls of gate seal spacer 80 / gate spacer 86 . Gate dielectric layer 92 may also be formed on the top surface of first interlayer dielectric 88 . In some embodiments, gate dielectric layer 92 comprises silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, gate dielectric layer 92 comprises a high-k dielectric material, and in these embodiments, gate dielectric layer 92 may have a dielectric constant value greater than approximately 7.0 and may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. Methods for forming gate dielectric layer 92 may include molecular-beam deposition (MBD), atomic layer deposition (ALD), plasma-assisted chemical vapor deposition, and the like. In the embodiment where a portion of the dummy dielectric layer 60 remains in the recess 90 , the gate dielectric layer 92 comprises the material of the dummy dielectric layer 60 (eg, SiO 2-- ).

[0112] The gate electrodes 94 are deposited over the gate dielectric layer 92 and fill the remaining portion of the recess 90. The gate electrodes 94 may comprise a metal-containing material such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiple layers thereof. For example, although Figure 18B A single layer of gate electrode 94 is shown, but gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and filler materials 94C, such as Figure 18C As shown. After filling the recess 90, a planarization process (e.g., chemical mechanical polishing) may be performed to remove excess portions of the gate dielectric layer 92 and gate electrode 94 material that are above the top surface of the first interlayer dielectric 88. Thus, the remaining portions of the gate electrode 94 and gate dielectric layer 92 material form the replacement gate of the final FinFET. The gate electrode 94 and gate dielectric layer 92 may be collectively referred to as a "gate stack." The gate and gate stack may extend along the sidewalls of the channel region 58 of the fin 52.

[0113] The formation of gate dielectric layer 92 in region 50N and region 50P can occur simultaneously, such that gate dielectric layer 92 in each region is formed of the same material, and the formation of gate electrode 94 can occur simultaneously, such that gate electrode 94 in each region is formed of the same material. In some embodiments, gate dielectric layer 92 in each region can be formed using different processes, such that gate dielectric layer 92 can be made of different materials, and / or gate electrode 94 in each region can be formed using different processes, such that gate electrode 94 can be made of different materials. When different processes are used, various masking steps can be used to mask and expose appropriate regions.

[0114] exist Figure 19A and Figure 19B In some embodiments, the second interlayer dielectric 108 is deposited over the first interlayer dielectric 88. In some embodiments, the second interlayer dielectric 108 is a flowable film formed by a flowable chemical vapor deposition method. In some embodiments, the second interlayer dielectric 108 is formed of a dielectric material, such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like, and can be deposited by any suitable method, such as chemical vapor deposition and plasma-assisted chemical vapor deposition. According to some embodiments, before forming the second interlayer dielectric 108, the gate stack (including the gate dielectric layer 92 and the corresponding upper gate electrode 94) is recessed so that a recess is formed directly above the gate stack and between the two side portions of the gate spacer 86, such as Figure 19A and Figure 19BAs shown. A gate mask 96 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, or the like) is filled in the recess. Next, a planarization process is performed to remove the excess portion of the dielectric material extending above the first interlayer dielectric 88. The gate contact 110 (see Figure 20A and Figure 20B ) penetrates the gate mask 96 to contact the top surface of the recessed gate electrode 94.

[0115] exist Figure 20A and Figure 20B In the figure, according to some embodiments, gate contact 110 and source / drain contact 112 are formed through second interlayer dielectric 108 and first interlayer dielectric 88. An opening for source / drain contact 112 is formed through first interlayer dielectric 88 and second interlayer dielectric 108, while an opening for gate contact 110 is formed through second interlayer dielectric 108 and gate mask 96. The opening can be formed using suitable photolithography and etching techniques. Because epitaxial source / drain regions 82 are of high quality, the landing area for source / drain contact 112 is increased. This allows for a larger lithography window for forming the opening for source / drain contact 112. As a result, overall productivity can be increased.

[0116] A liner (e.g., a diffusion barrier, adhesion layer, or the like) and a conductive material are formed in the opening. The liner may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, cobalt, aluminum, nickel, or the like. A planarization process (e.g., chemical mechanical polishing) may be performed to remove excess material from the surface of the second interlayer dielectric 108. The remaining liner and conductive material form source / drain contacts 112 and gate contact 110 in the opening. An annealing process may be performed to form silicide at the interface between the epitaxial source / drain regions 82 and the source / drain contacts 112. The source / drain contacts 112 are physically and electrically coupled to the epitaxial source / drain regions 82, and the gate contact 110 is physically and electrically coupled to the gate electrode 94. The source / drain contacts 112 and the gate contact 110 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each source / drain contact 112 and gate contact 110 can be formed in different cross-sections to avoid shorting of the contacts. Because the process described in the embodiments of the present disclosure provides a larger landing area for the epitaxial source / drain regions 82, the corresponding source / drain contacts 112 can achieve better electrical and physical connections to the epitaxial source / drain regions 82.

[0117] According to some embodiments, Figure 21, a block diagram of a process tool 200 is shown. The process tool 200 includes a computer host 205 that includes control capabilities to move a workpiece from one cavity of the process tool 200 to another cavity. The computer host 205 is also configured to receive the workpiece at a load port and provide the workpiece to an outlet of the process tool 200. The computer host 205 is also configured to move the workpiece to a location not shown in FIG. Figure 21 other tools and / or cavities of the processing tool 200.

[0118] The processing cavity 210 is a processing cavity that forms a U-shaped recess (such as recess 150) in the substrate 50 (see Figure 10B After the recess 150 is formed in the substrate 50, the computer host 205 can move the workpiece with the substrate 50 from the processing chamber 210 to the processing chamber 215, and the processes of the high temperature heat treatment 160 and the selective hydrogen radical treatment 165 can be performed in the processing chamber 215 (see Figure 11B and Figure 12B In some embodiments, when the workpiece is moved from processing chamber 210 to processing chamber 215, the vacuum in processing chamber 210 may be broken, allowing ambient air to contact substrate 50, oxidize substrate 50, and affect residue 155 generated when forming recess 150. In other embodiments, the vacuum may be maintained when the workpiece is moved from processing chamber 210 to processing chamber 215. After processing in processing chamber 215, computer host 205 may move the workpiece to another processing chamber 220 for epitaxially growing epitaxial source / drain regions 82.

[0119] exist Figure 22 In more detail Figure 21 The processing chamber 215 includes a working chamber 300. The processing chamber 215 may also include a remote plasma chamber 320 and a transfer chamber 310 connecting the working chamber 300 to the remote plasma chamber 320. The susceptor 350 may be supported by a mechanism 340 to move the susceptor up and down. The susceptor 350 may be heated and may be made of a metal alloy (e.g., aluminum nitride (AlN)). x )) or other suitable materials to provide uniform heat distribution on the susceptor 350. A workpiece 370 can be placed on the susceptor 350 in the work chamber 300. To prevent the heated material of the susceptor 350 from dissipating or leaching into the workpiece 370 during the high-temperature heat treatment 160, a metal coating 360 can be formed over the susceptor 350. A heated showerhead 380 can be positioned above the workpiece 370 in the work chamber 300 to provide additional heat to the workpiece 370 and optionally provide products of the remote plasma 335 to the work chamber 300.

[0120] The high temperature heat treatment 160 may be performed by activating the heated susceptor 350 and the heated showerhead 380 in the work chamber 300 until the temperature of the workpiece 370 reaches between 700° C. and 900° C. for a duration between 60 seconds and 120 seconds.

[0121] The hydrogen radical treatment 165 can be performed by activating a remote plasma generator 325 and providing a gas source 330 to the remote plasma chamber 320. The remote plasma generator 325 generates a plasma from a gas source 330 (e.g., hydrogen). The remote plasma 335 products can include hydrogen radicals and ions, as well as plasma effluents. By generating a remote plasma, the effluents and ions of the remote plasma 335 can be filtered during transport of the remote plasma 335 to the work chamber 300 via the transfer chamber 310. The walls of the transfer chamber 310 or plates disposed within the transfer chamber 310 can be charged so that when hydrogen ions pass through, the ions are attracted to the charged surfaces and neutralized.

[0122] In some embodiments, the hydrogen radical treatment 165 may be performed simultaneously with or overlapped with the high-temperature thermal treatment 160. The high temperature during the hydrogen radical treatment 165 provides for higher dissociation of hydrogen radicals. In other embodiments, the hydrogen radical treatment 165 may be performed without the high-temperature thermal treatment 160. In these embodiments, the hydrogen radical treatment 165 is performed at a temperature greater than 250° C. to provide sufficient energy for generating sufficient hydrogen radicals.

[0123] Figure 23-24 A process of forming and removing a metal coating 360 of a susceptor 350 is shown according to some embodiments. In some embodiments, the susceptor 350 can be coated in situ without removing the susceptor 350 from the process chamber 215. Figure 23 In step 410, the cavity is emptied so that there is no workpiece in the cavity. In step 420, a metal coating 360 is deposited on the susceptor 350. Any suitable deposition process may be used, such as physical vapor deposition (PVD), chemical vapor deposition, sputtering deposition, or other techniques known and used in the art to deposit the selected material. The material of the metal coating 360 may include any suitable material, such as iron, cobalt, nickel, and the like. The metal coating 360 may be deposited to a thickness of between about 1 μm and about 10 μm, but other thicknesses may be used. If the metal coating 360 is too thin, the material of the susceptor 350 may still be immersed in the workpiece 370. If the metal coating 360 is too thick, the heat provided by the susceptor 350 may not be applied to the workpiece 370 in the intended manner, resulting in undesirable effects. In step 430, the wafer or workpiece 370 may be loaded for processing. In Figure 24In step 440, the metal coating 360 can be removed from the susceptor 350. This step can be performed so that the process chamber 215 can be used for other processing functions. In step 440, the process chamber 215 can be emptied of any workpiece, thereby exposing the susceptor 350. In step 450, the metal coating 360 can be removed from the susceptor by any suitable process, such as by etching. In step 460, processing in the process chamber 215 can be resumed.

[0124] The disclosed embodiments provide a method for treating the notch by high temperature heat treatment and selective hydrogen radical treatment. These treatments improve the surface quality of the notch so that the epitaxial source / drain region is deposited in the notch with higher quality, resulting in less leakage current and a more efficient device. The processing apparatus includes a processing chamber for providing high temperature heat treatment, the processing chamber includes a heated platform and a heated nozzle, the heated platform is coated with metal to prevent the platform material from diffusing into the workpiece, and the heated platform and the heated nozzle together provide high heat to the workpiece. The processing chamber may also include a remote plasma source that provides hydrogen radicals to the workpiece for hydrogen radical treatment. The final device has an increased drive current performance. In particular, the drive current (I deff ) and leakage current (I off ) ratio can be increased by 3% to 4%. In other words, leakage current is reduced. Furthermore, the process described herein achieves superior epitaxial growth of the source / drain regions, which improves on-current. Furthermore, a yield window for optimal landing of the subsequent contact formation can be achieved. In other words, because the epitaxial growth is of higher quality, the epitaxial top surface has a larger effective landing area to receive the contact, allowing for a larger lithographic window for fault tolerance in forming the source / drain contact and increasing overall yield.

[0125] One embodiment is a method comprising forming a fin from a substrate, forming a gate structure over the fin, etching a source / drain recess on one side of the gate structure, heating the source / drain recess to a temperature greater than 700° C. to smooth the surface of the source / drain recess by 6% to 12%, and growing epitaxial source / drain regions in the source / drain recess.

[0126] In some other embodiments, the step of heating the source / drain recess includes: activating a heated susceptor; and activating a heated showerhead.

[0127] In some other embodiments, the step of heating the source / drain recesses further comprises providing hydrogen to the processing chamber while heating the source / drain recesses.

[0128] In some other embodiments, the above method further includes: after heating the source / drain recesses, performing a hydrogen radical treatment process on the source / drain recesses.

[0129] In some other embodiments, the hydrogen radical treatment process forms silane on the surface of the source / drain recesses.

[0130] In some other embodiments, the hydrogen radical treatment process removes a portion of the fin below a portion of the gate structure.

[0131] In some other embodiments, the method further includes: generating a plasma from hydrogen in a first chamber, the plasma comprising hydrogen ions and hydrogen radicals; transferring the plasma to a second chamber via a transfer chamber; and providing the hydrogen radicals to the source / drain recesses, wherein the first chamber is remote from the second chamber.

[0132] In some other embodiments, the method further includes filtering out hydrogen ions in the plasma when transferring the plasma to the second chamber.

[0133] Another embodiment is a method comprising etching a substrate to form a fin from the substrate. The method comprises forming a gate structure over the fin, the gate structure comprising a gate stack, a first gate spacer on a first side of the gate stack, and a second gate spacer on a second side of the gate stack. Etching a recess in the fin on the first side of the gate structure adjacent to the first gate spacer. Treating the recess to remove byproducts and oxides of the fin material from the recess and smoothing the surface of the recess. Forming epitaxial source / drain regions in the recess.

[0134] In some other embodiments, the step of treating the recess includes providing a heat treatment to the recess, wherein the heat treatment heats the recess to a temperature greater than 700°C.

[0135] In some other embodiments, the processing step includes: heating a heating element disposed above the recess to provide heat to the recess; and heating a base below the recess to provide heat to the recess.

[0136] In some other embodiments, wherein a metal layer is disposed above the pedestal, the metal layer blocks material of the pedestal from seeping into the substrate.

[0137] In some other embodiments, the above method further includes: after treating the recess, treating the recess with a hydrogen radical treatment.

[0138] In some other embodiments, wherein the hydrogen radical treatment enlarges the recess, wherein a lateral extent of the recess extends below the first gate spacer.

[0139] In some other embodiments, wherein the hydrogen radical treatment forms a hydrogen compound at a surface of the fin in the recess, the hydrogen compound comprising the material of the fin and hydrogen, wherein the hydrogen compound inhibits oxidation of the material of the fin.

[0140] In some other embodiments, the treating step smoothes the surface in the recess by 6% to 12%.

[0141] Another embodiment provides an apparatus comprising a remote plasma chamber comprising a plasma generator and a gas source. The apparatus also comprises a plasma transfer chamber and a work chamber, wherein the work chamber comprises a showerhead and a susceptor. The showerhead and susceptor are configured to heat a workpiece on the susceptor to provide heat of at least 700° C. The susceptor comprises a metal alloy and a metal coating overlying the metal alloy. The plasma transfer chamber connects the remote plasma chamber to the work chamber and is configured to provide plasma products to the work chamber.

[0142] In some other embodiments, the metal coating comprises iron, cobalt, or nickel.

[0143] In some other embodiments, wherein the susceptor includes a heating element disposed in the metal alloy, the heating element is configured to provide heat to the workpiece.

[0144] In some other embodiments, the transfer chamber is configured to provide a bias voltage to attract ions of the plasma.

[0145] The foregoing text summarizes the features of many embodiments, so that those skilled in the art can better understand the embodiments of the present disclosure from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present disclosure, and thereby achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the invention of the present disclosure. Various changes, substitutions or modifications can be made to the embodiments of the present disclosure without departing from the spirit and scope of the invention of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A fin is formed from a base; forming a gate structure above the fin; etching a source / drain recess on one side of the gate structure; heating the source / drain recess to a temperature greater than 700° C. and less than 900° C. to smooth a surface of the source / drain recess by reducing the root mean square of the surface by 6% to 12%, wherein a metal layer covers a pedestal supporting the substrate during the heating of the source / drain recess; as well as An epitaxial source / drain region is grown in the source / drain recess.

2. The method for forming a semiconductor device according to claim 1 , wherein the step of heating the source / drain recess comprises: activating the heated base; and Activate a heated nozzle.

3. The method for forming a semiconductor device according to claim 1 , wherein the step of heating the source / drain recess further comprises: While the source / drain recesses are heated, hydrogen is provided to a processing chamber.

4. The method for forming a semiconductor device according to claim 1 , further comprising: After heating the source / drain recess, a hydrogen radical treatment process is performed on the source / drain recess. 5 . The method for forming a semiconductor device as claimed in claim 4 , wherein the hydrogen radical treatment process forms a silane on the surface of the source / drain recess. 6 . The method for forming a semiconductor device as claimed in claim 4 , wherein the hydrogen radical treatment process removes a portion of the fin below a portion of the gate structure.

7. The method for forming a semiconductor device according to claim 4 , further comprising: generating a plasma from hydrogen in a first chamber, the plasma comprising hydrogen ions and hydrogen radicals; transferring the plasma to a second chamber via a transfer chamber; and The hydrogen radicals are provided to the source / drain recess, wherein the first cavity is away from the second cavity.

8. The method for forming a semiconductor device according to claim 1 , further comprising: Before heating the source / drain recesses, disposing the metal layer above the pedestal in a processing chamber, the metal layer preventing material of the pedestal from leaching into the substrate during heating of the source / drain recesses; and After heating the source / drain recesses, the metal layer is removed. 9 . The method for forming a semiconductor device according to claim 1 , wherein a ratio of a driving current to a drain current is increased by 3% to 4% compared to a sample in which the source / drain recesses are not heated.

10. A method for forming a semiconductor device, comprising: etching a substrate to form a fin from the substrate; forming a gate structure over the fin, the gate structure comprising a gate stack, a first gate spacer on a first side of the gate stack, and a second gate spacer on a second side of the gate stack; etching a recess in the fin on the first side of the gate structure adjacent to the first gate spacer; treating the recess to remove byproducts and oxides of the fin material from the recess and smooth the surface by reducing the root mean square of a surface of the recess by 6% to 12%, wherein a metal layer covers a pedestal that supports the substrate during the treating of the recess; After processing the recess, performing a hydrogen radical treatment on the recess, wherein the hydrogen radical treatment expands the width and height of the recess; and An epitaxial source / drain region is formed in the recess.

11. The method for forming a semiconductor device according to claim 10 , wherein the step of processing the recess comprises: A heat treatment is provided to the recess, wherein the heat treatment heats the recess to a temperature greater than 700° C. and less than 900° C.

12. The method for forming a semiconductor device according to claim 10 , wherein the processing step comprises: heating a heating element disposed above the recess to provide heat to the recess; and The base below the recess is heated to provide heat to the recess. 13 . The method for forming a semiconductor device as claimed in claim 12 , wherein the metal layer prevents material of the base from penetrating into the substrate.

14. The method for forming a semiconductor device according to claim 13 , further comprising: After forming the epitaxial source / drain regions, the metal layer is removed from the pedestal. 15 . The method for forming a semiconductor device according to claim 10 , wherein the hydrogen radical treatment enlarges the recess, wherein a lateral extent of the recess extends below the first gate spacer. 16 . The method for forming a semiconductor device according to claim 10 , wherein the hydrogen radical treatment forms a hydrogen compound at a surface of the fin in the recess, the hydrogen compound comprising a material of the fin and hydrogen, wherein the hydrogen compound inhibits oxidation of the material of the fin.

17. A method for forming a semiconductor device, comprising: A fin is formed from a base; forming a gate structure above the fin; Etching a source / drain recess on one side of the gate structure, wherein after etching the source / drain recess, a surface of the source / drain recess has a first root mean square roughness; performing a thermal treatment, the thermal treatment comprising heating the source / drain recess to a temperature between 700° C. and 900° C., wherein after the source / drain recess is heated, the surface of the source / drain recess has a second root mean square roughness (RMS) that is 6% to 12% less than the first RMS roughness, wherein during the heating of the source / drain recess, a metal layer covers a pedestal that supports the substrate; as well as An epitaxial source / drain region is grown in the source / drain recess.

18. The method for forming a semiconductor device according to claim 17 , further comprising: After the source / drain recess is heated, a radical treatment is performed. The radical treatment includes remotely generating a hydrogen plasma and transferring a radical from the hydrogen plasma to the source / drain recess. The radical expands the source / drain recess. 19 . The method for forming a semiconductor device according to claim 18 , wherein a landing area of ​​the epitaxial source / drain region is 200% to 300% larger than a landing area of ​​a sample without the thermal treatment and the radical treatment.

20. The method for forming a semiconductor device according to claim 17, further comprising: Depositing the metal layer above the pedestal in a processing chamber before heating the source / drain recess, the metal layer being disposed between the substrate and the pedestal; and After heating the source / drain recesses, the metal layer is removed.

21. A method for forming a semiconductor device, comprising: A fin is formed from a base; forming a gate structure above the fin; etching a source / drain recess on one side of the gate structure; Performing a smoothing process, the smoothing process comprising: heating the source / drain recess, wherein a metal layer covers a pedestal that supports the substrate during the heating of the source / drain recess; and After heating the source / drain recess, performing a radical treatment process on the source / drain recess; moving the source / drain recess to a deposition chamber; as well as An epitaxial source / drain region is grown in the source / drain recess.

22. The method for forming a semiconductor device according to claim 21 , wherein the step of heating the source / drain recess comprises: A heated susceptor and a heated showerhead are activated to heat the source / drain recesses to a temperature between 700° C. and 900° C. 23 . The method for forming a semiconductor device according to claim 21 , wherein the smoothing process reduces a root mean square of a surface of the source / drain recess by 6% to 12%.

24. The method for forming a semiconductor device as claimed in claim 21, wherein the radical treatment process uses a hydrogen radical. 25 . The method for forming a semiconductor device according to claim 24 , wherein the radical treatment process forms silane on the surface of the source / drain recess, and the silane inhibits oxidation of the source / drain recess during the process of moving the source / drain recess to the deposition chamber. 26 . The method for forming a semiconductor device as claimed in claim 24 , wherein the radical treatment process expands the source / drain recesses to be wider and deeper. 27 . The method for forming a semiconductor device according to claim 21 , wherein after the source / drain recess is moved to the deposition chamber, an etching process is performed to remove the metal layer from the base.

28. A method for forming a semiconductor device, comprising: etching a substrate to form a fin from the substrate; forming a gate structure over the fin, the gate structure comprising a gate stack, a first gate spacer on a first side of the gate stack, and a second gate spacer on a second side of the gate stack; etching a recess in the fin on the first side of the gate structure adjacent to the first gate spacer; reducing a surface roughness of the recess, wherein during the reducing of the surface roughness of the recess, a metal layer covers a base, and the base supports the substrate; applying a hydrogen radical to the notch; transferring the substrate to a deposition chamber; and An epitaxial source / drain region is formed in the recess.

29. The method for forming a semiconductor device according to claim 28 , wherein the step of reducing the surface roughness of the recess comprises: The recess is provided with a heat treatment that heats the recess to between 700°C and 900°C.

30. The method for forming a semiconductor device according to claim 28 , wherein the step of reducing the surface roughness of the recess comprises: heating a heating element disposed above the recess to provide heat to the recess; and A base below the recess is heated to provide heat to the recess. 31 . The method for forming a semiconductor device according to claim 28 , wherein during the step of reducing the surface roughness of the recess, the metal layer is disposed between the substrate and the pedestal supporting the substrate.

32. The method for forming a semiconductor device according to claim 31 , further comprising: After the substrate is transferred to the deposition chamber, the metal layer is removed from the susceptor. 33 . The method for forming a semiconductor device according to claim 28 , wherein the step of applying the hydrogen radicals enlarges the recess, wherein a lateral extent of the recess extends below the first gate spacer.

34. The method for forming a semiconductor device as claimed in claim 28, wherein the step of applying the hydrogen radicals to the recess forms a hydrogen compound on the surface of the recess, the hydrogen compound comprising the material of the fin and hydrogen, and the hydrogen compound inhibits oxidation of the material of the fin during the transfer of the substrate to the deposition chamber.

35. A method for forming a semiconductor device, comprising: A fin is formed from a base; forming a gate structure above the fin; etching a source / drain recess on one side of the gate structure; removing an etch byproduct from the source / drain recess, wherein a metal layer covers a pedestal that supports the substrate during the removal of the etch byproduct; exposing the source / drain recess to a hydrogen radical to form a hydrogen compound on a surface of the source / drain recess; Transferring the substrate to a deposition chamber, wherein during the transfer of the substrate, the surface of the source / drain recess is free of oxidation of the portion of the hydrogen compound, and the surface of the source / drain recess is partially unoxidized with the portion of the hydrogen compound; as well as An epitaxial source / drain region is formed in the source / drain recess.

36. The method for forming a semiconductor device according to claim 35 , wherein the step of removing the etching byproducts from the source / drain recess comprises: The source / drain recesses are heated to a temperature between 700° C. and 900° C. by a heated pedestal or a heated showerhead. 37 . The method for forming a semiconductor device as claimed in claim 35 , wherein the step of removing the etching byproducts smoothes the source / drain recesses and reduces the root mean square of the surface of the source / drain recesses by 6% to 12%.

38. The method for forming a semiconductor device according to claim 35 , further comprising: The metal layer is deposited above the pedestal in a processing chamber, the metal layer being disposed between the substrate and the pedestal, before removing the etch byproducts from the source / drain recesses.

39. The method for forming a semiconductor device according to claim 35, wherein the step of exposing the source / drain recess to the hydrogen radicals causes the source / drain recess to widen, such that a sidewall of the source / drain recess is below the gate structure.

40. A semiconductor device comprising: a remote plasma chamber comprising a plasma generator and a gas source; a plasma delivery chamber; and A work chamber includes a showerhead and a pedestal, wherein the showerhead and the pedestal are configured to heat a workpiece on the pedestal to provide heat of at least 700°C, the pedestal comprising a metal alloy and a metal coating over the metal alloy, wherein the plasma delivery chamber connects the remote plasma chamber to the work chamber and is configured to provide a plasma product to the work chamber, wherein the metal coating covers the pedestal during heating of the workpiece, and the pedestal supports the workpiece. The semiconductor device of claim 40 , wherein the metal coating comprises iron, cobalt, or nickel.

42. The semiconductor device of claim 40, wherein the pedestal comprises a heating element disposed in the metal alloy, the heating element configured to provide heat to the workpiece.

43. The semiconductor device of claim 40, wherein the plasma transfer chamber is configured to provide a bias voltage to attract ions of the plasma.

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