Semiconductor processing methods and stress assessment methods

Abstract

This disclosure discloses a method for evaluating non-uniform stress in thin films using high-order wafer warpage, comprising the steps of: measuring a net wafer warpage attributable to thin film deposition across a wafer region, adapting a two-dimensional low-order polynomial to these wafer warpage measurements, and subtracting the low-order polynomial from the net wafer warpage across the wafer region.

Description

Technical Field

[0001] The embodiments disclosed herein relate to methods for reducing or preventing higher-order alignment residues, higher-order film stresses, and / or peeling defects caused by non-uniform stress in deposited films. Background Technology

[0002] Thin films deposited or grown on semiconductor wafers can contain stresses, which can cause overlay (OVL) residues or alignment errors in subsequent lithography processes. Overlay residues describe lithographic alignment errors from one layer to the next photoresist pattern and adversely affect integrated circuit (IC) yield. Semiconductor processes with feature sizes below 5 nanometers have stringent OVL residue specifications to improve IC yield. Summary of the Invention

[0003] This disclosure provides a semiconductor processing method comprising the following steps: depositing a thin film on a surface of a substrate; measuring a warpage of the substrate at a plurality of measurement locations on the surface of the substrate after the thin film deposition; determining a warpage of the substrate attributable to the thin film deposition at the plurality of measurement locations on the surface of the substrate; adapting the warpage measurement value determined attributable to the thin film deposition on the substrate to a low-order polynomial based on the coordinates of the plurality of measurement locations on the surface of the substrate; evaluating the low-order polynomial for at least one coordinate of a measurement location; and subtracting the evaluated low-order polynomial for at least one coordinate of the measurement location from the warpage measurement value of the substrate after the thin film is deposited at the measurement location.

[0004] This disclosure provides a method for evaluating higher-order stress in a thin film deposited on a semiconductor wafer, comprising the following steps: determining lower-order wafer warpage based on the location on the semiconductor wafer using warpage measurements from multiple locations on the semiconductor wafer; determining higher-order warpage based on the warpage measurements from multiple locations on the semiconductor wafer and the determined location of the lower-order warpage; and measuring multiple higher-order stacking errors across the semiconductor wafer using multiple stacking patterns.

[0005] This disclosure provides a semiconductor processing method comprising the following steps: measuring warpage of the semiconductor wafer at multiple locations on the surface of the semiconductor wafer in a direction substantially perpendicular to the surface of the semiconductor wafer, the multiple locations being identified using coordinate axes substantially parallel to the surface of the semiconductor wafer; generating a regression polynomial based on at least one of the coordinate axes substantially parallel to the surface of the semiconductor wafer and the warpage measurements at the multiple locations on the surface of the semiconductor wafer; generating a higher-order polynomial by removing lower-order elements of the regression polynomial; and evaluating the higher-order polynomial for the locations on the surface of the semiconductor wafer.

[0006] This disclosure provides a method for evaluating stress deposited on a thin film on a semiconductor wafer, comprising the following steps: determining low-order wafer warpage based on the location on the semiconductor wafer using warpage measurements from multiple locations on the semiconductor wafer; and performing mathematical operations on the low-order wafer warpage and the warpage measurements.

[0007] This disclosure provides a semiconductor processing method, including the following steps: measuring the warpage of the semiconductor wafer at multiple locations on the surface of the semiconductor wafer, the multiple locations being identified using coordinate axes; generating a polynomial based on at least one of the coordinate axes of the surface of the semiconductor wafer and the warpage measurement values ​​at the multiple locations on the surface of the semiconductor wafer; and performing mathematical operations on the polynomial.

[0008] This disclosure provides a semiconductor processing method, including the following steps: determining low-order wafer warpage based on warpage measurements from multiple locations on a semiconductor wafer; determining high-order warpage based on the warpage measurements from multiple locations on the semiconductor wafer and the determined location of the low-order warpage; and comparing the determined high-order warpage at each of the multiple locations on the semiconductor wafer with a high-order overlap error measured at the nearest location among the multiple locations. Attached Figure Description

[0009] The state of this disclosure is in relation to the accompanying documents. Figure 1 The best way to understand this text is by referring to the following detailed description. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0010] Figure 1 A flowchart of a method according to some embodiments for determining higher-order warpage Z_HO(X,Y);

[0011] Figure 2A This is a schematic side view of a portion of a semiconductor wafer according to some embodiments, illustrating a first set of warpage measurements Z1(X,Y) before thin film deposition.

[0012] Figure 2B This is a schematic side view of a portion of a semiconductor wafer according to some embodiments, illustrating a second set of warpage measurements Z2(X,Y) after thin film deposition;

[0013] Figure 2CThis is a schematic side view of a portion of a semiconductor wafer according to some embodiments, illustrating a measured high-order stack residue OVL(X,Y) after thin film deposition and after photoresist has been deposited, exposed, and developed on top of the thin film.

[0014] Figure 2D This is a top view of a semiconductor wafer according to some embodiments, the surface of which is substantially parallel to the XY plane;

[0015] Figure 3A To represent the contour plot of the wafer warpage measurement Z(X,Y) attributed to the deposited thin film A on the semiconductor wafer, the wafer warpage measurement Z(X,Y) is based on... Figure 1 Implementation example determination;

[0016] Figure 3B A grayscale map of the higher-order warpage Z_HO(X,Y) attributed to the deposited thin film A, which is based on... Figure 1 The determination is made based on the implementation examples;

[0017] Figure 3C To represent the measured higher stack pair residue OVL(X,Y) pattern attributed to the deposited thin film A, the measured higher stack pair residue OVL(X,Y) has the same characteristics as according to... Figure 1 The correlation of higher-order warpage Z_HO(X,Y) determined by the embodiment;

[0018] Figure 4A A contour plot of the wafer warpage measurement Z(X,Y) on the semiconductor wafer attributable to the deposited thin film B, the wafer warpage measurement Z(X,Y) is based on... Figure 1 Implementation example determination;

[0019] Figure 4B For a grayscale map of the higher-order warpage Z_HO(X,Y) attributed to the deposited thin film B, the higher-order warpage Z_HO(X,Y) is based on... Figure 1 Implementation example determination;

[0020] Figure 4C To represent the measured higher stack pair residue OVL(X,Y) pattern attributed to the deposited thin film B, the measured higher stack pair residue OVL(X,Y) has the same characteristics as according to... Figure 1 The correlation of higher-order warpage Z_HO(X,Y) determined by the embodiment;

[0021] Figure 5 The graphs attributed to the higher-order warpage Z_HO(X,Y) of thin films A and B across the wafer diameter are shown. The higher-order warpage Z_HO(X,Y) is based on... Figure 1 Implementation example determination;

[0022] Figure 6A The contour plot of the wafer warpage measurement Z(X,Y) attributed to the deposited thin film C on the semiconductor wafer is based on... Figure 1 Implementation example determination;

[0023] Figure 6B A grayscale map of the higher-order warpage Z_HO(X,Y) attributed to the deposited thin film C, based on... Figure 1 Implementation example determination;

[0024] Figure 6C The graph is attributed to the observed peeling events of the deposited thin film C. The peeling events have a correlation with the data... Figure 1 The correlation of higher-order warpage Z_HO(X,Y) determined by the embodiment;

[0025] Figure 7A To represent the contour plot of the wafer warpage measurement Z(X,Y) attributed to the deposited thin film D on the semiconductor wafer, the wafer warpage measurement Z(X,Y) is based on... Figure 1 Implementation example determination;

[0026] Figure 7B A grayscale map of the higher-order warpage Z_HO(X,Y) attributed to the deposited thin film D, based on... Figure 1 Implementation example determination;

[0027] Figure 7C The graph is attributed to the observed peeling events of the deposited thin film D. The peeling events have a relationship with the graph based on the observed peeling events of the deposited thin film D. Figure 1 The correlation of higher-order warpage Z_HO(X,Y) determined by the embodiment;

[0028] Figure 8 A flowchart of a method according to an alternative embodiment for determining a higher-order warpage Z_HO(X) across the diameter of a semiconductor wafer;

[0029] Figure 9 A flowchart of a method according to an alternative embodiment for determining a higher-order warpage Z_HO(X) across the diameter of a semiconductor wafer;

[0030] Figure 10 A flowchart of a method according to an alternative embodiment for determining higher-order stresses in a thin film by utilizing fine wafer alignment, removal of translation and rotation;

[0031] Figure 11 A flowchart of a method according to an alternative embodiment for determining higher-order stresses in a thin film using fine wafer alignment (FIWA) and liner modeling;

[0032] Figures 12A to 12C For illustration purposes Figure 10 The method is used to determine the FIWA wafer map of higher-order stress in thin film E;

[0033] Figures 13A to 13C For illustration purposes Figure 10 The method is used to determine the FIWA wafer map of higher-order stress in thin film F;

[0034] Figures 14A to 14C For illustration purposes Figure 11 The method is used to determine the wafer map of higher-order stresses in thin film G;

[0035] Figures 15A to 15C For illustration purposes Figure 11 The method is used to determine the wafer map of higher-order stresses in thin film H.

[0036] [Symbol Explanation]

[0037] 100: Method

[0038] 102: Steps

[0039] 104: Steps

[0040] 106: Steps

[0041] 108: Steps

[0042] 110: Steps

[0043] 112: Steps

[0044] 200: Side view section

[0045] 201: Side View Section

[0046] 202: Semiconductor wafers

[0047] 203: Side View Section

[0048] 205: Top-down view

[0049] 230: Dielectric layer

[0050] 232a, 232b: Overlapping pair markers (first overlapping pair markers)

[0051] 234 : Film

[0052] 236a, 236b: Overlapping markers

[0053] 254: Surface

[0054] 256: Wafer reference mark

[0055] 302: Contour Map

[0056] 304: Semiconductor wafer

[0057] 306: Grayscale map

[0058] 308: Area

[0059] 310: Vector Graphics

[0060] 312: Area

[0061] 402: Contour Chart

[0062] 404: Semiconductor wafer

[0063] 406: Grayscale map

[0064] 408a, 408b: Area

[0065] 410: Vector Graphics

[0066] 600: Line chart

[0067] 602: Contour Map

[0068] 604: Semiconductor wafer

[0069] 606: Grayscale map

[0070] 608a to 608e: Area

[0071] 610: External perimeter

[0072] 612: High-order wafer warpage rings

[0073] 614: Stripping Event Diagram

[0074] 616a to 616f: Stripping Events

[0075] 702: Contour Map

[0076] 704: Semiconductor wafer

[0077] 706: Grayscale Map

[0078] 708: Orthogonal higher-order ring

[0079] 710: External perimeter

[0080] 712: Stripping Event Diagram

[0081] 714a, 714b: Stripping Events

[0082] 800: Method

[0083] 802: Steps

[0084] 804: Steps

[0085] 806: Steps

[0086] 808: Steps

[0087] 810: Steps

[0088] 812: Steps

[0089] 900: Method

[0090] 902: Steps

[0091] 904: Steps

[0092] 906: Steps

[0093] 908: Steps

[0094] 910: Steps

[0095] 912: Steps

[0096] 1000: Method

[0097] 1002: Steps

[0098] 1004: Steps

[0099] 1006: Steps

[0100] 1008: Steps

[0101] 1010: Steps

[0102] 1012: Steps

[0103] 1100: Method

[0104] 1102: Steps

[0105] 1104: Steps

[0106] 1106: Steps

[0107] 1108: Steps

[0108] 1110: Steps

[0109] 1112: Steps

[0110] 1200a: Graphic

[0111] 1200b: Graphic

[0112] 1200c: Graphic

[0113] 1300a: Graphic

[0114] 1300b: Graphic

[0115] 1300c: Graphic

[0116] 1400a: Graphic

[0117] 1400b: Graphic

[0118] 1400c: Graphics

[0119] 1500a: Graphic

[0120] 1500b: Graphic

[0121] 1500c: Graphics

[0122] OVL(X,Y): High-order stacking residue

[0123] Z_HO(X,Y): Higher-order warping

[0124] Z(X,Y): Wafer warpage measurement (net wafer warpage measurement)

[0125] Z1(X,Y): First set of warpage measurements

[0126] Z1ref: First reference plane

[0127] Z2(X,Y): Second set of warpage measurements

[0128] Z2ref: Second reference plane

[0129] Z3(X,Y): Warped polynomial

[0130] (X,Y): Measurement location

[0131] (Xref, Yref): Reference location Detailed Implementation

[0132] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0133] Additionally, spatial relative terms, such as “below,” “under,” “lower,” “above,” “upper,” and similar terms, may be used herein for ease of description to describe the relationship between one element or feature and another, as illustrated in the figures. Spatial relative terms are intended to cover the orientation of a device in use or operation other than that depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0134] In semiconductor technologies below 5 nanometers, processing margins are small, and high-order OVL (Optical Value Lift) limits are stringent to achieve high-performance semiconductor devices. Minimizing and controlling high-order OVL residues is challenging and is typically induced by non-uniform film stress. Generally, global wafer shape distortion, with or without a thin film, is described by wafer warpage; however, after a thin film has been deposited on the wafer, wafer warpage has a low correlation with high-order OVL residues. According to embodiments described herein, the inventors have found that high-order wafer warpage attributable to thin film deposition is strongly correlated with the presence of high-order stacking residues, high-order film stress, and peeling defects in the deposited film. Therefore, according to some embodiments described herein, high-order wafer warpage inspection (before and after thin film deposition) is used in the process to reduce or prevent high-order OVL residues, high-order film stress, and / or peeling defects in the deposited film caused by non-uniform stress in the deposited film. According to embodiments of this disclosure, high-order wafer warpage inspection (before and after thin film deposition) utilizes fine wafer alignment measurements before or after thin film deposition, or uses wafer warpage measurements (before and after thin film deposition) to determine high-order wafer warpage. According to embodiments of this disclosure, the results of the high-order wafer warpage measurements are used in the process to reduce or prevent high-order OVL residues, high-order film stress, and / or peeling defects in the deposited film caused by non-uniform stress in the deposited film.

[0135] The top surface of a semiconductor wafer used for integrated circuits (ICs) may lie in the XY plane used for photolithography. During the photolithography process, overlap residues or overlap errors in the XY plane are measured between the IC layer and the next photoresist pattern on the IC during the semiconductor process. As an example, in a step prior to thin film deposition, first overlap marks are generated on the semiconductor wafer using a material such as silicon dioxide, silicon nitride, a metal, or another material compatible with the semiconductor process. A thin film is then deposited on the semiconductor wafer. Such a thin film can cause the wafer to warp due to stress in the film. After thin film deposition, the semiconductor wafer moves to the photolithography region to generate a photoresist pattern on the thin film, typically used to pattern the film. Second overlap marks are portions of the photoresist pattern. The positions of these second overlap marks can be compared to the positions of the corresponding first overlap marks. The overlap residues or mismatches in the XY plane between the positions of the first and second overlap marks are measured by inspection of the semiconductor wafer from above. The stacking residue is measured in both the X and Y directions and is represented as the stacking error vector at the measurement position (X,Y) of the stacking mark on the semiconductor wafer.

[0136] Thin film processes, through deposition or otherwise formation on semiconductor wafers, can influence higher-order stack residues (OVLs) attributable to non-uniform stresses in the deposited or grown film. According to the disclosed embodiments, stack residue measurements on the semiconductor wafer are used to modify operating conditions in the thin film process for the purpose of reducing internal stresses in the film deposited or otherwise formed on subsequent semiconductor wafers. The time delay between film deposition and stack residue measurement can range from several hours to a day. A long time delay between film deposition and stack residue measurement can introduce instabilities into the thin film deposition process, for example, by failing to adjust the thin film process in a manner that reduces stresses in the deposited film. Estimating or predicting these higher-order stack residues (OVLs) attributable to film stresses as quickly as possible after film deposition on the semiconductor wafer avoids such instabilities in the thin film deposition process, which are inherently caused by the time delay between film deposition and stack residue measurement. Estimating or predicting, as quickly as possible, the higher-order stack-pair residues (OVLs) attributable to film stress after thin film deposition on a semiconductor wafer allows for adjustment of process parameters during the thin film formation process while simultaneously measuring the OVLs. The correlation between higher-order wafer warpage measurement and the OVLs (X,Y) allows higher-order wafer warpage inspection (before and after film deposition) to be used as an auxiliary control of the thin film deposition process before the measurement of OVLs is completed. Because wafer warpage measurement after film deposition is performed with a smaller delay compared to the delay involved in determining or measuring OVLs, the thin film deposition process can be adjusted based on wafer warpage measurement information, even with a time delay, compared to the time delay used to determine which changes should be made to the thin film deposition process to reduce stress in the formed film when measured or otherwise determined OVLs are used.

[0137] According to the disclosed embodiments, wafer warpage is measured in the Z direction, perpendicular to the average XY plane of the semiconductor wafer, using, for example, an interferometer. Warpage measurements across the semiconductor wafer can be adapted to polynomials with both low-order and high-order terms. For the purposes of this application, the polynomial adaptation to the semiconductor wafer warpage measurements is referred to as a warpage polynomial. Warpage polynomial terms of third order and above are referred to as high-order warpage terms. In the embodiments, the sum of the high-order warpage terms is calculated for each warpage measurement location (X,Y) on the semiconductor wafer. A second-order warpage polynomial is determined by adapting a set of net warpage measurements Z(X,Y) to a second-order polynomial. To determine high-order wafer warpage for each measurement location (X,Y), the second-order warpage polynomial is evaluated and subtracted from the net warpage measurement Z(X,Y).

[0138] The inventors of this application have also determined that peeling events or peeling defects can be associated with higher-order warpage. A peeling event occurs when a portion of the film separates or peels off from the substrate on which the film is deposited.

[0139] An embodiment of a method for determining higher-order wafer warpage caused by higher-order or non-uniform film stress using measurements of semiconductor wafer warpage will be described. Figure 1 For method 100 used to determine higher-order warpage Z_HO(X,Y) across a region of a semiconductor wafer, a thin film has been deposited or otherwise formed on the semiconductor wafer. According to the disclosed embodiments, higher-order wafer warpage Z_HO(X,Y) is associated with stacking residues across the semiconductor wafer.

[0140] In the first step 102, prior to thin film deposition, a first set of warpage measurements Z1(X,Y) is taken across a 2D (X and Y) semiconductor wafer region using a warpage measurement device. Examples of warpage measurement devices include interferometers, micrometers, and confocal multicolor sensors. Other warpage measurement methods known in the industry can also be used. Embodiments according to this disclosure are not limited to using the aforementioned warpage measurement device to obtain warpage measurements. The first set of warpage measurements Z1(X,Y) is obtained using a first surface of the semiconductor wafer prior to thin film deposition. According to embodiments of this disclosure, warpage measurements can be obtained from other surfaces of the semiconductor wafer.

[0141] In step 104, a thin film is deposited on the first surface of the semiconductor wafer. In step 106, after the thin film deposition, a plurality of second sets of warpage measurements Z2(X,Y) are obtained across the semiconductor wafer at the same measurement positions (X,Y) where the first set of warpage measurements Z1(X,Y) were obtained. In some embodiments, the surface of the formed thin film opposite to the first surface of the semiconductor wafer is used for the second warpage measurement. Other surfaces, such as the second surface of the semiconductor wafer opposite to the first surface of the semiconductor wafer, may be used.

[0142] According to the disclosed embodiment, in step 108, a set of net wafer warpage measurements Z(X,Y) attributable to thin film deposition is determined by subtracting the first set of warpage measurements Z1(X,Y) from the second set of warpage measurements Z2(X,Y) for each measurement position (X,Y) across the semiconductor wafer.

[0143] Z(X,Y) = Z2(X,Y) – Z1(X,Y)

[0144] According to the disclosed embodiment, in step 110, a two-dimensional polynomial adaptation is performed on the set of net wafer warpage measurements Z(X,Y) based on coordinates X and Y to generate a second-order warpage polynomial Z3(X,Y).

[0145] Z3(X,Y) = A00 + A 10 X + A 01 Y + A 20 X 2 + A 02 Y 2 + A 11 XY

[0146] Various computer numerical analysis tools can be used to perform regression or fitting of two dimensions or two independent variables, thereby generating coefficients A. 00 A 10 A 01 A 20 A 02 and A 11 As with other regressions, the resulting polynomial can be plotted across the X and Y ranges. For these X and Y ranges, a first set of warpage measurements Z1(X,Y) and a second set of warpage measurements Z2(X,Y) are obtained to check and confirm that the regression algorithm does not cause typically large deviations from the self-measured warpage within the X and Y ranges. Adjustments to the regression criteria specific to the numerical analysis tool may be necessary to reduce any typically large deviations from the self-measured warpage within the X and Y ranges.

[0147] In step 112, the higher-order warpage Z_HO(X,Y) is determined by subtracting the second-order warpage polynomial Z3(X,Y) from the net wafer warpage measurement Z(X,Y) for each measurement location (X,Y).

[0148] Z_HO(X,Y) = Z(X,Y) – Z3(X,Y)

[0149] Figure 2A This is a schematic side view portion 200 of a semiconductor wafer 202 having a first set of warpage measurements Z1(X,Y). The semiconductor wafer 202 is shown having a dielectric layer 230 and first stacking marks 232a and 232b before the deposition of a thin film. In the illustrated semiconductor wafer 202, the first set of warpage measurements Z1(X,Y) is illustrated with reference to a first reference plane Z1ref parallel to the XY plane, and is shown at the reference positions (Xref, Yref) (see...). Figure 2D The X, Y, and Z axes are established by measurements taken on the Z-axis at point ( ). The X, Y, and Z axes are plotted for reference and are derived from... Figure 2A and Figure 2B Shared. For clarity, in Figures 2A to 2C The diagram illustrates only linear warping. However, it should be understood that second-order, third-order, and higher-order warping may exist.

[0150] Figure 2B This is a schematic side view of part 201, and is Figure 2AThe side view portion 200 is shown after the thin film 234 has been deposited on the dielectric layer 230. The semiconductor wafer 202 has a second set of warpage measurements Z2(X,Y) after the thin film 234 has been deposited. The second set of warpage measurements Z2(X,Y) is illustrated with reference to a second reference plane Z2ref parallel to the XY plane, and is obtained by measurements taken on the Z-axis at reference positions (Xref, Yref) (see [reference]). Figure 2D The warpage measurement can be established using a method that measures warpage from 0 to 10 micrometers (µm), with an accuracy of 0.1 µm.

[0151] Figure 2C This is a schematic side view portion 203, which includes... Figure 2B The side view portion 201 after the photoresist overlap marks 236a and 236b have been deposited and patterned on the thin film 234. According to an embodiment of the present disclosure, overlap marks 236a and 236b are compared with overlap marks 232a and 232b, respectively. Overlap mark 232a is used to align the photolithography mask, thereby causing a minimal alignment error or overlap residue between overlap marks 232a and 236a. However, stress in the thin film 234 has caused the semiconductor wafer 202 to warp, thereby causing a higher-order overlap residue OVL(X,Y) between overlap marks 232b and 236b. According to an embodiment of the present disclosure, the higher-order overlap residue OVL(X,Y) is measured and compared with the determined higher-order warpage Z_HO(X,Y) for the measurement position (X,Y) on the semiconductor wafer 202 (see...). Figure 2D Compared to ),

[0152] Figure 2D In a top-down view 205 of a semiconductor wafer 202 with marked reference positions (Xref, Yref), a thin film 234 has a surface 254 and one of a set of measurement positions (X, Y) on the semiconductor wafer 202. One or more wafer reference marks 256 on the semiconductor wafer 202 can be used to orient the semiconductor wafer 202 relative to the X and Y axes. Although the reference positions (Xref, Yref) can be selected at any location on the semiconductor wafer 202, it is useful to select a convenient location such as the center of the semiconductor wafer 202.

[0153] Shown Figures 2A to 2D The overlapping pair notation shown is a simple example to explain the selection of overlapping pair residues. Overlapping pair notations used in industry are known and are far more complex than those illustrated.

[0154] Figures 3A to 4C Examples of semiconductor wafers with thin films deposited on them and according to Figure 1 Methods for determining higher-order warping and reference Figures 2A to 2DThe correlation between the measured high-order overlay (OVL) residues is described. Figures 3A to 4C In this study, wafer warpage measurements before and after thin film deposition are performed using an interferometer on the side of the semiconductor wafer where the thin film will be deposited or has already been deposited.

[0155] Figure 3A Contour plot 302 shows a set of net wafer warpage measurements Z(X,Y) for a semiconductor wafer 304 on which thin film A has been deposited. Wafer warpage attributable to thin film A is plotted over a total range of 62 µm as between -30 µm and +32 µm. The regions of net wafer warpage between -30 µm and -20 µm are determined relative to the central portion of semiconductor wafer 304. (Illustrated in...) Figure 3A The wafer warpage measurements shown herein represent the embodiments disclosed herein. According to the embodiments disclosed herein, the wafer warpage measurements can vary and can be greater or less than the values ​​specified in the original text. Figure 3A The image shows the wafer warpage measurement.

[0156] Figure 3B Grayscale map 306 shows the high-order warpage Z_HO(X,Y) determined for semiconductor wafer 304 after the deposition of thin film A. Figure 3B In the process, the region of semiconductor wafer 304 with significant high-order warpage is... Figure 3B The region with a larger higher-order warp value is identified; for example, a region of semiconductor wafer 304 indicated by a higher-order warp value of 2.0 has a larger higher-order warp than a region of semiconductor wafer 304 indicated by a higher-order warp value less than 2.0. Figure 3B In the wafer, region 308 near the center has the highest value of high-order warpage.

[0157] Figure 3C The vector diagram 310 shows the measured high-order stacking residue OVL(X,Y) of the semiconductor wafer 304 after the deposition of thin film A. Figure 3C The illustration shows that region 312 near the center of the semiconductor wafer has a large higher-order stacking residue OVL(X,Y), which is connected to the semiconductor wafer via... Figure 3B The region 308 is associated with the larger higher-order warping characterization in the middle.

[0158] Figure 4A Contour chart 402 shows the net wafer warpage measurements Z(X,Y) of the semiconductor wafer 404 after the deposition of thin film B. The net wafer warpage attributable to thin film B is between -40µm and +38µm for a range of 78µm.

[0159] Figure 4BGrayscale map 406 shows the determined higher-order warpage Z_HO(X,Y) of semiconductor wafer 404 after the deposition of thin film B. Regions 408a and 408b near the edge of semiconductor wafer 404 have the highest positive higher-order warpage.

[0160] Figure 4C Vector plot 410 of the measured high-order stacking residue OVL(X,Y) of a semiconductor wafer 404 with the deposited thin film B. The region of the high-order OVL residue is readily apparent.

[0161] From Figure 3A and Figure 4A Visual comparison of the net wafer warpage measurement Z(X,Y) suggests that the larger measured warpage of the wafer with film B, compared to the stack residue of the wafer with film A, may indicate a higher higher-order stack residue OVL(X,Y). However, Figure 3C and Figure 4C The comparison indicates that the actual measured stacking error is significantly higher in the case of wafers with thin film A. Figure 3B The determined higher-order warpage Z_HO(X,Y) and Figure 4B Compared with Figure 3C and Figure 4C The measured higher-order stacks correlate well with the residual OVL(X,Y).

[0162] According to the embodiments described herein, higher-order warpage thresholds can be set by associating wafer regions exceeding higher-order stacking specifications with the same regions exhibiting higher-order warpage. Examples of this scenario, where higher and lower limits for higher-order wafer regions are established using a single dimension beyond the wafer, are described below.

[0163] Figure 5 To compare and cross separately Figure 3A Semiconductor wafer 304 (thin film A) and Figure 4A A line graph 600 showing the determined high-order warpage of the diameter of semiconductor wafer 404 (thin film B). The upper limit LIMIT_HIGH and lower limit LIMIT_LOW of high-order warpage can be determined by comparing the measured high-order warpage of each wafer with the measured high-order stack residue. For example, the upper limit LIMIT_HIGH and lower limit LIMIT_LOW of high-order warpage can be determined by process metrics such as wafer yield, with + / - 5 nanometers defining the higher and lower limits of high-order stack residue. Figure 1The method involves determining the higher-order warpage Z_HO(X,Y) and comparing it with the higher-order stack residue OVL(X,Y) measured for each wafer. This comparison results in a determination of higher-order wafer warpage corresponding to a 5 nm higher-order OVL residue of + / - 0.5 µm. The higher-order wafer warpage limits LIMIT_HIGH and LIMIT_LOW can be set to +0.5 µm and -0.5 µm, respectively, to produce films with higher-order stack residue of less than 5 nm. The higher-order wafer warpage limits LIMIT_HIGH and LIMIT_LOW can be used to manage modifications to process parameter values ​​used in thin film deposition in an on-the-fly manner. For example, process parameters including deposition time, deposition rate, chamber pressure, and chemical ratio can be modified for subsequent wafers to be processed, thereby improving wafer yield for those wafers. By controlling the higher-order warpage Z_HO(X,Y) within the limits LIMIT_HIGH and LIMIT_LOW, the higher-order OVL residue is maintained under control (within its limits), resulting in improved wafer yield.

[0164] According to the embodiments described herein, other techniques for determining limits regarding higher-order warpage may include inspecting wafer regions and comparing regions with higher-order stacked pair residues OVL(X,Y) exceeding process limits with the same regions for higher-order wafer warpage. The scatter plot of the higher-order stacked pair residues OVL(X,Y) to the higher-order warpage Z_HO(X,Y) pair can be correlated. The comparison of higher-order warpage Z_HO(X,Y) to higher-order stacked pair residues OVL(X,Y) can be performed on multiple wafers. If necessary, the comparison can be performed while updating the higher-order warpage limits (LIMIT_HIGH and LIMIT_LOW).

[0165] According to the embodiments described herein, peeling events or peeling defects in the formed thin film are related to higher-order warpage Z_HO(X,Y), and the results are used to modify the parameters used in the thin film deposition process to manage the formation of such peeling events. A peeling event occurs when a portion of the thin film separates or "peels" from the substrate on which the film is deposited. Peeling events can be caused by higher-order stresses in the thin film.

[0166] Figures 6A to 7C This is an example of a semiconductor wafer with a thin film deposited on it. According to... Figure 1 The comparison between higher-order warpage and peeling events determined by the method is demonstrated according to the disclosed embodiments. Wafer warpage measurements before and after thin-film deposition are performed using an interferometer on the side of the semiconductor wafer to which the thin film will be deposited or on which the thin film has already been deposited.

[0167] Figure 6AContour plot 602 shows the set of net wafer warpage measurements Z(X,Y) for the semiconductor wafer 604 on which the thin film C has been deposited. The set of net wafer warpage measurements Z(X,Y) attributable to the thin film C is between -8.0 µm and +9.3 µm over a range of 17.3 µm.

[0168] Figure 6B Grayscale map 606 for the determined high-order warpage Z_HO(X,Y) of the semiconductor wafer 604 after the deposition of thin film C. Figure 6B In the process, the region of semiconductor wafer 604 with significant high-order warpage is... Figure 6B Regions with larger higher-order warp values ​​are identified; for example, a region on semiconductor wafer 304 with a higher-order warp value of 2.0 has larger higher-order warp than a region on semiconductor wafer 304 with a higher-order warp value less than 2.0. Figure 6B In the semiconductor wafer 604, regions 608a to 608e near the outer periphery 610 have the highest positive higher-order warpage. A positive higher-order wafer warpage ring 612 surrounds the entire semiconductor wafer 604.

[0169] Figure 6C Figure 614 shows the stripping events. Stripping events 616a to 616f are illustrated as following the outer periphery of semiconductor wafer 604, thus... Figure 6B The positive high-order wafer warpage ring 612 is related.

[0170] Figure 7A Contour plot 702 shows the net wafer warpage measurements Z(X,Y) of the semiconductor wafer 704 on which the thin film D has been deposited. The net wafer warpage measurements Z(X,Y) attributable to the thin film D range from -22.3 µm to +23.6 µm over a 45.9 µm area. Compared to... Figure 6A The range of net wafer warpage measurements Z(X,Y) for semiconductor wafer 604 is more than twice as high.

[0171] Figure 7B Grayscale map 706 showing the determined high-order warpage Z_HO(X,Y) of the semiconductor wafer 704 after the deposition of thin film D. Figure 7B In the process, the distributed positive high-order rings 708 exist near the outer periphery 710 of the semiconductor wafer 704. The distributed positive high-order rings 708, compared to... Figure 6B The high-order wafer warpage ring 612 is less significant. Figure 7B The grayscale map 706 does not have high positive high-order warping regions, such as Figure 6B Regions 608a to 608e.

[0172] Figure 7CFigure 712 shows the peeling events of the semiconductor wafer 704 after the deposition of the thin film D. Two peeling events 714a and 714b are illustrated along the outer perimeter 710 of the semiconductor wafer 704. Compared to... Figure 6C The lower number of stripping events, along with the placement of stripping events 714a and 714b near the outer perimeter 710, are associated with more scattered positive higher-order rings 708 and lower higher-order warpage Z_HO(X,Y).

[0173] In one embodiment, a method for estimating stacking residues caused by higher-order or non-uniform film stress will be described using rapid measurements of semiconductor wafer warpage attributable to thin-film deposition. Figure 8 A method 800 for determining higher-order warpage Z_HO(X) across the diameter of a semiconductor wafer. The higher-order warpage Z_HO(X) can be correlated with the stacking residue across the semiconductor wafer.

[0174] In the initial step 802, prior to thin film deposition, a first set of warpage measurements Z1(X) is obtained using a warpage measurement device across the diameter of the semiconductor wafer. The first set of warpage measurements Z1(X) is obtained using a thin film that will subsequently be deposited on a first surface of the semiconductor wafer.

[0175] In step 804, a thin film is deposited on the first surface of the semiconductor wafer.

[0176] In step 806, after the thin film is deposited, a second set of warpage measurements Z2(X) is obtained by using a warpage measurement device across the semiconductor diameter. The surface of the thin film opposite to the first surface of the semiconductor wafer can be used for the second warpage measurement.

[0177] In step 808, the warpage attributed to the thin film deposition Z(X) is determined by subtracting the first set of warpage measurements Z1(X) from the second set of warpage measurements Z2(X) for each measurement point X across the semiconductor wafer diameter.

[0178] Z(X) = Z2(X) – Z1(X)

[0179] In step 810, a one-dimensional polynomial regression is performed on the warpage measurement Z(X) to generate a second-order polynomial Z3(X) based on the coordinate X.

[0180] Z3(X) = B0 + B1X + B2X 2

[0181] Various computer numerical analysis tools can be used to perform one-dimensional regression, generating coefficients B0, B1, and B2. As with other regressions, the resulting polynomial can be plotted across the X range for which the first set of warp measurements Z1(X) and the second set of warp measurements Z2(X) are obtained, to check and confirm that the regression algorithm does not cause typically large deviations from the measured warp in the X and Y ranges. Adjustments to the regression criteria specific to the numerical analysis tool may be necessary to reduce the typically large deviations from the measured warp in the X range.

[0182] In step 812, the higher-order wafer warpage Z_HO(X) is determined by subtracting the second-order polynomial Z3(X) from the wafer warpage measurement Z(X,Y) for each measurement position X along the diameter of the semiconductor wafer.

[0183] Z_HO(X) = Z(X) – Z3(X)

[0184] A comparison of the higher-order warpage Z_HO(X) with the measured OVL residue obtained across the same diameter of the semiconductor wafer can be performed to determine the appropriate limits as previously described.

[0185] Figure 9 An alternative method 900 for determining higher-order warpage Z_HO(X,Y) of a semiconductor wafer according to embodiments described herein. Step 902 involves measuring a first set of warpage measurements Z1(X,Y) across the wafer region or pre-depositing. Step 904 involves depositing a thin film on the semiconductor wafer. Step 906 involves measuring a second set of warpage measurements Z2(X,Y) across the wafer region or post-depositing. Step 908 involves determining a set of net wafer warpage measurements Z(X,Y) across the wafer region. Step 910 involves performing a two-dimensional (X and Y dimensions) regression on the set of net wafer warpage measurements Z(X,Y) to determine a third-order or higher warpage polynomial Z3(X,Y). Step 912 involves determining the higher-order warpage Z_HO(X,Y) of the semiconductor wafer by evaluating the third-order and higher-order terms of the warpage polynomial Z3(X,Y) (if a higher-order polynomial has been determined).

[0186] Precise wafer alignment is an alternative metrology technique used as a basis for determining higher-order stresses in thin films. Fine wafer alignment utilizes fine wafer alignment marks generated before the thin film is deposited on the substrate. After film deposition, the wafer is placed in a lithography tool and aligned with a master photomask having corresponding fine wafer alignment marks beneath the film. Fine wafer alignment is faster than overlay residue metrology because it can be performed without subsequent photoresist deposition and patterning.

[0187] Figure 10An alternative method 1000 for determining higher-order stresses in a thin film using fine wafer alignment and removing translations and rotations. Step 1002 includes measuring a first original fine wafer alignment shift S1'(X,Y) at a measurement location across a semiconductor wafer region. Step 1004 includes removing translations, extensions, and rotations from the first original fine wafer alignment shift S1'(X,Y) to determine the fine wafer alignment shift S1(X,Y). Translation and rotation removal can be performed by lithography tools or mathematically after the first original fine wafer alignment shift S1'(X,Y) has been measured.

[0188] Step 1006 includes depositing a thin film on the wafer. Step 1008 includes measuring a second original fine wafer alignment shift S2'(X,Y) across the semiconductor wafer region. Step 1010 removes translations and rotations from the second original fine wafer alignment shift S2'(X,Y) to determine the fine wafer alignment shift S2(X,Y).

[0189] Step 1012 includes determining the net fine wafer alignment shift S(X,Y) attributable to thin film deposition by subtracting the first fine wafer alignment shift S1(X,Y) from the second fine wafer alignment shift S2(X,Y).

[0190] S(X,Y) = S2(X,Y) - S1(X,Y)

[0191] With the filtering and rotation terms removed, non-uniform stress can be determined with greater certainty at the center of the semiconductor wafer surface because fine wafer alignment errors are usually small at the center of the wafer.

[0192] Figure 11 An alternative method 1100 is provided for using a linear model of fine wafer alignment and FIWA error. Step 1102 includes measuring a first fine wafer alignment shift T1'(X,Y) across a semiconductor wafer region. Step 1104 includes removing translation, expansion, and rotation terms from the linear model T1(X,Y) of the first fine wafer alignment shift T1'(X,Y). Step 1106 includes depositing a thin film on the semiconductor wafer surface. Step 1108 includes measuring a second fine wafer alignment shift T2'(X,Y) across the semiconductor wafer. Step 1110 includes performing a linear model T2(X,Y) of the second fine wafer alignment shift T2'(X,Y). Step 1112 includes determining the net linear fine wafer alignment shift T(X,Y) attributable to thin film deposition by subtracting the linear model T1(X,Y) from the linear model T2(X,Y).

[0193] T(X,Y)=T2(X,Y)-T1(X,Y)

[0194] Figures 12A to 12C as well as Figures 13A to 13CAccording to Figure 10 Method 1000 is used to determine the nonlinear stress in the deposited thin film.

[0195] Figures 12A to 12C The figure shows a thin film E with high nonlinear stress. Figure 12A A graph 1200a is used to illustrate the first FIWA shift S1(X,Y) before the deposition of the thin film E. Figure 12B Graph 1200b is used to illustrate the second FIWA shift S2(X,Y) after the deposition of film E. Translation, expansion, and rotation have been removed in graphs 1200a and 1200b. Figure 12C A graph 1200c is used to illustrate the net FIWA shift S(X,Y) attributed to thin film deposition.

[0196] Figures 13A to 13C The figure shows a thin film F with low nonlinear stress. Figure 13A A graph 1300a is used to illustrate the first FIWA shift S1(X,Y) before the deposition of the thin film F. Figure 13B Graph 1300b is used to illustrate the second FIWA shift S2(X,Y) after the deposition of the thin film F. Translation and rotation have been removed in graphs 1300a and 1300b. Figure 13C A graph 1300c is used to illustrate the net FIWA shift S(X,Y) attributed to thin film deposition.

[0197] Figures 14A to 14C as well as Figures 15A to 15C According to Figure 11 Method 1100 is used to determine the nonlinear stress in the deposited thin film.

[0198] Figures 14A to 14C The figure shows a thin film G with high nonlinear stress. Figure 14A A graph 1400a is used to illustrate the FIWA shift T'(X,Y) attributed to the deposition of thin film G. Figure 14B Graph 1400b is used to illustrate the linear model T(X,Y) of the FIWA shift T'(X,Y). Translation and rotation have been removed in graphs 1400a and 1400b. Figure 14C To illustrate the higher-order stacked pair residue OVL(X,Y), a graph 1400c is shown. The correlation between the FIWA linear model T(X,Y) and the higher-order stacked pair residue OVL(X,Y) can be observed.

[0199] Figures 15A to 15C The figure shows a thin film H with low nonlinear stress. Figure 15A A graph 1500a is used to illustrate the FIWA shift T'(X,Y) attributed to the deposition of thin film H. Figure 15BGraph 1500b is used to illustrate the linear model T(X,Y) of the FIWA shift T'(X,Y). Translation and rotation have been removed in graphs 1500a and 1500b. Figure 15C A graph (1500c) is used to plot the higher-order stacked pair residue OVL(X,Y). The correlation between the FIWA linear model T(X,Y) and the higher-order stacked pair residue OVL(X,Y) can be observed.

[0200] In one embodiment, a method for determining high-order stacking residue includes: depositing a thin film on a surface of a substrate, and measuring warpage of the substrate after film deposition at multiple measurement locations on the surface of the substrate. Warpage at the multiple measurement locations on the surface of the substrate attributable to the film deposition can be determined. The determined warpage measurement attributable to the film deposition can be adapted to a low-order polynomial based on the coordinates of the multiple measurement locations on the surface of the substrate. The low-order polynomial can be evaluated for at least one coordinate of the measurement location. The evaluated low-order polynomial for at least one coordinate of the measurement location can be subtracted from the warpage measurement of the substrate after film deposition at the measurement location.

[0201] In the above embodiments, the method further includes measuring a first warpage of the substrate at multiple measurement locations on the surface of the substrate before depositing the thin film; wherein the step of determining a warpage of the substrate attributable to the thin film deposition includes the following steps: subtracting the first warpage measurement value from the warpage measurement value of the substrate at multiple locations on the surface of the substrate attributable to the thin film deposition.

[0202] In the above embodiments, the low-order polynomial is a first- or second-order polynomial.

[0203] In the above embodiments, the method further includes using the result of the subtraction step to determine an adjustment of a parameter of a step that affects the deposition of the thin film.

[0204] In the above embodiments, the step of measuring the warpage of the substrate includes: measuring in a direction substantially perpendicular to the surface of the substrate.

[0205] In the above embodiments, the step of measuring the warpage of the substrate includes: interferometric measurement of a difference between a reference plane and the surface of the substrate.

[0206] In one embodiment, a method for evaluating higher-order stresses in a thin film deposited on a semiconductor wafer includes determining lower-order wafer warpage based on the location on the semiconductor wafer using warpage measurements from multiple locations on the semiconductor wafer. Higher-order warpage can be determined based on the warpage measurements from multiple locations on the semiconductor wafer and the determined location of lower-order warpage. Multiple higher-order overlap errors can be measured across the semiconductor wafer using multiple overlap patterns.

[0207] In the above embodiments, the method further includes comparing the determined higher-order warpage at each of a plurality of locations on the semiconductor wafer with the higher-order overlap error measured at the nearest location of each of the plurality of locations; and determining a threshold value for higher-order warpage when the higher-order overlap error at the plurality of locations exceeds a threshold value for overlap error.

[0208] In the above embodiments, the higher-order overlap error at multiple locations is a single value.

[0209] In the above embodiments, the higher-order overlap error threshold includes: an upper threshold; and a lower threshold.

[0210] In the above embodiments, the threshold values ​​for higher-order warpage include: an upper threshold value; and a lower threshold value.

[0211] In the above embodiments, the method further includes determining whether a change in a parameter of a process used to deposit a thin film is necessary when the higher-order warpage is above or below the higher-order warpage threshold.

[0212] In one embodiment, a method includes measuring warpage of a semiconductor wafer at multiple locations on the surface of the semiconductor wafer in a direction generally perpendicular to the surface of the semiconductor wafer, the multiple locations being identified using coordinate axes generally parallel to the surface of the semiconductor wafer. A regression polynomial may be generated based on at least one of the coordinate axes generally parallel to the surface of the semiconductor wafer and the warpage measurements at the multiple locations on the surface of the semiconductor wafer. Higher-order polynomials may be generated by removing lower-order elements of the regression polynomial. The higher-order polynomials may be evaluated for locations on the surface of the semiconductor wafer.

[0213] In the above embodiments, the regression polynomial has an order of at least third order.

[0214] In the above embodiments, the lower-order elements removed in the step of generating the regression polynomial have an order of second or less.

[0215] In the above embodiments, the method further includes depositing a thin film on the surface of a semiconductor wafer, wherein the step of measuring a warpage of the semiconductor wafer at multiple locations on a surface of the semiconductor wafer in a direction substantially perpendicular to the surface of the semiconductor wafer includes the following steps: before the step of depositing the thin film on the surface of the semiconductor wafer, measuring a first warpage of the semiconductor wafer at multiple locations on the surface of the semiconductor wafer; and after the step of depositing the thin film on the surface of the semiconductor wafer, measuring a second warpage of the semiconductor wafer at multiple locations on the surface of the semiconductor wafer.

[0216] In the above embodiments, the method further includes determining a warpage of the semiconductor wafer at multiple locations attributable to the deposition of a thin film at multiple locations by subtracting a measured first warpage at multiple locations from a measured second warpage at multiple locations.

[0217] In the above embodiments, the method further includes comparing the determined warpage in the semiconductor wafer attributable to the deposition of a thin film with a higher-order warpage upper limit and a higher-order warpage lower limit.

[0218] In the above embodiments, the method further includes determining the upper limit and lower limit of higher-order warpage by comparing higher-order warpage with a fine wafer alignment error threshold.

[0219] In the above embodiments, the fine wafer alignment error threshold has a removed translation and a rotation.

[0220] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and replacements can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for semiconductor processing, characterized in that, Comprising the following steps: Depositing a thin film on a surface of a substrate; Measuring a warp of the substrate at a plurality of measurement positions on the surface of the substrate after the thin film is deposited; Determining a low-order warp of the substrate attributable to the thin film deposition at a plurality of measurement positions on the surface of the substrate; Adapting the measured warp values of the substrate determined to be attributable to the thin film deposition to a low-order polynomial according to the coordinates of the plurality of measurement positions on the surface of the substrate; Evaluating the low-order polynomial for at least one coordinate of a measurement position; And After the thin film is deposited at the measurement position, determining a high-order warp based on the measured warp values at a plurality of measurement positions on the surface of the substrate and the position of the determined low-order warp, including subtracting the evaluated low-order polynomial from the measured warp values of the substrate for at least one coordinate of the measured position to generate a high-order polynomial.

2. The method according to claim 1, further comprising, before depositing the thin film, measuring a first warpage of the substrate at a plurality of measurement positions on the surface of the substrate; wherein the step of determining a warpage of the substrate attributable to the thin film deposition comprises the following steps: Subtracting the first measured warp value from the measured warp values of the substrate attributable to the thin film deposition at a plurality of positions on the surface of the substrate.

3. The method according to claim 1, wherein the low-order polynomial is a second-order polynomial.

4. The method according to claim 1, further comprising using the result of the subtracting step to determine an adjustment of a parameter affecting the step of depositing the thin film.

5. The method according to claim 1, wherein the step of measuring the warp of the substrate comprises: Measuring in a direction perpendicular to the surface of the substrate.

6. The method according to claim 1, wherein the step of measuring the warp of the substrate comprises: Interferometric measurement of a difference between a reference plane and the surface of the substrate.

7. A method for evaluating higher-order stress in a thin film deposited on a semiconductor wafer, characterized in that, Comprising: Determining a low-order wafer warp according to the positions on the semiconductor wafer using the measured warp values at a plurality of positions of the thin film on the semiconductor wafer; Determining a high-order warp based on the measured warp values at a plurality of positions of the thin film on the semiconductor wafer and the position of the determined low-order wafer warp; And Measuring a plurality of high-order overlay errors across the semiconductor wafer using a plurality of overlay patterns.

8. The method according to claim 7, further comprising: Comparing the determined high-order warp at each of a plurality of positions of the thin film on the semiconductor wafer with the measured high-order overlay error at the nearest position to each of the plurality of positions; and When the high-order overlay error at a plurality of positions exceeds a high-order overlay error threshold value, determining a threshold value of the high-order warp.

9. The method according to claim 8, wherein the high-order overlay error at a plurality of positions is a magnitude.

10. The method according to claim 8, wherein the high-order stack pair error threshold value includes: An upper threshold value; and a lower threshold value.

11. The method according to claim 10, wherein the threshold value of the high-order warpage includes: An upper threshold value; and a lower threshold value.

12. The method according to claim 11, further comprising determining whether it is necessary to change a parameter affecting a process for depositing the thin film when the high-order warp is higher than the threshold value of the high-order warp or lower than the threshold value of the high-order warp.

13. A method for semiconductor processing, characterized in that, Comprising: Measuring the warp of the semiconductor wafer at a plurality of positions on the surface of the semiconductor wafer in a direction substantially perpendicular to the surface of the semiconductor wafer, and identifying the plurality of positions using coordinate axes substantially parallel to the surface of the semiconductor wafer; Generating a regression polynomial based on at least one of the coordinate axes substantially parallel to the surface of the semiconductor wafer and the measured warp values at a plurality of positions on the surface of the semiconductor wafer; Generating a high-order polynomial by removing low-order elements of the regression polynomial; and Evaluating the high-order polynomial for positions on the surface of the semiconductor wafer.

14. The method according to claim 13, wherein the regression polynomial has an order of at least three.

15. The method according to claim 14, wherein the low-order elements removed in the step of generating the regression polynomial have an order of two or less.

16. The method according to claim 13, further comprising depositing a thin film on the surface of the semiconductor wafer, wherein the step of measuring a warp of the semiconductor wafer in a direction substantially perpendicular to the surface of the semiconductor wafer at a plurality of positions on a surface of the semiconductor wafer comprises the following steps: Measuring a first warp of the semiconductor wafer at a plurality of positions on the surface of the semiconductor wafer before the step of depositing the thin film on the surface of the semiconductor wafer; and Measuring a second warp of the semiconductor wafer at a plurality of positions on the surface of the semiconductor wafer after the step of depositing the thin film on the surface of the semiconductor wafer.

17. The method according to claim 14, further comprising determining a warp of the semiconductor wafer attributable to deposition of the thin film at a plurality of positions by subtracting the measured second warp at a plurality of positions from the measured first warp at a plurality of positions.

18. The method according to claim 17, further comprising comparing the determined warp of the semiconductor wafer attributable to deposition of the thin film with an upper high-order warp limit value and a lower high-order warp limit value.

19. The method according to claim 18, further comprising determining the upper high-order warp limit value and the lower high-order warp limit value by comparing the high-order warp with a fine wafer alignment error limit value.

20. The method according to claim 19, wherein the fine wafer alignment error limit value has a removed translation and rotation.

21. A method for evaluating stress deposited on a thin film of a semiconductor wafer, characterized in that, Comprising: Using warp measurement values from a plurality of positions on a semiconductor wafer to determine a low-order wafer warp based on positions on the semiconductor wafer, wherein determining the low-order wafer warp comprises fitting to a low-order polynomial based on coordinates of a plurality of measurement positions on the surface of the semiconductor wafer attributable to the determined warp measurement values; and Performing a mathematical operation on the low-order wafer warp and the warp measurement values, performing the mathematical operation comprising: Evaluating the low-order polynomial for at least one coordinate of a measurement position; and Subtracting the evaluated low-order polynomial on the at least one coordinate of the measured position from the warp measurement value.

22. The method according to claim 21, wherein the low-order polynomial is a second-order polynomial.

23. The method according to claim 21, wherein performing the mathematical operation comprises determining a high-order warp based on using the warp measurement values from a plurality of positions on the semiconductor wafer and the position of the determined low-order wafer warp, the method comprising measuring a plurality of high-order alignment errors using a plurality of alignment patterns across the semiconductor wafer.

24. The method according to claim 23, further comprising: Compare the determined higher-order warpage at each of a plurality of locations on the semiconductor wafer with the higher-order overlay error measured at the closest location to each of the plurality of locations; and Determine a threshold value of the higher-order warpage when the higher-order overlay error at a plurality of locations exceeds a higher-order overlay error threshold value.

25. The method according to claim 24, wherein the higher-order overlay error at a plurality of locations is a magnitude.

26. The method according to claim 24, wherein the high-order stack pair error threshold value includes: An upper threshold value; and a lower threshold value.

27. The method according to claim 24, wherein the threshold value of the high-order warpage comprises: An upper threshold value; and a lower threshold value.

28. The method according to claim 27, further comprising determining whether a change in a parameter affecting a process for depositing the thin film is necessary when the higher-order warpage is higher than the threshold value of the higher-order warpage or lower than the threshold value of the higher-order warpage.

29. A method for semiconductor processing, characterized in that, Comprising: Measure the warpage of the semiconductor wafer at a plurality of locations on the surface of the semiconductor wafer, and the plurality of locations are identified using coordinate axes; Generate a regression polynomial based on at least one of the coordinate axes of the surface of the semiconductor wafer and the warpage measurement values at a plurality of locations on the surface of the semiconductor wafer; And Perform a mathematical operation on the polynomial, wherein performing the mathematical operation includes generating a higher-order polynomial by removing low-order elements of the regression polynomial.

30. The method according to claim 29, wherein the method evaluates the higher-order polynomial for locations on the surface of the semiconductor wafer.

31. The method according to claim 30, wherein measuring the warpage of the semiconductor wafer includes measuring the warpage of the semiconductor wafer in a direction substantially perpendicular to the surface of the semiconductor wafer at a plurality of locations on the surface of the semiconductor wafer, and the coordinate axes are substantially parallel to the surface of the semiconductor wafer.

32. The method according to claim 31, wherein the regression polynomial has an order of at least three.

33. The method according to claim 32, wherein the low-order elements removed in the step of generating the regression polynomial have an order of second or lower.

34. The method according to claim 31, further comprising depositing a thin film on the surface of the semiconductor wafer, wherein the step of measuring the warpage of the semiconductor wafer in a direction substantially perpendicular to the surface of the semiconductor wafer at a plurality of locations on a surface of the semiconductor wafer includes the following steps: Before the step of depositing the thin film on the surface of the semiconductor wafer, measure a first warpage of the semiconductor wafer at a plurality of locations on the surface of the semiconductor wafer; And After the step of depositing the thin film on the surface of the semiconductor wafer, measure a second warpage of the semiconductor wafer at a plurality of locations on the surface of the semiconductor wafer.

35. A method for semiconductor processing, characterized in that, Comprising: Determine the low-order wafer warpage based on the warpage measurement values at a plurality of locations on the semiconductor wafer, wherein determining the low-order wafer warpage includes fitting the determined warpage measurement values to a low-order polynomial based on the coordinates of a plurality of measurement locations on the surface of the semiconductor wafer; Determining high-order warpage based on the warpage measurement values from multiple positions on the semiconductor wafer and the determined position of the low-order wafer warpage, including measuring multiple high-order overlay errors using multiple overlay patterns across the semiconductor wafer; and comparing the determined high-order warpage at each of the multiple positions on the semiconductor wafer with the high-order overlay error measured at the nearest location to each of the multiple positions.

36. The method according to claim 35, further comprising: When the high-order overlay error at multiple positions exceeds a high-order overlay error threshold value, determining a threshold value of the high-order warpage.

37. The method according to claim 36, wherein the high-order overlay error at each of the multiple positions is a magnitude.

38. The method according to claim 36, wherein the high-order stack pair error threshold value includes: An upper threshold value; and a lower threshold value.

39. The method according to claim 38, wherein the threshold value of the high-order warpage includes: An upper threshold value; and a lower threshold value.

40. The method according to claim 35, further comprising determining whether a change in a parameter affecting a process for depositing a thin film is necessary when the high-order warpage is higher than the threshold value of the high-order warpage or lower than the threshold value of the high-order warpage.

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