Integrated Circuit Device with Redistribution Pattern

Abstract

An integrated circuit device includes a wiring structure, a first inter-wiring insulating layer, a second inter-wiring insulating layer, a redistribution pattern, and a covering insulating layer. The wiring structure includes a wiring layer having a multi-layer wiring structure and via plugs. The first inter-wiring insulating layer surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs connect to the wiring structure through the second inter-wiring insulating layer. The redistribution pattern on the second inter-wiring insulating layer includes a pad pattern and a dummy pattern. The thickness of each pattern is greater than the thickness of each wiring layer. The covering insulating layer covers some of the redistribution patterns. The dummy pattern is in the form of a line extending in a horizontal direction parallel to the substrate.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0109414, filed with the Korean Intellectual Property Office on September 4, 2019, the entire disclosure of which is incorporated herein by reference.

[0003] and is incorporated herein. Technical Field

[0004] The present disclosure relates to an integrated circuit device, and more particularly, to an integrated circuit device having a redistribution pattern.

[0005] scheme. Background Art

[0006] With the development of the electronics industry and the demands of users, electronic devices have multiple functions and large capacities, and are miniaturized and lightened. Therefore, integrated circuit devices used in electronic devices need to have a high degree of integration. To stably supply power to high - integrated circuit devices or ensure the reliability of the electrical connection between the integrated circuit device and the electronic device, a redistribution pattern that is electrically connected to a wiring structure including

[0007] a wiring layer and a via plug has been introduced. Summary of the Invention

[0008] One aspect is to provide an integrated circuit device having a redistribution pattern designed to increase the reliability of the integrated circuit device.

[0009] According to one or more aspects of the embodiments, an integrated circuit device is provided. The integrated circuit device includes: a wiring structure on a substrate and a first inter - wiring insulating layer configured to surround the wiring structure, the wiring structure including a plurality of wiring layers having a multi - layer wiring structure and a plurality of via plugs; a second inter - wiring insulating layer and a plurality of redistribution via plugs on the first inter - wiring insulating layer, the plurality of redistribution via plugs passing through the second inter - wiring insulating layer and connecting to the wiring structure; a plurality of redistribution patterns on the second inter - wiring insulating layer, which include a plurality of pad patterns and a plurality of dummy patterns, the thickness of each of the plurality of pad patterns and each of the plurality of dummy patterns being greater than the thickness of each of the plurality of wiring layers; and a cover insulating layer configured to cover a part of the plurality of redistribution patterns, wherein the plurality of dummy patterns extend linearly in a horizontal direction parallel to the substrate and are completely surrounded by the second inter - wiring insulating layer and the cover insulating layer to be electrically isolated from each other.

[0010] According to one aspect of one or more embodiments, there is provided an integrated circuit device including: a wiring structure on a substrate and a first inter-wiring insulating layer configured to surround the wiring structure, the wiring structure including a plurality of wiring layers having a multi-layer wiring structure and a plurality of via plugs; a second inter-wiring insulating layer and a plurality of redistribution via plugs on the first inter-wiring insulating layer, the plurality of redistribution via plugs passing through the second inter-wiring insulating layer and connected to the wiring structure; a plurality of redistribution patterns on the second inter-wiring insulating layer, including a plurality of pad patterns, a plurality of dummy patterns, and a plurality of power patterns, the thickness of each of the plurality of pad patterns, the plurality of dummy patterns, and the plurality of power patterns being not less than twice the thickness of each of the plurality of wiring layers; a covering insulating layer configured to cover the plurality of dummy patterns and the plurality of power patterns and not cover at least a part of the plurality of pad patterns; and a plurality of connection terminals respectively connected to the plurality of pad patterns, wherein the plurality of dummy patterns are in the form of lines extending in a horizontal direction parallel to the substrate and are completely surrounded by the second inter-wiring insulating layer and the covering insulating layer to be electrically isolated from each other.

[0011] According to one aspect of one or more embodiments, there is provided an integrated circuit device including: a device layer on a substrate, including a plurality of semiconductor devices; a wiring structure on the device layer, including a plurality of wiring layers having a multi-layer wiring structure including a topmost wiring layer and a plurality of via plugs; a first inter-wiring insulating layer on the device layer configured to surround the wiring structure; a second inter-wiring insulating layer on the first inter-wiring insulating layer and the wiring structure; a plurality of redistribution via plugs connected to the topmost wiring layer through the second inter-wiring insulating layer; a plurality of redistribution patterns including a plurality of pad patterns, a plurality of dummy patterns, and a plurality of power patterns, each of the plurality of pad patterns being connected to one of the plurality of redistribution via plugs on the second inter-wiring insulating layer, each of the plurality of dummy patterns being in the form of a line extending in a horizontal direction parallel to the substrate, and each of the plurality of power patterns being connected to at least two of the plurality of redistribution via plugs and having a thickness not less than twice the thickness of the topmost wiring layer; a covering insulating layer configured to cover the plurality of dummy patterns and the plurality of power patterns; and a plurality of connection terminals respectively connected to the plurality of pad patterns, each of the plurality of connection terminals including a conductive post and a conductive cap configured to cover an upper surface of the conductive post, wherein the plurality of dummy patterns are completely surrounded by the second inter-wiring insulating layer and the covering insulating layer and are electrically isolated from each other, and wherein, among an upper surface, a side surface, and a lower surface of each of the plurality of power patterns, a portion not connected to the at least two redistribution via plugs is covered by the second inter-wiring insulating layer and the covering insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Various embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1A and Figure 1B are a plan view and a cross-sectional view showing an integrated circuit device according to an embodiment, respectively;

[0014] Figure 2A is a plan view showing an integrated circuit device according to an embodiment, Figures 2B to 2C is a cross-sectional view showing an integrated circuit device according to an embodiment;

[0015] Figure 3 is a plan view showing an integrated circuit device according to an embodiment;

[0016] Figure 4 is a plan view showing an integrated circuit device according to an embodiment;

[0017] Figure 5A and Figure 5B are a plan view and a cross-sectional view showing an integrated circuit device according to an embodiment, respectively;

[0018] Figure 6 is a plan view showing an integrated circuit device according to an embodiment;

[0019] Figure 7A and Figure 7B are a plan view and a cross-sectional view showing an integrated circuit device according to an embodiment, respectively;

[0020] Figure 8 is a flowchart showing a method of manufacturing an integrated circuit device according to an embodiment. Detailed Description

[0021] In this specification, the phrase "at least one of A and B" includes "only A", "only B", and "both A and B".

[0022] Figure 1A and Figure 1B are a plan view and a cross-sectional view showing an integrated circuit device according to an embodiment, respectively. Specifically, Figure 1B is a cross-sectional view taken along the line IB–IB’ of Figure 1A .

[0023] Referring to Figure 1A and Figure 1B, the integrated circuit device 1 includes a device layer 130, which includes a plurality of semiconductor devices 120 on a substrate 110. For example, the substrate 110 may include silicon (Si). Alternatively, in some embodiments, the substrate 110 may include a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Alternatively, in some embodiments, the substrate 110 may have a silicon-on-insulator (SOI) structure. For example, the substrate 110 may include a buried oxide (BOX) layer. The substrate 110 may include conductive regions (e.g., wells or structures doped with impurities). Alternatively, in some embodiments, the substrate 110 may have various device isolation structures such as a shallow trench isolation (STI) structure. The substrate 110 may have an active surface and a non-active surface opposite the active surface.

[0024] The device layer 130 including the plurality of semiconductor devices 120 may be disposed on the active surface of the substrate 110. In Figure 1B , a portion of the device layer 130 in which the plurality of semiconductor devices 120 are formed on the active surface of the substrate 110 is shown. However, the embodiments are not limited thereto. For example, in some embodiments, the plurality of semiconductor devices 120 may be formed on a portion of the active surface of the substrate 110 and above the device layer 130.

[0025] At least some of the plurality of semiconductor devices 120 may be transistors. For example, at least some of the plurality of semiconductor devices 120 may be bipolar junction transistors (BJTs) or field effect transistors (FETs). For example, at least some of the plurality of semiconductor devices 120 may be planar transistors or FinFET transistors. When at least some of the plurality of semiconductor devices 120 are FinFET transistors, on the substrate 110, a plurality of fin active regions may protrude and extend parallel to each other in a horizontal direction (X direction or Y direction).

[0026] In some embodiments, the plurality of semiconductor devices 120 may be various types of individual devices for forming a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, an electrically erasable programmable read-only memory (EEPROM) device, a phase change random access memory (PRAM) device, a magnetic random access memory (MRAM) device, or a resistive random access memory (RRAM) device. For example, the plurality of semiconductor devices 120 may be various types of individual devices for forming a high bandwidth memory (HBM) DRAM device, and the integrated circuit device 1 may be an HBM DRAM device.

[0027] In other embodiments, a plurality of semiconductor devices 120 may form a logic unit. The logic unit may be formed differently to include a plurality of circuit devices such as transistors and registers. For example, the logic unit may form AND, NAND, OR, NOR, exclusive OR (XOR), exclusive NOR (XNOR), inverter INV, adder ADD, buffer BUF, delay DLY, filter FIL, multiplexer MXT / MXIT, OR / AND / INVERTER (OAI), and AND / OR (AO), AND / OR / INVERTER (OAI), D flip-flop, reset flip-flop, master-slave flip-flop, or latch. The logic unit may form a standard unit that performs a desired logic function, such as a counter or a buffer. For example, the integrated circuit device 1 may be a central processing unit (CPU), a graphics processing unit (GPU), or an application processor (AP).

[0028] The device layer 130 may include a plurality of semiconductor devices 120, conductive lines and conductive plugs for connecting the plurality of semiconductor devices 120, and an interlayer insulating layer filling the space between the plurality of semiconductor devices 120, conductive lines, and conductive plugs. The device layer 130 may be formed of various kinds and shapes of conductive materials, semiconductor materials, and insulating materials. In some embodiments, the interlayer insulating layer filling the conductive lines and conductive plugs may include an oxide.

[0029] The wiring structure MS and the first inter-wiring insulating layer 210 surrounding the wiring structure MS may be disposed on the substrate 110 on which the device layer 130 is formed.

[0030] The wiring structure MS may include a plurality of wiring layers ML and a plurality of via plugs MV connected to the plurality of wiring layers ML. The plurality of wiring layers ML may have a multi-layer wiring structure including a plurality of wiring layers ML positioned at different levels within the device layer 130. Figure 1B The illustrated connection relationship between the plurality of wiring layers ML and the plurality of via plugs MV is for exemplarily showing the multi-layer wiring structure, and the actual connection relationship may not be shown.

[0031] In this specification, "horizontal" means the height in the vertical direction (Z direction) with respect to the main surface (e.g., the upper surface of the substrate 110). That is, being positioned at the "same" level or "uniform" level means having a position with an equal or uniform height in the vertical direction (Z direction) with respect to the main surface of the substrate 110, and being positioned at a "low" or "high" level means having a position with a smaller or larger height in the vertical direction (Z direction) with respect to the main surface of the substrate 110.

[0032] The wiring structure MS may include a metallic material such as aluminum (Al), copper (Cu), or tungsten (W). In some embodiments, the wiring structure MS may include a wiring barrier layer or a wiring metal layer. The wiring barrier layer may be formed of a nitride or an oxide of a metal such as titanium (Ti), tantalum (Ta), ruthenium (R), manganese (Mn), or cobalt (Co) or W, or an alloy such as cobalt tungsten phosphide (CoWP), cobalt tungsten boron (CoWB), or cobalt tungsten boron phosphide (CoWBP). The wiring metal layer may include at least one of W, Al, Ti, Ta, Ru, Mn, and Cu.

[0033] Each of the plurality of wiring layers ML may have a thickness of not more than 0.5 μm. In some embodiments, each of the uppermost wiring layers ML-T disposed at the uppermost end among the plurality of wiring layers ML may have a thickness of not more than about 0.5 μm, and each of the remaining wiring layers ML may have a thickness of not more than about 0.3 μm (which is less than the thickness of each uppermost wiring layer ML-T).

[0034] Some of the uppermost wiring layers ML-T disposed at the uppermost end among the plurality of wiring layers ML may be used as sub-pads electrically connected to the pad patterns RL-P among the plurality of redistribution patterns RL. A plurality of connection terminals 300 may be respectively disposed on the pad patterns RL-P. Other uppermost wiring layers ML-T may be used as wirings for electrically connecting the plurality of wiring layers ML forming the wiring structure MS and the plurality of via plugs MV to each other.

[0035] The via plug MV disposed at the lowermost end among the plurality of via plugs MV may extend from the lower surface of the plurality of wiring layers ML toward the device layer 130. The wiring structure MS may be electrically connected to the plurality of semiconductor devices 120. The plurality of via plugs MV may extend from the lower surface of the plurality of wiring layers ML having a multilayer wiring structure and positioned at different levels toward the substrate 110.

[0036] Some of the plurality of via plugs MV may connect the plurality of wiring layers ML positioned at different levels to each other, and other via plugs MV among the plurality of via plugs MV may connect some of the plurality of wiring layers ML to the plurality of semiconductor devices 120 or the substrate 110 to each other. For example, the via plug MV disposed at the lowermost end among the plurality of via plugs MV may connect the wiring layer ML disposed at the lowermost end among the plurality of wiring layers ML to the plurality of semiconductor devices 120 or the substrate 110 to each other.

[0037] The first interlayer insulating layer 210 may have a multi-layer structure in which a plurality of low-k dielectric insulating layers are stacked to correspond to the multi-layer wiring structure of the plurality of wiring layers ML. In some embodiments, the first interlayer insulating layer 210 may be formed of an insulating material having a dielectric constant less than that of Si oxide. For example, in some embodiments, the first interlayer insulating layer 210 may include an ultra-low-k (ULK) layer having an ultra-low dielectric constant K of about 2.2 to about 2.4. The ULK layer may include a SiOC layer or a SiCOH layer. The first interlayer insulating layer 210 may be referred to as a low-k dielectric insulating layer.

[0038] In other embodiments, the first interlayer insulating layer 210 may have a multi-layer structure in which an insulating material having a dielectric constant less than that of Si oxide and another insulating material having a dielectric constant equal to or greater than that of Si oxide are stacked. For example, at least one of the multi-layer structures of the first interlayer insulating layer 210 may include an oxide layer or a nitride layer. For example, the first interlayer insulating layer 210 may include an etch stop layer formed of a nitride, which is used in the process of forming the plurality of wiring layers ML. However, the ratio of the etch stop layer formed of a nitride to the first interlayer insulating layer 210 may be very low.

[0039] The second interlayer insulating layer 220 and the redistribution via plug RV connected to the wiring structure MS through the second interlayer insulating layer 220 may be formed on the wiring structure MS and the first interlayer insulating layer 210.

[0040] The second interlayer insulating layer 220 may include an oxide layer, a nitride layer, a carbide layer, a polymer, or a combination of these compounds. The second interlayer insulating layer 220 may be formed of an insulating material having a dielectric constant greater than that of the first interlayer insulating layer 210. For example, the second interlayer insulating layer 220 may be formed of an oxide. In some embodiments, the second interlayer insulating layer 220 may be formed of tetraethyl orthosilicate (TEOS). In some embodiments, the level of the upper surface of the second interlayer insulating layer 220 may be substantially uniform.

[0041] In some embodiments, the redistribution via plug RV may include a barrier layer and a metal layer. The barrier layer may be formed of a nitride or an oxide of a metal such as Ti, Ta, Ru, Mn, Co, or W, or an alloy such as CoWP, CoWB, or CoWBP. The metal layer may include at least one of W, Al, Ti, Ta, Ru, Mn, and Cu.

[0042] In Figure 1BAmong them, it is shown that the uppermost wiring layer ML-T among the plurality of wiring layers ML is disposed on the first inter-wiring insulating layer 210 such that the lower surface of the uppermost wiring layer ML-T and the lower surface of the second inter-wiring insulating layer 220 are positioned at the same level. However, the embodiment is not limited thereto. In some embodiments, the upper surface of the uppermost wiring layer ML-T may be positioned at the same level as the upper surface of the first inter-wiring insulating layer 210.

[0043] A plurality of redistribution patterns RL may be disposed on the second inter-wiring insulating layer 220 and the redistribution via plugs RV. The value of the thickness of each of the plurality of redistribution patterns RL may be greater than the value of the thickness of each of the plurality of wiring layers ML. For example, the value of the thickness of each of the plurality of redistribution patterns RL may be not less than twice the value of the thickness of each of the plurality of wiring layers ML. In some embodiments, the thickness of each of the plurality of redistribution patterns RL may be about 1 to about 5. In some embodiments, the ratio of the planar area of the plurality of redistribution patterns RL to the planar area of the intervals between the plurality of redistribution patterns RL may be about 3.5:1 to about 4.5:1.

[0044] The plurality of redistribution patterns RL may include a plurality of pad patterns RL-P and a plurality of dummy patterns RL-D. In some embodiments, the plurality of redistribution patterns RL may include a barrier layer and a metal layer. The barrier layer may be formed of a nitride or oxide of a metal such as Ti, Ta, Ru, Mn, Co, or W or an alloy such as CoWP, CoWB, or CoWBP. The metal layer may include at least one of W, Al, Ti, Ta, Ru, Mn, and Cu.

[0045] The lower surfaces of the plurality of pad patterns RL-P may respectively contact the upper surfaces of the redistribution via plugs RV such that the plurality of pad patterns RL-P may be electrically connected to the wiring structure MS respectively through the plurality of redistribution via plugs RV. The lower surfaces of the plurality of dummy patterns RL-D may contact the upper surface of the second inter-wiring insulating layer 220 such that the plurality of dummy patterns RL-D may be electrically isolated from the wiring structure MS, and the second inter-wiring insulating layer 220 is located between the plurality of dummy patterns RL-D and the wiring structure MS.

[0046] The plurality of pad patterns RL-P may be arranged in at least one column in the horizontal direction (X direction or Y direction). In some embodiments, the plurality of pad patterns RL-P may be horizontally arranged in a matrix. The plurality of connection terminals 300 may be respectively connected to the plurality of pad patterns RL-P. For example, the plurality of pad patterns RL-P may be center pads two-dimensionally arranged in the center of the integrated circuit device 1. However, the embodiment is not limited thereto. In some embodiments, the plurality of pad patterns RL-P may be edge pads two-dimensionally arranged adjacent to the edge of the integrated circuit device 1.

[0047] Each of the plurality of dummy patterns RL-D may be in the form of a line extending in a first horizontal direction (X direction) or a second horizontal direction (Y direction). In Figure 1A , it is shown that the plurality of dummy patterns RL-D are in the form of lines extending in the same direction (i.e., the first horizontal direction (X direction)). However, the embodiments are not limited thereto. For example, some of the plurality of dummy patterns RL-D are in the form of lines extending in the first horizontal direction (X direction), and the remaining dummy patterns RL-D are in the form of lines extending in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction).

[0048] Each of the plurality of dummy patterns RL-D may be in the form of a line extending with a width of not less than about 20 μm and a length of not less than about 100 μm. For example, each of the plurality of dummy patterns RL-D may have a length of about 100 μm to about 400 μm. For example, the ratio of the length to the width of each of the plurality of dummy patterns RL-D may be about 5:1 to about 20:1. The plurality of dummy patterns RL-D may be arranged at an interval of not more than about 10. In some embodiments, the ratio of the planar area of the plurality of dummy patterns RL-D to the planar area of the intervals between the plurality of dummy patterns RL-D may be about 3.5:1 to about 4.5:1.

[0049] In Figure 1A , it is exemplarily shown that the plurality of dummy patterns RL-D extend with the same width and the same length. However, the embodiments are not limited thereto. In some embodiments, the ratio of the length to the width of each of the plurality of dummy patterns RL-D is about 5:1 to about 20:1, and the value of the length or width of each of some of the plurality of dummy patterns RL-D may be different from the value of the length or width of each of the other plurality of dummy patterns RL-D. Alternatively, in some embodiments, the ratio of the planar area of the plurality of dummy patterns RL-D to the planar area of the intervals between the plurality of dummy patterns RL-D may be about 3.5:1 to about 4.5:1, and the value of the length or width of each of some of the plurality of dummy patterns RL-D may be different from the value of the length or width of each of the other plurality of dummy patterns RL-D.

[0050] Each of the plurality of pad patterns RL-P may be a two-dimensional square or a two-dimensional rectangle. In some embodiments, the value of the ratio of the planar area of the plurality of pad patterns RL-P to the planar area of the intervals between the plurality of pad patterns RL-P may be the same as the value of the ratio of the planar area of the plurality of dummy patterns RL-D to the planar area of the intervals between the plurality of dummy patterns RL-D. For example, the ratio of the planar area of the plurality of pad patterns RL-P to the planar area of the intervals between the plurality of pad patterns RL-P may be about 3.5:1 to about 4.5:1.

[0051] In some embodiments, in addition to the plurality of pad patterns RL-P and the plurality of dummy patterns RL-D, the plurality of redistribution patterns RL may further include redistribution patterns for transmitting power and / or redistribution patterns for transmitting signals.

[0052] The cover insulating layer 230 may be formed on the second inter-wiring insulating layer 220 and the plurality of redistribution patterns RL. The cover insulating layer 230 may cover the plurality of dummy patterns RL-D of the plurality of redistribution patterns RL.

[0053] The plurality of dummy patterns RL-D may be completely surrounded by the second inter-wiring insulating layer 220 and the cover insulating layer 230, and may be spaced apart from each other and electrically isolated. Additionally, the plurality of dummy patterns RL-D may be completely surrounded by the second inter-wiring insulating layer 220 and the cover insulating layer 230, and may be electrically isolated from other conductive components of the integrated circuit device 1. For example, the upper surface and side surfaces of the plurality of dummy patterns RL-D may be covered by the cover insulating layer 230, and the lower surface of the plurality of dummy patterns RL-D may be covered by the second inter-wiring insulating layer 220. In some embodiments, the upper surface of the plurality of dummy patterns RL-D may be covered by the cover insulating layer 230, and the side surfaces and lower surface of the plurality of dummy patterns RL-D may be covered by the second inter-wiring insulating layer 220.

[0054] The cover insulating layer 230 may not cover some upper surfaces of the plurality of pad patterns RL-P of the plurality of redistribution patterns RL. The plurality of connection terminals 300 may be disposed on some portions of the upper surfaces of the plurality of pad patterns RL-P that are not covered by the cover insulating layer 230 and are exposed. Some lower surfaces of the plurality of pad patterns RL-P may be covered by the second inter-wiring insulating layer 220, and the remaining portions of the lower surfaces of the plurality of pad patterns RL-P that are not covered by the second inter-wiring insulating layer 220 may be respectively connected to the plurality of redistribution via plugs RV. The cover insulating layer 230 may cover the side surfaces of the plurality of pad patterns RL-P. In some embodiments, the side surfaces of the plurality of pad patterns RL-P may be covered by the second inter-wiring insulating layer 220.

[0055] The cover insulating layer 230 may be formed of, for example, photosensitive polyimide (PSPI). In some embodiments, the cover insulating layer 230 may have a multi-layer structure in which at least two insulating layers are stacked. For example, the cover insulating layer 230 may have a multi-layer structure in which a layer formed of nitride and a layer formed of PSPI are stacked.

[0056] Alternatively, in some embodiments, the cover insulating layer 230 may be formed of, for example, an oxide. In some embodiments, the cover insulating layer 230 may be formed of TEOS. The cover insulating layer 230 may have a multilayer structure in which at least two insulating layers are stacked. For example, the cover insulating layer 230 may have a multilayer structure in which a layer formed of a nitride and a layer formed of TEOS are stacked.

[0057] Although the plurality of redistribution patterns RL are formed to be thick in the integrated circuit device 1, since the plurality of redistribution patterns RL arranged two-dimensionally have a uniform density, that is, the ratio of the planar area of the plurality of redistribution patterns RL to the planar area of the intervals between the plurality of redistribution patterns RL is about 3.5:1 to about 4.5:1, the integrated circuit device 1 can be prevented from being bent due to the plurality of redistribution patterns RL. Therefore, the reliability of the integrated circuit device 1 can be increased, and the reliability of the electrical connection between the plurality of connection terminals 300 arranged on the plurality of pad patterns RL-P and an external device can be increased.

[0058] When the plurality of redistribution patterns RL are formed to be thick, since deformation may occur at the planar shape of the plurality of redistribution patterns RL due to grain boundaries between the metal layers forming the plurality of redistribution patterns RL, it may be difficult to detect defects in the plurality of redistribution patterns RL. However, since the plurality of redistribution patterns RL in the integrated circuit device 1 include a plurality of dummy patterns RL-D having a large width and length, the deformation occurring at the planar shape of the plurality of redistribution patterns RL due to grain boundaries can be minimized. Therefore, since defects that may occur in the plurality of redistribution patterns RL can be easily detected, the integrated circuit device 1 without defects can be formed.

[0059] Figure 2A is a plan view showing an integrated circuit device according to an embodiment, Figures 2B to 2C is a cross-sectional view showing an integrated circuit device according to an embodiment. Specifically, Figure 2A is showing Figure 1A an enlarged plan layout view of region IIA of Figure 2B and Figure 2C are cross-sectional views taken along line IIB–IIB’ and line IIC–IIC’ of Figure 2A respectively.

[0060] Referring to Figure 2A , the plurality of redistribution patterns RL may include a plurality of pad patterns RL-P and a plurality of dummy patterns RL-D. As Figure 2C shown, the plurality of redistribution via plugs RV may be respectively connected to the lower surfaces of the plurality of pad patterns RL-P. The plurality of connection terminals 300 may be respectively connected to the upper surfaces of the plurality of pad patterns RL-P. The plurality of pad patterns RL-P may electrically connect the plurality of connection terminals 300 and the plurality of redistribution via plugs RV to each other.

[0061] Each of the plurality of dummy patterns RL-D may be in the form of a line extending in a first horizontal direction (X direction) or a second horizontal direction (Y direction).

[0062] Each of the plurality of dummy patterns RL-D may be in the form of a line extending with a first width WD and a first length LD. For example, the first width WD may have a value of not less than about 20 μm. For example, the first length LD may have a value of about 100 μm to about 400 μm. In some embodiments, the ratio of the first length LD to the first width WD may be about 5:1 to about 20:1.

[0063] The plurality of dummy patterns RL-D may be spaced from each other in a longitudinal direction (i.e., in the X direction in Figure 2A ) by a first longitudinal spacing SDL and in a width direction (i.e., in the Y direction in the example of Figure 2A ) by a first widthwise spacing SDW. Each of the first longitudinal spacing SDL and the first widthwise spacing SDW may have a value not exceeding half (1 / 2) of the first width WD. For example, the first longitudinal spacing SDL may have a value not exceeding about 10 μm. For example, the first widthwise spacing SDW may have a value not exceeding about 10 μm. In some embodiments, the first longitudinal spacing SDL and the first widthwise spacing SDW may have the same value or similar values.

[0064] In some embodiments, the ratio of the planar area of the plurality of dummy patterns RL-D to the planar area of the spaces between the plurality of dummy patterns RL-D may be about 3.5:1 to about 4.5:1. In Figure 2A , as an example, a planar pattern area AD of one of the plurality of dummy patterns RL-D and a planar spacing area AS of the space corresponding on average to one dummy pattern RL-D are shown. The ratio of the pattern area AD to the spacing area AS may be about 3.5:1 to about 4.5:1.

[0065] Each of the plurality of pad patterns RL-P may be a two-dimensional square or a two-dimensional rectangle. The width and height of the square of each of the plurality of pad patterns RL-P and the spacing between the plurality of pad patterns RL-P may be selected according to the width of each of the plurality of connection terminals 300 and the spacing between the plurality of connection terminals 300. The width of each of the plurality of connection terminals 300 and the spacing between the plurality of connection terminals 300 may be selected differently in consideration of the electrical connection between the integrated circuit device 1 ( Figure 1A and Figure 1B ) and an external device.

[0066] For example, as in Figure 2AAs shown, the width and height of the square of each of the plurality of pad patterns RL-P may have the same value as the first width WD. However, the embodiments are not limited thereto. In some embodiments, the values of the width and height of the square of each of the plurality of pad patterns RL-P may be greater than the value of the first width WD. In other embodiments, the values of the width and height of the square of each of the plurality of pad patterns RL-P may be less than the value of the first width WD.

[0067] In some embodiments, the ratio of the planar area of the plurality of pad patterns RL-P to the planar area of the spaces between the plurality of pad patterns RL-P may have the same value as the ratio of the planar area of the plurality of dummy patterns RL-D to the planar area of the spaces between the plurality of dummy patterns RL-D. For example, the ratio of the planar area of the plurality of pad patterns RL-P to the planar area of the spaces between the plurality of pad patterns RL-P may be about 3.5:1 to about 4.5:1.

[0068] Referring to Figure 2B and Figure 2C , each of the plurality of dummy patterns RL-D may be completely surrounded by the second inter-wiring insulating layer 220 and the covering insulating layer 230 to be electrically isolated from the outside and may be electrically floating. Accordingly, the plurality of dummy patterns RL-D may be spaced apart from each other and electrically isolated, and may be electrically isolated from other conductive components of the integrated circuit device 1.

[0069] Each of the uppermost wiring layers ML-T disposed at the uppermost end among the plurality of wiring layers ML may have a first thickness TML1, and each of the remaining wiring layers among the plurality of wiring layers ML other than the uppermost wiring layer ML-T may have a second thickness TML2. For example, the first thickness TML1 may have a value not exceeding about 0.5 μm. For example, the value of the second thickness TML2 may be less than the value of the first thickness TML1. For example, the second thickness TML2 may have a value not exceeding about 0.3 μm. In Figure 2B and Figure 2C , it is shown that the remaining wiring layers among the plurality of wiring layers ML other than the uppermost wiring layer ML-T have the same thickness. However, the embodiments are not limited thereto. For example, among the remaining wiring layers among the plurality of wiring layers ML other than the uppermost wiring layer ML-T, one or more wiring layers ML may have different thicknesses from each other.

[0070] Each of the plurality of redistribution patterns RL may have a third thickness TRL. In some embodiments, the value of the third thickness TRL may not be less than twice the value of the first thickness TML1. For example, the third thickness TRL may be about 1 μm to about 5 μm.

[0071] The covering insulating layer 230 may surround the side surfaces of the dummy pattern RL-D and the pad pattern RL-P. The covering insulating layer 230 may cover the upper surface of the dummy pattern RL-D. The covering insulating layer 230 may cover a part of the upper surface of the pad pattern RL-P and may expose the remaining part, as Figure 2C shown.

[0072] On the exposed part of the upper surface of each of the plurality of pad patterns RL-P that is not covered by the covering insulating layer 230, connection terminals 300 may be arranged, as Figure 2C shown. In some embodiments, the covering insulating layer 230 and the connection terminals 300 may be spaced apart from each other. Between the covering insulating layer 230 and the connection terminals 300, the upper surface of each of the plurality of pad patterns RL-P may be exposed to the outside and not covered by the covering insulating layer 230 and the connection terminals 300.

[0073] The covering insulating layer 230 may include a first covering insulating layer 232 and a second covering insulating layer 234 provided on the first covering insulating layer 232. The first covering insulating layer 232 may conformally cover the upper surface of the second inter-wiring insulating layer 220 and some surfaces of the plurality of redistribution patterns RL (e.g., at least a part of the upper surface and the side surfaces of the redistribution pattern RL). For example, the first covering insulating layer 232 may be formed of a nitride. The second covering insulating layer 234 may cover the first covering insulating layer 232. The second covering insulating layer 234 may be thicker than the first covering insulating layer 232. For example, the second covering insulating layer 234 may be formed of PSPI. Alternatively, in some embodiments, for example, the second covering insulating layer 234 may be formed of an oxide such as TEOS.

[0074] The connection terminal 300 may include a conductive post 310 provided on the pad pattern RL-P and a conductive cap 320 covering the upper surface of the conductive post 310, as Figure 2C shown.

[0075] In some embodiments, the conductive post 310 may include a base post 312 and a covering post 314 formed on the upper surface of the base post 312. The covering post 314 may cover the upper surface of the base post 312. The base post 312 may include, for example, copper (Cu), and the covering post 314 may include at least one of, for example, nickel (Ni), Cu, palladium (Pd), platinum (Pt), and gold (Au). In some embodiments, the covering post 314 may include Ni. In other embodiments, the covering post 314 may have a multi-layer structure including a first layer and a second layer, the first layer including Ni, and the second layer covering the first layer and including Cu.

[0076] The conductive cap 320 may connect the integrated circuit device 1 ( Figure 1A and Figure 1B) is connected to an external device (not shown), and can electrically connect the integrated circuit device 1 and the external device to each other. The conductive cap 32 may include at least one of, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), Cu, silver (Ag), Au, zinc (Zn), and lead (Pb).

[0077] In Figure 2C , a redistribution via plug RV, the uppermost wiring layer ML-T on which the redistribution via plug RV is disposed, and the connection terminal 300 are shown to be aligned in the vertical direction (Z direction). However, the embodiment is not limited thereto. In some embodiments, in the pad pattern RL-P, the portion in contact with the connection terminal 300 and the portion connected to the redistribution via plug RV may be spaced apart from each other in the horizontal direction (X direction, Y direction, or X-Y direction). In this configuration, at least some of the plurality of corresponding connection terminals 300 and the plurality of redistribution via plugs RV may not be aligned in the vertical direction (Z direction). In this configuration, at least some of the plurality of pad patterns RL-P can be used as a redistribution layer for horizontally dispersing the arrangement of the plurality of connection terminals 300 instead of the arrangement of the plurality of uppermost wiring layers ML-T on which the plurality of redistribution via plugs RV are disposed, so as to be used as sub-pads.

[0078] Figure 3 is a plan layout diagram showing an integrated circuit device according to an embodiment. The same reference numerals always refer to the same elements. In Figure 3 's description, for the sake of brevity, the repeated description of the elements previously referred to in Figures 1A to 2C may be omitted.

[0079] Referring to Figure 3 , the integrated circuit device 1a includes a plurality of redistribution patterns RLa. The plurality of redistribution patterns RLa may include a plurality of pad patterns RL-P and a plurality of dummy patterns RL-D.

[0080] The plurality of pad patterns RL-P may be arranged to form at least one column in the horizontal direction (X direction or Y direction). In some embodiments, the plurality of pad patterns RL-P may be horizontally arranged in a matrix. The plurality of connection terminals 300 may be respectively connected to the plurality of pad patterns RL-P.

[0081] Each of the plurality of dummy patterns RL-D may be in the form of a line extending in the first horizontal direction (X direction) or the second horizontal direction (Y direction). The plurality of dummy patterns RL-D may be in the form of lines extending in different directions. For example, as Figure 3As shown, some of the plurality of dummy patterns RL-D may be in the form of lines extending in a first horizontal direction (X direction), and other dummy patterns RL-D among the plurality of dummy patterns RL-D may be in the form of lines extending in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction).

[0082] Each of the plurality of dummy patterns RL-D may be in the form of a line extending with a width of not less than about 20 μm and a length of about 100 μm to about 400 μm. For example, the ratio of the length to the width of each of the plurality of dummy patterns RL-D may be about 5:1 to about 20:1. The plurality of dummy patterns RL-D may be arranged at an interval of not more than about 10. In some embodiments, the ratio of the planar area of the plurality of dummy patterns RL-D to the planar area of the interval between the plurality of dummy patterns RL-D may be about 3.5:1 to about 4.5:1.

[0083] Among the plurality of dummy patterns RL-D, some dummy patterns RL-D extending in the first horizontal direction (X direction) and other dummy patterns RL-D extending in the second horizontal direction (Y direction) may have the same width and length. However, the embodiments are not limited thereto. In some embodiments, the ratio of the length to the width of each of the plurality of dummy patterns RL-D is about 5:1 to about 20:1, and the value of the length or width of each of some dummy patterns RL-D extending on the pad in the first horizontal direction (X direction) may be different from the value of the length or width of each of the other dummy patterns RL-D extending in the second horizontal direction (Y direction). Alternatively, in some embodiments, although the ratio of the length to the width of each of the plurality of dummy patterns RL-D extending in the same direction is about 5:1 to about 20:1, each of the plurality of dummy patterns RL-D may have different lengths and / or widths.

[0084] Figure 4 is a plan layout diagram showing an integrated circuit device according to an embodiment. Figure 5A and Figure 5B are respectively a plan layout diagram and a cross-sectional view showing an integrated circuit device according to an embodiment of Figure 4 . Specifically, Figure 5A is an enlarged plan layout diagram showing a region VA of Figure 4 , Figure 5B is a cross-sectional view taken along a line VB–VB’ of Figure 5A . The same reference numerals always refer to the same elements. For the sake of brevity, the description given previously with reference to Figures 1A to 3 may be omitted. Figures 4 to 5B

[0085] Refer to Figure 4, the integrated circuit device 2 includes a plurality of redistribution patterns RLa. The plurality of redistribution patterns RLa may include a plurality of pad patterns RL-P, a plurality of power patterns RL-W, and a plurality of dummy patterns RL-D.

[0086] The plurality of pad patterns RL-P may be arranged in at least one column in a horizontal direction (the X direction or the Y direction). In some embodiments, the plurality of pad patterns RL-P may be horizontally arranged in a matrix. The plurality of connection terminals 300 may be respectively connected to the plurality of pad patterns RL-P.

[0087] Each of the plurality of dummy patterns RL-D may be in the form of a line extending in a first horizontal direction (the X direction) or a second horizontal direction (the Y direction). In some embodiments, the plurality of dummy patterns RL-D may be in the form of lines extending in different directions.

[0088] Each of the plurality of dummy patterns RL-D may be in the form of a line extending with a width of not less than about 20 μm and a length of about 100 μm to about 400 μm. For example, the ratio of the length to the width of each of the plurality of dummy patterns RL-D may be about 5:1 to about 20:1. The plurality of dummy patterns RL-D may be arranged at an interval of not more than about 10. In some embodiments, the ratio of the planar area of the plurality of dummy patterns RL-D to the planar area of the intervals between the plurality of dummy patterns RL-D may be about 3.5:1 to about 4.5:1.

[0089] In Figure 4 , it is shown that the plurality of dummy patterns RL-D extend with the same width and length. However, the embodiments are not limited thereto. In some embodiments, the ratio of the length to the width of each of the plurality of dummy patterns RL-D may be about 5:1 to about 20:1, and the value of the length or width of each of some of the plurality of dummy patterns RL-D may be different from the value of the length or width of each of the other plurality of dummy patterns RL-D. Alternatively, in some embodiments, the ratio of the planar area of the plurality of dummy patterns RL-D to the planar area of the intervals between the plurality of dummy patterns RL-D may be about 3.5:1 to about 4.5:1, and the value of the length or width of each of some of the plurality of dummy patterns RL-D may be different from the value of the length or width of each of the other plurality of dummy patterns RL-D.

[0090] In some embodiments, the ratio of the planar area of the plurality of pad patterns RL-P to the planar area of the spaces between the plurality of pad patterns RL-P may be the same as the ratio of the planar area of the plurality of dummy patterns RL-D to the planar area of the spaces between the plurality of dummy patterns RL-D. For example, the ratio of the planar area of the plurality of pad patterns RL-P to the planar area of the spaces between the plurality of pad patterns RL-P may be from about 3.5:1 to about 4.5:1.

[0091] Each of the plurality of power patterns RL-W may be in the form of a line linearly extending in a first horizontal direction (X direction) or a second horizontal direction (Y direction), or may be in the form of a line extending in both the first horizontal direction (X direction) and the second horizontal direction (Y direction). The power pattern RL-W in the form of a line extending in both the first horizontal direction (X direction) and the second horizontal direction (Y direction) may be said to be bent. In Figure 4 , exemplarily shown are a plurality of power patterns RL-W extending in the second horizontal direction (Y direction) and then extending in the first horizontal direction (X direction) and being bent once. However, the embodiments are not limited thereto. For example, some of the plurality of power patterns RL-W may be in the form of lines extending in the first horizontal direction (X direction). Alternatively, in some embodiments, for example, other power patterns RL-W among the plurality of power patterns RL-W may be in the form of lines having a bend of not less than two times and having portions extending in both the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0092] Each of the plurality of pad patterns RL-P may be electrically connected to a redistribution via plug RV and a connection terminal 300. The plurality of dummy patterns RL-D may not be connected to the redistribution via plug RV and the connection terminal 300 and may be electrically isolated from the redistribution via plug RV and the connection terminal 300. Each of the plurality of power patterns RL-W may be electrically connected to at least two redistribution via plugs RV.

[0093] Referring to Figure 4 and Figure 5A , a part of the plurality of dummy patterns RL-D may be in the form of a line extending with a first width WD and a first length LD. For example, the first width WD may have a value of not less than about 20 μm. For example, the first length LD may have a value from about 100 μm to about 400 μm. In some embodiments, the ratio of the first length LD to the first width WD may be from about 5:1 to about 20:1. Another part of the plurality of dummy patterns RL-D may be in the form of a line extending with the first width WD and a length LD1 shorter than the first length LD. For example, the length LD1 may be shorter than the first length LD by the width WW of the power pattern RL-W and the space SWW (to be further described below).

[0094] Multiple dummy patterns RL-D may be spaced apart from each other in the longitudinal direction by a first longitudinal spacing SDL and in the width direction by a first width spacing SDW. For example, the first longitudinal spacing SDL may have a value of no more than about 10 μm. For example, the first width spacing SDW may have a value of no more than about 10. In some embodiments, the first longitudinal spacing SDL and the first width spacing SDW may have the same value or similar values.

[0095] In some embodiments, the ratio of the planar area of the multiple dummy patterns RL-D to the planar area of the spacing between the multiple dummy patterns RL-D may be from about 3.5:1 to about 4.5:1.

[0096] Each of the multiple power patterns RL-W may be in the form of a line linearly extending with a second width WW and a second length LW or extending by bending with a second width WW and a second length LW. For example, the second width WW may have a value of no less than about 20 μm. For example, the second length LW may have a value of about 100 to about 400. In some embodiments, the ratio of the second length LW to the second width WW may be from about 5:1 to about 20:1.

[0097] The multiple power patterns RL-W may be spaced apart from the dummy patterns RL-D in the longitudinal direction by a second longitudinal spacing SWL and in the width direction by a second width spacing SWW. For example, the second longitudinal spacing SWL may have a value of no more than about 10 μm. For example, the second width spacing SWW may have a value of no more than about 10. In some embodiments, the second longitudinal spacing SWL and the second width spacing SWW may have the same value or similar values.

[0098] In some embodiments, the value of the ratio of the planar area of the multiple power patterns RL-W to the planar area of the spacing between the multiple power patterns RL-W may be the same as the value of the ratio of the planar area of the multiple dummy patterns RL-D to the planar area of the spacing between the multiple dummy patterns RL-D. In some embodiments, the ratio of the planar area of the multiple power patterns RL-W to the planar area of the spacing between the multiple power patterns RL-W may be from about 3.5:1 to about 4.5:1.

[0099] In some embodiments, the ratio of the length to the width of each of the plurality of power patterns RL-W may be from about 5:1 to about 20:1, and the value of the length or width of each of some of the power patterns RL-W among the plurality of power patterns RL-W may be different from the value of the length or width of each of the other power patterns RL-W among the plurality of power patterns RL-W. Alternatively, in some embodiments, the ratio of the planar area of the plurality of power patterns RL-W to the planar area of the spacing between the plurality of power patterns RL-W may be from about 3.5:1 to about 4.5:1, and the value of the length or width of each of some of the power patterns RL-W among the plurality of power patterns RL-W may be different from the value of the length or width of each of the other power patterns RL-W among the plurality of power patterns RL-W.

[0100] Each of the plurality of power patterns RL-W may be electrically connected to at least two redistribution via plugs RV. At least two redistribution via plugs RV may be connected to the lower surface of each of the plurality of power patterns RL-W. Each of the plurality of power patterns RL-W may be electrically connected to a power-supplied connection terminal 300 among the plurality of connection terminals 300 through a wiring structure MS and a via plug RV. For example, the power-supplied connection terminal 300 among the plurality of connection terminals 300 may be electrically connected to the power pattern RL-W through a pad pattern RL-P, a via plug RV, the topmost wiring layer ML-T, and another via plug RV. One power pattern RL-W is electrically connected to at least two redistribution via plugs RV and may transmit the power supplied to the connection terminal 300 to the integrated circuit device 2.

[0101] In some embodiments, one power pattern RL-W may be connected to another via plug RV, and the other via plug RV is connected to a topmost wiring layer ML-T connected through a pad pattern RL-P, one via plug RV, and at least two other via plugs RV. Therefore, one power pattern RL-W may be electrically connected to a portion of the topmost wiring layer ML-T through at least two other via plugs RV, and the topmost wiring layer ML-T is two-dimensionally positioned in another portion of the integrated circuit device 2.

[0102] As Figure 5B shown, the upper surface and the side surfaces of each of the plurality of power patterns RL-W may be completely covered by an insulating layer 230. In the lower surface of each of the plurality of power patterns RL-W, the portion not connected to at least two via plugs RV may be covered by a second inter-wiring insulating layer 220.

[0103] For example, when the plurality of pad patterns RL-P on which the plurality of connection terminals 300 are arranged are as Figure 4When the central pads are two-dimensionally arranged in the center of the integrated circuit device 2 or the edge pads are two-dimensionally arranged adjacent to the edge of the integrated circuit device 2, power loss may occur while the power supplied through some of the plurality of connection terminals 300 is two-dimensionally transmitted to a portion of the integrated circuit device 2 spaced apart from the plurality of pad patterns RL-P or is two-dimensionally transmitted to other portions of the integrated circuit device 2 through one power pattern RL-W. However, power can be transmitted to the integrated circuit device 2 according to various embodiments through the power pattern RL-W of the redistribution pattern RL having a relatively large thickness and width, thereby minimizing power loss. Therefore, since power is transmitted to the integrated circuit device 2 with minimized power loss, high-speed operation of the integrated circuit device 2 can be achieved.

[0104] Although a plurality of redistribution patterns RLa including a plurality of power patterns RL-W are formed to be relatively thick in the integrated circuit device 2 according to various embodiments to facilitate minimizing power loss for achieving high-speed operation, since the plurality of two-dimensionally arranged redistribution patterns RLa have a uniform density, that is, the ratio of the planar area of the plurality of redistribution patterns RLa to the planar area of the spaces between the plurality of redistribution patterns RLa is about 3.5:1 to about 4.5:1, the integrated circuit device 2 can be prevented from being bent due to the plurality of redistribution patterns RLa. Therefore, the reliability of the integrated circuit device 2 can be increased, and the reliability of the electrical connection between the plurality of connection terminals 300 arranged on the plurality of pad patterns RL-P and an external device can be increased.

[0105] When the plurality of redistribution patterns RLa are formed to be relatively thick, since deformation may occur at the planar shape of the plurality of redistribution patterns RLa due to grain boundaries between the metal layers forming the plurality of redistribution patterns RL, it may be difficult to detect defects in the plurality of redistribution patterns RLa. However, since the plurality of redistribution patterns RLa in the integrated circuit device 2 according to various embodiments include a plurality of dummy patterns RL-D and a plurality of power patterns RL-W having relatively large widths and lengths, deformation occurring at the planar shape of the plurality of redistribution patterns RLa due to grain boundaries can be minimized. Therefore, since defects that may occur in the plurality of redistribution patterns RLa can be easily detected, the integrated circuit device 2 without defects can be formed.

[0106] Figure 6 is a plan layout diagram showing an integrated circuit device according to an embodiment. Figure 7A and Figure 7B are respectively a plan layout diagram and a cross-sectional view showing an integrated circuit device according to an embodiment. Specifically, Figure 7A is a diagram showing Figure 6 an enlarged plan layout of part VIIA of Figure 7B is along Figure 7ACross-sectional view taken along line VIIB–VIIB’. The same reference numerals always refer to the same elements. For the sake of brevity, descriptions previously referred to Figures 1A to 5B given Figures 6 to 7B are omitted.

[0107] Referring to Figure 6 , the integrated circuit device 3 includes a plurality of redistribution patterns RLb. The plurality of redistribution patterns RLb may include a plurality of pad patterns RL-P, at least one power pattern RL-W, a plurality of signal patterns RL-S, and a plurality of dummy patterns RL-D.

[0108] The plurality of pad patterns RL-P may be arranged in at least one column in the horizontal direction (X direction or Y direction). The plurality of connection terminals 300 may be respectively connected to the plurality of pad patterns RL-P. Each of the plurality of dummy patterns RL-D may be in the form of a line extending in the first horizontal direction (X direction) or the second horizontal direction (Y direction). Each of the plurality of power patterns RL-W may be in the form of a line linearly extending in the first horizontal direction (X direction) or the second horizontal direction (Y direction), or may be in the form of a line extending in a bent manner.

[0109] In some embodiments, the ratio of the planar area of the plurality of pad patterns RL-P to the planar area of the spaces between the plurality of pad patterns RL-P, the ratio of the planar area of the plurality of dummy patterns RL-D to the planar area of the spaces between the plurality of dummy patterns RL-D, and the ratio of the planar area of the plurality of power patterns RL-W to the planar area of the spaces between the plurality of power patterns RL-W may have the same value.

[0110] Each of the plurality of signal patterns RL-S may be in the form of a line linearly extending in the first horizontal direction (X direction) or the second horizontal direction (Y direction), or may be in the form of a line extending in a bent manner. In Figure 6 , the plurality of signal patterns RL-S are exemplarily shown to be in the form of lines extending in the first horizontal direction (X direction). However, the embodiments are not limited thereto. For example, in some embodiments, a part of the plurality of signal patterns RL-S may be in the form of lines extending in the second horizontal direction (Y direction). Alternatively, in some embodiments, for example, a part of the plurality of signal patterns RL-S may be in the form of lines having at least one bend and extending in the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0111] One end of each of the plurality of signal patterns RL-S (e.g., Figures 7A to 7B the inner end in the example shown) may be connected to a redistribution via plug RV, and the other end of each of the plurality of signal patterns RL-S (e.g., Figures 7A to 7BThe outer end in the illustrated example) can be connected to the pad pattern RL-P. The redistribution via plug RV can be connected to the lower surface of one end of each of the plurality of signal patterns RL-S. The connection terminal 300 can be arranged on the pad pattern RL-P connected to the other end of each of the plurality of signal patterns RL-S.

[0112] Among the plurality of pad patterns RL-P, the redistribution via plug RV may not be connected to the lower surface of the pad pattern RL-P connected to the other end of one of the plurality of signal patterns RL-S. Among the plurality of pad patterns RL-P, the redistribution via plug RV can be connected to the lower surface of the pad pattern RL-P not connected to one of the plurality of signal patterns RL-S.

[0113] Each of the plurality of signal patterns RL-S can be in the form of a line linearly extending or bent and extending with a third width WS and a third length LS. For example, the value of the third width WS can be less than the values of the first width WD and the second width WW. For example, the third length LS can have a value of about 100 to about 400. In some embodiments, the value of the ratio of the third length LS to the third width WS can be greater than the value of the ratio of the first length LD to the first width WD.

[0114] The plurality of signal patterns RL-S can be spaced apart from other patterns by a third longitudinal direction interval SSL and a third width direction interval SSW. More specifically, the plurality of signal patterns RL-S can be spaced apart from the plurality of pad patterns RL-P, the plurality of dummy patterns RL-D, or other signal patterns RL-S by the third longitudinal direction interval SSL and by the third width direction interval SSW. For example, the third longitudinal direction interval SSL can be the same as or greater than the first longitudinal direction interval ( Figure 2A or Figure 5A SDL) of. For example, the value of the third width direction interval SSW can be greater than the values of the first width direction interval SDW and the second width direction interval SWW.

[0115] In some embodiments, the value of the ratio of the planar area of the plurality of signal patterns RL-S to the planar area of the intervals between the plurality of signal patterns RL-S can be different from the value of the ratio of the planar area of the plurality of dummy patterns RL-D to the planar area of the intervals between the plurality of dummy patterns RL-D. For example, the value of the ratio of the planar area of the plurality of signal patterns RL-S to the planar area of the intervals between the plurality of signal patterns RL-S can be greater than the value of the ratio of the planar area of the plurality of dummy patterns RL-D to the planar area of the intervals between the plurality of dummy patterns RL-D.

[0116] Figure 8 is a flowchart showing a method of manufacturing an integrated circuit device according to an embodiment. Specifically, Figure 8 is shown in FIGS. 1 to Figure 7BFlowcharts of manufacturing methods of the integrated circuit devices 1, 1a, 2, and 3 described. For simplicity, the descriptions previously referred to Figures 1A to 7B given Figure 8 may be omitted. The description will be made with reference to Figures 1A to 7B described Figure 8 .

[0117] Referring to Figure 8 , in operation S100, semiconductor devices are formed on the substrate 110. For example, a device layer 130 including a plurality of semiconductor devices 120 is formed on the substrate 110. The substrate 110 may include, for example, silicon (Si). Alternatively, in some embodiments, the substrate 110 may include a semiconductor element such as Ge or a compound semiconductor such as SiC, GaAs, InAs, or InP.

[0118] At least some of the plurality of semiconductor devices 120 may be transistors. In some embodiments, the plurality of semiconductor devices 120 may be various types of individual devices for forming a DRAM device, an SRAM device, a flash memory device, an EEPROM device, a PRAM device, an MRAM device, or an RRAM device. For example, the plurality of semiconductor devices 120 may be various types of individual devices for forming a high bandwidth memory (HBM) DRAM device, and the integrated circuit devices 1, 1a, 2, and 3 may be HBM DRAM devices.

[0119] In other embodiments, the plurality of semiconductor devices 120 may form logic units. For example, the integrated circuit devices 1, 1a, 2, and 3 may be a CPU, a GPU, or an AP.

[0120] In operation S200, a wiring structure is formed. For example, a wiring structure MS and a first inter-wiring insulating layer 210 surrounding the wiring structure MS are formed on the substrate 110 on which the device layer 130 is formed. The wiring structure MS may include a plurality of wiring layers ML and a plurality of via plugs MV connected to the plurality of wiring layers ML.

[0121] In some embodiments, each uppermost wiring layer ML-T disposed at the uppermost end among the plurality of wiring layers ML may have a first thickness TML1, and each remaining wiring layer ML may have a second thickness TML2, and the value of the second thickness TML2 is less than the value of the first thickness TML1. For example, the first thickness TML1 may have a value not exceeding about 0.5 μm. For example, the value of the second thickness TML2 may be less than the value of the first thickness TML1, that is, not exceeding about 0.3 μm.

[0122] In operation S300, a redistribution pattern is formed. For example, a second inter-wiring insulating layer 220 and redistribution via plugs RV connected to the wiring structure MS through the second inter-wiring insulating layer 220 may be formed on the wiring structure MS and the first inter-wiring insulating layer 210, and a plurality of redistribution patterns RL, RLa, and RLb may be formed on the second inter-wiring insulating layer 220 and the redistribution via plugs RV.

[0123] The plurality of redistribution patterns RL, RLa, and RLb may have a third thickness TRL. The value of the third thickness TRL may not be less than twice the value of the first thickness TML1. For example, the third thickness TRL may be from about 1 μm to about 5 μm.

[0124] In some embodiments, the plurality of redistribution patterns RL may include a plurality of pad patterns RL-P and a plurality of dummy patterns RL-D. In some embodiments, the plurality of redistribution patterns RLa may include a plurality of pad patterns RL-P, a plurality of power patterns RL-W, and a plurality of dummy patterns RL-D. In other embodiments, the plurality of redistribution patterns RLb may include a plurality of pad patterns RL-P, at least one power pattern RL-W, a plurality of signal patterns RL-S, and a plurality of dummy patterns RL-D.

[0125] After forming the plurality of redistribution patterns RL, RLa, and RLb, an automatic visual inspection (AVI) may be performed in operation S400. For example, an automatic visual inspection (AVI) may be performed on the plurality of redistribution patterns RL, RLa, and RLb.

[0126] When the plurality of redistribution patterns RL, RLa, and RLb are formed to have a relatively large third thickness TRL, it may be difficult to detect defects in the plurality of redistribution patterns RL, RLa, and RLb because deformation may occur at the planar shape of the plurality of redistribution patterns RL, RLa, and RLb due to grain boundaries between the metal layers forming the plurality of redistribution patterns RL, RLa, and RLb.

[0127] However, since the plurality of redistribution patterns RL, RLa, and RLb according to the embodiments disclosed herein include a plurality of dummy patterns RL-D and a plurality of power patterns RL-W having widths and lengths greater than those of the plurality of pad patterns RL-P or the plurality of signal patterns RL-S, deformation occurring due to grain boundaries at the planar shapes of the plurality of redistribution patterns RL, RLa, and RLb can be minimized. Accordingly, defects that may occur in the plurality of redistribution patterns RL, RLa, and RLb can be easily detected. Accordingly, although defects are not directly detected in the plurality of pad patterns RL-P or the plurality of signal patterns RL-S having smaller widths and lengths, since the defects can be detected by the plurality of dummy patterns RL-D and / or the plurality of power patterns RL-W having larger widths and lengths, defects in the plurality of redistribution patterns RL, RLa, and RLb can be determined.

[0128] Accordingly, integrated circuit devices 1, 1a, 2, and 3 can be formed without defects and having improved reliability.

[0129] Although the inventive concept has been specifically shown and described with reference to various embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: A wiring structure on a substrate and a first inter-wiring insulating layer configured to surround the wiring structure, the wiring structure including a plurality of wiring layers having a multi-layer wiring structure and a plurality of via plugs; A second inter-wiring insulating layer and a plurality of redistribution via plugs on the first inter-wiring insulating layer, the plurality of redistribution via plugs passing through the second inter-wiring insulating layer and connecting to the wiring structure; A plurality of redistribution patterns on the second inter-wiring insulating layer, the plurality of redistribution patterns including a plurality of pad patterns and a plurality of dummy patterns, the thickness of each of the plurality of pad patterns and each of the plurality of dummy patterns being greater than the thickness of each of the plurality of wiring layers; And A covering insulating layer configured to cover a part of the plurality of redistribution patterns, Wherein, the plurality of dummy patterns extend linearly in a horizontal direction parallel to the substrate and are completely surrounded by the second inter-wiring insulating layer and the covering insulating layer to be electrically isolated from each other, Wherein, the plurality of dummy patterns are spaced apart from each other at a first longitudinal interval in a longitudinal direction and at a first width interval in a width direction, Wherein, each of the plurality of dummy patterns has a first width and a first length and extends in the horizontal direction, and Wherein, each of the first longitudinal interval and the first width interval has a value not exceeding 1 / 2 of the first width.

2. The integrated circuit device according to claim 1, wherein, The plurality of redistribution patterns further include a plurality of power patterns, the plurality of power patterns each linearly extending and having a second width and a second length, and Wherein, the lower surface of each of the plurality of power patterns is connected to at least two of the plurality of redistribution via plugs, and the upper surface and side surfaces of each of the plurality of power patterns are covered by the covering insulating layer.

3. The integrated circuit device according to claim 2, wherein, Each of the ratio of the first length to the first width and the ratio of the second length to the second width is from 5:1 to 20:

1.

4. The integrated circuit device according to claim 2, wherein, Each of the first length and the second length has a value not less than 100 μm, and each of the first width and the second width has a value not less than 20 μm.

5. The integrated circuit device according to claim 2, wherein, Each of the first longitudinal interval and the first width interval has a value not exceeding 10 μm.

6. The integrated circuit device according to claim 2, wherein, One of the plurality of power patterns is electrically connected to one of a plurality of connection terminals through one of the plurality of redistribution via plugs, one of the plurality of wiring layers, another of the plurality of redistribution via plugs, and one of the plurality of pad patterns.

7. The integrated circuit device according to claim 1, wherein, The value of the thickness of each of the plurality of redistribution patterns is not less than twice the value of the thickness of each of the plurality of wiring layers.

8. The integrated circuit device according to claim 7, wherein, Each of the plurality of redistribution patterns has a thickness with a value of not less than 1 μm, and the uppermost wiring layer disposed at the uppermost end among the plurality of wiring layers has a thickness with a value of not more than 0.5 μm.

9. The integrated circuit device according to claim 1, wherein, The ratio of the planar area of the plurality of redistribution patterns to the planar area of the intervals between the plurality of redistribution patterns is from 3.5:1 to 4.5:

1.

10. An integrated circuit device, comprising: A wiring structure on a substrate and a first inter-wiring insulating layer configured to surround the wiring structure, the wiring structure including a plurality of wiring layers having a multi-layer wiring structure and a plurality of via plugs; A second inter-wiring insulating layer and a plurality of redistribution via plugs on the first inter-wiring insulating layer, the plurality of redistribution via plugs passing through the second inter-wiring insulating layer and connecting to the wiring structure; A plurality of redistribution patterns on the second inter-wiring insulating layer, which include a plurality of pad patterns, a plurality of dummy patterns, and a plurality of power patterns, and the thickness of each of the plurality of pad patterns, the plurality of dummy patterns, and the plurality of power patterns is not less than twice the thickness of each of the plurality of wiring layers; A covering insulating layer configured to cover the plurality of dummy patterns and the plurality of power patterns and not cover at least a part of the plurality of pad patterns; And A plurality of connection terminals respectively connected to the plurality of pad patterns, wherein the plurality of dummy patterns extend linearly in a horizontal direction parallel to the substrate and are completely surrounded by the second inter-wiring insulating layer and the covering insulating layer to be electrically isolated from each other, wherein the plurality of dummy patterns are spaced apart from each other at a first longitudinal direction interval in a longitudinal direction and at a first width direction interval in a width direction, wherein each of the plurality of dummy patterns has a first width and a first length and extends in the horizontal direction, and wherein each of the first longitudinal direction interval and the first width direction interval has a value not exceeding 1 / 2 of the first width.

11. The integrated circuit device according to claim 10, wherein, The ratio of the planar area of the plurality of redistribution patterns to the planar area of the intervals between the plurality of redistribution patterns is from 3.5:1 to 4.5:

1.

12. The integrated circuit device according to claim 10, wherein, A part of the lower surface of each of the plurality of power patterns is covered by the second inter-wiring insulating layer, and at least two of the plurality of redistribution via plugs are connected to the remaining part not covered by the second inter-wiring insulating layer, and wherein the upper surface and side surfaces of each of the plurality of power patterns are covered by the covering insulating layer.

13. The integrated circuit device according to claim 12, wherein, The ratio of the first length to the first width is from 5:1 to 20:

1.

14. An integrated circuit device, comprising: A device layer on a substrate, which includes a plurality of semiconductor devices; A wiring structure on the device layer, which includes a plurality of wiring layers and a plurality of via plugs, and the plurality of wiring layers have a multi-layer wiring structure including an uppermost wiring layer; The first inter-wiring insulating layer on the device layer, which is configured to surround the wiring structure; The second inter-wiring insulating layer on the first inter-wiring insulating layer and the wiring structure; A plurality of redistribution via plugs, the plurality of redistribution via plugs passing through the second inter-wiring insulating layer and connecting to the topmost wiring layer; A plurality of redistribution patterns, the plurality of redistribution patterns including a plurality of pad patterns, a plurality of dummy patterns, and a plurality of power patterns, each of the plurality of pad patterns being connected to one of the plurality of redistribution via plugs on the second inter-wiring insulating layer, each of the plurality of dummy patterns extending linearly in a horizontal direction parallel to the substrate, and each of the plurality of power patterns being connected to at least two of the plurality of redistribution via plugs and having a thickness not less than twice the thickness of the topmost wiring layer; A covering insulating layer, which is configured to cover the plurality of dummy patterns and the plurality of power patterns; And A plurality of connection terminals, the plurality of connection terminals being respectively connected to the plurality of pad patterns, each of the plurality of connection terminals including a conductive post and a conductive cap configured to cover an upper surface of the conductive post, wherein the plurality of dummy patterns are completely surrounded by the second inter-wiring insulating layer and the covering insulating layer and are electrically isolated from each other, wherein the plurality of dummy patterns are spaced apart from each other at a first longitudinal interval in a longitudinal direction and at a first width interval in a width direction, wherein each of the plurality of dummy patterns has a width and a length and extends in the horizontal direction, wherein each of the first longitudinal interval and the first width interval has a value not exceeding 1 / 2 of the width, and wherein, among an upper surface, a side surface, and a lower surface of each of the plurality of power patterns, a portion not connected to the at least two redistribution via plugs is covered by the second inter-wiring insulating layer and the covering insulating layer.

15. The integrated circuit device according to claim 14, wherein, each of a ratio of a planar area of the plurality of dummy patterns to a planar area of an interval between the plurality of dummy patterns and a ratio of a planar area of the plurality of power patterns to a planar area of an interval between the plurality of power patterns is 3.5:1 to 4.5:

1.

16. The integrated circuit device according to claim 14, wherein, a ratio of a length to a width of each of the plurality of dummy patterns is 5:1 to 20:

1.

17. The integrated circuit device according to claim 14, wherein, each of the plurality of dummy patterns extends with a width of not less than 20 μm and a length of 100 μm to 400 μm.

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