Display devices

Abstract

A display device includes a first substrate including a transmissive region, a display region surrounding at least a portion of the transmissive region, and a first non-display region between the transmissive region and the display region; an insulating layer in the display region and the first non-display region; a plurality of display elements in the display region; a spacer over the insulating layer in the first non-display region and surrounding the transmissive region; and a second substrate facing the first substrate.

Description

Technical Field

[0001] Aspects of one or more example embodiments relate to a display apparatus. Background Art

[0002] Recently, various uses of display devices have been diversified. In addition, the thickness and weight of display devices have been reduced overall, resulting in a wider range of potential uses of display devices.

[0003] By increasing the size of the display area of ​​a display device, various functions to be combined with or connected to the display device can be added. As a way of adding various functions by increasing the area, research is underway on display devices having an area in the display area for adding various functions (not for displaying images).

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the Invention

[0005] Aspects of one or more example embodiments relate to a display device, for example, to a display device including a transmissive area.

[0006] Aspects of one or more embodiments include a high-quality display device having a transmissive region through which light can be transmitted, the transmissive region serving as a region within the display region for adding various functions. However, these features are merely examples, and the scope of the embodiments of the present disclosure is not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented disclosed example embodiments.

[0008] According to one or more example embodiments, a display device includes: a first substrate including a transmissive area, a display area surrounding at least a portion of the transmissive area, and a first non-display area located between the transmissive area and the display area; an insulating layer located in the display area and the first non-display area; a plurality of display elements located in the display area; a spacer located above the insulating layer in the first non-display area and surrounding the transmissive area; and a second substrate facing the first substrate.

[0009] According to some example embodiments, the insulating layer may include at least one inorganic insulating layer and at least one organic insulating layer.

[0010] According to some example embodiments, each of the plurality of display elements may include a first electrode, a second electrode facing the first electrode, and an emission layer located between the first electrode and the second electrode, and the at least one organic insulating layer may include a pixel defining layer located between the first electrodes of the display elements.

[0011] According to some example embodiments, a spacer may be disposed over the pixel defining layer in the first non-display area.

[0012] According to some example embodiments, the second electrode may cover the pixel defining layer and the spacer.

[0013] According to some example embodiments, the spacer may include a plurality of ring-shaped second spacers surrounding the transmission area and spaced apart from each other.

[0014] According to some example embodiments, each of the plurality of ring-shaped second spacers may include a lower layer and an upper layer, and the lower layer may be a portion of the insulating layer located in the first non-display area.

[0015] According to some example embodiments, the display device may further include a sealant bonding the first substrate and the second substrate together and disposed in the second non-display area surrounding the display area.

[0016] According to some example embodiments, the display device may further include a signal line bent along an edge of the transmission area and arranged in the first non-display area.

[0017] According to some example embodiments, the spacer may overlap the signal line.

[0018] According to some example embodiments, the spacer may include an organic insulating material.

[0019] According to some example embodiments, the display apparatus may further include a transparent layer disposed in the transmission area.

[0020] According to some example embodiments, a display device includes a first substrate; an insulating layer on the first substrate and having a through hole; a spacer over the insulating layer and surrounding the through hole along an edge of the through hole; and a second substrate facing the first substrate.

[0021] According to some example embodiments, the insulating layer may include at least one inorganic insulating layer and at least one organic insulating layer, and the spacer may be disposed over the at least one organic insulating layer.

[0022] According to some example embodiments, the spacer may include an organic insulating material.

[0023] According to some example embodiments, the spacer may include a plurality of second spacers surrounding the through hole and spaced apart from each other.

[0024] According to some example embodiments, each of the plurality of second spacers may include a lower layer and an upper layer, and the lower layer may be a portion of the insulating layer.

[0025] According to some example embodiments, the display device may further include a transparent layer in the through hole of the insulating layer.

[0026] According to some example embodiments, the display device may further include a plurality of display elements adjacent to the through-hole, and the spacer may be disposed between the display elements and the through-hole and may have a ring shape and may surround the through-hole.

[0027] According to some example embodiments, each of the multiple display elements may include a first electrode, a second electrode facing the first electrode, and an emission layer located between the first electrode and the second electrode, and the insulating layer may include a pixel defining layer arranged between the first electrodes of the display elements, and the spacer may be arranged on the pixel defining layer adjacent to the through hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects, features and characteristics according to certain embodiments of the present disclosure will become more apparent through the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1A and Figure 1B is a perspective view schematically illustrating a display device according to some example embodiments;

[0030] Figure 2A and Figure 2B is a cross-sectional view schematically illustrating a display device according to some example embodiments;

[0031] Figure 3A is a plan view schematically illustrating a display panel according to some example embodiments, Figure 3B It is along Figure 3A a cross-sectional view of the display panel taken along line II-II';

[0032] Figure 4 is a plan view schematically illustrating a display panel according to some example embodiments, Figure 5 It is schematically shown Figure 4 An equivalent circuit diagram of a pixel of a display panel;

[0033] Figure 6A and Figure 6B is a plan view illustrating a portion of a display panel according to some example embodiments;

[0034] Figure 7 is a cross-sectional view of one pixel of a display panel according to some example embodiments;

[0035] Figure 8 is a view schematically illustrating a portion of a display panel according to some example embodiments, Figures 9 to 13 It is along Figure 8 a cross-sectional view of the display panel taken along line IV-IV';

[0036] Figure 14 is a view schematically illustrating a portion of a display panel according to some example embodiments, Figures 15 to 19 It is along Figure 14 a cross-sectional view of the display panel taken along line V-V'; and

[0037] Figure 20 is a view schematically illustrating a portion of a display panel according to some example embodiments, Figure 21 It is along Figure 20 1 is a cross-sectional view of the display panel taken along line VII-VII'. DETAILED DESCRIPTION

[0038] Reference will now be made in more detail to aspects of embodiments according to the present disclosure, examples of which are shown in the accompanying drawings, wherein like reference numerals always represent like elements. In this regard, this example embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, example embodiments will be described below only by reference to the accompanying drawings to explain aspects of this specification. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0039] It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms.

[0040] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0041] It will also be understood that the terms “comprises” and / or “comprising” as used herein indicate the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0042] It will be understood that when a layer, region, or element is referred to as being “formed on” another layer, region, or element, it can be directly or indirectly formed on the other layer, region, or element. That is, for example, intervening layers, regions, or elements may be present.

[0043] For the convenience of explanation, the size of the elements in the drawings may be exaggerated or reduced. In other words, since the size and thickness of the elements in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0044] In this specification, "A and / or B" means A, B, or A and B. In addition, in this specification, "at least one of A and B" means A, B, or A and B.

[0045] In the following embodiments, when a wiring (or line) is referred to as "extending in (or along) the first direction or the second direction", this means that the wiring extends not only in a straight line but also in a zigzag or curved form in the first direction or the second direction.

[0046] In the following embodiments, when a layer, region, or element is referred to as being "on a plane," this means viewing the layer, region, or element in an upward direction, and when a layer, region, or element is referred to as being "on a cross-section," this means viewing the layer, region, or element in a lateral direction of a vertically cut cross-section. In the following embodiments, "overlaying" includes both "planar" overlaying and "cross-sectional" overlaying.

[0047] Figure 1A and Figure 1B is a perspective view schematically illustrating a display device according to some example embodiments.

[0048] Reference Figure 1A , the display device 1 may include a first area A1 and a second area A2 surrounding at least a portion of the first area A1. A plurality of pixels (e.g., a pixel array) may be arranged in the second area A2. An image may be displayed in the second area A2 using the pixel array. The second area A2 corresponds to a display area in which an image (e.g., a video image or a static image) may be displayed. At least a portion of the first area A1 may be surrounded by the second area A2. Therefore, according to some example embodiments, at an edge of the second area A2, the first area A1 may at least partially extend through a line corresponding to an edge of the second area A2, such that a portion of the first area A1 is located on one side of the line, and another portion of the first area A1 is located on the other side of the line.

[0049] According to some example embodiments, Figure 1BAs shown in , the first area A1 can be completely surrounded by the second area A2. The first area A1 can be an area in which components serving as electronic components for providing various functions to the display device 1 are arranged. The first area A1 may include a transmissive area through which light, sound, and / or other signals can be output or transmitted from the component to the outside, or light, sound, or other signals can be transmitted to or received from an external source through the component at the transmissive area. For example, when the component includes a sensor or camera using light, the first area A1 can be a transmissive area through which light from the sensor or light traveling toward the camera can be transmitted.

[0050] The third area A3 may be located between the first area A1 and the second area A2. The third area A3 may include a non-display area in which no pixels are arranged. The fourth area A4 surrounding the second area A2 may include an area in which no pixels are arranged, as in the third area A3. Various wirings and circuits may be arranged in the fourth area A4. Figure 1A As shown in , the third area A3 can be connected to the fourth area A4, as shown in Figure 1B As shown in , the third area A3 may be an independent area that is not connected to the fourth area A4.

[0051] Each pixel in the display device 1 may include a light-emitting diode as a display element for emitting light having a specific color. The light-emitting diode may include an organic light-emitting diode, which includes an organic material as an emission layer. Alternatively, the light-emitting diode may include an inorganic light-emitting diode. Alternatively, the light-emitting diode may include quantum dots as an emission layer. Hereinafter, for ease of explanation, embodiments according to the present disclosure will be described in the context of a light-emitting diode including an organic light-emitting diode, but the embodiments are not limited thereto.

[0052] exist Figure 1A and Figure 1B , the first area A1 is located at the center of the second area A2 in the width direction (e.g., ±x direction) of the display device 1 (and / or the second area A2). However, embodiments according to the present disclosure are not limited thereto. According to some example embodiments, the first area A1 may be offset to the left or to the right in the width direction of the display device 1. Alternatively, the first area A1 may be located at various positions, such as in an upward direction in the length direction (e.g., ±y direction) of the display device 1, in the middle in the length direction (e.g., ±y direction) of the display device 1, or in a downward direction in the length direction (e.g., ±y direction) of the display device 1.

[0053] Figure 1A and Figure 1BThe display device 1 is shown to include one first area A1. According to some example embodiments, the display device 1 may include a plurality of first areas A1. That is, the display device 1 may include a plurality of component areas (A1) overlapping with or within the display area (A2). The shape, size, and position of the first area A1 may be modified in various ways.

[0054] Figure 2A and Figure 2B is a cross-sectional view schematically illustrating a display device according to some example embodiments, Figure 2A and Figure 2B Corresponding to the Figure 1A and Figure 1B A cross section of the display device taken along line II'.

[0055] Reference Figure 2A The display device 1 may include a display panel 10, an input sensing portion 40 on the display panel 10, and an optical function portion 50. These components may be covered by a window 60. The window 60 may be bonded to a component below the window 60 (e.g., the optical function portion 50) using an adhesive layer such as an optically clear adhesive (OCA). The display device 1 may be provided in various electronic devices such as mobile phones, tablet personal computers (PCs), laptop computers, and smart watches.

[0056] The display panel 10 may include a plurality of diodes arranged in the second area A2. The input sensing portion 40 may obtain coordinate information based on an external input (e.g., a touch event). The input sensing portion 40 may include sensing electrodes (or touch electrodes) and traces connected to the sensing electrodes (or touch electrodes). The input sensing portion 40 may be located on the display panel 10. The input sensing portion 40 may sense the external input using any suitable sensing mechanism (such as a mutual capacitance method or a self-capacitance method).

[0057] The input sensing portion 40 may be directly formed on the display panel 10. Alternatively, the input sensing portion 40 may be formed separately and then combined with the display panel 10 using an adhesive layer (such as OCA). Figure 2A As shown in FIG, the input sensing part 40 may be directly formed on the display panel 10. In this case, an adhesive layer may not be provided between the input sensing part 40 and the display panel 10.

[0058] The optical function portion 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) incident from the outside toward the display panel 10 through the window 60. The anti-reflection layer may include a retarder and a polarizer. The retarder may be a film-type or a liquid crystal coating type, and may include a λ / 2 retarder or a λ / 4 retarder. The polarizer may also be a film-type or a liquid crystal coating type. The film-type may include an elongated synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a certain arrangement. The retarder and the polarizer may also include a protective film.

[0059] According to some example embodiments, the anti-reflection layer may include a structure of a black matrix and a color filter. The color filter may be arranged taking into account the color of light emitted from each pixel of the display panel 10. According to some example embodiments, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer located on different layers. The first reflected light and the second reflected light reflected from the first reflective layer and the second reflective layer, respectively, may destructively interfere with each other. Thus, the reflectivity of external light may be reduced.

[0060] The optical function portion 50 may include a lens layer. The lens layer may improve the emission efficiency of light emitted from the display panel 10 or reduce color shift. The lens layer may include a layer having a concave lens shape (or a convex lens shape) or / and a plurality of layers having different reflectivities. The optical function portion 50 may include all or one of the anti-reflection layer and the lens layer described above.

[0061] Each of the input sensing portion 40 and the optical function portion 50 may include a hole corresponding to the first area A1. For example, the input sensing portion 40 may include a first hole 40H passing through the top and bottom surfaces of the input sensing portion 40, and the optical function portion 50 may include a second hole 50H passing through the top and bottom surfaces of the optical function portion 50. The first hole 40H and the second hole 50H may be located in the first area A1 and overlap each other. When the adhesive layer between the window 60 and the optical function portion 50 includes OCA, as shown Figure 2A As shown in , the adhesive layer may not include a hole corresponding to the first area A1. According to some example embodiments, as Figure 2B As shown in , the OCA may include a hole OCAH corresponding to the first area A1.

[0062] As discussed above, the component 20 can be arranged in the first area A1. The component 20 may include an electronic component, such as a sensor or a signal transmitter. For example, the component 20 may be an electronic component that uses light or sound. For example, the electronic component may include a sensor that receives light and uses light (such as an infrared sensor), a camera that receives light to capture an image, a sensor that outputs and detects light or sound to measure distance or recognize a fingerprint, a small lamp that outputs light, or a speaker that outputs sound, etc. In the electronic component using light, light with various wavelength bands (such as visible light, infrared light, and ultraviolet light) can be used. According to some example embodiments, the first area A1 may be a transmission area, and light output from the component 20 to the outside or traveling from the outside toward the component 20 can be transmitted through the transmission area.

[0063] According to some example embodiments, when the display device 1 is used as a smartwatch or a car dashboard, the component 20 may be a member such as a watch hand or a pointer indicating predetermined information (e.g., vehicle speed, etc.). When the display device 1 includes a watch hand or a pointer indicating predetermined information (e.g., vehicle speed, etc.), the component 20 may pass through the window 60 and be exposed to the outside. The window 60 may include an opening corresponding to the first area A1.

[0064] The components 20 may include components that may add specific functions to the display device 1 as described above or components such as accessories for increasing the aesthetics of the display panel 10 .

[0065] Figure 3A is a plan view schematically illustrating a display panel according to some example embodiments, Figure 3B It is along Figure 3A sectional view of the display panel taken along line II-II'.

[0066] Reference Figure 3A and Figure 3B The display panel 10 includes a display layer 200 on a substrate 100. The substrate 100 may include a glass material or a polymer resin. For example, the substrate 100 may include a glass material having silicon dioxide (SiO2) as a main component or a resin such as reinforced plastic.

[0067] The display layer 200 may be positioned to correspond to the second area A2 and include a plurality of pixels P. Each of the plurality of pixels P included in the display layer 200 may include a pixel circuit and a display element electrically connected to the pixel circuit. The pixel circuit may include a transistor and a storage capacitor. The display element may include a light emitting diode (e.g., an organic light emitting diode OLED (see FIG. Figure 5 )).

[0068] The display layer 200 may be covered by the encapsulation substrate 300. The encapsulation substrate 300 may include a glass material or a polymer resin. For example, the encapsulation substrate 300 may include a glass material having SiO2 as a main component or a resin such as reinforced plastic. The encapsulation substrate 300 is arranged to face the substrate 100, and the sealant ST may be positioned or deposited between the substrate 100 and the encapsulation substrate 300. The sealant ST may be located in the fourth area A4, for example, the sealant ST may be continuously arranged along the edge of the substrate 100 between the substrate 100 and the encapsulation substrate 300 and completely surround the display layer 200. When viewed from a direction perpendicular to or orthogonal to the top surface of the substrate 100 (or in a plan view), the second area A2 may be completely surrounded by the sealant ST. The sealant ST may bond the substrate 100 to the encapsulation substrate 300, thereby preventing oxygen or moisture from penetrating into the display layer 200 and improving the strength of the device.

[0069] The sealant ST may be an inorganic material such as glass frit. The sealant ST may be dispensed by a dispenser or a screen printing method. The glass frit may include glass raw materials having a powder type material, but may include a paste type glass frit in which a laser (or IR) absorbing material, an organic binder, and a filler for reducing the coefficient of thermal expansion are added to the main material of SiO2. The paste type glass frit may be cured by removing the organic binder and moisture via a drying process or a firing process. The laser (or IR) absorbing material may include a transition metal compound. Laser may be used as a heat source for curing the sealant ST to combine the substrate 100 with the encapsulation substrate 300.

[0070] A portion of the display layer 200 (eg, a portion corresponding to the first area A1) may be removed. Figure 3B The display layer 200 is shown to include a fourth hole 200H. The display layer 200 may include the pixel circuits and display elements described above, and may also include an insulating layer located between wiring connected to each pixel circuit, between electrodes of the pixel circuits, and / or between electrodes of the display elements. For example, the fourth hole 200H may be formed by stacking the holes of each insulating layer in the display layer 200 described above. The fourth hole 200H of the display layer 200 may be formed to pass through the top and bottom surfaces of the display layer 200. The display layer 200 in the third area A3 may not include pixel circuits and display elements.

[0071] A spacer SPC may be disposed in the third area A3. The spacer SPC may be disposed at an upper portion of at least one insulating layer extending from the second area A2 to the third area A3 and may include an organic material. The spacer SPC may surround the first area A1. According to some example embodiments, in order to reduce the area of ​​the third area A3, the width W of the spacer SPC may be smaller than the width Ws of the sealant ST. The spacer SPC may maintain a gap between the substrate 100 and the encapsulation substrate 300, thereby supporting the encapsulation substrate 300, and may function as a dam for preventing a material introduced through the first area A1 from penetrating into the display layer 200 by separating the first area A1 from the second area A2.

[0072] A pad unit 140 having a plurality of pads (also referred to as "pads") may be arranged on one side of the fourth area A4. The pad unit 140 may not be covered by an insulating layer but may be exposed so as to be electrically connected to a printed circuit board (PCB). The pad unit 140 may be arranged outside the sealant ST. The sealant ST may be arranged on top of a plurality of connection wirings that are used to connect wirings of the pixels P connected to the second area A2 to the pad unit 140, so that the sealant ST may overlap with a portion of the plurality of connection wirings.

[0073] Figure 4 is a plan view schematically illustrating a display panel according to some example embodiments, Figure 5 It is schematically shown Figure 4 Equivalent circuit diagram of a pixel of a display panel.

[0074] The appearance of the display panel 10 can be the same as that of the above reference Figure 3A and Figure 3B For example, the display panel 10 may include a first area A1, a second area A2 surrounding the first area A1, a third area A3 between the first and second areas A1, and a fourth area A4 surrounding the second area A2.

[0075] The display panel 10 may include a plurality of pixels P arranged in the second area A2. Each pixel P may be as shown in FIG. Figure 5 As shown in FIG, a pixel circuit PC and a display element (e.g., an organic light emitting diode OLED) connected to the pixel circuit PC are included. The pixel circuit PC may include a first transistor T1, a second transistor T2, and a capacitor Cst. Each pixel P may emit, for example, red light, green light, or blue light (or red light, green light, blue light, or white light) via the organic light emitting diode OLED. The first transistor T1 and the second transistor T2 may be implemented using thin film transistors.

[0076] The second transistor T2, which is a switching transistor, may be connected to the scan line SL and the data line DL and may transmit a data signal input from the data line DL to the first transistor T1 according to a switching voltage input from the scan line SL. The capacitor Cst may be connected to the second transistor T2 and the driving voltage line PL and may store a voltage corresponding to a difference between a voltage transmitted from the second transistor T2 and a first power supply voltage ELVDD supplied to the driving voltage line PL.

[0077] The first transistor T1, which serves as a driving transistor, can be connected to the driving voltage line PL and the capacitor Cst, and can control the driving current flowing from the driving voltage line PL through the organic light emitting diode OLED in accordance with the voltage value stored in the capacitor Cst. The organic light emitting diode OLED can emit light with a certain brightness due to the driving current. The second power supply voltage ELVSS can be supplied to the counter electrode (e.g., cathode) of the organic light emitting diode OLED.

[0078] Figure 5 The pixel circuit PC is shown to include two transistors and one storage capacitor. However, the embodiments of the present disclosure are not limited thereto. The number of transistors and the number of storage capacitors can be changed in various ways according to the design of the pixel circuit PC.

[0079] Return to reference Figure 4 The third area A3 may surround the first area A1. The third area A3 may be an area where no display elements, such as organic light-emitting diodes (OLEDs) for emitting light, are arranged. Signal lines for providing signals to the plurality of pixels P near the first area A1 may bypass or pass through the third area A3. A first scan driver 1100 and a second scan driver 1200 for providing scan signals to each pixel P, a data driver 1300 for providing data signals to each pixel P, and main power supply wiring for providing a first power supply voltage ELVDD and a second power supply voltage ELVSS may be arranged in the fourth area A4. Each of the first scan driver 1100 and the second scan driver 1200 may be located in the fourth area A4 and on both sides of the second area A2, with the second area A2 being between the first scan driver 1100 and the second scan driver 1200. The first scan driver 1100, the second scan driver 1200, and the data driver 1300 may be located outside the sealant ST in the fourth area A4.

[0080] Figure 4 The data driver 1300 is shown adjacent to one side of the substrate 100. However, according to some example embodiments, the data driver 1300 may be located on a flexible printed circuit board (FPCB) electrically connected to a pad located at one side of the display panel 10.

[0081] Figure 6A and Figure 6B is a plan view illustrating a portion of a display panel according to some example embodiments.

[0082] Reference Figure 6A , some pixels P in the second area A2 may be separated from each other based on the first area A1. For example, the first area A1 may be located Figure 6A Similarly, the first area A1 may be located between two pixels P in the ±x direction. Figure 6A Between two pixels P in the ±y direction.

[0083] Two pixels P in the ±y direction (with the first area A1 between them) can be electrically connected to the same data line DL, which can bend in the third area A3. For example, a portion of the data line DL can bend from the third area A3 along the edge of the first area A1 (e.g., along the arc direction of the first area A1) and can extend. The data line DL can extend in the ±y direction and may include: a first portion DL-L1 and a second portion DL-L2, which pass through the second area A2; and a third portion DL-D, which connects the first portion DL-L1 to the second portion DL-L2 and extends along the arc direction of the first area A1 in the third area A3.

[0084] Two pixels P in the ±x direction (with the first area A1 therebetween) may be electrically connected to different scan lines SL. The scan line SL at the left side of the first area A1 may be electrically connected to the above referenced Figure 4 The first scan driver 1100 described above, and the scan lines SL at the right side of the first area A1 can be electrically connected to the first scan driver 1100 described above. Figure 4 The second scan driver 1200 is described. Figure 4 As shown in , when the display panel 10 includes two scan drivers, the pixels P at both sides of the first area A1 may be electrically connected to the scan lines SL that are separated from each other.

[0085] According to some example embodiments, Figure 6B As shown in , when the second scan driver 1200 is omitted, two pixels P in the ±x direction (with the first area A1 therebetween) can be connected to the same scan line SL, and the scan line SL described above can also include a portion extending along the arc direction of the first area A1 in the third area A3. For example, the scan line SL can include: a first portion SL-L1 and a second portion SL-L2 extending in the ±x direction and passing through the second area A2; and a third portion SL-D connecting the first portion SL-L1 to the second portion SL-L2 and extending along the arc direction of the first area A1 in the third area A3.

[0086] Figure 7 is a cross-sectional view of one pixel of a display panel according to some example embodiments, Figure 7 Can correspond to along Figure 6A A cross section of the display panel taken along line III-III'.

[0087] Reference Figure 7 , the pixel circuit PC may be arranged on the substrate 100, and the organic light emitting diode OLED may be arranged on the pixel circuit PC and electrically connected to the pixel circuit PC. The substrate 100 may include the above reference Figure 3A and Figure 3B The glass or polymer resin described above. The substrate 100 may have a single-layer structure or a multi-layer structure.

[0088] A buffer layer 201 may be formed on the substrate 100 to prevent or reduce the penetration of impurities into the semiconductor layer Act of the thin film transistor TFT. The buffer layer 201 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and may have a single-layer structure or a multi-layer structure including the above-mentioned inorganic insulating material.

[0089] The pixel circuit PC may be disposed on the buffer layer 201. The pixel circuit PC may include a thin film transistor TFT and a capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Figure 7 The thin film transistor TFT shown in FIG. 1 may include the thin film transistor TFT shown in FIG. Figure 5 One of the transistors described, for example, a driving transistor. According to some example embodiments, the gate electrode GE is a top-gate type: the gate electrode GE is arranged on the semiconductor layer Act and the gate insulating layer 203 is located between the gate electrode GE and the semiconductor layer Act. However, according to some example embodiments, the thin film transistor TFT may be a bottom-gate type.

[0090] The semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, or an organic semiconductor. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like. The gate electrode GE may have a single-layer structure or a multi-layer structure including the materials described above.

[0091] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The gate insulating layer 203 may have a single layer structure or a multilayer structure including the materials described above.

[0092] The source electrode SE and the drain electrode DE may include a material having excellent electrical conductivity. The source electrode SE and the drain electrode DE may include a conductive material including Mo, Al, Cu, Ti, and the like, and may have a multilayer structure or a single layer structure including the materials described above. According to some example embodiments, the source electrode SE and the drain electrode DE may have a multilayer structure of Ti / Al / Ti.

[0093] The capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 overlapping the lower electrode CE1, with the first interlayer insulating layer 205 interposed between the lower electrode CE1 and the upper electrode CE2. The capacitor Cst may overlap the thin film transistor TFT. In this regard, Figure 7 The gate electrode GE of the thin film transistor TFT is shown to be the lower electrode CE1 of the capacitor Cst. According to some example embodiments, the capacitor Cst may not overlap with the thin film transistor TFT. The capacitor Cst may be covered by the second interlayer insulating layer 207.

[0094] Each of the first interlayer insulating layer 205 and the second interlayer insulating layer 207 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. Each of the first interlayer insulating layer 205 and the second interlayer insulating layer 207 may have a single-layer structure or a multi-layer structure including the materials described above.

[0095] The pixel circuit PC including the thin film transistor TFT and the capacitor Cst may be covered by the first organic insulating layer 209. The first organic insulating layer 209, which serves as a planarization insulating layer, may have a substantially flat surface on its top. The first organic insulating layer 209 may include an organic insulating material such as a general polymer (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a blend thereof. According to some example embodiments, the first organic insulating layer 209 may include polyimide.

[0096] The connection electrode CM may be formed on the first organic insulating layer 209. The connection electrode CM may include a conductive material such as Mo, Al, Cu, and Ti, and may have a multilayer structure or a single layer structure including the materials described above. The connection electrode CM may include the same material as the source electrode SE or the drain electrode DE of the thin film transistor TFT. For example, the connection electrode CM may have a multilayer structure of Ti / Al / Ti.

[0097] The second organic insulating layer 211 may be formed on the connection electrode CM. The second organic insulating layer 211 may include a substantially flat surface at its top. The second organic insulating layer 211 may include an organic insulating material such as a general polymer (e.g., PMMA or PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and a blend thereof. According to some example embodiments, the second organic insulating layer 211 may include polyimide. According to some example embodiments, an inorganic insulating layer may also be arranged between the first organic insulating layer 209 and the second organic insulating layer 211.

[0098] The pixel electrode 221 may be formed on the second organic insulating layer 211. The pixel electrode 221 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). According to some example embodiments, the pixel electrode 221 may include a reflective film including silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a mixture thereof. According to some example embodiments, the pixel electrode 221 may further include a film including ITO, IZO, ZnO, or In2O3 on / under the reflective film described above.

[0099] The pixel defining layer 215 may be formed on the pixel electrode 221. The pixel defining layer 215 may include an opening OP for exposing the top surface of the pixel electrode 221 and may cover the edge of the pixel electrode 221. The pixel defining layer 215 may be arranged between the plurality of pixel electrodes 221 and surround the plurality of pixel electrodes 221. The pixel defining layer 215 may include an organic insulating material. Alternatively, the pixel defining layer 215 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. Alternatively, the pixel defining layer 215 may include an organic insulating material and an inorganic insulating material.

[0100] Intermediate layer 222 may include an emissive layer 222b. Emissive layer 222b may include, for example, an organic material. Emissive layer 222b may include a polymer material or a low-molecular-weight organic material that emits light of a specific color. Intermediate layer 222 may include a first functional layer 222a located below emissive layer 222b and / or a second functional layer 222c located above emissive layer 222b.

[0101] The first functional layer 222a may have a single-layer structure or a multi-layer structure. For example, when the first functional layer 222a includes a polymer material, the first functional layer 222a as a hole transport layer (HTL) having a single-layer structure may include poly (3,4-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). When the first functional layer 222a includes a low-molecular-weight organic material, the first functional layer 222a may include a hole injection layer (HIL) and the HTL.

[0102] The second functional layer 222c may be selectively formed. For example, when the first functional layer 222a and the emission layer 222b include a polymer material, the second functional layer 222c may be formed. The second functional layer 222c may have a single-layer structure or a multi-layer structure. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0103] The emission layer 222b of the intermediate layer 222 may be disposed in each pixel P in the second area A2. The emission layer 222b may overlap the opening OP of the pixel defining layer 215 or / and the pixel electrode 221. Each of the first functional layer 222a and the second functional layer 222c of the intermediate layer 222 as a single body may be formed in the second area A2 and the third area A3.

[0104] The counter electrode 223 may include a conductive material having a small work function. For example, the counter electrode 223 may include a (semi) transparent layer comprising Ag, Mg, Al, Pt, palladium (Pd), Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca) or an alloy thereof. Alternatively, the counter electrode 223 may further include a layer such as ITO, IZO, ZnO or In2O3 located on the (semi) transparent layer comprising the materials described above. The counter electrode 223 as a single body may be formed to cover the plurality of pixel electrodes 221 in the second area A2. The intermediate layer 222 and the counter electrode 223 may be formed by thermal deposition.

[0105] The capping layer 230 may be disposed on the counter electrode 223. The capping layer 230 may include an inorganic material such as lithium fluoride (LiF) or / and an organic material. According to some example embodiments, the capping layer 230 may be omitted.

[0106] Figure 8 is a view schematically illustrating a portion of a display panel according to some example embodiments. Figures 9 to 12 Can correspond to along Figure 8 A cross section of the display panel taken along line IV-IV' in the plan view PV.

[0107] Figure 8 A portion of the display panel 10 including a first area A1 and a third area A3 surrounding the first area A1 is shown. Figure 8 The plan view PV represents a view defined in the xy plane, and Figure 8 The cross-sectional view CSV represents a view defined in the xz plane. Figure 8 The cross-sectional view CSV may correspond to a cross section of the display panel 10 taken along line IV-IV′ in the plan view PV.

[0108] Reference Figure 8 , the spacer SPC may be arranged in the third area A3 of the display panel 10. The spacer SPC may be arranged on at least one inorganic insulating layer IL and at least one organic insulating layer OL, which are arranged above the substrate 100. The at least one inorganic insulating layer IL and the at least one organic insulating layer OL may be insulating layers extending from the second area A2 to the third area A3. For example, the inorganic insulating layer IL may include Figure 7 The organic insulating layer OL may include at least one of the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205 and the second interlayer insulating layer 207 shown in FIG. Figure 7 At least one of the first organic insulating layer 209, the second organic insulating layer 211 and the pixel defining layer 215 shown in FIG.

[0109] The spacer SPC may have a ring or annular shape that completely surrounds the first area A1. The width W of the spacer SPC may be equal to or less than the width of the third area A3. The spacer SPC may include an organic insulating material such as polyimide. Alternatively, the spacer SPC may include an inorganic insulating material (such as silicon nitride or silicon oxide) or an organic insulating material and an inorganic insulating material. The spacer SPC may include a material different from the material used to form the pixel defining layer 215. Alternatively, the spacer SPC may include the same material as the pixel defining layer 215. In this case, the pixel defining layer 215 and the spacer SPC may be formed together in a mask process using a halftone mask. According to some example embodiments, the pixel defining layer 215 and the spacer SPC may include polyimide.

[0110] Reference Figure 9 , a buffer layer 201, a gate insulating layer 203, a first interlayer insulating layer 205, a second interlayer insulating layer 207, a first organic insulating layer 209 and a second organic insulating layer 211 are arranged on the substrate 100. The pixel circuit PC may include a thin film transistor and a capacitor. The semiconductor layer and electrodes of the thin film transistor and the electrodes of the capacitor may be arranged on the substrate 100. Figure 7 Description of the insulation layer.

[0111] The pixel electrode 221 may be connected to the connection electrode CM via a contact hole in the second organic insulating layer 211, and the connection electrode CM may be connected to the thin film transistor of the pixel circuit PC via a contact hole in the first organic insulating layer 209. According to some example embodiments, the connection electrode CM may be omitted. The pixel electrode 221 may be connected to the thin film transistor of the pixel circuit PC via the contact holes in the first organic insulating layer 209 and the second organic insulating layer 211.

[0112] The pixel defining layer 215 on the pixel electrode 221 may include an opening overlapping the pixel electrode 221, and the opening of the pixel defining layer 215 may define the emission area EA. The first functional layer 222a, the emission layer 222b, the second functional layer 222c, the counter electrode 223, and the capping layer 230 stacked in sequence may be arranged on the pixel defining layer 215. The materials and features of the display layer 200 on the substrate 100 are as described above with reference to Figure 7 described.

[0113] The first region A1 may be between pixels, for example, between light emitting diodes including a stack of a pixel electrode 221, an emission layer 222b, and an opposing electrode 223. The display layer 200 may include a fourth hole 200H in the first region A1.

[0114] When the through holes formed in the insulating layer of the display layer 200 overlap each other, the fourth hole 200H may be formed. The insulating layer of the display layer 200 (e.g., the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, the second interlayer insulating layer 207, the first organic insulating layer 209, the second organic insulating layer 211, and the pixel defining layer 215) may include a through hole in the first area A1. The size of the fourth hole 200H may be defined by the insulating layer having a small-sized hole used to define the insulating layer of the display layer 200 described above. According to some example embodiments, Figure 9 It is shown that the fourth hole 200H is defined by the size of the through hole of the buffer layer 201 .

[0115] The third portion SL-D of each of the plurality of scan lines SL in the third area A3 may be located between the gate insulating layer 203 and the first interlayer insulating layer 205. The third portion DL-D of each of the plurality of data lines DL in the third area A3 may be arranged between the second interlayer insulating layer 207 and the first organic insulating layer 209. According to some example embodiments, the third portion SL-D of each of the plurality of scan lines SL and the third portion DL-D of each of the plurality of data lines DL may be arranged between the first interlayer insulating layer 205 and the second interlayer insulating layer 207. The third portion SL-D of each of the plurality of scan lines SL and the third portion DL-D of each of the plurality of data lines DL may overlap the spacer SPC.

[0116] In the third area A3, a spacer SPC may be arranged above the pixel defining layer 215. The spacer SPC may maintain a gap between the substrate 100 and the encapsulation substrate 300. The spacer SPC may include a through hole SPCH corresponding to the first area A1 and may be arranged in the third area A3 in a closed loop form (such as a ring shape or a circular ring shape) along the arc of the first area A1. At least one of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 230 extending from the second area A2 may be arranged above the spacer SPC. Figure 9 An example is shown in which the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cover layer 230 extending from the second area A2 are arranged above the spacer SPC so as to cover the spacer SPC. Similarly, in the insulating layer of the display layer 200, each of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cover layer 230 may further include a hole formed when a portion of each of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cover layer 230 corresponding to the first area A1 is removed. According to some example embodiments, as Figure 10 As shown in FIG, the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 230 arranged in the second area A2 may not extend into the third area A3 or may be removed from the third area A3 and thus may not be arranged over the spacer SPC.

[0117] The encapsulation substrate 300 is arranged to face the substrate 100. In the first area A1, the material included in the display layer 200 may not be deposited between the bottom surface of the encapsulation substrate 300 and the top surface of the substrate 100. In other words, the top surface of the substrate 100 in the first area A1 may directly face the bottom surface of the encapsulation substrate 300. The encapsulation substrate 300 may include the same material as the substrate 100 and may have the same refractive index. For example, the substrate 100 and the encapsulation substrate 300 may have a refractive index of approximately 1.3 to approximately 1.7 (e.g., approximately 1.5). An air gap may be formed in the first area A1 by the substrate 100 and the encapsulation substrate 300.

[0118] like Figure 9 As shown in FIG, the top surface of the capping layer 230 may be in direct contact with the package substrate 300, or as shown in FIG. Figure 10 As shown in , the top surface of the spacer SPC may be in direct contact with the package substrate 300. According to some example embodiments, as Figure 11 , the top surface of the spacer SPC may not contact the package substrate 300 but may be separated from the package substrate 300 by a specific distance. When the capping layer 230 is disposed over the spacer SPC, the top surface of the capping layer 230 may not contact the package substrate 300 but may be separated from the package substrate 300 by a specific distance.

[0119] like Figure 12 As shown in FIG, the window 60 is arranged above the package substrate 300, and the input sensing portion 40 and the optical function portion 50 may be arranged between the package substrate 300 and the window 60. The OCA may be arranged between the window 60 and the optical function portion 50. The second hole 50H of the optical function portion 50 may overlap with the first hole 40H of the input sensing portion 40. The hole OCAH of the OCA may overlap with the first hole 40H of the input sensing portion 40.

[0120] According to some example embodiments, the first transparent layer TRL1 may be disposed in the holes 40H, 50H, and OCAH between the package substrate 300 and the window 60. According to some example embodiments, as shown in FIG. Figure 13As shown in , the second transparent layer TRL2 can be arranged in the hole 200H and SPCH between the substrate 100 and the encapsulation substrate 300. The first transparent layer TRL1 and the second transparent layer TRL2 may include a transparent material having a refractive index similar to that of the substrate 100 and the encapsulation substrate 300. The first transparent layer TRL1 and the second transparent layer TRL2 may have a refractive index of about 1.3 to about 1.7 (for example, about 1.5). The first transparent layer TRL1 and the second transparent layer TRL2 may include a transparent resin for filling without degassing. For example, the first transparent layer TRL1 and the second transparent layer TRL2 may include an optically clear resin (OCR). At least one of the first transparent layer TRL1 and the second transparent layer TRL2 may correspond to the first area A1. Therefore, the transmittance and reflectance of the light passing through the first area A1 can be improved.

[0121] When an air gap is formed in the first area A1 due to the holes 200H and SPCH between the substrate 100 and the package substrate 300, a portion of the package substrate 300 corresponding to the first area A1 may be recessed toward the substrate 100 or may be cracked. Therefore, a phenomenon in which an edge of the first area A1 is seen may occur.

[0122] According to some exemplary embodiments of the present disclosure, in the third area A3, the spacer SPC may be arranged between the substrate 100 and the encapsulation substrate 300. Therefore, the encapsulation substrate 300 can be supported, so that the encapsulation substrate 300 can be prevented from being concave, thereby preventing the edge of the first area A1 from being visible as described above. Furthermore, according to some exemplary embodiments of the present disclosure, the second transparent layer TRL2 may be arranged in the first area A1. Therefore, the encapsulation substrate 300 can be supported, so that the encapsulation substrate 300 can be prevented from being concave, thereby more effectively preventing or reducing the edge of the first area A1 from being visible as described above.

[0123] When the second transparent layer TRL2 does not completely fill the first area A1 or extends into the second area A2, the second transparent layer TRL2 may be visible. The spacer SPC in the third area A3 can appropriately place the second transparent layer TRL2 in the first area A1, thereby completely filling the first area A1 with the second transparent layer TRL2 and preventing the second transparent layer TRL2 from extending into the second area A2. In this case, the top surface of the spacer SPC or the top surface of the uppermost layer above the spacer SPC (for example, the cover layer 230) can contact the encapsulation substrate 300, so that the material used to form the second transparent layer TRL2 can be more effectively prevented from penetrating into the second area A2.

[0124] Regarding the alignment error during the assembly process of the display device and / or the quality of the image captured by the camera according to the viewing angle of the camera as the component 20, the second width W2 of the first hole 40H of the input sensing unit 40 and the second hole 50H of the optical function unit 50 may be greater than the first width W1 of the fourth hole 200H of the display layer 200 (W1 < W2).

[0125] Figure 14 is a view schematically showing a part of a display panel according to some example embodiments. Figures 15 to 19 may correspond to a cross-section of the display panel taken along the line V-V' in the plan view PV of Figure 14 .

[0126] Figure 14 shows a part of the display panel 10 including the first region A1 and the third region A3 surrounding the first region A1. Figure 14 The plan view PV of Figure 14 represents a view defined in the xy plane, and Figure 14 The cross-sectional view CSV of Figure 14 may correspond to a cross-section of the display panel taken along the line V-V' in the plan view PV. Figure 8 The embodiment shown in Figure 14 is different from the embodiment in which a single spacer SPC is arranged because in Figure 8 's embodiment, multiple spacers SPC are arranged in the third region A3. A description of the structure identical to that of

[0127] Referring to Figure 14 , multiple spacers SPCa, SPCb, and SPCc may be arranged in the third region A3 of the display panel 10, and thus, a spacer SPC having an uneven structure may be formed. In Figure 14 , three spacers SPCa, SPCb, and SPCc may be arranged in the third region A3. According to the size of the third region A3, the number of spacers may be two or more. The spacers SPCa, SPCb, and SPCc may completely surround the first region A1, may be separated from each other by a specific distance, and each of the spacers SPCa, SPCb, and SPCc may have an annular shape or a toroidal shape. As the distance from the first region A1 increases, the diameters of the spacers SPCa, SPCb, and SPCc may increase (D1 < D2 < D3). The spacer SPCa among the spacers SPCa, SPCb, and SPCc that is closest to the first region A1 may include a through hole SPCH' corresponding to the first region A1 (see Figure 15), and may be arranged in the form of a ring or annulus along the arc of the first area A1 in the third area A3. The spacer SPCb may be separated from the spacer SPCa and may surround the spacer SPCa. The spacer SPCc may be separated from the spacer SPCb and may surround the spacer SPCb. The spacers SPCa, SPCb, and SPCc may be arranged on at least one inorganic insulating layer IL and at least one organic insulating layer OL above the substrate 100. The width of each of the plurality of spacers SPCa, SPCb, and SPCc may be less than Figure 8 1 and 2. The width W of a single spacer SPC is shown in FIG. The widths of the spacers SPCa, SPCb, and SPCc may be the same as or different from each other.

[0128] Reference Figure 15 , a plurality of spacers SPCa, SPCb, and SPCc may be arranged in the third area A3 over the pixel defining layer 215. The spacers SPCa, SPCb, and SPCc may maintain a gap between the substrate 100 and the encapsulation substrate 300. At least one of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 230 extending from the second area A2 to the third area A3 may be arranged over at least one of the spacers SPCa, SPCb, and SPCc. Figure 15 An example is shown in which the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 230 extending from the second area A2 to the third area A3 are arranged above the spacers SPCa, SPCb, and SPCc and at the gaps between the spacers SPCa, SPCb, and SPCc, thereby covering the spacers SPCa, SPCb, and SPCc and the gaps between the spacers SPCa, SPCb, and SPCc. According to some example embodiments, at least one of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 230 extending from the second area A2 to the third area A3 may be arranged only above the spacer SPCc adjacent to the second area A2. According to some example embodiments, as Figure 16 As shown in the figure, the first functional layer 222a, the second functional layer 222c, the counter electrode 223 and the cover layer 230 arranged in the second area A2 may not extend into the third area A3 or may be removed from the third area A3, so that they may not be arranged above the spacers SPCa, SPCb and SPCc.

[0129] According to some example embodiments, the spacer SPC may have a multi-layer structure. Figure 17As shown in , the pixel defining layer 215 in the third area A3 may constitute a part of the spacer SPC. That is, each of the spacers SPCa, SPCb and SPCc may constitute an upper layer of the spacer SPC, and each of the pixel defining layer patterns 215a, 215b and 215c arranged below each of the spacers SPCa, SPCb and SPCc may constitute a lower layer of the spacer SPC. The top surface of the second organic insulating layer 211 may be exposed at the gap between the pixel defining layer patterns 215a, 215b and 215c. By simultaneously patterning the pixel defining layer forming layer and the spacer forming layer, the pixel defining layer patterns 215a, 215b and 215c and the spacers SPCa, SPCb and SPCc may be formed simultaneously. In this case, the side surface of each of the spacers SPCa, SPCb and SPCc and the side surface of each of the pixel defining layer patterns 215a, 215b and 215c may coincide with each other. In Figure 17 In the embodiment, Figure 15 As shown in the figure, the first functional layer 222a, the second functional layer 222c, the counter electrode 223 and the cover layer 230 extending from the second area A2 to the third area A3 can be arranged above the spacers SPCa, SPCb and SPCc and in the gaps between the spacers SPCa, SPCb and SPCc, thereby covering the spacers SPCa, SPCb and SPCc and the gaps between the spacers SPCa, SPCb and SPCc.

[0130] like Figure 15 As shown in FIG, the top surface of the capping layer 230 may be in direct contact with the package substrate 300, or as shown in FIG. Figure 16 and Figure 17 , the top surface of the spacer SPC may be in direct contact with the package substrate 300. According to some example embodiments, the top surface of the spacer SPC may not be in contact with the package substrate 300 but may be separated from the package substrate 300 by a specific distance. When the capping layer 230 is disposed over the spacer SPC, the top surface of the capping layer 230 may not be in contact with the package substrate 300 but may be separated from the package substrate 300 by a specific distance.

[0131] The window 60 may be arranged in Figures 15 to 17 The window 60 is shown in FIG. 4 , and the input sensing portion 40 and the optical function portion 50 may be disposed between the package substrate 300 and the window 60 . Figure 18 and Figure 19 Shown is located Figure 15 and Figure 17 The input sensing portion 40, the optical function portion 50 and the window 60 above the display panel 10 may also be arranged on the display panel 10. Figure 16The OCA may be disposed between the window 60 and the optical function portion 50. The second hole 50H of the optical function portion 50 may overlap with the first hole 40H of the input sensing portion 40. The hole OCAH of the OCA may overlap with the first hole 40H of the input sensing portion 40.

[0132] The first transparent layer TRL1 may be disposed in the holes 40H, 50H, and OCAH between the encapsulation substrate 300 and the window 60. The second transparent layer TRL2 may be further disposed in the holes 200H and SPCH′ between the substrate 100 and the encapsulation substrate 300. Due to the spacer SPC having an uneven structure, a path for the second transparent layer TRL2 to penetrate into the second area A2 may be increased, thereby preventing the second transparent layer TRL2 from extending into the second area A2.

[0133] Figure 20 is a view schematically illustrating a portion of a display panel according to some example embodiments. Figure 20 The cross-sectional view CSV may correspond to a cross section of the display panel 10 taken along the line VI-VI' in the plan view PV, and Figure 21 Can correspond to along Figure 20 A cross section of the display panel 10 taken along line VII-VII' in the plan view PV of FIG.

[0134] Figure 20 An example is in Figure 8 In the embodiment of the present invention, a spacer is further arranged in the second area A2. Figure 8 The constructor is the same as the description of the constructor.

[0135] Reference Figure 20 , the third area A3 may be located between the first area A1 and the second area A2. The second area A2 may include a plurality of emission areas EA and a non-emission area NEA surrounding the plurality of emission areas EA. Figure 21 As shown in , the emission area EA may be defined by the opening of the pixel defining layer 215 .

[0136] The first spacer SPC1 may be arranged in the third area A3, and the plurality of second spacers SPC2 may be arranged in the second area A2. The first spacer SPC1 may completely surround the first area A1 and may have a ring shape or a donut shape. Figure 14Similar to the embodiment shown in , a plurality of first spacers SPC1 having a ring shape or an annular shape can completely surround the first area A1. Second spacers SPC2 can be arranged at a specific distance in the non-emission area NEA between adjacent emission areas EA. For example, the emission area EA can emit red light, green light, blue light, or white light. The emission areas EA can have various arrangements, such as a stripe arrangement, a pentile arrangement, and a mosaic arrangement.

[0137] Reference Figure 21 , the second spacer SPC2 may be formed on the pixel defining layer 215 in the second area A2. The second spacer SPC2 may include an organic insulating material such as polyimide. Alternatively, the second spacer SPC2 may include an inorganic insulating material (such as silicon nitride or silicon oxide) or an organic insulating material and an inorganic insulating material. The second spacer SPC2 may include a material different from that of the pixel defining layer 215. Alternatively, the second spacer SPC2 may include the same material as that of the pixel defining layer 215. In this case, the pixel defining layer 215 and the second spacer SPC2 may be formed together in a mask process using a halftone mask. According to some example embodiments, the pixel defining layer 215 and the second spacer SPC2 may include polyimide. The first spacer SPC1 may include a material different from that of the second spacer SPC2. Alternatively, the first spacer SPC1 may include the same material as that of the second spacer SPC2. In this case, the first spacer SPC1 and the second spacer SPC2 may be formed simultaneously in the same process.

[0138] The first spacer SPC1 and the second spacer SPC2 may have the same height and may maintain a gap between the substrate 100 and the encapsulation substrate 300 in the second and third areas A2 and A3 .

[0139] According to one or more embodiments of the present disclosure, the transmissive area of ​​a display device having a transmissive area in a display area may not be visible, and damage to the display device may be prevented or reduced. These effects are merely examples, and the scope of the embodiments of the present disclosure is not limited thereto.

[0140] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: a first substrate comprising a transmission area, a display area surrounding at least a portion of the transmission area, and a first non-display area between the transmission area and the display area; an insulating layer located in the display area and the first non-display area and including a first through hole in the transmission area; a plurality of display elements located in the display area; a spacer located above the insulating layer in the first non-display area and including a second through hole corresponding to the first through hole to surround the transmission area, wherein a side surface of the spacer forms a sidewall of the second through hole; a second substrate facing the first substrate, with an upper surface of the spacer in contact with the second substrate and the spacer maintaining a gap between the first substrate and the second substrate; as well as a transparent layer located in the transmission area, wherein the spacer is configured to provide a dam for preventing a material introduced through the transmission area from penetrating into the display area by distinguishing the transmission area from the display area, and The spacer and the transparent layer are configured to support the second substrate to prevent the second substrate from being dented and to prevent an edge of the transmission area from being seen.

2. The display device according to claim 1, wherein The insulating layer includes at least one inorganic insulating layer and at least one organic insulating layer.

3. The display device according to claim 2, wherein Each of the plurality of display elements includes a first electrode, a second electrode facing the first electrode, and an emission layer located between the first electrode and the second electrode, and The at least one organic insulating layer includes a pixel defining layer located between the first electrodes of the plurality of display elements.

4. The display device according to claim 3, wherein The spacer is located above the pixel defining layer in the first non-display area.

5. The display device according to claim 3, wherein The second electrode covers the pixel defining layer and the spacer. The display device according to claim 1 , wherein: The spacer includes a plurality of ring-shaped second spacers surrounding the transmission area and spaced apart from each other.

7. The display device according to claim 6, wherein Each of the plurality of annular second spacers includes a lower layer and an upper layer, and The lower layer is a portion of the insulating layer located in the first non-display area. 8 . The display device of claim 1 , further comprising a sealant bonding the first substrate and the second substrate together and disposed in a second non-display area surrounding the display area. 9 . The display device according to claim 1 , further comprising a signal line bent along an edge of the transmission area and arranged in the first non-display area.

10. The display device according to claim 9, wherein The spacer overlaps the signal line.

11. The display device according to claim 1, wherein The spacer includes an organic insulating material.

12. A display device, comprising: first base; an insulating layer, located on the first substrate and having a first through hole; a spacer located above the insulating layer and having a second through hole corresponding to the first through hole so as to surround the first through hole along an edge of the first through hole; a second substrate facing the first substrate, with an upper surface of the spacer in contact with the second substrate and the spacer maintaining a gap between the first substrate and the second substrate; as well as a transparent layer located in the first through hole of the insulating layer and the second through hole of the spacer, Wherein, the side surface of the spacer forms the side wall of the second through hole.

13. The display device according to claim 12, wherein The insulating layer includes at least one inorganic insulating layer and at least one organic insulating layer, and The spacer is located over the at least one organic insulating layer.

14. The display device according to claim 12, wherein The spacer includes an organic insulating material.

15. The display device according to claim 12, wherein The spacer includes a plurality of second spacers surrounding the second through hole and spaced apart from each other.

16. The display device according to claim 15, wherein Each of the plurality of second spacers includes a lower layer and an upper layer, and The lower layer is a portion of the insulating layer.

17. The display device according to claim 12, further comprising a plurality of display elements adjacent to the second through hole, in, The spacer is located between the plurality of display elements and the second through hole and has a ring shape, and surrounds the second through hole.

18. The display device according to claim 17, wherein Each of the plurality of display elements includes a first electrode, a second electrode facing the first electrode, and an emission layer located between the first electrode and the second electrode. The insulating layer includes a pixel defining layer located between the first electrodes of the plurality of display elements, and The spacer is arranged on the pixel defining layer adjacent to the second through hole.

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