Display device

Abstract

A display device including a plurality of pixels on a substrate, the display device comprising: a pixel defining layer covering an edge of a first electrode of each of the plurality of pixels; a first spacer arranged on the pixel defining layer and comprising a first portion and a second portion, the first portion of the first spacer having a width that increases toward the substrate, and the second portion of the first spacer being arranged between the first portion of the first spacer and the substrate and having a width that decreases toward the substrate; and a first hole arranged separated from the first electrode between the plurality of pixels, the first hole being formed in the second portion of the first spacer and the pixel defining layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0109577 filed on September 4, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present disclosure relate to a display device and a method of manufacturing the same. Background Art

[0004] A display device is a device that visually displays data. Recently, applications of display devices have become more diverse. Also, as display devices become thinner and lighter, their scope of use has greatly expanded.

[0005] In order to protect the display area from external moisture and impurities, the display area of ​​the display device may be encapsulated with an encapsulation member. Recently, as the demand for thin and flexible display devices increases, a thin film encapsulation layer including a flexible organic insulating layer and / or a flexible inorganic insulating layer, which replaces metal or glass, has been used as an encapsulation member. However, during a subsequent process after a process of forming the thin film encapsulation layer as an encapsulation member, a defect may occur in which the thin film encapsulation layer is peeled off from the back panel of the display device. Summary of the invention

[0006] Exemplary embodiments of the present disclosure include display devices and methods of manufacturing the same, wherein defects of thin film encapsulation layer peeling off from a backplane of the display device are reduced. However, it should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for limiting the present disclosure.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of exemplary embodiments of the disclosure.

[0008] According to an exemplary embodiment of the present disclosure, a display device includes: a display area located on a substrate, the display area includes a plurality of pixels, each of the plurality of pixels includes a first electrode, a second electrode, and an intermediate layer including an emission layer and arranged between the first electrode and the second electrode; a pixel defining layer, the pixel defining layer covering an edge of the first electrode of each of the plurality of pixels; a first spacer, the first spacer is arranged on the pixel defining layer and includes a first portion and a second portion, the first portion of the first spacer has a width that increases toward the substrate, and the second portion of the first spacer is arranged between the first portion of the first spacer and the substrate and has a width that decreases toward the substrate; and a first hole arranged between the plurality of pixels and separated from the first electrode, the first hole being formed in the second portion of the first spacer and the pixel defining layer.

[0009] The intermediate layer and the second electrode may be located inside the first hole.

[0010] The emission layer may be located on the first electrode and may not be located inside the first hole.

[0011] The display device may further include a thin film encapsulation layer encapsulating multiple pixels, wherein the thin film encapsulation layer may include a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer located between the first inorganic encapsulation layer and the second inorganic encapsulation layer, the first inorganic encapsulation layer may cover the second electrode located on the inner side of the first hole and the entire inner surface of the first hole, and the organic encapsulation layer may fill the entire inner portion of the first hole.

[0012] The pixel defining layer may include the same material as that of the first spacer.

[0013] The display device may further include a first planarization layer and a second planarization layer sequentially arranged from the substrate between the substrate and the pixel defining layer, and the first hole may extend into the second planarization layer.

[0014] The display device may further include a first anti-etching layer disposed below a bottom surface of the first hole.

[0015] The display device may further include a thin film transistor located between the substrate and the first planarization layer, and a connecting line located between the first planarization layer and the second planarization layer and configured to connect the thin film transistor to the first electrode, wherein the first anti-etching layer may include the same material as that of the connecting line.

[0016] The first non-display area may be located outside the display area, the pixel defining layer may extend from the display area to the first non-display area, and the display device may further include: a second spacer, which is arranged on the pixel defining layer of the first non-display area, includes a material that is the same as that of the first spacer, and includes a first part and a second part, the first part of the second spacer has a width that increases toward the substrate, and the second part of the second spacer is arranged between the first part of the second spacer and the substrate and has a width that decreases toward the substrate; and a second hole located in the first non-display area, the second hole being formed in the second part of the second spacer and the pixel defining layer.

[0017] The intermediate layer and the second electrode may extend to the first non-display area and may be located inside the second hole.

[0018] The first inorganic encapsulation layer, the organic encapsulation layer and the second inorganic encapsulation layer may extend to the first non-display area, the first inorganic encapsulation layer may cover the second electrode located inside the second hole and the entire inner surface of the second hole, and the organic encapsulation layer may fill the entire inner portion of the second hole.

[0019] The display device may further include a power supply voltage line located in the first non-display area, the power supply voltage line surrounding a portion of the display area, wherein the second electrode extending to the first non-display area may be electrically connected to the power supply voltage line.

[0020] The display device may further include a first dam portion and a second dam portion, each located in the first non-display area, wherein the first dam portion and the second dam portion may each include a layer containing the same material as the second spacer and the pixel defining layer, and the second dam portion may cover an end portion of the power supply voltage line.

[0021] The display device may further include a first planarization layer and a second planarization layer sequentially arranged from the substrate in the first non-display area between the substrate and the pixel defining layer, wherein the second hole may extend into the second planarization layer.

[0022] The display device may further include a second anti-etching layer disposed below a bottom surface of the second hole.

[0023] The second non-display area may surround an opening formed inside the display area, and the display device in the second non-display area may further include: a base layer comprising a material identical to that of a pixel defining layer of the display area; a third spacer on the base layer, the third spacer comprising a material identical to that of the first spacer and comprising a first portion and a second portion, the first portion of the third spacer having a width that increases toward the substrate, and the second portion of the third spacer being arranged between the first portion of the third spacer and the substrate and having a width that decreases toward the substrate; and a third hole in the second non-display area, the third hole being formed in the second portion of the third spacer and the base layer.

[0024] The display device may further include a groove passing through a portion of the substrate in the second non-display area.

[0025] The intermediate layer and the second electrode may extend to the second non-display area and may be located inside the third hole and the groove.

[0026] The first inorganic encapsulation layer, the organic encapsulation layer, and the second inorganic encapsulation layer may extend to the second non-display area, and the first inorganic encapsulation layer and the second inorganic encapsulation layer may cover the second electrode located inside the third hole and groove and the entire inner surface of the third hole and groove.

[0027] According to an exemplary embodiment of the present disclosure, a display device includes: a display area, which is located on a substrate and includes a plurality of pixels, each of the plurality of pixels includes a first electrode, a second electrode, and an intermediate layer including an emission layer and located between the first electrode and the second electrode; a non-display area, which is located on the substrate and outside the display area; a thin film encapsulation layer, which encapsulates the plurality of pixels and includes a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer located between the first inorganic encapsulation layer and the second inorganic encapsulation layer; a pixel defining layer, which covers an edge of the first electrode and extends from the display area to the non-display area; a first spacer, which is located on the pixel defining layer in the display area; a second spacer, which is located on the pixel defining layer in the non-display area, includes a material that is the same as that of the first spacer and includes a first portion and a second portion, the first portion of the second spacer having a width that increases toward the substrate, and the second portion of the second spacer is arranged between the first portion of the second spacer and the substrate and has a width that decreases toward the substrate; and a hole located in the non-display area, the hole being formed in the second portion of the second spacer and the pixel defining layer.

[0028] A portion of the intermediate layer except the emission layer formed in the display area, and the second electrode can extend to the non-display area and can be located inside the hole, the first inorganic encapsulation layer can extend to the non-display area to cover the second electrode located inside the hole and the entire inner surface of the hole, and the organic encapsulation layer can fill the entire inner part of the hole.

[0029] The first inorganic encapsulation layer, the organic encapsulation layer, and the second inorganic encapsulation layer may extend to the non-display area, the first inorganic encapsulation layer may cover the second electrode located inside the hole and the entire inner surface of the hole, and the organic encapsulation layer may fill the entire inner portion of the hole.

[0030] The display device may further include a first planarization layer and a second planarization layer sequentially arranged from the substrate in a non-display area between the substrate and the pixel defining layer, wherein the hole may extend into the second planarization layer.

[0031] The display device may further include an anti-etching layer disposed below a bottom surface of the hole.

[0032] According to an exemplary embodiment of the present disclosure, a display device includes: a display area, which is located on a substrate and includes a plurality of pixels, each of the plurality of pixels includes a first electrode, a second electrode, and an intermediate layer including an emission layer and located between the first electrode and the second electrode; a pixel defining layer, which covers an edge of the first electrode; a first spacer, which is located on the pixel defining layer in the display area; a thin film encapsulation layer, which is arranged on the pixel defining layer and the first spacer and includes a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer located between the first inorganic encapsulation layer and the second inorganic encapsulation layer. a mounting layer; a non-display area surrounding an opening formed inside the display area; a base layer located in the non-display area and including a material that is the same as that of the pixel defining layer; a second spacer located on the base layer, including a material that is the same as that of the first spacer, and including a first portion and a second portion, the first portion of the second spacer having a width that increases toward the substrate, and the second portion of the second spacer being arranged between the first portion of the second spacer and the substrate and having a width that decreases toward the substrate; and a hole located in the non-display area, the hole being formed in the second portion of the second spacer and the base layer.

[0033] The display device may further include a groove passing through a portion of the substrate in the non-display area.

[0034] The intermediate layer and the second electrode may extend to the non-display area and may be located inside the hole and the groove.

[0035] The first inorganic encapsulation layer, the organic encapsulation layer, and the second inorganic encapsulation layer may extend to the non-display area, and the first inorganic encapsulation layer and the second inorganic encapsulation layer may cover the second electrode located inside the hole and the groove and the entire inner surface of the hole and the groove.

[0036] According to an exemplary embodiment of the present disclosure, a method for manufacturing a display device, the display device includes a display area including a plurality of pixels and a thin film encapsulation layer that encapsulates the display area, each of the plurality of pixels includes a first electrode, a second electrode, and an intermediate layer including an emission layer and located between the first electrode and the second electrode, the method including: forming a pixel defining layer and a first spacer on a substrate, the pixel defining layer covering an edge of the first electrode, and the first spacer being on the pixel defining layer; forming a barrier layer to cover the pixel defining layer and the first spacer, and exposing a portion of the surface of the pixel defining layer and the first spacer by patterning the barrier layer; forming a first hole in the exposed pixel defining layer and the first spacer, the first hole being separated from the first electrode; removing the barrier layer; forming an intermediate layer and a second electrode on the inner and outer sides of the first hole so that the intermediate layer and the second electrode are disconnected on the inner and outer sides of the first hole; forming a first inorganic encapsulation layer of the thin film encapsulation layer on the inner and outer sides of the first hole so that the first inorganic encapsulation layer is connected on the inner and outer sides of the first hole; and forming an organic encapsulation layer of the thin film encapsulation layer so that the organic encapsulation layer fills the inner side of the first hole.

[0037] The pixel defining layer may include the same material as that of the first spacer, and the pixel defining layer and the first spacer may be formed during the same process.

[0038] The method may further include: forming a first planarization layer and a second planarization layer arranged sequentially from the substrate between the substrate and the pixel defining layer; forming a first anti-etching layer on the first planarization layer; and extending the first hole into the second planarization layer and to the first anti-etching layer.

[0039] The method may further include: extending the pixel defining layer to a first non-display area outside the display area; forming a second spacer on the pixel defining layer in the first non-display area, the second spacer comprising a material that is the same as that of the first spacer; covering the pixel defining layer and the second spacer in the first non-display area with a barrier layer, and exposing a portion of the surface of the pixel defining layer and the second spacer by patterning the barrier layer; forming a second hole in the exposed pixel defining layer and the second spacer; removing the barrier layer; forming an intermediate layer and a second electrode on the inside and outside of the second hole so that the intermediate layer and the second electrode are disconnected on the inside and outside of the second hole; forming a first inorganic encapsulation layer on the inside and outside of the second hole so that the first inorganic encapsulation layer is connected on the inside and outside of the second hole without being disconnected; and forming an organic encapsulation layer so that the organic encapsulation layer fills the inside of the second hole.

[0040] The pixel defining layer in the first non-display area may include the same material as that of the second spacer, and the pixel defining layer in the first non-display area and the second spacer may be formed during the same process.

[0041] The method may further include: in the first non-display area, forming a first planarization layer and a second planarization layer arranged sequentially from the substrate between the substrate and the pixel defining layer; forming a second anti-etching layer on the first planarization layer; and extending the second hole into the second planarization layer and to the second anti-etching layer.

[0042] The method may further include: forming a base layer in a second non-display area surrounding an opening formed inside the display area, the base layer comprising a material identical to that of a pixel defining layer; forming a third spacer on the base layer, the third spacer comprising a material identical to that of the first spacer; covering the base layer and the third spacer with a barrier layer, and exposing a portion of the surface of the base layer and the third spacer by patterning the barrier layer; forming a third hole in the exposed base layer and the third spacer; removing the barrier layer; forming an intermediate layer and a second electrode inside and outside the third hole so that the intermediate layer and the second electrode are disconnected inside and outside the third hole; and forming a first inorganic encapsulation layer and a second inorganic encapsulation layer inside and outside the third hole so that the first inorganic encapsulation layer and the second inorganic encapsulation layer are connected inside and outside the third hole without being disconnected.

[0043] The base layer may include the same material as that of the third spacer, and the base layer and the third spacer may be formed during the same process.

[0044] The method may further include forming a groove through a portion of the substrate while forming the third hole.

[0045] The method may further include: forming an intermediate layer and a second electrode on the inside and outside of the groove so that the intermediate layer and the second electrode are disconnected on the inside and outside of the groove; and forming a first inorganic encapsulation layer and a second inorganic encapsulation layer on the inside and outside of the groove so that the first inorganic encapsulation layer and the second inorganic encapsulation layer are connected on the inside and outside of the groove without being disconnected.

[0046] According to an exemplary embodiment of the present disclosure, a display device includes: a display area located above a substrate, the display area includes a plurality of pixels, each of the plurality of pixels includes a first electrode, a second electrode, and an intermediate layer including an emission layer and arranged between the first electrode and the second electrode; a pixel defining layer, the pixel defining layer covering an edge of the first electrode of each of the plurality of pixels; a first spacer, the first spacer is arranged on the pixel defining layer and includes a first portion and a second portion, and the second portion of the first spacer is arranged between the first portion of the first spacer and the substrate; and a first hole arranged separately from the first electrode in the display area, the first hole being formed in the second portion of the first spacer and the pixel defining layer, wherein the first hole has a first upper end portion and a second upper end portion, and a first height of the first upper end portion from the substrate is different from a second height of the second upper end portion from the substrate.

[0047] The first portion of the first spacer may have a width that increases toward the substrate, and the second portion of the first spacer may have a width that decreases toward the substrate.

[0048] The first height may be the same as a height of a top surface of the pixel defining layer from the substrate, and the second height may be the same as a height of a top surface of the second portion of the first spacer from the substrate.

[0049] The first height may be smaller than the second height. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The above and other characteristic aspects and features of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0051] Figure 1 is a plan view of a display device according to an exemplary embodiment of the present disclosure;

[0052] Figure 2A and Figure 2B is an equivalent circuit diagram of an example of one pixel included in a display device according to an exemplary embodiment of the present disclosure;

[0053] Figure 3 yes Figure 1 The floor plan of Area III;

[0054] Figure 4 It is along Figure 3 A cross-sectional view of the display device taken along line IVA-IVB;

[0055] Figure 5 is corresponding to Figure 4 A cross-sectional view of the shape of the pixel defining layer and the first spacer in region V;

[0056] 6A to 6F According to an exemplary embodiment of the present disclosure, Figure 4 A cross-sectional view of a manufacturing process for forming a first hole in a region V;

[0057] Figure 7 is a cross-sectional view of a portion of a display device according to an exemplary embodiment of the present disclosure;

[0058] Figure 8 is a cross-sectional view of a portion of a display device according to an exemplary embodiment of the present disclosure;

[0059] Fig. 9 is a cross-sectional view of a portion of a display device according to an exemplary embodiment of the present disclosure;

[0060] Fig.10 It is along Figure 1 A cross-sectional view of the display device taken along line XA-XB;

[0061] Fig.11 is a cross-sectional view of a portion of a display device according to an exemplary embodiment of the present disclosure;

[0062] Fig.12 yes Fig.11 A cross-sectional view of region XII;

[0063] Fig.13 yes Fig.11 A cross-sectional view of region XIII of ; and

[0064] FIG. 14A to FIG. 14F According to the exemplary embodiment of the present disclosure, Fig.11 A cross-sectional view of a process for a display device.

[0065] because Figures 1 to 14F The drawings in the drawings are intended for illustrative purposes, so the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for the purpose of clarity. DETAILED DESCRIPTION

[0066] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are shown in the accompanying drawings, wherein the same reference numerals throughout the text refer to the same elements. In this regard, the present exemplary embodiments may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the following, by reference to the figures, only exemplary embodiments are described to explain aspects of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout the present disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or its variations. In this specification, the expression "at least one of a and b" indicates only a, only b, both a and b, or its variations.

[0067] It will be understood that although the terms "first", "second", etc. are used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another component.

[0068] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0069] It will be further understood that the terms “comprises” and / or “comprising” used herein indicate the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0070] It will be understood that when a layer, region or component is referred to as being “formed on” another layer, region or component, it may be directly or indirectly formed on the other layer, region or component. That is, for example, intervening layers, regions or components may be present.

[0071] When a certain exemplary embodiment can be implemented differently, the specific process order can be performed differently from the described order. For example, two processes described successively can be performed substantially simultaneously, or in the reverse order of the described order.

[0072] It will be understood that when a layer, region, or component is referred to as being “connected” to another layer, region, or component, it may be “directly connected” to the other layer, region, or component, and / or may be “indirectly connected” to the other layer, region, or component, with other layers, regions, or components interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being “electrically connected” to another layer, region, or component, it may be “directly electrically connected” to the other layer, region, or component, and / or may be “indirectly electrically connected” to the other layer, region, or component, with other layers, regions, or components interposed therebetween.

[0073] The display device according to an exemplary embodiment of the present disclosure is a device that displays an image and may be various devices such as a liquid crystal display, an electrophoretic display, an organic light emitting display, an inorganic light emitting display, a field emission display, a surface conduction electron emitter display, a plasma display, and a cathode ray display.

[0074] Hereinafter, although the display device according to the exemplary embodiment of the present disclosure is described as an organic light emitting display device as an example, the display device according to the present disclosure is not limited thereto and may be various display devices.

[0075] Figure 1 is a plan view of a display device 1 according to an exemplary embodiment of the present disclosure, Figure 2A and Figure 2B is an equivalent circuit diagram of an example of one pixel included in the display device 1 according to the exemplary embodiment of the present disclosure, Figure 3 yes Figure 1 A floor plan of Zone III, and Figure 4 It is along Figure 3 A cross-sectional view of the display device 1 taken along line IVA-IVB.

[0076] refer to Figure 1, the display device 1 includes a display area DA arranged on a substrate 100. The display area DA includes pixels P connected to data lines DL and scan lines SL, the data lines DL extend in a first direction, and the scan lines SL extend in a second direction intersecting the first direction. Each pixel P may be connected to a driving voltage line PL extending in the first direction. In an exemplary embodiment of the present disclosure, a plurality of pixels P may be arranged in a matrix shape, but the present disclosure is not limited thereto. For example, a plurality of pixels P may be arranged in a pentile matrix shape or a diamond shape.

[0077] One pixel P may emit, for example, red light, green light, blue light, or white light, and may include, for example, an organic light emitting diode. Moreover, each pixel P may further include elements such as a thin film transistor and a capacitor. The display area DA may provide a predetermined image using light emitted from the pixel P. For example, in the display area DA, a plurality of pixels P may be arranged, for example, an array of pixels, and a predetermined image may be displayed via the array of pixels.

[0078] The display device 1 may include a non-display area NDA in which pixels P emitting light are not arranged. The non-display area NDA may include a first non-display area NDA1 and a second non-display area NDA2, the first non-display area NDA1 being arranged outside the display area DA and surrounding the display area DA, and the second non-display area NDA2 surrounding an opening area OA, the opening area OA being at least partially surrounded by the display area DA. For example, Figure 1 , the second non-display area NDA2 and the opening area OA are completely surrounded by the display area DA. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, a portion of the opening area OA is not surrounded by the display area DA.

[0079] A first power voltage line 10 and a second power voltage line 20 may be disposed in the first non-display area NDA1 , and the second power voltage line 20 provides a voltage different from that of the first power voltage line 10 .

[0080] The first power supply voltage line 10 may include a first main voltage line 11 and a first connection line 12 each arranged on one side of the display area DA. For example, in a case where the display area DA is rectangular, the first main voltage line 11 may be arranged to correspond to one of the sides of the display area DA. The first connection line 12 may extend from the first main voltage line 11 in a first direction and may be connected to the first terminal 32 of the terminal unit 30.

[0081] The second power supply voltage line 20 may include a second main voltage line 21 and a second connection line 22, the second main voltage line 21 surrounds two opposite end portions of the first main voltage line 11 and partially surrounds the display area DA, and the second connection line 22 extends from the second main voltage line 21 in the first direction. For example, in a case where the display area DA is rectangular, the second main voltage line 21 may extend along two opposite end portions of the first main voltage line 11 and the remaining sides of the display area DA except for one side adjacent to the first main voltage line 11. The second connection line 22 extends in a first direction parallel to the first connection line 12 and is connected to the second terminal 33 of the terminal unit 30. The second power supply voltage line 20 may be bent to surround the end portion of the first power supply voltage line 10.

[0082] The terminal unit 30 is arranged on one end portion of the substrate 100 and includes a plurality of terminals, i.e., a first terminal 32, a second terminal 33, and a third terminal 31. The terminal unit 30 may be exposed by not being covered by an insulating layer and electrically connected to a controller, such as a flexible printed circuit board (FPCB) or a driver integrated circuit (IC) chip. In an exemplary embodiment of the present disclosure, the FPCB may be electrically connected to the terminal unit 30 located at one side of the display device 1 in the first non-display area NDA1. The FPCB may be bent and electrically connected to the display device 1. Therefore, the FPCB used as a controller may output a signal to the display device 1 or receive a signal from the display device 1 through the terminal unit 30.

[0083] The controller may be configured to convert a plurality of image signals transmitted from the outside into a plurality of image data signals, and transmit the plurality of image data signals to the display area DA through the third terminal 31. Moreover, the controller may be configured to receive a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, generate a control signal for controlling the operation of the first gate driver and the second gate driver, and transmit the generated control signal to the first gate driver and the second gate driver through the terminal. Each of the control signals generated by the controller may include a vertical start signal for controlling the operation of the first gate driver and the second gate driver, and at least one clock signal for determining the output timing of the signal.

[0084] The controller may be configured to transmit different voltages to the first power voltage line 10 and the second power voltage line 20 through the first terminal 32 and the second terminal 33 , respectively.

[0085] The first power supply voltage line 10 can transmit the first power supply voltage ELVDD (see Figure 2A and Figure 2B ) is provided to each pixel P, and the second power supply voltage line 20 can provide the second power supply voltage ELVSS (see Figure 2A and Figure 2B ) is provided to each pixel P.

[0086] The first power supply voltage ELVDD may be supplied to each pixel P through the driving voltage line PL connected to the first power supply voltage line 10. The second power supply voltage ELVSS may be supplied to the organic light emitting diode OLED (see FIG. Figure 2A and Figure 2B ). In this case, the second main voltage line 21 of the second power voltage line 20 may be connected to the cathode of the organic light emitting diode OLED in the first non-display area NDA1.

[0087] A scan driver, a data driver, etc. may be further arranged in the first non-display area NDA1, the scan driver supplies a scan signal to the scan line SL of each pixel P, and the data driver supplies a data signal to the data line DL of each pixel P. The data driver may be located on one edge of the substrate 100, or may be located on an FPCB electrically connected to the terminal unit 30 at one side of the display device 1 located in the first non-display area NDA1.

[0088] The first dam portion 110 may be separated from the second dam portion 120 in the first non-display area NDA1 , and the first dam portion 110 and the second dam portion 120 each surround the display area DA.

[0089] The first dam portion 110 and the second dam portion 120 may be used to form a thin film encapsulation layer 400 (see FIG. 4 ) including an organic material (eg, Figure 4 ) monomer) of the organic encapsulation layer 420 (see Figure 4 and Figure 8 ) while blocking the organic material from flowing in the edge direction of the substrate 100. Therefore, the first dam portion 110 and the second dam portion 120 can prevent the edge tail of the organic encapsulation layer 420 from being formed at the edge of the substrate 100 (see Figure 8 ).like Figure 1 As shown in FIG. 1 , the first dam portion 110 and the second dam portion 120 may surround the display area DA.

[0090] refer to Figure 2A Each pixel P includes a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC, and the pixel circuit PC is connected to a scan line SL and a data line DL. Each pixel P can emit, for example, red light, green light, or blue light, or emit red light, green light, blue light, or white light via the organic light emitting diode OLED.

[0091] The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2 and a storage capacitor Cst. The switching thin film transistor T2 for controlling the pixel P to be turned on and off is configured to transmit a data signal Dm input through the data line DL to the driving thin film transistor T1 in response to a scan signal Sn input through the scan line SL.

[0092] The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL and may be configured to store a voltage corresponding to a difference between a voltage transmitted from the switching thin film transistor T2 and a first power source voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0093] The driving thin film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and can be configured to control the driving current flowing from the driving voltage line PL through the organic light emitting diode OLED in response to the voltage stored in the storage capacitor Cst. The organic light emitting diode OLED can be configured to emit light with a predetermined brightness according to the driving current. The on-time of the driving thin film transistor T1 can be determined according to the amount of the voltage stored in the storage capacitor Cst. The driving thin film transistor T1 can then provide the organic light emitting diode OLED with a first power supply voltage ELVDD transmitted through the driving voltage line PL during the on-time.

[0094] although Figure 2A , the pixel circuit PC includes two thin film transistors and one storage capacitor, but the present disclosure is not limited thereto. For example, the pixel circuit PC may include three, four, five, six, seven or more transistors instead of the two transistors. Moreover, more than one storage capacitor may be included in the pixel circuit PC.

[0095] refer to Figure 2B The pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, a first emission control thin film transistor T5, a second emission control thin film transistor T6 and a second initialization thin film transistor T7.

[0096] although Figure 2B , each pixel P includes signal lines SLn, SLn-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL, but the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, at least one of the signal lines SLn, SLn-1, EL, and DL and / or the initialization voltage line VL may be shared by pixels adjacent to each other.

[0097] The drain electrode of the driving thin film transistor T1 can be electrically connected to the anode (e.g., pixel electrode) of the organic light emitting diode OLED through the second emission control thin film transistor T6. The driving thin film transistor T1 is configured to receive the data signal Dm depending on the switching operation of the switching thin film transistor T2 and supply a driving current to the organic light emitting diode OLED.

[0098] The gate electrode of the switching thin film transistor T2 is connected to the first scan line SLn, and the source electrode of the switching thin film transistor T2 is connected to the data line DL. The drain electrode of the switching thin film transistor T2 can be connected to the source electrode of the driving thin film transistor T1 and simultaneously connected to the driving voltage line PL through the first emission control thin film transistor T5.

[0099] The switching thin film transistor T2 is turned on in response to a first scan signal Sn transmitted through the first scan line SLn, and is configured to perform a switching operation of transmitting a data signal Dm transmitted through the data line DL to a source electrode of the driving thin film transistor T1.

[0100] The gate electrode of the compensation thin film transistor T3 may be connected to the first scan line SLn. The source electrode of the compensation thin film transistor T3 may be connected to the drain electrode of the driving thin film transistor T1, and simultaneously connected to the pixel electrode of the organic light emitting diode OLED through the second emission control thin film transistor T6. The drain electrode of the compensation thin film transistor T3 may be simultaneously connected to one of the electrodes of the storage capacitor Cst, the source electrode of the first initialization thin film transistor T4, and the gate electrode of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on in response to the first scan signal Sn transmitted through the first scan line SLn, and is configured to diode-connect the driving thin film transistor T1 by connecting the gate electrode of the driving thin film transistor T1 to the drain electrode of the driving thin film transistor T1.

[0101] The gate electrode of the first initialization thin film transistor T4 may be connected to the second scan line SLn-1 (also referred to as the previous scan line). The drain electrode of the first initialization thin film transistor T4 may be connected to the initialization voltage line VL. The source electrode of the first initialization thin film transistor T4 may be simultaneously connected to one of the electrodes of the storage capacitor Cst, the drain electrode of the compensation thin film transistor T3, and the gate electrode of the driving thin film transistor T1. The first initialization thin film transistor T4 may be turned on in response to the second scan signal Sn-1 transmitted through the second scan line SLn-1, and is configured to transmit the initialization voltage VINT to the gate electrode of the driving thin film transistor T1, thereby performing an initialization operation of initializing the voltage of the gate electrode of the driving thin film transistor T1.

[0102] The gate electrode of the first emission control thin film transistor T5 may be connected to the emission control line EL. The source electrode of the first emission control thin film transistor T5 may be connected to the driving voltage line PL. The drain electrode of the first emission control thin film transistor T5 is connected to the source electrode of the driving thin film transistor T1 and the drain electrode of the switching thin film transistor T2.

[0103] The gate electrode of the second emission control thin film transistor T6 may be connected to the emission control line EL. The source electrode of the second emission control thin film transistor T6 may be connected to the drain electrode of the driving thin film transistor T1 and the source electrode of the compensation thin film transistor T3. The drain electrode of the second emission control thin film transistor T6 may be electrically connected to the pixel electrode of the organic light emitting diode OLED. The first emission control thin film transistor T5 and the second emission control thin film transistor T6 are simultaneously turned on in response to the emission control signal En received through the emission control line EL, the first power supply voltage ELVDD is transmitted to the organic light emitting diode OLED, and the driving current flows through the organic light emitting diode OLED.

[0104] The gate electrode of the second initialization thin film transistor T7 may be connected to the second scan line SLn-1. The source electrode of the second initialization thin film transistor T7 may be connected to the pixel electrode of the organic light emitting diode OLED. The drain electrode of the second initialization thin film transistor T7 may be connected to the initialization voltage line VL. The second initialization thin film transistor T7 may be turned on in response to the second scan signal Sn-1 transmitted through the second scan line SLn-1 to initialize the pixel electrode of the organic light emitting diode OLED.

[0105] although Figure 2B , the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the second scan line SLn-1, but the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the first initialization thin film transistor T4 may be connected to the second scan line SLn-1 (which is the previous scan line) and driven in response to the second scan signal Sn-1, and the second initialization thin film transistor T7 may be connected to a separate signal line (e.g., the next scan line) and driven in response to a signal transmitted through the separate signal line.

[0106] One of the electrodes of the storage capacitor Cst may be simultaneously connected to the gate electrode of the driving thin film transistor T1, the drain electrode of the compensation thin film transistor T3, and the source electrode of the first initialization thin film transistor T4. The other electrode of the storage capacitor Cst may be connected to the driving voltage line PL. In an exemplary embodiment of the present disclosure, an additional capacitor may be formed so that the potential on the gate electrode of the driving thin film transistor T1 is increased to a predetermined level by the voltage of the first scan signal Sn. One end of the additional capacitor may be connected to the first scan line SLn, and the other end of the additional capacitor may be connected to the drain electrode of the compensation thin film transistor T3 and the gate electrode of the driving thin film transistor T1.

[0107] An opposite electrode (eg, cathode) of the organic light emitting diode OLED is configured to receive a second power voltage ELVSS (or a common power voltage). The organic light emitting diode OLED receives a driving current from the driving thin film transistor T1 and emits light to display an image.

[0108] The pixel circuit PC is not limited to the reference Figure 2A and Figure 2B The number of thin film transistors, the number of capacitors, and the circuit design described above can be variously changed.

[0109] refer to Figure 3 , multiple pixels P are arranged in Figure 1 The plurality of pixels P are surrounded by the pixel defining layer 113, and the first spacer 115-1 is disposed on the pixel defining layer 113. The plurality of first holes TH1 are disposed between the pixels P, and the plurality of first holes TH1 pass through the insulating layer.

[0110] although Figure 3 2 shows that the pixels P have a quadrilateral shape of the same size, but this is provided as an example, and the present disclosure is not limited thereto. For example, the size, shape, and arrangement of the pixels P may be changed.

[0111] The first spacer 115-1 may be disposed between some of the pixels P among the plurality of pixels P. When the intermediate layer 320 including the emission layer is deposited using a mask (see Figure 4 ), the first spacer 115-1 maintains separation between the mask and the substrate 100 to prevent the intermediate layer 320 from being cut or torn by the mask during the deposition process.

[0112] The first spacer 115-1 may include the same material as that of the pixel defining layer 113. While the pixel defining layer 113 is formed by using a halftone mask, the first spacer 115-1 may be simultaneously formed with the pixel defining layer 113 at a height different from that of the pixel defining layer 113 by using the same material as that of the pixel defining layer 113.

[0113] The first hole TH1 may be disposed between some pixels P among the plurality of pixels P, and may include a predetermined open space passing through a portion of the first spacer 115-1 and a portion of the pixel defining layer 113 to fix the thin film encapsulation layer 400 described below to the back plate. The back plate may be a structure of the display device 1 just before forming the thin film encapsulation layer 400. For example, the first hole TH1 may serve as an anchor, and thus may increase the contact strength between the thin film encapsulation layer 400 and the back plate.

[0114] refer to Figure 4 , a buffer layer 101 is disposed on the substrate 100 , and a driving thin film transistor T1 , a switching thin film transistor T2 , and a storage capacitor Cst are disposed on the buffer layer 101 .

[0115] The substrate 100 may include various materials, such as, for example, glass, metal or plastic. For example, the substrate 100 may include a flexible substrate including a polymer resin, such as, for example, polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC) or cellulose acetate propionate (CAP).

[0116] The buffer layer 101 may be provided on the substrate 100 and may include an inorganic insulating (insulating) material such as, for example, silicon oxide (SiO x ), silicon oxynitride (SiON) and / or silicon nitride (SiN x ), and may be formed to prevent penetration of impurities. The buffer layer 101 may be a single layer or a multilayer including an inorganic insulating material.

[0117] The driving thin film transistor T1 includes a driving semiconductor layer A1 and a driving gate electrode G1, and the switching thin film transistor T2 includes a switching semiconductor layer A2 and a switching gate electrode G2. The first gate insulating layer 103 is arranged between the driving semiconductor layer A1 and the driving gate electrode G1 and between the switching semiconductor layer A2 and the switching gate electrode G2. The first gate insulating layer 103 may include an inorganic insulating material such as, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), lanthanum oxide (La 2 O 3 )、ZrO2 ), hafnium oxide (HfO 2 ) etc. The first gate insulating layer 103 may be a single layer or multiple layers including the aforementioned materials.

[0118] The driving semiconductor layer A1 and the switching semiconductor layer A2 may include amorphous silicon (a-Si) or polycrystalline silicon (p-Si). In an exemplary embodiment of the present disclosure, the driving semiconductor layer A1 and the switching semiconductor layer A2 may include, for example, an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn).

[0119] The driving semiconductor layer A1 may include a driving channel region, a driving source region, and a driving drain region, the driving channel region overlaps with the driving gate electrode G1 and is not doped with impurities, and the driving source region and the driving drain region are on two opposite sides of the driving channel region and are doped with impurities. For example, the driving source region and the driving drain region may be doped with n-type dopants or p-type dopants. The driving source electrode S1 and the driving drain electrode D1 may be connected to the driving source region and the driving drain region, respectively.

[0120] The switch semiconductor layer A2 may include a switch channel region, a switch source region, and a switch drain region, the switch channel region overlaps with the switch gate electrode G2 and is not doped with impurities, and the switch source region and the switch drain region are on two opposite sides of the switch channel region and are doped with impurities. For example, the switch source region and the switch drain region may be doped with n-type dopants or p-type dopants. The switch source electrode S2 and the switch drain electrode D2 may be connected to the switch source region and the switch drain region, respectively.

[0121] The driving source electrode S1, the driving drain electrode D1, the switching source electrode S2, and the switching drain electrode D2 may each include a highly conductive material. Each of the driving source electrode S1, the driving drain electrode D1, the switching source electrode S2, and the switching drain electrode D2 may include a conductive material, such as silver (Ag), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), nickel (Ni), titanium (Ti), alloys thereof, etc., and may be a multilayer or a single layer including the aforementioned materials. In an exemplary embodiment of the present disclosure, each of the driving source electrode S1, the driving drain electrode D1, the switching source electrode S2, and the switching drain electrode D2 may be formed as a multilayer of titanium / aluminum / titanium (Ti / Al / Ti).

[0122] The driving gate electrode G1 and the switching gate electrode G2 may each include a single layer or multiple layers including at least one of, for example, silver (Ag), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), nickel (Ni), titanium (Ti), and alloys thereof.

[0123] In an exemplary embodiment of the present disclosure, the storage capacitor Cst may overlap with the driving thin film transistor T1. In this case, the area of ​​the storage capacitor Cst and the driving thin film transistor T1 may be increased and a high-quality image may be provided. For example, the driving gate electrode G1 may be used as a first storage capacitor plate CE1 of the storage capacitor Cst. The second storage capacitor plate CE2 of the storage capacitor Cst may overlap with the first storage capacitor plate CE1, with the second gate insulating layer 105 interposed therebetween. The second gate insulating layer 105 may include an inorganic insulating material such as, for example, silicon oxide (SiO x ), silicon nitride (SiN x ) and / or silicon oxynitride (SiON). The second storage capacitor plate CE2 of the storage capacitor Cst may include a conductive material including, for example, silver (Ag), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), nickel (Ni), titanium (Ti), alloys thereof, etc., and may be a multilayer or single layer including the foregoing materials.

[0124] The driving thin film transistor T1 , the switching thin film transistor T2 , and the storage capacitor Cst may be covered by the interlayer insulating layer 107 .

[0125] The interlayer insulating layer 107 may include an inorganic material such as, for example, silicon oxide (SiO x ), silicon nitride (SiN x ) and / or silicon oxynitride (SiON).

[0126] The data line DL is disposed on the interlayer insulating layer 107. The data line DL is connected to the switching semiconductor layer A2 of the switching thin film transistor T2 through a contact hole passing through the interlayer insulating layer 107. The data line DL may function as a switching source electrode S2.

[0127] The driving source electrode S1 , the driving drain electrode D1 , the switching source electrode S2 , and the switching drain electrode D2 may be disposed on the interlayer insulating layer 107 , and may be connected to the driving semiconductor layer A1 or the switching semiconductor layer A2 through a contact hole passing through the interlayer insulating layer 107 .

[0128] The data line DL, the driving source electrode S1 , the driving drain electrode D1 , the switching source electrode S2 , and the switching drain electrode D2 may be covered by an inorganic protective layer.

[0129] The inorganic protective layer may include silicon oxide (SiO x ) and silicon nitride (SiN x The inorganic protective layer may prevent some wirings exposed in the first non-display area NDA1 (e.g., wirings formed simultaneously during the same process as that of forming the data line DL) from being damaged by an etchant used while patterning the pixel electrode 310.

[0130] The driving voltage line PL may be arranged on a layer different from the layer on which the data line DL is arranged. In this specification, when A and B are referred to as being arranged on different layers, at least one insulating layer is arranged between A and B, one of A and B is arranged under at least one insulating layer, and the other of A and B is arranged over at least one insulating layer. The first planarization layer 109 may be arranged between the driving voltage line PL and the data line DL, and the driving voltage line PL may be covered by the second planarization layer 111.

[0131] The driving voltage line PL may include a single layer or multiple layers including at least one of aluminum (Al), copper (Cu), titanium (Ti), and alloys thereof. In an exemplary embodiment of the present disclosure, the driving voltage line PL may include three layers of titanium / aluminum / titanium (Ti / Al / Ti).

[0132] although Figure 4 A configuration is shown in which the driving voltage line PL is arranged on the first planarization layer 109, but the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the driving voltage line PL may be connected to a lower additional voltage line arranged on the same layer on which the data line DL is arranged through a through hole formed in the first planarization layer 109 to reduce resistance.

[0133] Each of the first planarization layer 109 and the second planarization layer 111 may include a single layer or a plurality of layers.

[0134] The first planarization layer 109 and the second planarization layer 111 may include an organic insulating material. For example, the organic insulating material may include a general polymer (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof.

[0135] The first planarization layer 109 and the second planarization layer 111 may include an inorganic insulating material. For example, the inorganic insulating material may include silicon oxide (SiO x ), silicon nitride (SiN x ) and / or silicon oxynitride (SiON).

[0136] The organic light emitting diode OLED may be positioned on the second planarization layer 111 and may include a pixel electrode 310 , an opposing electrode 330 , and an intermediate layer 320 interposed between the pixel electrode 310 and the opposing electrode 330 , the intermediate layer 320 including an emission layer 320 b .

[0137] The pixel electrode 310 is connected to a connection line CL formed on the first planarization layer 109, and the connection line CL is connected to the driving drain electrode D1 of the driving thin film transistor T1. The connection line CL may include a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), alloys thereof, etc., and may be formed as a multilayer or a single layer including the foregoing materials. The connection line CL may include the same material as that included in the driving source electrode S1, the driving drain electrode D1, the switching source electrode S2, and the switching drain electrode D2. For example, the connection line CL may be formed as a multilayer of titanium / aluminum / titanium (Ti / Al / Ti).

[0138] The pixel electrode 310 may include a transparent electrode or a reflective electrode.

[0139] In the case where the pixel electrode 310 includes a transparent electrode, the pixel electrode 310 may include a transparent conductive layer. The transparent conductive layer may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In this case, in addition to the transparent conductive layer, the pixel electrode 310 may further include a semi-transmissive layer to improve light efficiency, the semi-transmissive layer including a thin film ranging from several micrometers to tens of micrometers and including, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) and ytterbium (Yb) At least one.

[0140] In the case where the pixel electrode 310 includes a reflective electrode, the pixel electrode 310 may include a reflective layer and a transparent conductive layer on and / or below the reflective layer, the reflective layer including, for example, at least one of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and compounds thereof. The transparent conductive layer may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), at least one of indium gallium oxide (IGO) and aluminum zinc oxide (AZO). However, the present disclosure is not limited thereto, and the pixel electrode 310 may include various materials and have various structures including a single layer and / or a multilayer.

[0141] The pixel defining layer 113 may be disposed on the pixel electrode 310 .

[0142] The pixel defining layer 113 defines the pixel P by including the first opening OP1 exposing the pixel electrode 310, and may cover the edge of the pixel electrode 310. Also, the pixel defining layer 113 may prevent arcing from occurring at an end portion of the pixel electrode 310 by increasing a distance between the edge of the pixel electrode 310 and the opposite electrode 330. The pixel defining layer 113 may include an organic material such as, for example, polyimide (PI) or hexamethyldisiloxane (HMDSO).

[0143] The intermediate layer 320 includes an emission layer 320b. The intermediate layer 320 may include a first functional layer 320a and / or a second functional layer 320c, the first functional layer 320a being arranged below the emission layer 320b, and the second functional layer 320c being arranged on the emission layer 320b. The emission layer 320b may include a polymer organic material or a low molecular weight organic material each emitting light having a predetermined color. In an exemplary embodiment of the present disclosure, the emission layer 320b may include at least one of a material emitting red light, green light, and blue light, and may include a fluorescent material or a phosphorescent material.

[0144] The first functional layer 320a may include a single layer or multiple layers. For example, in the case where the first functional layer 320a includes a polymer organic material, the first functional layer 320a is a hole transport layer (HTL) having a single layer structure and may include poly (3,4-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). In the case where the first functional layer 320a includes a low molecular weight organic material, the first functional layer 320a may include a hole injection layer (HIL) and a hole transport layer (HTL).

[0145] The second functional layer 320c may be omitted. For example, in the case where the first functional layer 320a and the emission layer 320b include a polymer organic material, the second functional layer 320c may be formed. The second functional layer 320c may include a single layer or multiple layers. The second functional layer 320c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). For example, the intermediate layer 320 may include at least one of a hole transport layer (HTL), a hole injection layer (HIL), an electron injection layer (EIL), and an electron transport layer (ETL).

[0146] For each pixel P in the display area DA, an emission layer 320b of the intermediate layer 320 may be arranged. The emission layer 320b may be formed on a portion of the pixel electrode 310 exposed through the first opening OP1 of the pixel defining layer 113. The emission layer 320b may be arranged to overlap with the first opening OP1 of the pixel defining layer 113 and / or the pixel electrode 310. The first functional layer 320a and the second functional layer 320c of the intermediate layer 320 may be formed as an integral layer common to a plurality of pixel electrodes 310, and thus may be formed not only in the display area DA but also in the first non-display area NDA1, while the emission layer 320b is formed only in the display area DA. The intermediate layer 320 may be formed by various methods such as vacuum deposition.

[0147] The opposing electrode 330 may be arranged in the display area DA and may cover the display area DA. That is, the opposing electrode 330 may be formed as one body over the plurality of organic light emitting diodes OLED to correspond to the plurality of pixel electrodes 310. The opposing electrode 330 is electrically connected to the second power supply voltage line 20 (see FIG. 1 ) described below. Figure 1 ).

[0148] The opposing electrode 330 may include a transparent electrode or a reflective electrode. In the case where the opposing electrode 330 includes a transparent electrode, the opposing electrode 330 may include, for example, at least one of silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), calcium (Ca), copper (Cu), lithium fluoride / calcium (LiF / Ca), lithium fluoride / aluminum (LiF / Al), magnesium-silver (MgAg) and calcium-silver (CaAg), and may include a thin film having a thickness ranging from several microns to tens of microns. Alternatively, the opposing electrode 330 may include a thin film having a thickness ranging from several nanometers to hundreds of nanometers.

[0149] In the case where the opposing electrode 330 includes a reflective electrode, the opposing electrode 330 may include, for example, at least one of silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), calcium (Ca), copper (Cu), lithium fluoride / calcium (LiF / Ca), lithium fluoride / aluminum (LiF / Al), magnesium-silver (MgAg), and calcium-silver (CaAg). However, the composition and material of the opposing electrode 330 are not limited thereto and may be variously changed. The opposing electrode 330 may be formed not only in the display area DA but also in the first non-display area NDA1.

[0150] The first spacer 115-1 is disposed on the pixel defining layer 113 and protrudes in a direction from the pixel defining layer 113 to the thin film encapsulation layer 400. During a process of depositing the intermediate layer 320 including the emission layer 320b by using a mask, the first spacer 115-1 maintains separation between the mask and the substrate 100 to prevent the intermediate layer 320 from being cut or torn by the mask during the deposition process.

[0151] The first spacer 115-1 may include an organic material such as, for example, polyimide (PI) or hexamethyldisiloxane (HMDSO). For example, the first spacer 115-1 may include the same material as that of the pixel defining layer 113. The first spacer 115-1 may be arranged between the first dam portion 110 and the second dam portion 120 described below (see Figure 1 ) and can be used to prevent moisture from penetrating and can form a step difference in the dam portion.

[0152] Since the organic light emitting diode OLED may be easily damaged by external moisture or oxygen, the organic light emitting diode OLED may be covered and protected by the thin film encapsulation layer 400 .

[0153] The thin film encapsulation layer 400 may cover the display area DA and extend outside the display area DA. For example, the thin film encapsulation layer 400 may encapsulate the display area DA. Since the display area DA includes a plurality of pixels P, the thin film encapsulation layer 400 may encapsulate the plurality of pixels P. The thin film encapsulation layer 400 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. In an exemplary embodiment of the present disclosure, the thin film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.

[0154] The first inorganic encapsulation layer 410 may completely cover the opposite electrode 330 and may include, for example, silicon oxide (SiO x ), silicon nitride (SiN x ) and / or silicon oxynitride (SiON).

[0155] When necessary, other layers (such as a capping layer) may be disposed between the first inorganic encapsulation layer 410 and the opposite electrode 330. For example, in order to improve light efficiency, the capping layer may include a silicon oxide (SiO x ), silicon nitride (SiN x )、ZnO、TiO 2 )、ZrO 2 ), indium tin oxide (ITO), indium zinc oxide (IZO), tris-(8-hydroxyquinoline) aluminum (Alq 3), copper (II) phthalocyanine (CuPc), (4,4'-N,N'-dicarbazole) biphenyl (CBP) and N,N'-di-[(1-naphthyl)-N,N'-diphenyl]-1,1'-biphenyl)-4,4'-diamine (a-NPB). In an exemplary embodiment of the present disclosure, the capping layer may allow plasma resonance to occur relative to the light generated by the organic light emitting diode OLED. For example, the capping layer may include nanoparticles. The capping layer may prevent the organic light emitting diode OLED from being damaged by heat, plasma, etc. that occur during a chemical vapor deposition (CVD) process or a sputtering process for forming the thin film encapsulation layer 400. For example, the capping layer may include an epoxy-based material, the epoxy-based material including, for example, at least one of a bisphenol-type epoxy resin, an epoxidized butadiene resin, a fluorine-type epoxy resin, and a phenolic epoxy resin. The capping layer may have an area larger than that of the opposite electrode 330 so that an end of the opposite electrode 330 is covered, thereby preventing oxidation of the opposite electrode 330 during a chemical vapor deposition (CVD) process or a sputtering process of forming the thin film encapsulation layer 400 .

[0156] When necessary, a layer including lithium fluoride (LiF) or the like may be disposed between the first inorganic encapsulating layer 410 and the capping layer.

[0157] Because the first inorganic encapsulation layer 410 is formed along the structure below it, the top surface of the first inorganic encapsulation layer 410 is not flat. For example, the first inorganic encapsulation layer 410 may be conformally formed on the structure below it. The organic encapsulation layer 420 covers the first inorganic encapsulation layer 410 and may be planarized. For example, the organic encapsulation layer 420 may be formed on the first inorganic encapsulation layer 410 by a spin coating process. The top surface of the organic encapsulation layer 420 corresponding to the display area DA may be approximately flat.

[0158] The organic encapsulation layer 420 may include, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyimide (PI), polyvinyl sulfonate (PES), polyoxymethylene (POM), polyarylate (PAR), hexamethyldisiloxane (HMDSO), acrylic resin (e.g., polymethyl methacrylate (PMMA), polyacrylic acid (PAA), etc.), or any combination thereof.

[0159] The second inorganic encapsulating layer 430 may cover the organic encapsulating layer 420 and may include, for example, silicon oxide (SiO x ), silicon nitride (SiN x) and / or silicon oxynitride (SiON). Because the second inorganic encapsulation layer 430 is deposited to directly contact the first inorganic encapsulation layer 410 in the edge region of the display device 1, the second inorganic encapsulation layer 430 can seal the organic encapsulation layer 420 so that the organic encapsulation layer 420 is not exposed to the outside. Therefore, it is possible to prevent or reduce the penetration of moisture or oxygen into the display area DA through the organic encapsulation layer 420.

[0160] During a subsequent process after the thin film encapsulation layer 400 is formed, for example, during a process of forming a touch sensor layer on the thin film encapsulation layer 400 or removing a protective film that has been adhered to the thin film encapsulation layer 400 before attaching a polarizing film on the thin film encapsulation layer 400, a defect in which the thin film encapsulation layer 400 may be peeled off from the backplane of the display device 1 may occur. The backplane may be a structure of the display device 1 just before the thin film encapsulation layer 400 is formed. For example, in a case where the opposite electrode 330 is formed just before the thin film encapsulation layer 400 is formed, a peeling defect may occur between the thin film encapsulation layer 400 and the display device 1 including the opposite electrode 330. For example, in a case where a capping layer is formed between the thin film encapsulation layer 400 and the opposite electrode 330 just before the thin film encapsulation layer 400 is formed, a peeling defect may occur between the thin film encapsulation layer 400 and the display device 1 including the capping layer. For example, in a case where a layer containing LiF is formed between the capping layer and the first inorganic encapsulation layer 410, a peeling defect may occur between the thin film encapsulation layer 400 and the display device 1 including the layer containing LiF. In addition, in the case where another functional layer is further added between the opposite electrode 330 and the thin film encapsulation layer 400 just before forming the thin film encapsulation layer 400, the display device 1 including the organic light emitting diode OLED and the functional layer may be understood as a backplane.

[0161] In order to reduce the peeling defect of the thin film encapsulation layer 400, the present exemplary embodiment may increase the contact strength between the thin film encapsulation layer 400 and the back plate by forming a plurality of first holes TH1 serving as anchors for the thin film encapsulation layer 400 between the plurality of pixels P in the display area DA. For example, the plurality of first holes TH1 may enhance the adhesive force between the thin film encapsulation layer 400 and the back plate, thereby reducing the peeling defect of the thin film encapsulation layer 400.

[0162] The first hole TH1 is formed to pass through a portion of the first spacer 115 - 1 and a portion of the pixel defining layer 113 and may have a predetermined opening space, and the first hole TH1 is arranged in a position separated from the pixel electrode 310 .

[0163] The first hole TH1 may have a first upper end UE1 and a second upper end UE2 having different heights from the substrate 100. A first height H1 from the substrate 100 to the first upper end UE1 of the first hole TH1 is the same as a height from the substrate 100 to the top surface of the pixel defining layer 113, and a second height H2 from the substrate 100 to the second upper end UE2 of the first hole TH1 is the same as a height from the substrate 100 to the top surface of the second portion SP2 of the first spacer 115-1. That is, the second height H2 is greater than the first height H1.

[0164] In a virtual boundary surface between the first portion SP1 and the second portion SP2 of the first spacer 115-1, the bottom surface of the first portion SP1 of the first spacer 115-1 may coincide with the top surface of the second portion SP2 of the first spacer 115-1. On the other hand, because the first portion SP1 of the first spacer 115-1 is located above the second portion SP2, the third height H3 (which is the height from the substrate 100 to the top surface of the first portion SP1) is higher than the second height H2.

[0165] refer to Figure 5 , which is Figure 4 1 and 15 - 1 in a cross-sectional view of the shape of the pixel defining layer 113 and the first spacer 115 - 1 in the region V in which the first hole TH1 is formed, the first hole TH1 is formed to have an undercut shape UC in the second portion SP2 of the first spacer 115 - 1 and the pixel defining layer 113 .

[0166] The first spacer 115-1 may include a first portion SP1 and a second portion SP2, the first portion SP1 having a width that increases from a direction away from the substrate 100 toward the substrate 100, and the second portion SP2 being arranged between the first portion SP1 and the substrate 100 and having a width that decreases toward the substrate 100. For example, a first width W1 of the first spacer 115-1 at any point of the first portion SP1 in a direction parallel to the substrate 100 increases from a point L2 to a point L1, the point L2 is farthest from the substrate 100, and the point L1 is closer to the substrate 100 than the point L2. A second width W2 of the first spacer 115-1 at any point of the second portion SP2 in a direction parallel to the substrate 100 may decrease from a point L1 to a point L0. Figure 5, point L0 may be at the lowest level of the first spacer 115-1, point L2 may be at the highest level of the first spacer 115-1, and point L1 may be at a level where the first portion SP1 and the second portion SP2 intersect, for example, at an interface between the first portion SP1 and the second portion SP2. Alternatively, a tangent line l1 at any point on the surface of the first portion SP1 of the first spacer 115-1 (for example, a point selected at the right surface of the first spacer 115-1) may form an acute angle θ1 in the clockwise direction with respect to an imaginary line parallel to the substrate 100. A tangent line l2 at any point on the surface of the second portion SP2 of the first spacer 115-1 (for example, a point selected at the right surface of the first spacer 115-1) may form an obtuse angle θ2 in the clockwise direction with respect to an imaginary line parallel to the substrate 100. That is, the first portion SP1 as the top area of ​​the first spacer 115-1 may be a forward tapered shape, and the second portion SP2 as the bottom area of ​​the first spacer 115-1 may be an inverted tapered shape.

[0167] When the top region of the first spacer 115-1 is formed in an inverted tapered shape, the contact area between the mask and the first spacer 115-1 increases during a process of depositing the intermediate layer 320 including the emission layer 320b by using a mask, and the number of particles generated by the mask may increase. In contrast, according to the present exemplary embodiment, since the top region of the first spacer 115-1 is formed in a forward tapered shape, the number of particles generated by the mask may decrease.

[0168] Since the second portion SP2 as the bottom area of ​​the first spacer 115 - 1 is formed in an inverted tapered shape, the second portion SP2 cooperates with a portion of the pixel defining layer 113 to constitute the first hole TH1 , which constitutes a predetermined open space.

[0169] Reference again Figure 4 , the intermediate layer 320 and the opposite electrode 330 may be formed on the bottom surface of the first hole TH1. The deposition of the intermediate layer 320 and the opposite electrode 330 on the bottom surface of the first hole TH1 may be non-conformal.

[0170] The first functional layer 320a and the second functional layer 320c of the intermediate layer 320 may be formed inside the first hole TH1, and the emission layer 320b of the intermediate layer 320 may not be formed inside the first hole TH1. This is because the emission layer 320b may be deposited only in the emission area patterned for each pixel by the patterned mask, and the first functional layer 320a and the second functional layer 320c may be deposited on all pixels as a common layer without being patterned for each pixel. For example, the first functional layer 320a and the second functional layer 320c may be formed not only in the area above the pixel, but also in the area between the pixels. Like the first functional layer 320a and the second functional layer 320c, the relative electrode 330 may be deposited on all pixels as a common layer. For example, the relative electrode 330 may be formed not only in the area above the pixel, but also in the area between the pixels.

[0171] The first inorganic encapsulation layer 410 of the thin film encapsulation layer 400 is formed on the opposite electrode 330 inside the first hole TH1. The first inorganic encapsulation layer 410 is formed not only on the bottom surface of the first hole TH1 but also on the entire inner surface of the first hole TH1 including the bottom surface of the first hole TH1 above the opposite electrode 330. The deposition of the first inorganic encapsulation layer 410 on the bottom surface of the first hole TH1 above the opposite electrode 330 may be conformal.

[0172] Although the first inorganic encapsulation layer 410 directly contacts the opposite electrode 330 on the bottom surface inside the first hole TH1, the first inorganic encapsulation layer 410 may directly contact the pixel defining layer 113 and the first spacer 115-1 on the lateral surface of the first hole TH1. Therefore, the contact area between the first inorganic encapsulation layer 410 and the organic insulating layer increases, and thus the adhesion of the thin film encapsulation layer 400 may be enhanced.

[0173] The organic encapsulation layer 420 fills the entire inner side of the first hole TH1. In particular, according to the present exemplary embodiment, since the shape of the opening formed in the first hole TH1 is an undercut shape UC in which the first portion SP1 protrudes further than the second portion SP2 at the interface between the first portion SP1 and the second portion SP2 of the first spacer 115-1, and the organic encapsulation layer 420 fills the opening having the undercut shape UC, the first hole TH1 serves as an anchor, and thus the contact strength between the thin film encapsulation layer 400 and the back plate can be increased.

[0174] As described above, the display device 1 according to the present exemplary embodiment can increase the contact strength between the thin film encapsulation layer 400 and the back plate by forming a plurality of first holes TH1 between a plurality of pixels in the display area DA, thereby reducing a defect in which the thin film encapsulation layer 400 is peeled off from the back plate. Moreover, particles generated by the deposition mask can be reduced by forming the top portion of the first spacer 115-1 in a forward tapered shape, and the contact strength between the thin film encapsulation layer 400 and the back plate can be increased by forming the bottom area of ​​the first spacer 115-1 in an inverted tapered shape and thereby disconnecting the intermediate layer 320 and the common electrode 330 (or the opposite electrode 330) inside and outside the first hole TH1 having an undercut shape UC.

[0175] In the following, reference 6A to 6F Describe the formation Figure 4 FIG. 1 is a manufacturing process of the first hole TH1.

[0176] 6A to 6F According to an exemplary embodiment of the present disclosure, Figure 4 4 is a cross-sectional view of a manufacturing process of forming the first hole TH1 in the region V of FIG.

[0177] refer to Fig. 6A , the first spacer 115-1 is located on the pixel defining layer 113. Fig. 6A , the pixel defining layer 113 and the first spacer 115-1 are shown as different layers with different hatching, but the present disclosure is not limited thereto. For example, the pixel defining layer 113 and the first spacer 115-1 may include the same material. For example, the pixel defining layer 113 and the first spacer 115-1 may be formed simultaneously during the same process by using a halftone mask. For example, the pixel defining layer 113 and the first spacer 115-1 may each include an organic material, such as, for example, polyimide (PI) or hexamethyldisiloxane (HMDSO).

[0178] refer to Figure 6B The barrier layer BL is formed by a deposition process on Fig. 6A The second opening OP2 is formed on the structure of the first spacer 115 - 1 by patterning the barrier layer BL, and the second opening OP2 exposes a portion of the pixel defining layer 113 and a portion of the surface of the bottom region of the first spacer 115 - 1 .

[0179] refer to Figure 6C The first hole TH1 is formed by etching a portion of the pixel defining layer 113 and a portion of the first spacer 115 - 1 each corresponding to the second opening OP2 using the barrier layer BL as an etching mask. The first hole TH1 may be formed by dry etching.

[0180] refer to Fig.6D , the barrier layer BL is removed by wet etching.

[0181] The second portion SP2, which is a dry-etched region of the first spacer 115-1, may have an inverted tapered shape in which the second width W2 of the first spacer 115-1 decreases toward the substrate 100, and the first portion SP1, which is a non-etched region of the first spacer 115-1, may have a forward tapered shape in which the first width W1 of the first spacer 115-1 increases toward the substrate 100. Therefore, the first hole TH1 may have an undercut shape UC in which the first portion SP1 further protrudes than the second portion SP2 at an interface between the first portion SP1 and the second portion SP2 of the first spacer 115-1. For example, the undercut shape UC of the first hole TH1 is formed in the second portion SP2 of the first spacer 115-1 and the pixel defining layer 113 on one side of the first spacer 115-1, and the first hole TH1 passes through a portion of the first spacer 115-1 and a portion of the pixel defining layer 113.

[0182] refer to Fig. 6E , the intermediate layer 320 and the opposite electrode 330 are deposited in the first hole TH1. The intermediate layer 320 and the opposite electrode 330 are formed on the bottom surface of the first hole TH1, the top surface of the pixel defining layer 113 outside the first hole TH1, and the top surface of the first spacer 115-1. That is, the intermediate layer 320 and the opposite electrode 330 may be disconnected around the undercut shape UC of the first hole TH1. For example, the intermediate layer 320 and the opposite electrode 330 may be formed inside and outside the first hole TH1 so that the intermediate layer 320 and the opposite electrode 330 are disconnected inside and outside the first hole TH1. The intermediate layer 320 formed in the first hole TH1 may include a first functional layer 320a and a second functional layer 320c, and may not include an emission layer 320b.

[0183] The intermediate layer 320 and the opposite electrode 330 may be formed by physical vapor deposition (PVD) with poor step coverage. Therefore, the intermediate layer 320 and the opposite electrode 330 may be formed non-conformally on the bottom surface of the first hole TH1, the top surface of the pixel defining layer 113 outside the first hole TH1, and the top surface of the first spacer 115-1. For example, the intermediate layer 320 and the opposite electrode 330 may be formed by, for example, one of sputtering, thermal evaporation, electron beam evaporation, laser molecular beam epitaxy, and pulsed laser deposition.

[0184] refer to Fig. 6F , a thin film encapsulation layer 400 is formed in the first hole TH1 , and the thin film encapsulation layer 400 includes a first inorganic encapsulation layer 410 , an organic encapsulation layer 420 , and a second inorganic encapsulation layer 430 .

[0185] The first inorganic encapsulation layer 410 is stacked not only on the bottom surface of the first hole TH1 above the opposing electrode 330 inside the first hole TH1, but also on the entire inner surface of the first hole TH1. Moreover, the first inorganic encapsulation layer 410 is formed on the top surface of the pixel defining layer 113 outside the first hole TH1 and on the top surface and lateral surface of the first spacer 115-1. That is, despite the undercut shape UC, the first inorganic encapsulation layer 410 can be continuously formed inside and outside the first hole TH1 without being disconnected.

[0186] The first inorganic encapsulation layer 410 may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) having excellent step coverage compared to physical vapor deposition (PVD). Therefore, the first inorganic encapsulation layer 410 may be conformally formed on the entire inner surface of the first hole TH1, on the top surface of the opposing electrode 330 outside the first hole TH1, and on the top surface and lateral surface of the first spacer 115-1. For example, the first inorganic encapsulation layer 410 may be formed by, for example, thermal CVD, plasma CVD, metal organic (MO) CVD, and hydride vapor phase epitaxy (HVPE).

[0187] After forming the first inorganic encapsulation layer 410, the organic encapsulation layer 420 is formed. The organic encapsulation layer 420 fills the entire inner portion of the first hole TH1 and may have a planarized top surface. For example, the organic encapsulation layer 420 may be formed on the first inorganic encapsulation layer 410 by a spin coating process. After forming the organic encapsulation layer 420, the second inorganic encapsulation layer 430 is formed.

[0188] Figure 7 is a cross-sectional view of a portion of a display device 2 according to an exemplary embodiment of the present disclosure. Figure 7 An exemplary embodiment of Figure 4 The differences between the exemplary embodiments of FIG.

[0189] refer to Figure 7 , the first anti-etching layer ES1 is located on a portion of the first planarization layer 109 on which the first hole TH1 is formed. For example, the first anti-etching layer ES1 may be arranged below the bottom surface of the first hole TH1. The first hole TH1 is formed not only in the second portion SP2 (which is the bottom area of ​​the first spacer 115-1) and the pixel defining layer 113, but also extends into the second planarization layer 111.

[0190] The first anti-etching layer ES1 may be separated from the connection line CL, may include the same material as that of the connection line CL, and may be formed during the same process as the process of forming the connection line CL. The first anti-etching layer ES1 may prevent the first planarization layer 109 and various wirings, electrodes, circuits, etc. of the display device 2 arranged thereunder from being deteriorated during the process of forming the first hole TH1, for example, while forming the opening space of the first hole TH1 by dry etching.

[0191] In the present exemplary embodiment, the intermediate layer 320 and the opposing electrode 330 are formed on the bottom surface of the first hole TH1, and the intermediate layer 320 may include the first functional layer 320a and the second functional layer 320c and may not include the emission layer 320b. Moreover, the first inorganic encapsulation layer 410 is not only stacked on the bottom surface of the first hole TH1 above the opposing electrode 330, but is also continuously formed on the entire inner surface of the first hole TH1 including the bottom surface of the first hole TH1 and on the outside of the first hole TH1, and the organic encapsulation layer 420 fills the inner part of the first hole TH1. Therefore, the adhesion of the thin film encapsulation layer 400 can be enhanced. For example, the plurality of first holes TH1 can be used as anchors of the thin film encapsulation layer 400 between the plurality of pixels in the display area DA, and the adhesion between the thin film encapsulation layer 400 and the back plate can be enhanced, thereby reducing the peeling defect of the thin film encapsulation layer 400.

[0192] Figure 8 is a cross-sectional view of a portion of a display device 3 according to an exemplary embodiment of the present disclosure. Figure 8 Exemplary embodiments and Figure 4 The differences between the exemplary embodiments of FIG. Figure 8 Shows along Figure 1 A cross-sectional area taken along line VIIIA-VIIIB, and a portion of the display area DA.

[0193] refer to Figure 8 In the present exemplary embodiment, a plurality of second holes TH2 are formed in the first non-display area NDA1, and the first dam portion 110 and the second dam portion 120 are located outside the second holes TH2. The first dam portion 110 may be separated from the second dam portion 120 in the first non-display area NDA1, and each may surround the display area DA. Figure 4 The same as the exemplary embodiment of FIG. 1 , the first hole TH1 may be formed in the display area DA in the present exemplary embodiment, but the case in which the second hole TH2 is formed in the first non-display area NDA1 is mainly described in the present exemplary embodiment.

[0194] A first planarization layer 109, a second planarization layer 111, and a pixel defining layer 113 each extending from the display area DA are located in the first non-display area NDA1, and a second spacer 115-2 including the same material as the first spacer 115-1 is located in the first non-display area NDA1.

[0195] The second hole TH2 is formed to pass through a portion of the second spacer 115-2 and a portion of the pixel defining layer 113, and may have a predetermined opening space. The structure of the second hole TH2 is similar to that of the first hole TH1. For example, the first portion SP1 as the top area of ​​the second spacer 115-2 may be a forward tapered shape, and the second portion SP2 as the bottom area of ​​the second spacer 115-2 may be an inverted tapered shape.

[0196] The intermediate layer 320 and the opposite electrode 330 may be formed not only in the display area DA but also in a portion of the first non-display area NDA1 outside the display area DA. That is, the intermediate layer 320 and the opposite electrode 330 may be formed on the bottom surface of the second hole TH2.

[0197] The first functional layer 320a and the second functional layer 320c of the intermediate layer 320 may be formed inside the second hole TH2, and the emission layer 320b of the intermediate layer 320 may not be formed inside the second hole TH2. Like the intermediate layer 320, the opposing electrode 330 is formed on the bottom surface of the second hole TH2 and is not formed on the lateral surface of the second hole TH2. For example, the intermediate layer 320 and the opposing electrode 330 may be formed inside and outside the second hole TH2 so that the intermediate layer 320 and the opposing electrode 330 are disconnected inside and outside the second hole TH2. Like the first functional layer 320a and the second functional layer 320c, the opposing electrode 330 may be deposited as a common layer on all pixels. Similar to the first spacer 115-1, during the process of depositing the intermediate layer 320 including the emission layer 320b by using a mask, the second spacer 115-2 may maintain the separation between the mask and the substrate 100 to prevent the intermediate layer 320 from being cut or torn by the mask during the deposition process.

[0198] When viewed from a side parallel to the substrate 100, the opposing electrode 330 extending from the display area DA may be electrically connected to the second power voltage line 20 through the pixel electrode connecting line 310a because the opposing electrode 330 is completely connected outside the opening in which the second hole TH2 is formed.

[0199] The first inorganic encapsulation layer 410 is formed on the opposite electrode 330. The first inorganic encapsulation layer 410 is not only stacked on the bottom surface of the second hole TH2 above the opposite electrode 330, but also formed on the entire inner surface of the second hole TH2 including the bottom surface of the second hole TH2, extending to the outside of the second hole TH2, and extending to the first dam portion 110 and the second dam portion 120.

[0200] Although the first inorganic encapsulation layer 410 directly contacts the opposite electrode 330 on the bottom surface inside the second hole TH2, the first inorganic encapsulation layer 410 may directly contact the pixel defining layer 113 and the second spacer 115-2 on the lateral surface of the second hole TH2. Therefore, the contact area between the first inorganic encapsulation layer 410 and the organic insulating layer increases, and thus the adhesion of the thin film encapsulation layer 400 may be enhanced.

[0201] The organic encapsulation layer 420 fills the entire inner portion of the second hole TH2. Because the shape of the opening formed in the second hole TH2 is an undercut shape UC in which the first portion SP1 protrudes further than the second portion SP2 at the interface between the first portion SP1 and the second portion SP2 of the second spacer 115-2, and the organic encapsulation layer 420 fills the opening having the undercut shape UC, the second hole TH2 serves as an anchor, and thus the contact strength between the thin film encapsulation layer 400 and the back plate can be increased. For example, the plurality of second holes TH2 can serve as anchors for the thin film encapsulation layer 400 in the first non-display area NDA1, and the adhesive force between the thin film encapsulation layer 400 and the back plate can be enhanced, thereby reducing the peeling defect of the thin film encapsulation layer 400.

[0202] because Figure 4 The first holes TH1 described in the embodiment are provided as a plurality of first holes TH1 in the display area DA, so when the first holes TH1 are additionally arranged in the display area DA between the pixels P, space limitation occurs as the resolution increases. In contrast, since the second holes TH2 according to the present exemplary embodiment are formed in the first non-display area NDA1, a greater number of holes per unit area may be formed at a high density without space limitation.

[0203] The first and second dam portions 110 and 120 are arranged at positions overlapping the second power voltage line 20 outside the second hole TH2 .

[0204] The first dam portion 110 may include a first layer 111a including the same material as the second planarization layer 111, a second layer 113a including the same material as the pixel defining layer 113, and a third layer 115a including the same material as the first spacer 115-1 and the second spacer 115-2. However, the layers constituting the first dam portion 110 are not limited thereto, and the number of layers and the materials of the layers may be changed. For example, in an exemplary embodiment of the present disclosure, the first dam portion 110 may further include another layer including the same material as the first planarization layer 109 to form a four-layer structure.

[0205] A portion of the first dam portion 110 may overlap the opposing electrode 330 extending from the display area DA. Since the end portion of the opposing electrode 330 extends to the second power voltage line 20, noise that may affect the touch sensor layer formed on the thin film encapsulation layer 400 may be blocked.

[0206] The second dam portion 120 may include a first layer 109b including the same material as the first planarization layer 109, a second layer 111b including the same material as the second planarization layer 111, a third layer 113b including the same material as the pixel defining layer 113, and a fourth layer 115b including the same material as the first spacer 115-1 and the second spacer 115-2. However, the layers constituting the second dam portion 120 are not limited thereto, and the number of layers and the materials of the layers may be changed.

[0207] The first dam portion 110 and the second dam portion 120 may function as dams to block the organic material from flowing in an edge direction of the substrate 100 while forming the organic encapsulation layer 420 including the organic material (see FIG. Figure 8 ). The second dam portion 120 may be higher than the first dam portion 110. Since the height of the second dam portion 120 is higher than the height of the first dam portion 110, the organic encapsulation layer 420 may be prevented from overflowing over the second dam portion 120 to generate an edge tail. Moreover, during the process of depositing the intermediate layer 320 by using a mask, the second dam portion 120 maintains the separation between the mask and the substrate 100 to prevent the intermediate layer 320 from being cut or torn by the mask during the deposition process.

[0208] The first layer 109 b of the second dam portion 120 may cover an end portion of the second power voltage line 20 to prevent the second power voltage line 20 from being degraded during wet etching.

[0209] The first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 cover the first dam portion 110 and the second dam portion 120 across the display area DA and the area in which the second hole TH2 is formed, and extend to the edge portion of the substrate 100. The first inorganic encapsulation layer 410 may directly contact the second inorganic encapsulation layer 430 outside the second dam portion 120 to prevent external moisture or impurities from diffusing into the display device through the organic encapsulation layer 420.

[0210] According to the present exemplary embodiment, the second hole TH2 formed in the first non-display area NDA1 can prevent peeling of the thin film encapsulation layer 400 by enhancing the adhesive strength between the thin film encapsulation layer 400 and the back plate as described above. Also, since the open space is formed in a direction perpendicular to the substrate 100 by the depth of the second hole TH2 formed in the second spacer 115-2 and the pixel defining layer 113, the second hole TH2 can reduce the reflow speed of the organic insulating material during the process of forming the organic encapsulation layer 420 by using the organic insulating material having fluidity.

[0211] The organic encapsulation layer 420 may be prevented from overflowing over the second dam portion 120 and generating an edge tail at the edge of the substrate 100 by forming the height of the second dam portion 120 to be higher than the height of the first dam portion 110. However, in a case where the interval between the first dam portion 110 and the second dam portion 120 is reduced to reduce the width of the dead space, it may be difficult to control the reflow speed of the organic encapsulation layer 420, and the organic encapsulation layer 420 may overflow over the second dam portion 120. In this case, in the absence of the second hole TH2, the first dam portion 110 and the second dam portion 120 may not be sufficient to prevent the organic insulating material of the organic encapsulation layer 420 from overflowing over the second dam portion 120 and generating an edge tail at the edge of the substrate 100.

[0212] The second holes TH2 according to the present exemplary embodiment are a plurality of open spaces formed between the display area DA and the first dam portion 110. The second holes TH2 can prevent generation of edge tails due to the organic insulating material by reducing a reflow speed of the organic insulating material flowing in an edge direction of the substrate 100 and allowing the organic insulating material to be sufficiently hardened before the organic insulating material reaches the second dam portion 120.

[0213] Fig. 9 is a cross-sectional view of a portion of a display device 4 according to an exemplary embodiment of the present disclosure. Fig. 9 Exemplary embodiments and Figure 8 The differences between the exemplary embodiments of FIG.

[0214] refer to Fig. 9, a plurality of second holes TH2 are formed in the first non-display area NDA1, and the first dam portion 110 and the second dam portion 120 are located outside the second holes TH2.

[0215] The second anti-etching layer ES2 is located on the first planarization layer 109 extending from the display area DA to the first non-display area NDA1. For example, the second anti-etching layer ES2 may be arranged below the bottom surface of the second hole TH2. The second hole TH2 is not only formed in the second portion SP2 (which is the bottom area of ​​the second spacer 115-2) and the pixel defining layer 113, but also extends to the second planarization layer 111. In addition, the second hole TH2 may extend to the second anti-etching layer ES2, for example, to the top surface of the second anti-etching layer ES2.

[0216] The second anti-etching layer ES2 may be separated from the connection line CL, may include the same material as that of the connection line CL, and may be formed during the same process as the process of forming the connection line CL. The second anti-etching layer ES2 may prevent the first planarization layer 109 and various wirings, electrodes, circuits, etc. of the display device 4 arranged thereunder from being deteriorated during the process of forming the second hole TH2, for example, while forming the opening space of the second hole TH2 by dry etching.

[0217] In the present exemplary embodiment, the intermediate layer 320 and the opposing electrode 330 are formed on the bottom surface of the second hole TH2, and the intermediate layer 320 may include the first functional layer 320a and the second functional layer 320c and may not include the emission layer 320b. Moreover, the first inorganic encapsulation layer 410 is not only stacked on the bottom surface of the second hole TH2 above the opposing electrode 330, but is also continuously formed on the entire inner surface of the second hole TH2 including the bottom surface of the second hole TH2 and the outside of the second hole TH2, and the organic encapsulation layer 420 fills the inner part of the second hole TH2. Therefore, the adhesion of the thin film encapsulation layer 400 can be enhanced. For example, the plurality of second holes TH2 can be used as anchors for the thin film encapsulation layer 400 in the first non-display area NDA1, and the adhesion between the thin film encapsulation layer 400 and the back plate can be enhanced, thereby reducing the peeling defect of the thin film encapsulation layer 400.

[0218] Since the second holes TH2 are formed in the first non-display area NDA1, a greater number of holes per unit area can be formed at a high density without spatial limitation, and the reflow speed of the organic insulating material can be reduced by making the depth of the second holes TH2 deeper. Therefore, during the process of forming the organic encapsulation layer 420 including the organic insulating material, the second holes TH2 having a deeper depth can prevent the generation of edge tails due to the organic insulating material by reducing the reflow speed of the organic insulating material flowing in the edge direction of the substrate 100 and allowing the organic insulating material to be sufficiently hardened before the organic insulating material reaches the second dam portion 120.

[0219] Fig.10 It is along Figure 1 A cross-sectional view of the display device taken along line XA-XB, Fig.11 is a cross-sectional view of a portion of a display device 5 according to an exemplary embodiment of the present disclosure, Fig.12 yes Fig.11 A cross-sectional view of Region XII, and Fig.13 yes Fig.11 The following mainly describes Fig.11 Exemplary embodiments and Figure 4 The differences between the exemplary embodiments of FIG.

[0220] refer to Fig.10 , display device 5 (see Fig.11 ) may include an input sensing layer 40 , an optical function layer 50 , and a window 60 , each of which is arranged on the display panel 10 ′, and the window 60 covers the input sensing layer 40 and the optical function layer 50 .

[0221] The display panel 10' may be understood as a structure including a backplane and a thin film encapsulation layer 400 in the display devices 1, 2, 3, and 4 of the previous exemplary embodiments. The input sensing layer 40 arranged on the display panel 10' may obtain coordinate information corresponding to an external input (e.g., a touch event), and the optical functional layer 50 may include an anti-reflection layer including a phase retarder and a polarizer. The input sensing layer 40 may sense an external input according to a mutual capacitance method or a self-capacitance method. For example, the input sensing layer 40 may obtain information about an external input through a change in capacitance between two sensing electrodes. Although the input sensing layer 40 may be Fig.10 The input sensing layer 40 is shown to be located between the display panel 10 ′ and the optical function layer 50 , but the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the input sensing layer 40 may be located above the optical function layer 50 .

[0222] In an exemplary embodiment of the present disclosure, the optical function layer 50 may include a black matrix and a color filter, and may include a lens layer. The color filter may be arranged by considering the color of the light beam emitted by the pixel of the display panel 10'. Therefore, the desired color may be achieved by filtering the light emitted by each pixel with a color filter. The lens layer may improve the emission efficiency or reduce the color deviation of the light emitted from the display panel 10'. In an exemplary embodiment of the present disclosure, an array of lenses of the lens layer may cover an array of pixels, wherein at least one of the lenses may cover at least one of the pixels.

[0223] Openings 10H, 40H, and 50H may be formed in an opening area OA surrounded by the display area DA, and the openings 10H, 40H, and 50H pass through the display panel 10 ′, the input sensing layer 40 , and the optical function layer 50 , respectively.

[0224] Various components 20' may be arranged in the opening area OA, such as, for example, sensors, cameras, speakers, lights, etc. The component 20' may detect an external target received through the opening area OA, or provide a sound signal, such as voice, to the outside through the opening area OA. In addition, the component 20' may include a plurality of configurations and is not limited to any one exemplary embodiment. Moreover, as shown in dotted lines, the component 20' may be arranged under the display panel 10'. In this case, at least one of the display panel 10', the input sensing layer 40, and the optical functional layer 50 may not include an opening.

[0225] although Figure 1 and Fig.10 A structure in which one circular opening area OA is completely surrounded by the display area DA is shown, but the present disclosure is not limited thereto. For example, the number of opening areas OA, the shape and arrangement of the opening areas OA may be changed differently. For example, in an exemplary embodiment of the present disclosure, the shape of the opening area OA may be modified in various ways, such as, for example, a circular shape, an elliptical shape, a polygonal shape, a star shape, or a diamond shape. When two or more opening areas OA are provided, the opening areas OA may have the same shape or different shapes, and may have the same size or different sizes. Moreover, a second non-display area NDA2 may be located around the opening area OA, and the second non-display area NDA2 may be surrounded by the display area DA.

[0226] refer to Fig.11 According to the present exemplary embodiment, a plurality of third holes TH3 and a plurality of grooves G1, G2, and G3 are formed in the second non-display area NDA2. Figure 4 The same as the exemplary embodiment of the present invention, in the present exemplary embodiment, the first hole TH1 may be formed in the display area DA and Figure 8The same as the exemplary embodiment of FIG. 1 , the second hole TH2 may be formed in the first non-display area NDA1 in the present exemplary embodiment. However, the present exemplary embodiment mainly describes a case in which the third hole TH3 is formed in the second non-display area NDA2 surrounding the opening area OA.

[0227] The partition wall 500 may be located in the second non-display area NDA2 , the partition wall 500 including a first planarization layer 109 , a second planarization layer 111 , and a pixel defining layer 113 , each of which extends from the display area DA.

[0228] The partition wall 500 may surround the opening area OA, and may prevent the organic encapsulation layer 420 from penetrating into the opening area OA by controlling the backflow of the organic encapsulation layer 420, thereby preventing external impurities from entering the display area DA through the opening area OA through the organic encapsulation layer 420. The number, height, and material of the partition wall 500 are not limited to Fig.11 of those and may be changed differently.

[0229] The third spacer 115-3 may be located on the base layer 113c in the second non-display area NDA2, and the base layer 113c includes the same material as the pixel defining layer 113. The third spacer 115-3 may include the same material as the first spacer 115-1. Also, the third spacer 115-3 may include the same material as the second spacer 115-2 (see Figure 8 ) of the same material.

[0230] The third hole TH3 is formed to pass through a portion of the third spacer 115-3 and a portion of the base layer 113c, and may have a predetermined opening space. The structure of the third hole TH3 is similar to that of the first hole TH1. For example, the first portion SP1 as the top area of ​​the third spacer 115-3 may be a forward tapered shape, and the second portion SP2 as the bottom area of ​​the third spacer 115-3 may be an inverted tapered shape.

[0231] A plurality of grooves G1, G2, and G3 are located in the second non-display area NDA2, and the plurality of grooves G1, G2, and G3 expose a portion of the substrate 100. The first groove G1, the second groove G2, and the third groove G3 are arranged in order close to the display area DA. Fig.11 , three grooves are shown, but the present disclosure is not limited thereto, and the number of grooves may be adjusted. Moreover, each of the grooves may have a ring shape completely surrounding the opening area OA in a plan view.

[0232] refer to Fig.11 , Fig.12 and Fig.13The intermediate layer 320 and the opposite electrode 330 may be formed not only in the display area DA but also in a portion of the second non-display area NDA2 surrounding the opening area OA. The intermediate layer 320 and the opposite electrode 330 may be formed on the bottom surfaces of the third hole TH3 and the third groove G3.

[0233] The first functional layer 320a and the second functional layer 320c of the intermediate layer 320 may be formed inside the third hole TH3 and the third groove G3, and the emission layer 320b of the intermediate layer 320 may not be formed inside the third hole TH3 and the third groove G3. Like the intermediate layer 320, the opposite electrode 330 is formed on the bottom surface of the third hole TH3 and the third groove G3, and is not formed on the lateral surface of the third hole TH3 and the third groove G3.

[0234] The first inorganic encapsulation layer 410 is formed on the opposite electrode 330. The first inorganic encapsulation layer 410 is not only stacked on the bottom surface of the third hole TH3 above the opposite electrode 330, but also formed on the entire inner surface of the third hole TH3 including the bottom surface of the third hole TH3, and extends to the outside of the third hole TH3. Moreover, the first inorganic encapsulation layer 410 is not only stacked on the bottom surface of the third groove G3, but also formed on the entire inner surface of the third groove G3 including the bottom surface of the third groove G3, and extends to the outside of the third groove G3 to cooperate with the first inorganic encapsulation layer 410 extending from the third hole TH3 to completely encapsulate the second non-display area NDA2.

[0235] Unlike the previous exemplary embodiment, according to the present exemplary embodiment, the second inorganic encapsulation layer 430 is connected without disconnection at the inner and outer sides of the third hole TH3 and the third groove G3 to completely encapsulate the second non-display area NDA2. The first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430, which are each connected without disconnection at the inner and outer sides of the third hole TH3 and the third groove G3, can enhance the adhesion of the thin film encapsulation layer 400 by increasing their contact area. Moreover, since the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 extend to the opening area OA without the organic encapsulation layer 420, external impurities passing through the opening area OA can be prevented from entering the display area DA through the organic encapsulation layer 420.

[0236] In this case, only the first inorganic encapsulating layer 410 may be connected without being disconnected inside and outside the first groove G1 formed between the partition wall 500 and the display area DA, and the organic encapsulating layer 420 may fill the inner portion of the first groove G1.

[0237] In the case where an adhesive layer including an organic insulating material is further formed on the second inorganic encapsulation layer 430 of the display panel 10', the adhesive layer may fill the inner portion of the third hole TH3 and the third groove G3 to enhance the adhesive force between the adhesive layer and the display panel 10'. For example, the third hole TH3 and the third groove G3 may be used as anchors for the thin film encapsulation layer 400 and the adhesive layer in the second non-display area NDA2, and the adhesive force between the adhesive layer / thin film encapsulation layer 400 and the back plate may be enhanced, thereby reducing peeling defects of the thin film encapsulation layer 400 and the adhesive layer.

[0238] In the following, reference FIG. 14A to FIG. 14F Describe the formation Fig.11 FIG. 1 is a diagram showing a manufacturing process of the third hole TH3.

[0239] FIG. 14A to FIG. 14F According to the exemplary embodiment of the present disclosure, Fig.11 A cross-sectional view of a process of display device 5.

[0240] refer to Fig.14A The partition wall 500 is formed in the second non-display area NDA2, and the partition wall 500 includes a first planarization layer 109, a second planarization layer 111, and a pixel defining layer 113, each extending from the display area DA. The third spacer 115-3 is formed on the base layer 113c including the same material as the pixel defining layer 113 in the display area DA.

[0241] although Fig.14A 1 and 2 show that the base layer 113c and the third spacer 115-3 are represented as different layers by different hatching, but the present disclosure is not limited thereto. For example, the base layer 113c and the third spacer 115-3 may include the same material. For example, the base layer 113c and the third spacer 115-3 may be formed simultaneously by using a half-tone mask during the same process.

[0242] refer to Fig. 14B The barrier layer BL is formed by a deposition process on Fig.14A The third opening OP3 is formed by patterning the barrier layer BL, and the third opening OP3 exposes a portion of the base layer 113c and a portion of the surface of the bottom area of ​​the third spacer 115-3. In this case, the third opening OP3 that exposes a portion of the surface of the buffer layer 101 on the substrate 100 is formed at the same time.

[0243] refer to Fig. 14CThe third hole TH3 is formed by etching a portion of the base layer 113c and a portion of the third spacer 115-3, each corresponding to the third opening OP3, using the barrier layer BL as an etching mask, and the first to third grooves G1, G2, and G3 are formed by etching a portion of the buffer layer 101 and a portion of the substrate 100, each corresponding to the third opening OP3, using the barrier layer BL as an etching mask. The third hole TH3 and the first to third grooves G1, G2, and G3 may be formed by dry etching.

[0244] refer to Fig.14D , the barrier layer BL is removed by wet etching.

[0245] The second portion SP2 of the dry-etched third spacer 115-3 may have an inverted tapered shape, and the first portion SP1 of the unetched third spacer 115-3 may have a forward tapered shape. Therefore, the third hole TH3 may have an undercut shape UC in which the first portion SP1 further protrudes than the second portion SP2 at an interface between the first portion SP1 and the second portion SP2 of the third spacer 115-3.

[0246] The end portion of the buffer layer 101 may protrude further than the lateral surface of the substrate 100 with respect to the surface of the buffer layer 101 on the substrate 100 contacting the substrate 100 in the region where the first to third grooves G1, G2, and G3 are formed. Therefore, the buffer layer 101 may have an undercut shape UC.

[0247] refer to Fig.14E , the intermediate layer 320 and the counter electrode 330 are deposited on Fig.14D in terms of structure.

[0248] The intermediate layer 320 and the opposite electrode 330 may be formed on the bottom surface of each of the third hole TH3 and the first to third grooves G1, G2, and G3, and may be disconnected without being connected to the outside of the third hole TH3 and the first to third grooves G1, G2, and G3. The intermediate layer 320 formed in the third hole TH3 and the first to third grooves G1, G2, and G3 may include a first functional layer 320a and a second functional layer 320c and may not include an emission layer 320b.

[0249] The intermediate layer 320 and the opposite electrode 330 may be formed by physical vapor deposition (PVD) with poor step coverage. Therefore, the intermediate layer 320 and the opposite electrode 330 may be formed non-conformally on the bottom surface of the third hole TH3 and the first to third grooves G1, G2, and G3, and on other surfaces outside the third hole TH3 and the first to third grooves G1, G2, and G3. For example, the intermediate layer 320 and the opposite electrode 330 may be formed by, for example, one of sputtering, thermal evaporation, electron beam evaporation, laser molecular beam epitaxy, and pulsed laser deposition.

[0250] refer to Fig.14F , the thin film encapsulation layer 400 is formed on Fig.14E In terms of structure, the thin film encapsulation layer 400 includes a first inorganic encapsulation layer 410 , an organic encapsulation layer 420 , and a second inorganic encapsulation layer 430 .

[0251] The first inorganic encapsulation layer 410 is not only stacked on the bottom surface of each of the third hole TH3 and the first to third grooves G1, G2 and G3, but also formed on the entire inner surface of each of the third hole TH3 and the first to third grooves G1, G2 and G3. Moreover, the first inorganic encapsulation layer 410 is formed on the top surface of the base layer 113c outside the third hole TH3 and the top surface and lateral surface of the third spacer 115-3. Moreover, the first inorganic encapsulation layer 410 is formed on the top surface of the buffer layer 101 outside the first to third grooves G1, G2 and G3. That is, despite the undercut shape UC, the first inorganic encapsulation layer 410 can be continuously formed inside and outside the third hole TH3 and the first to third grooves G1, G2 and G3 without being disconnected.

[0252] The first inorganic encapsulation layer 410 may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) having excellent step coverage compared to physical vapor deposition (PVD). Therefore, the first inorganic encapsulation layer 410 may be conformally formed on the entire inner surface of the third hole TH3 and the first to third grooves G1, G2, and G3, as well as other surfaces outside the third hole TH3 and the first to third grooves G1, G2, and G3. For example, the first inorganic encapsulation layer 410 may be formed by, for example, one of thermal CVD, plasma CVD, metal-organic (MO) CVD, and hydride vapor phase epitaxy (HVPE).

[0253] After forming the first inorganic encapsulating layer 410, the organic encapsulating layer 420 is formed. The organic encapsulating layer 420 is adjusted by the partition wall 500 and does not overflow over the partition wall 500. The organic encapsulating layer 420 may fill the entire inner portion of the first groove G1.

[0254] After forming the organic encapsulation layer 420, the second inorganic encapsulation layer 430 is formed. The second inorganic encapsulation layer 430 may include the same material as that of the first inorganic encapsulation layer 410, and may be formed using the same process as that of forming the first inorganic encapsulation layer 410. The second inorganic encapsulation layer 430 is not only stacked on the bottom surface of each of the third hole TH3 and the second and third grooves G2 and G3 above the first inorganic encapsulation layer 410, but is also formed on the entire inner surface of each of the third hole TH3 and the second and third grooves G2 and G3. Moreover, the second inorganic encapsulation layer 430 is formed on the top surface of the base layer 113c outside the third hole TH3 and the top and lateral surfaces of the third spacer 115-3. Moreover, the second inorganic encapsulation layer 430 is formed on the top surface of the buffer layer 101 outside the first to third grooves G1, G2, and G3. That is, despite the undercut shape UC, the second inorganic encapsulating layer 430 may be continuously formed without being disconnected inside and outside the third hole TH3 and the second and third grooves G3 .

[0255] According to the exemplary embodiments of the present disclosure described above, the thin film encapsulation layer can be prevented from peeling off by forming a plurality of holes in the display area and / or the non-display area and enhancing the adhesive strength between the thin film encapsulation layer and the backplane. However, the scope of the present disclosure is not limited to this effect.

[0256] It should be understood that the exemplary embodiments of the present disclosure described herein should be considered in a descriptive sense only and not for the purpose of limitation. The description of the features or aspects in each exemplary embodiment should generally be considered as other similar features or aspects that can be used in other exemplary embodiments. Although exemplary embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A display device, include: a display area located on the substrate, the display area including a plurality of pixels, each of the plurality of pixels including a first electrode, a second electrode, and an intermediate layer including an emission layer and arranged between the first electrode and the second electrode; a pixel defining layer, the pixel defining layer covering an edge of the first electrode of each of the plurality of pixels; a first spacer, the first spacer being disposed on the pixel defining layer and comprising a first portion and a second portion, and the second portion of the first spacer being disposed between the first portion of the first spacer and the substrate; as well as a first hole, the first hole being arranged separately from the first electrode in the display area, the first hole being formed in the second portion of the first spacer and the pixel defining layer, The first hole has a first upper end and a second upper end, a first height of the first upper end from the substrate is different from a second height of the second upper end from the substrate, and The first portion of the first spacer has a width that increases toward the substrate, and the second portion of the first spacer has a width that decreases toward the substrate.

2. The display device according to claim 1, in, The first height is the same as a height of a top surface of the pixel defining layer from the substrate, and the second height is the same as a height of a top surface of the second portion of the first spacer from the substrate.

3. The display device according to claim 2, in, The first height is smaller than the second height.

4. The display device according to claim 1, in, The intermediate layer and the second electrode are located inside the first hole.

5. The display device according to claim 4, in, The emission layer is located on the first electrode and is not located inside the first hole.

6. The display device according to claim 4, further comprising a thin film encapsulation layer encapsulating the plurality of pixels, The thin film encapsulation layer includes a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer located between the first inorganic encapsulation layer and the second inorganic encapsulation layer. The first inorganic encapsulation layer covers the second electrode located inside the first hole and the entire inner surface of the first hole, and The organic encapsulation layer fills an entire inner portion of the first hole.

7. The display device according to claim 1, in, The pixel defining layer includes the same material as that of the first spacer.

8. The display device according to claim 1, further comprising: include: a first planarization layer and a second planarization layer sequentially arranged from the substrate between the substrate and the pixel defining layer, The first hole extends into the second planarization layer. 9 . The display device of claim 8 , further comprising a first anti-etching layer disposed below a bottom surface of the first hole.

10. The display device according to claim 9, further comprising: include: A thin film transistor, wherein the thin film transistor is located between the substrate and the first planarization layer; as well as a connecting line located between the first planarization layer and the second planarization layer and configured to connect the thin film transistor to the first electrode, The first anti-etching layer comprises the same material as that of the connecting line.

11. The display device according to claim 6, in, The first non-display area is located outside the display area, The pixel defining layer extends from the display area to the first non-display area, and The display device further comprises: a second spacer disposed on the pixel defining layer of the first non-display area, including a material that is the same as that of the first spacer, and including a first portion and a second portion, the first portion of the second spacer having a width that increases toward the substrate, and the second portion of the second spacer being disposed between the first portion of the second spacer and the substrate and having a width that decreases toward the substrate; and A second hole is located in the first non-display area, and the second hole is formed in the second portion of the second spacer and the pixel defining layer.

12. The display device according to claim 11, in, The intermediate layer and the second electrode extend to the first non-display area and are located inside the second hole.

13. The display device according to claim 12, in, The first inorganic encapsulation layer, the organic encapsulation layer and the second inorganic encapsulation layer extend to the first non-display area, The first inorganic encapsulation layer covers the second electrode located inside the second hole and the entire inner surface of the second hole, and The organic encapsulation layer fills an entire inner portion of the second hole.

14. The display device according to claim 12, further comprising a power supply voltage line located in the first non-display area, the power supply voltage line surrounding a portion of the display area, The second electrode extending to the first non-display area is electrically connected to the power voltage line.

15. The display device according to claim 14, further comprising a first dam portion and a second dam portion each located in the first non-display area, wherein the first dam portion and the second dam portion each include a material that is the same as a material of the second spacer and the pixel defining layer, and The second dam portion covers an end portion of the power voltage line.

16. The display device according to claim 11, further comprising a first planarization layer and a second planarization layer sequentially arranged from the substrate in the first non-display area between the substrate and the pixel defining layer, The second hole extends into the second planarization layer. 17 . The display device of claim 16 , further comprising a second anti-etching layer disposed below a bottom surface of the second hole.

18. The display device according to claim 6, in, The second non-display area surrounds the opening formed inside the display area, and The display device in the second non-display area further comprises: a base layer, the base layer comprising a material that is the same as that of the pixel defining layer of the display area; a third spacer located on the base layer, including the same material as that of the first spacer, and including a first portion and a second portion, the first portion of the third spacer having a width that increases toward the substrate, and the second portion of the third spacer being disposed between the first portion of the third spacer and the substrate and having a width that decreases toward the substrate; and A third hole is located in the second non-display area, and the third hole is formed in the second portion of the third spacer and the base layer. 19 . The display device of claim 18 , further comprising a groove passing through a portion of the substrate in the second non-display area.

20. The display device according to claim 19, in, The intermediate layer and the second electrode extend to the second non-display area and are located inside the third hole and the groove.

21. The display device according to claim 20, in, The first inorganic encapsulation layer, the organic encapsulation layer and the second inorganic encapsulation layer extend to the second non-display area, and The first inorganic encapsulation layer and the second inorganic encapsulation layer cover the second electrode located inside the third hole and the groove, and the entire inner surface of the third hole and the groove.

22. A display device, include: A display area, the display area is located on the substrate and includes a plurality of pixels, each of the plurality of pixels includes a first electrode, a second electrode, and an intermediate layer including an emission layer and located between the first electrode and the second electrode; a non-display area, the non-display area being located on the substrate and outside the display area; a thin film encapsulation layer, the thin film encapsulation layer encapsulating the plurality of pixels and comprising a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer located between the first inorganic encapsulation layer and the second inorganic encapsulation layer; a pixel defining layer, the pixel defining layer covering an edge of the first electrode and extending from the display area to the non-display area; a first spacer, the first spacer being located on the pixel defining layer in the display area; a second spacer, the second spacer being located on the pixel defining layer in the non-display area, including a material that is the same as that of the first spacer, and including a first portion and a second portion, the first portion of the second spacer having a width that increases toward the substrate, and the second portion of the second spacer being disposed between the first portion of the second spacer and the substrate and having a width that decreases toward the substrate; as well as A hole is located in the non-display area, the hole being formed in the second portion of the second spacer and the pixel defining layer.

23. The display device according to claim 22, in, A portion of the intermediate layer except the emission layer formed in the display area and the second electrode extend to the non-display area and are located inside the hole, The first inorganic encapsulation layer extends to the non-display area to cover the second electrode located inside the hole and the entire inner surface of the hole, and The organic encapsulation layer fills the entire inner portion of the hole.

24. The display device according to claim 23, in, The first inorganic encapsulation layer, the organic encapsulation layer and the second inorganic encapsulation layer extend to the non-display area, The first inorganic encapsulation layer covers the second electrode located inside the hole and the entire inner surface of the hole, and The organic encapsulation layer fills the entire inner portion of the hole.

25. The display device according to claim 22, further comprising: include: a first planarization layer and a second planarization layer sequentially arranged from the substrate in the non-display area between the substrate and the pixel defining layer, wherein the hole extends into the second planarization layer. 26 . The display device of claim 25 , further comprising an anti-etching layer disposed below a bottom surface of the hole.

27. A display device, include: a display area located on the substrate, the display area including a plurality of pixels, each of the plurality of pixels including a first electrode, a second electrode, and an intermediate layer including an emission layer and arranged between the first electrode and the second electrode; a pixel defining layer, the pixel defining layer covering an edge of the first electrode of each of the plurality of pixels; a spacer, the spacer being arranged on the pixel defining layer; a thin film encapsulation layer, the thin film encapsulation layer being arranged on the pixel defining layer and the spacer and comprising a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer located between the first inorganic encapsulation layer and the second inorganic encapsulation layer; a hole arranged separately from the first electrode, the hole being formed in the spacer and the pixel defining layer, wherein the intermediate layer and / or the second electrode are located inside the hole and on top of the spacer, and the intermediate layer and / or the second electrode are not connected between the inside of the hole and the top of the spacer, and The spacer includes a first portion having a width that increases toward the substrate and a second portion having a width that decreases toward the substrate.

28. The display device according to claim 27, in, The first inorganic encapsulation layer is continuously located at the inner side of the hole and the top of the spacer.

29. The display device according to claim 27, in, The organic encapsulation layer fills the entire inner side of the hole.

30. The display device according to claim 27, further comprising a non-display area located outside the display area, The spacer and the hole are located in the display area and / or the non-display area.

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