Anti-aging architecture for power MOSFET devices

Abstract

Embodiments of the present disclosure relate to an anti-aging architecture for a power MOSFET device. The power MOS stage includes a first power MOS device and a second power MOS device, connected in parallel between a first node and a second node. The first power MOS device has a first rated voltage, and the second power MOS device has a second rated voltage, where the second rated voltage is lower than the first rated voltage. The driver circuit is configured to drive the control nodes of the first and second power MOS devices in a sequential manner when actuating the power MOS stage by actuating the first power MOS device before actuating the second power MOS device. When de-actuating the power MOS stage, the control nodes of the first and second power MOS devices are further driven in a sequential manner by de-actuating the second power MOS device before de-actuating the first power MOS device.

Description

Technical Field

[0001] Embodiments and implementations relate to power metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and more particularly to an architecture for a power MOSFET that prevents aging performance degradation when operating near or above the maximum operating voltage (MOV) of the device. Background Art

[0002] Power metal-oxide-semiconductor field-effect transistor (MOSFET) devices are conventional transistor switching devices used in numerous circuit applications well known to those skilled in the art. In power integrated circuits, efficiency is mainly related to power management circuits, and particularly to power MOSs and their drivers. This observation is valid for both low-power applications or operating conditions and high-power applications or operating conditions. In fact: Under low-power conditions, one of the main power losses is related to the switching losses of the power MOS and its driving stage; and under high-power conditions, the main contribution to power dissipation is related to Joule dissipation on the power MOS stage. Therefore, in these circuit applications, it is very important to optimize the size of the power MOS and, in a complete relationship, to optimize the size of the driver circuit that will control the operation of the power MOS.

[0003] The first criterion considered when selecting a power device is to evaluate the maximum voltage and select the correct voltage rating of the device itself, where the maximum voltage will be applied between the conductive terminals of the power MOS. As is known in the art, two limits of the rated voltage or capacity of a power MOS device are defined for a given technology platform: the maximum operating voltage (MOV): which identifies a maximum voltage up to which the device will operate without any degradation or damage; and the absolute maximum rating (AMR): which identifies the maximum voltage at which the device will definitely be damaged. The AMR voltage is greater than or at least equal to the MOV.

[0004] When a power device operates between the MOV and the AMR voltage, the device will be affected by some degradation but without any damage that prevents the normal operation of the device. In the specific case of a power MOS device, when the device operates above the MOV, the device will be affected in terms of an increase in leakage current (when the transistor switch is off) and a degradation of the resistance value (when the transistor switch is on). These effects occur during the lifetime of the device and can be evaluated by performing aging simulations, such as where some parameters are changed to evaluate the performance degradation during the lifetime of the device over a time period of, for example, 10 years.

[0005] Typically, it is effective that in terms of the resistivity per unit area, MOS with a lower voltage has better characteristics than MOS with a higher voltage, and thus a smaller area and the corresponding smaller parasitic capacitance of the driving stage can be utilized to achieve the same Rdson performance. For these reasons, MOS with a lower voltage can ensure better efficiency under low-power and high-power conditions. During the performance optimization process, the best solution is to use MOS with the lowest possible voltage suitable for the application under development.

[0006] Typically, for the selection of power-stage MOS, there are two typical and possible scenarios: using a power MOS with a MOV higher than the maximum application voltage and an AMR voltage higher than the maximum application voltage; or using a power MOS with an AMR voltage higher than the maximum application voltage but a MOV lower than the maximum voltage.

[0007] Considering the first scenario, assuming the same Rdson target specification, this target can be achieved by using a larger power MOS. Such a device will occupy more silicon area on the chip and will also require the use of a larger driver circuit, which will also affect the total occupied area of the device. Another performance loss due to using a larger power MOS is related to the increase in driver power consumption due to higher parasitic capacitance. In summary, using a power MOS with both a MOV voltage and an AMR voltage higher than the maximum applied voltage results in an increase in silicon area and higher switching power consumption.

[0008] Considering the second scenario, due to the better Rdson performance of the power MOS, a smaller power MOS can be used, but due to the risk of operating above the MOV voltage, the power MOS will be adversely affected by Rdson degradation and other effects (e.g., leakage). To compensate for these aging effects, a larger power MOS needs to be designed to ensure operation at least at the desired Rdson value. However, as a result, due to the increase in occupied area and power dissipation, this will lead to some of the disadvantages experienced in the first scenario above. Another possible problem with this solution is related to the aging effect, which causes some performance drift of the power MOS during the lifetime of the power MOS. In some circuit applications, this performance drift is unacceptable.

[0009] For example, assume that the power MOS is designed for a circuit application in which the device will have to operate at a maximum application voltage of 11V, and also assume that the only power MOS devices available in the selected technology platform are: a relatively high-voltage power MOS A with MOV = 18V and AMR = 25V; and a relatively low-voltage power MOS B with MOV = 8V and AMR = 12V.

[0010] The circuit designer can choose to use Power MOS A, which is guaranteed to operate below both MOV and AMR, and thus obtains: stable performance during the device lifetime; larger area occupancy due to the higher Rdson / area parameter; larger driver due to the larger MOS size; and higher switching dissipation due to the larger MOS size. The circuit designer can alternatively choose to use Power MOS B, which is guaranteed to operate above MOV but below AMR, and thus obtains: variable performance during the lifetime due to aging effects; larger area occupancy due to aging compensation; larger driver due to the larger MOS size; and higher switching dissipation due to the larger MOS size. Neither option is ideal.

[0011] Accordingly, there is a need in the art for a solution that will help optimize the selection and sizing of power MOSs. Preferably, the solution will support the use of power MOSs in a variety of circuit applications, including: power structures such as DC-DC converters (buck, boost, buck-boost, etc.) and power drivers (half-bridge, full-bridge, etc.). Summary of the Invention

[0012] In one embodiment, a circuit includes: a power MOS stage; and a driver circuit configured to drive the power MOS stage. The power MOS stage includes a first power MOS device and a second power MOS device, which are connected in parallel between a first node and a second node. The first power MOS device has a first rated voltage, and the second power MOS device has a second rated voltage, which is lower than the first rated voltage. The driver circuit is configured to drive the control nodes of the first power MOS device and the second power MOS device in a sequential manner when actuating the power MOS stage by: actuating the first power MOS device having the first rated voltage before actuating the second power MOS device having the second rated voltage.

[0013] In one embodiment, a circuit including a half-bridge driver includes: a high-side power MOS stage; a low-side power MOS stage serially coupled to the high-side power MOS stage at an intermediate node; and a driver circuit configured to drive the high-side power MOS stage and the low-side power MOS stage; wherein at least one of the high-side power MOS stage and the low-side power MOS stage includes: a first power MOS device and a second power MOS device connected in parallel between a first node and the intermediate node, the first power MOS device having a first rated voltage and the second power MOS device having a second rated voltage, the second rated voltage being lower than the first rated voltage; and wherein the driver circuit is configured to drive the control nodes of the first power MOS device and the second power MOS device in a sequential manner when actuating the power MOS stage by: actuating the first power MOS device having the first rated voltage before actuating the second power MOS device having the second rated voltage.

[0014] In one embodiment, a power MOS stage includes: a first power MOS device and a second power MOS device connected in parallel between a first node and a second node, the first power MOS device having a first rated voltage and the second power MOS device having a second rated voltage, the second rated voltage being lower than the first rated voltage. A method for driving a power MOS stage includes: driving the control nodes of the first power MOS device and the second power MOS device in a sequential manner when driving the power MOS stage by: actuating the first power MOS device having the first rated voltage; and then actuating the second power MOS device having the second rated voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Other advantages and features of the present invention will become apparent by examining the detailed description of the completely non-limiting embodiments and implementations and the drawings, wherein:

[0016] Figure 1 is a circuit diagram of a power circuit including a power MOS stage and a driver circuit;

[0017] Figure 2 is a circuit diagram of a power circuit including a half-bridge power MOS stage and a driver circuit;

[0018] Figure 3 is a circuit diagram of a power circuit including a half-bridge power MOS stage and a driver circuit. DETAILED DESCRIPTION

[0019] Now refer to Figure 1, which shows a circuit diagram of a power circuit 10. The power circuit 10 includes a power MOS stage 12 and a driver circuit 14 configured to drive the power MOS stage 12. The power MOS stage 12 is implemented using a plurality of power MOS devices 16(1)-16(N), and the plurality of power MOS devices 16(1)-16(N) are connected in parallel with each other between a first conductive node 18 and a second conductive node 20. All of the included power MOS devices 16(1)-16(N) are of the same conductivity type (i.e., they are all n-type devices or all p-type devices). In Figure 1 using the general MOS circuit schematic symbol, it should be understood that depending on the design choices of a given circuit application, the symbol used represents an n-type device or a p-type device. Each power MOS device 16 has a control terminal 22, and the control terminals 22(1)-22(N) are driven by signals generated by the driver circuit 14.

[0020] The power MOS devices 16(1)-16(N) have different rated voltage characteristics. For example, the power MOS device 16(1) has a rated voltage characteristic V1 (where MOV = V MOV1 and AMR = V AMR1 ), the power MOS device 16(2) has a rated voltage characteristic V2 (where MOV = V MOV2 and AMR = V AMR2 ), and the power MOS device 16(N) has a rated voltage characteristic VN (where MOV = V MOVN and AMR = V AMRN ). The relative relationship between the MOVs of the power MOS devices 16(1)-16(N) is: V MOV1 > V MOV2 > V MOVN . The relative relationship between the AMRs of the power MOS devices 16(1)-16(N) is: V AMR1 > V AMR2 > V AMRN .

[0021] When actuating (i.e., turning on) the power MOS stage 12, the driver circuit 14 operates to control the sequential actuation of the power MOS devices 16(1)-16(N) in an order that starts with the power MOS device 16 having the highest rated voltage characteristic and ends with the power MOS device 16 having the lowest rated voltage characteristic. In Figure 1In the example, the sequence of actuation will be to first actuate power MOS device 16(1), then actuate power MOS device 16(2), and finally actuate power MOS device 16(N). Thus, driver circuit 14 will first assert the signal applied to control terminal 22(1) (turn on MOS device 16(1)), then assert the signal applied to control terminal 22(2) (turn on MOS device 16(2)), and finally assert the signal applied to control terminal 22(N) (turn on MOS device 16(N)).

[0022] When deactuating (i.e., turning off) power MOS stage 12, driver circuit 14 operates to control the sequence of deactuation of power MOS devices 16(1)-16(N) in an order that starts with the power MOS device 16 having the lowest rated voltage characteristic and ends with the power MOS device 16 having the highest rated voltage characteristic. In Figure 1 the example, the sequence of deactuation will be to first deactuate power MOS device 16(N), then deactuate power MOS device 16(2), and finally deactuate power MOS device 16(1). Thus, driver circuit 14 will first deassert the signal applied to control terminal 22(N) (turn off MOS device 16(n)), then deassert the signal applied to control terminal 22(2) (turn off MOS device 16(2)), and finally deassert the signal applied to control terminal 22(N) (turn off MOS device 16(1)).

[0023] The operating concept here is to cause driver circuit 14 to turn on / off power MOS devices 16 having relatively high rated voltage characteristics during a time phase when that particular power MOS device 16 is more likely to be affected by degradation, and furthermore to cause driver circuit 14 to turn on / off power MOS devices 16 having relatively low rated voltage characteristics during a time phase when the drain-to-source voltage (Vds) across that particular power MOS device 16 is negligible due to the presence of power MOS devices 16 having higher rated voltage characteristics connected in parallel. This control sequence will prevent aging degradation on the lower voltage power MOS devices, while the higher voltage power MOS devices are naturally protected since the higher voltage power MOS devices operate at a Vds voltage lower than MOV.

[0024] When the MOS operates above MOV but below AMR, the concept of driving MOS devices with different rated voltage characteristics in parallel connection is directly related to the mechanism of aging degradation on the MOS. When the MOS transistor has a large Vds (above MOV) across its terminals and at the same time its gate-to-source (Vgs) is close to the threshold voltage, the MOS transistor will age and degrade. The duration and occurrence frequency of this operating condition directly affect the performance degradation of the MOS in terms of both Rdson and leakage current. In the power stage, these phases have a very short duration (on the order of a few ns), but may have a high occurrence rate due to the operating frequency of the power stage (hundreds of kHz or hundreds of MHz).

[0025] Now refer to Figure 2 , which shows a circuit diagram of a power circuit 110. The power circuit 110 includes a half-bridge power MOS stage 112 and a driver circuit 114 configured to drive the half-bridge power MOS stage 112. The half-bridge power MOS stage 112 includes a high-side power MOS circuit 112a, which is serially coupled with a low-side power MOS circuit 112b between a first node 118 and a second node 120. The series connection between circuits 112a and 112b is made at an intermediate node 119. The power circuit 110 can be used in combination with a DC-DC converter application, in which an input voltage is applied to the first node 118, an inductor is coupled to the intermediate node 119, and an output voltage is generated at the second node 120. The power circuit 110 can also be used in combination with a circuit application for driving an inductive load (such as a motor), in which an input voltage is applied to the first node 118, the inductive load (motor winding) is coupled to the intermediate node 119, and a ground voltage is applied to the second node 120.

[0026] The high-side power MOS circuit 112a is implemented using first and second n-channel power MOS devices 116(1)-116(2), which are connected in parallel with each other between the first node 118 and the intermediate node 119. Each power MOS device 116 has a control terminal 122, where the control terminals 122(1)-122(2) are driven by signals generated by the driver circuit 114.

[0027] The low-side power MOS circuit 112b is implemented using first and second n-channel power MOS devices 216(1)-216(2), which are connected in parallel with each other between an intermediate node 119 and a second node 120. Each power MOS device 216 has a control terminal 222, and the control terminals 222(1)-222(2) are driven by a signal generated by a driver circuit 114.

[0028] The exemplary use of two MOS devices in each circuit 112 is merely an example. It will be understood that each circuit 112 may include three or more MOS devices, as Figure 1 shown.

[0029] The power MOS devices 116(1)-116(2) have different rated voltage characteristics. For example, the power MOS device 116(1) has a rated voltage characteristic V1 (where MOV = V MOV1 and AMR = V AMR1 ), and the power MOS device 116(2) has a rated voltage characteristic V2 (where MOV = V MOV2 and AMR = V AMR2 ). The relative relationship between the MOVs of the power MOS devices 116(1)-116(2) is: V MOV1 > V MOV2 . The relative relationship between the AMRs of the power MOS devices 116(1)-116(2) is: V AMR1 > V AMR2 .

[0030] The power MOS devices 216(1)-216(2) have different rated voltage characteristics. For example, the power MOS device 216(1) has a rated voltage characteristic V1 (where MOV = V MOV1 and AMR = V AMR1 ), and the power MOS device 216(2) has a rated voltage characteristic V2 (where MOV = V MOV2 and AMR = V AMR2 ). The relative relationship between the MOVs of the power MOS devices 216(1)-216(2) is: V MOV1 > V MOV2 . The relative relationship between the AMRs of the power MOS devices 216(1)-216(2) is: V AMR1 > V AMR2 .

[0031] The actuation of the high-side power MOS circuit 112a involves the sequential actuation of the power MOS devices 116(1)-116(2) as follows:

[0032] - The driver circuit 114 applies a signal to the control terminal 122(1) to turn on the power MOS device 116(1), and there will be a relatively small Vds across this device; and

[0033] - After a short delay time (e.g., in the range of a few nanoseconds, during which Vds is small), the driver circuit 114 applies a signal to the control terminal 122(2) to turn on the power MOS device 116(2), and this turn-on occurs with a relatively small Vds, and thus there is no degradation.

[0034] The de-actuation of the high-side power MOS circuit 112a includes the following sequential de-actuation of the power MOS devices 116(1)-116(2):

[0035] - The driver circuit 114 applies a signal to the control terminal 122(2) to turn off the power MOS device 116(2), and this turn-off occurs with a relatively small Vds, and thus there is no degradation; and

[0036] - After a short delay time (e.g., in the range of a few nanoseconds), the driver circuit 114 applies a signal to the control terminal 122(1) to turn off the power MOS device 116(1), and there will be a relatively small Vds across this device.

[0037] The actuation of the low-side power MOS circuit 112b includes the following sequential actuation of the power MOS devices 216(1)-216(2):

[0038] - The driver circuit 114 applies a signal to the control terminal 222(1) to turn on the power MOS device 216(1), and there will be a relatively small Vds across this device; and

[0039] - After a short delay time (e.g., in the range of a few nanoseconds, during which Vds is small), the driver circuit 114 applies a signal to the control terminal 222(2) to turn on the power MOS device 216(2), and this turn-on occurs with a relatively small Vds, and thus there is no degradation.

[0040] The de-actuation of the low-side power MOS circuit 112b includes the following sequential de-actuation of the power MOS devices 216(1)-216(2):

[0041] - The driver circuit 114 applies a signal to the control terminal 222(2) to turn off the power MOS device 216(2), and this turn-off occurs with a relatively small Vds, and thus there is no degradation; and

[0042] - After a short delay time (e.g., in the range of a few nanoseconds), the driver circuit 114 applies a signal to the control terminal 222(1) to turn off the power MOS device 216(1), and there will be a relatively small Vds across the device.

[0043] It will be noted that, in the case of the half - bridge circuit implementation of Figure 2 , there is a delay between the de - actuation of the high - side power MOS circuit 112a and the actuation of the low - side power MOS circuit 112b to ensure there is no risk of shoot - through current.

[0044] With the sequential actuation / de - actuation of the power MOS devices as described, the lower - voltage power MOS is always protected by the higher - voltage power MOS, and as a result, during the operating life of the lower - voltage power MOS, there is no concern about performance degradation and fluctuations. Therefore, the lower - voltage power MOS can be designed and the target Rdson achieved with a smaller impact on MOS area, driver - circuit area, and switching power dissipation. This benefit stems from the fact that there is no need to increase the size of the MOS device to compensate for any aging degradation.

[0045] Adding a higher - voltage MOS in parallel with the lower - voltage MOS will have only a small or negligible impact on area and power consumption, since the added MOS is not used to achieve the target Rdson or any other performance of the circuit. Rather, the additional MOS is used only during the transition to protect the lower - voltage MOS transistor, and thus the size of the higher - voltage MOS can be made smaller than that of the lower - voltage MOS.

[0046] Due to the multi - gate drive stage and the sequence to be followed, the driver complexity in this architecture is slightly higher. However, considering that more complex drive stages already exist in many applications (e.g., for power distribution, voltage slew - rate control, etc.), the circuit designer can consider the complexity of the additional driver to be negligible.

[0047] Figure 3An alternative circuit implementation is shown, in which the high-side power MOS circuit 112a is instead implemented using first and second p-channel power MOS devices 116(1)-116(2), which are connected in parallel with each other between a first node 118 and an intermediate node 119. The power circuit 110 can be used in combination with a DC-DC converter application, in which an input voltage is applied through an inductor coupled to the intermediate node 119, an output voltage is generated at the first node 118, and a ground voltage is applied at a second node 120. The power circuit 110 can also be used in combination with a circuit application for driving an inductive load, such as a motor, in which an input voltage is applied to the first node 118, the inductive load (motor winding) is coupled to the intermediate node 119, and a ground voltage is applied to the second node 120.

[0048] Although the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. A circuit, comprising: A power MOS stage; And A driver circuit configured to drive the power MOS stage; Wherein the power MOS stage includes a first power MOS device and a second power MOS device, the first power MOS device and the second power MOS device are connected in parallel between a first node and a second node, the first power MOS device has a first rated voltage, and the second power MOS device has a second rated voltage, the second rated voltage being lower than the first rated voltage; And Wherein the driver circuit is configured to drive the control nodes of the first power MOS device and the second power MOS device in a sequential manner when actuating the power MOS stage by: actuating the first power MOS device having the first rated voltage before actuating the second power MOS device having the second rated voltage.

2. The circuit according to claim 1, wherein the driver circuit is configured to drive the control nodes of the first power MOS device and the second power MOS device in a sequential manner when de-actuating the power MOS stage by: de-actuating the second power MOS device having the second rated voltage before de-actuating the first power MOS device having the first rated voltage.

3. The circuit according to claim 1, wherein the first power MOS device and the second power MOS device are n-type devices.

4. The circuit according to claim 1, wherein the first power MOS device and the second power MOS device are p-type devices.

5. The circuit according to claim 1, wherein the power MOS stage is a switching circuit of a DC-DC converter.

6. The circuit according to claim 1, wherein the power MOS stage is a switching circuit of a half-bridge driver.

7. The circuit according to claim 1, wherein the power MOS stage is a switching circuit of a full-bridge driver.

8. The circuit according to claim 1, wherein the first rated voltage includes the maximum operating voltage MOV of V MOV1 and the absolute maximum rating AMR of V AMR1 , and wherein the second rated voltage includes the maximum operating voltage MOV of V MOV2 and the absolute maximum rating AMR of V AMR2 , where V MOV1 > V MOV2 and V AMR1 > V AMR2 .

9. The circuit according to claim 1, wherein the first rated voltage includes the maximum operating voltage MOV of V MOV1 and wherein the second rated voltage includes the maximum operating voltage MOV of V MOV2 , where V MOV1 > V MOV2 .

10. The circuit according to claim 1, wherein the first rated voltage includes the absolute maximum rating AMR of V AMR1 and wherein the second rated voltage includes the absolute maximum rating AMR of V AMR2 , where V AMR1 > V AMR2 .

11. A circuit including a half-bridge driver, comprising: A high-side power MOS stage; A low-side power MOS stage serially coupled to the high-side power MOS stage at an intermediate node; And A driver circuit configured to drive the high-side power MOS stage and the low-side power MOS stage; Wherein at least one of the high-side power MOS stage and the low-side power MOS stage includes: A first power MOS device and a second power MOS device connected in parallel between a first node and the intermediate node, the first power MOS device has a first rated voltage, and the second power MOS device has a second rated voltage, the second rated voltage being lower than the first rated voltage; And Wherein the driver circuit is configured to drive the control nodes of the first power MOS device and the second power MOS device in a sequential manner when actuating the power MOS stage by: actuating the first power MOS device having the first rated voltage before actuating the second power MOS device having the second rated voltage.

12. The circuit according to claim 11, wherein the driver circuit is configured to drive the control nodes of the first power MOS device and the second power MOS device in a sequential manner when de-actuating the power MOS stage by: de-actuating the second power MOS device having the second rated voltage before de-actuating the first power MOS device having the first rated voltage.

13. The circuit according to claim 11, wherein the first power MOS device and the second power MOS device are n-type devices.

14. The circuit according to claim 11, wherein the first power MOS device and the second power MOS device are p-type devices.

15. The circuit according to claim 11, wherein the first node is coupled to receive a supply voltage, and the intermediate node is coupled to drive an output load.

16. The circuit according to claim 11, wherein the first node is coupled to an inductor, and the intermediate node is coupled to drive an output load.

17. The circuit according to claim 16, wherein the inductor is coupled to a ground voltage.

18. The circuit according to claim 16, wherein the inductor is coupled to receive an input voltage.

19. The circuit according to claim 11, wherein the first node is coupled to an inductor, and the intermediate node is coupled to a ground voltage.

20. The circuit according to claim 19, wherein the inductor is coupled to receive an input voltage.

21. The circuit according to claim 11, wherein the first rated voltage includes the maximum operating voltage MOV of V MOV1 and the absolute maximum rating AMR of V AMR1 , and wherein the second rated voltage includes the maximum operating voltage MOV of V MOV2 and the absolute maximum rating AMR of V AMR2 , where V MOV1 > V MOV2 and V AMR1 > V AMR2 .

22. The circuit according to claim 11, wherein the first rated voltage includes the maximum operating voltage MOV of V MOV1 , and wherein the second rated voltage includes the maximum operating voltage MOV of V MOV2 , where V MOV1 > V MOV2 .

23. The circuit according to claim 11, wherein the first rated voltage includes the absolute maximum rating AMR of V AMR1 and wherein the second rated voltage includes the absolute maximum rating AMR of V AMR2 where V AMR1 > V AMR2 .

24. A method for driving a power MOS stage, the power MOS stage including a first power MOS device and a second power MOS device, connected in parallel between a first node and a second node, the first power MOS device having a first rated voltage, and the second power MOS device having a second rated voltage, the second rated voltage being lower than the first rated voltage, the method comprising: when actuating the power MOS stage by: driving the control nodes of the first power MOS device and the second power MOS device in a sequential manner: actuating the first power MOS device having the first rated voltage; and then actuating the second power MOS device having the second rated voltage.

25. The method according to claim 24, further comprising: when de-actuating the power MOS stage by: driving the control nodes of the first power MOS device and the second power MOS device in a sequential manner: de-actuating the second power MOS device having the second rated voltage; and then de-actuating the first power MOS device having the first rated voltage.

26. The method according to claim 24, wherein the first rated voltage includes the maximum operating voltage MOV of V MOV1 and the absolute maximum rating AMR of V AMR1 , and wherein the second rated voltage includes the maximum operating voltage MOV of V MOV2 and the absolute maximum rating AMR of V AMR2 , where V MOV1 > V MOV2 and V AMR1 > V AMR2 .

27. The method according to claim 24, wherein the first rated voltage includes the maximum operating voltage MOV of V MOV1 , and wherein the second rated voltage includes the maximum operating voltage MOV of V MOV2 , where V MOV1 > V MOV2 .

28. The method according to claim 24, wherein the first rated voltage includes the absolute maximum rating AMR of V AMR1 and wherein the second rated voltage includes the absolute maximum rating AMR of V AMR2 , where V AMR1 > V AMR2 .

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